Amplifier circuit

Abstract

This invention provides a cascode-type amplifier circuit with suppressed overvoltage input. [Solution] The amplification circuit 1 comprises an input terminal 101 and an output terminal 102, an FET 11 having a gate terminal g1, a drain terminal d1 and a source terminal s1, an FET 12 having a gate terminal g2, a drain terminal d2 and a source terminal s2, a diode 511 having a first anode terminal and a first cathode terminal, and a diode 512 having a second anode terminal and a second cathode terminal. The gate terminal g1 is connected to the input terminal 101, the drain terminal d1 is connected to the source terminal s2, the drain terminal d2 is connected to the output terminal 102, the first anode terminal and the second cathode terminal are connected to a first path connecting the input terminal 101 and the gate terminal g1, and the second anode terminal and the first cathode terminal are connected to the drain terminal d1.

Description

[Technical Field]

[0001] This invention relates to an amplification circuit. [Background technology]

[0002] Patent Document 1 discloses an amplification circuit comprising an amplifier having a cascode-connected common-source FET (Field Effect Transistor) and a common-gate FET, and a limiter circuit connected between the input node of the amplifier and ground. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-191551 [Overview of the project] [Problems that the invention aims to solve]

[0004] However, in the amplification circuit disclosed in Patent Document 1, when an overvoltage input is applied to the amplifier, the drain-gate voltage of the common-source FET increases, and the limiter circuit cannot suppress the drain-gate voltage, which may degrade the amplification characteristics of the amplifier.

[0005] Therefore, the present invention has been made to solve the above problems, and aims to provide a cascode-connected amplifier circuit in which overvoltage input is suppressed. [Means for solving the problem]

[0006] To achieve the above objective, an amplification circuit according to one aspect of the present invention comprises an input terminal and an output terminal, a first FET having a first gate terminal, a first drain terminal and a first source terminal, a second FET having a second gate terminal, a second drain terminal and a second source terminal, a first diode having a first anode terminal and a first cathode terminal, and a second diode having a second anode terminal and a second cathode terminal, wherein the first gate terminal is connected to the input terminal, the first drain terminal is connected to the second source terminal, the second drain terminal is connected to the output terminal, the first anode terminal and the second cathode terminal are connected to a first path connecting the input terminal and the first gate terminal, and the second anode terminal and the first cathode terminal are connected to the first drain terminal.

[0007] Furthermore, an amplification circuit according to one aspect of the present invention comprises an input terminal and an output terminal, a first FET having a first gate terminal, a first drain terminal and a first source terminal, a second FET having a second gate terminal, a second drain terminal and a second source terminal, a first diode having a first anode terminal and a first cathode terminal, and a second diode having a second anode terminal and a second cathode terminal, wherein the first gate terminal is connected to the input terminal, the first drain terminal is connected to the second source terminal, the second drain terminal is connected to the output terminal, the first anode terminal and the second cathode terminal are connected to a first path connecting the input terminal and the first gate terminal, and the second anode terminal and the first cathode terminal are connected to the second gate terminal. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a cascode-connected amplifier circuit in which overvoltage input is suppressed. [Brief explanation of the drawing]

[0009] [Figure 1] This is a circuit diagram of the amplification circuit according to Example 1. [Figure 2] This diagram schematically represents the input voltage applied to a cascode-connected amplifier circuit. [Figure 3] This is a circuit diagram showing the state when an overvoltage is applied to the amplification circuit according to Example 1. [Figure 4] It is a graph showing waveforms of the gate terminal-drain terminal voltage when an overvoltage is input to the amplifier circuits according to Example 1 and the comparative example. [Figure 5] It is a circuit configuration diagram of the amplifier circuit according to Example 2. [Figure 6] It is a circuit state diagram when an overvoltage is applied to the amplifier circuit according to Example 2.

MODE FOR CARRYING OUT THE INVENTION

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. All of the examples described below show comprehensive or specific examples. Numerical values, shapes, materials, components, arrangements of components, connection forms, etc. shown in the following examples are merely examples and are not intended to limit the present invention.

[0011] Each figure is a schematic diagram that has been appropriately emphasized, omitted, or adjusted in ratio to show the present invention, and is not necessarily drawn precisely, and may differ from the actual shape, positional relationship, and ratio. In each figure, the same reference numerals are given to substantially the same configurations, and duplicate explanations may be omitted or simplified.

[0012] In the circuit configuration of the present disclosure, "connected" includes not only cases directly connected by connection terminals and / or wiring conductors, but also cases electrically connected via other circuit elements. "Connected between A and B" means connected to both A and B between A and B.

[0013] Also, in the present disclosure, "path" means a transmission line composed of a wiring through which a high-frequency signal propagates, an electrode directly connected to the wiring, and a terminal directly connected to the wiring or the electrode. Also, "a path connecting A and B" means a path in the section between A and B, and does not include a path extending toward a circuit element (or terminal) other than A and B from A and a path extending toward a circuit element (or terminal) other than A and B from B.

[0014] Furthermore, in this disclosure, "component A is arranged in series with path B" means that both the signal input terminal and the signal output terminal of component A are connected to the wiring, electrodes, or terminals that constitute path B.

[0015] In this invention, "terminal," "input terminal," "output terminal," "gate terminal," "drain terminal," and "source terminal" refer to the point where a conductor within an element terminates. However, if the impedance of the conductors between elements is sufficiently low, a terminal is interpreted not only as a single point, but as any point on the conductor between elements or as an entire conductor.

[0016] (Embodiment) [1. Configuration of the amplifier circuit 1 according to Example 1] The circuit configuration of the amplifier circuit 1 according to Embodiment 1 will be described with reference to Figure 1. Figure 1 is a circuit diagram of the amplifier circuit 1 according to Embodiment 1. As shown in the figure, the amplifier circuit 1 includes an input terminal 101, an output terminal 102, FETs 11 and 12, limiter circuits 51 and 52, an LCR parallel resonant circuit 30, capacitors 21, 22 and 23, an inductor 24, resistors 25 and 26, and bias terminals 103 and 104.

[0017] Input terminal 101 is a terminal for inputting a high-frequency signal to the amplification circuit 1. Output terminal 102 is a terminal for outputting a high-frequency signal from the amplification circuit 1.

[0018] FET11 is an example of a first FET, an n-channel type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a gate terminal g1 (first gate terminal), a drain terminal d1 (first drain terminal), and a source terminal s1 (first source terminal). FET12 is an example of a second FET, an n-channel type MOSFET having a gate terminal g2 (second gate terminal), a drain terminal d2 (second drain terminal), and a source terminal s2 (second source terminal).

[0019] The gate terminal g1 is connected to the input terminal 101 via capacitor 21, the drain terminal d1 is connected to the source terminal s2, and the drain terminal d2 is connected to the output terminal 102 via capacitor 23.

[0020] Capacitor 21 is an example of a first capacitor and is arranged in series with the first path connecting the input terminal 101 and the gate terminal g1. Capacitor 21 is an element for blocking DC current and does not necessarily have to be included in the amplifier circuit 1.

[0021] The bias terminal 103 is an example of a first bias terminal and is connected to the path between the capacitor 21 and the gate terminal g1 of the first path. The bias terminal 103 is a terminal for supplying a bias voltage to the FET 11 and is connected to the bias circuit.

[0022] Capacitor 22 is an example of a second capacitor and is connected between the gate terminal g2 and ground. Capacitor 22 is an element that prevents DC current from leaking to the ground side and does not necessarily have to be included in the amplifier circuit 1. Also, since the gate terminal g2 is connected to ground via capacitor 22, the gate terminal g2 is high-frequency grounded.

[0023] The bias terminal 104 is an example of a second bias terminal and is connected to the second path connecting the gate terminal g2 and the capacitor 22. The bias terminal 104 is a terminal for supplying a bias voltage to the FET 12 and is connected to the bias circuit.

[0024] Inductor 24 is connected between the source terminal s1 and ground. Inductor 24 does not necessarily have to be included in the amplification circuit 1.

[0025] With the above configuration, FET11 and FET12 are connected in a cascode configuration, so the amplifier circuit 1 functions as a high-gain amplifier circuit.

[0026] The limiter circuit 51 includes diodes 511 and 512. Diode 511 is an example of a first diode and has a first anode terminal and a first cathode terminal. Diode 512 is an example of a second diode and has a second anode terminal and a second cathode terminal. The first anode terminal and the second cathode terminal are connected to node Y on a first path connecting the input terminal 101 and the gate terminal g1. The second anode terminal and the first cathode terminal are connected to node X on a path connecting the drain terminal d1 and the source terminal s2.

[0027] Diode 511 has a first threshold voltage, and when the voltage at node Y relative to node X becomes greater than or equal to the first threshold voltage (first on-voltage), current flows from the first anode terminal to the first cathode terminal, and the voltage at node Y relative to node X does not exceed the first threshold voltage (is limited by the first threshold voltage). Diode 512 has a second threshold voltage, and when the voltage at node X relative to node Y becomes greater than or equal to the second threshold voltage (second on-voltage), current flows from the second anode terminal to the second cathode terminal, and the voltage at node X relative to node Y does not exceed the second threshold voltage (is limited by the second threshold voltage). In this embodiment, the first threshold voltage and the second threshold voltage are the same value (denoted as on-voltage), but the first threshold voltage and the second threshold voltage may be different.

[0028] According to the limiter circuit 51, when an overvoltage is applied to the input terminal 101, it is possible to prevent the voltage amplitude between the gate terminal g1 and the drain terminal d1 of FET 11 from becoming larger than the on-voltage. In other words, the voltage amplitude between the gate terminal g1 and the drain terminal d1 of FET 11 can always be kept below the on-voltage.

[0029] Furthermore, diode 511 may have a configuration in which multiple first diode elements are connected in series. In this case, the first ON voltage of diode 511 is the sum of the threshold voltages of the multiple first diode elements. Also, the first anode terminal of diode 511 is the anode terminal of the first diode element connected to node Y among the multiple first diode elements, and the first cathode terminal of diode 511 is the cathode terminal of the first diode element connected to node X among the multiple first diode elements.

[0030] Furthermore, diode 512 may have a configuration in which multiple second diode elements are connected in series. In this case, the second ON voltage of diode 512 is the sum of the threshold voltages of the multiple second diode elements. Also, the second anode terminal of diode 512 is the anode terminal of the second diode element connected to node X among the multiple second diode elements, and the second cathode terminal of diode 512 is the cathode terminal of the second diode element connected to node Y among the multiple second diode elements.

[0031] Furthermore, since the limiter circuit 51 becomes a capacitive circuit during normal operation when no overvoltage is flowing, the closer it is placed to the gate terminal g1, the more likely it is to degrade the amplification characteristics of the FET 11. From this perspective, when the capacitor 21 is placed in the first path, it is preferable that the node Y to which the limiter circuit 51 is connected is placed in the path between the input terminal 101 and the capacitor 21, rather than in the path between the capacitor 21 and the gate terminal g1.

[0032] The limiter circuit 52 includes diodes 521 and 522. Diode 521 is an example of a third diode and has a third anode terminal and a third cathode terminal. Diode 522 is an example of a fourth diode and has a fourth anode terminal and a fourth cathode terminal. The third anode terminal and the fourth cathode terminal are connected to node Y. The fourth anode terminal and the third cathode terminal are connected to ground.

[0033] Diode 521 has a third threshold voltage, and when the voltage at node Y relative to ground becomes greater than or equal to the third threshold voltage (third on-voltage), current flows from the third anode to the third cathode, and the voltage at node Y relative to ground does not become greater than the third threshold voltage (it is limited by the third threshold voltage). Diode 522 has a fourth threshold voltage, and when the voltage at node Y relative to ground becomes less than or equal to a negative fourth threshold voltage (negative fourth on-voltage), current flows from the fourth anode to the fourth cathode, and the voltage at node Y relative to ground does not become less than the negative fourth threshold voltage (it is limited by the negative fourth threshold voltage). In this embodiment, the third threshold voltage and the fourth threshold voltage are the same value (denoted as on-voltage), but the third threshold voltage and the fourth threshold voltage may be different.

[0034] According to the limiter circuit 52, when an overvoltage is applied to the input terminal 101, it is possible to prevent the voltage amplitude between the gate terminal g1 of FET 11 and ground from becoming larger than the on-voltage. In other words, the voltage amplitude between the gate terminal g1 of FET 11 and ground can always be kept below the on-voltage.

[0035] Furthermore, diode 521 may have a configuration in which multiple third diode elements are connected in series. In this case, the third ON voltage of diode 521 is the sum of the threshold voltages of the multiple third diode elements. Also, the third anode terminal of diode 521 is the anode terminal of the third diode element connected to node Y among the multiple third diode elements, and the third cathode terminal of diode 521 is the cathode terminal of the third diode element connected to ground among the multiple third diode elements.

[0036] Furthermore, diode 522 may have a configuration in which multiple fourth diode elements are connected in series. In this case, the fourth ON voltage of diode 522 is the sum of the threshold voltages of the multiple fourth diode elements. Also, the fourth anode terminal of diode 522 is the anode terminal of the fourth diode element connected to ground among the multiple fourth diode elements, and the fourth cathode terminal of diode 522 is the cathode terminal of the fourth diode element connected to node Y among the multiple fourth diode elements.

[0037] Furthermore, since the limiter circuit 52 becomes a capacitive circuit during normal operation when no overvoltage is flowing, the closer it is placed to the gate terminal g1, the more likely it is to degrade the amplification characteristics of the FET 11. From this perspective, when the capacitor 21 is placed in the first path, it is preferable that the node Y to which the limiter circuit 52 is connected be placed in the path between the input terminal 101 and the capacitor 21, rather than in the path between the capacitor 21 and the gate terminal g1.

[0038] The LCR parallel resonant circuit 30 is connected between the power supply terminal (VDD) and the drain terminal d2, and has a circuit configuration in which a capacitor 31, an inductor 32, and a resistor 33 are connected in parallel. The LCR parallel resonant circuit 30 suppresses leakage of high-frequency signals near the resonant frequency to the power supply terminal (VDD) side. Note that the capacitor 31 may be a variable capacitance element, and the inductor 32 may be a variable inductance element. With this configuration, the resonant frequency of the LCR parallel resonant circuit 30 can be changed according to the frequency of the input signal.

[0039] Figure 2 schematically represents the input voltage applied to a cascode-connected amplifier circuit. The figure shows the waveforms of the input voltage at nodes X and Y of the cascode-connected FETs 11 and 12.

[0040] As shown in the figure, when a high-frequency signal is input to input terminal 101, the signal voltage waveform at node X is inverted with respect to the signal voltage waveform at node Y. Therefore, the voltage between the gate terminal g1 and the drain terminal d1 of FET11 (VGD ) becomes larger than the voltage (V GS ) between the gate terminal g1 and the ground of FET11. In particular, when an overvoltage high-frequency signal (strong input) is input to the input terminal 101, if the limiter circuit 51 is not arranged, the voltage V GD will increase significantly, and the structure between the gate terminal g1 and the drain terminal d1 of FET11 may deteriorate.

[0041] In contrast, in the conventional amplifier circuit, the limiter circuit 51 is not arranged, but the limiter circuit 52 is arranged between the node Y and the ground. According to this, for the overvoltage applied between the node Y and the ground, the limiter circuit 52 operates to limit the voltage (V GS ) between the gate terminal g1 and the ground of FET11 to below the on voltage. However, as described above, since the voltage (V GD ) between the gate terminal g1 and the drain terminal d1 is larger than the voltage V GS , in the configuration where only the limiter circuit 52 is arranged without the limiter circuit 51, before the voltage V GS is limited, the voltage V GD will increase rapidly, and the structure between the gate terminal g1 and the drain terminal d1 of FET11 may deteriorate.

[0042] Furthermore, in the conventional amplifier circuit, when the impedance of the node Y (the impedance between the gate terminal g1 and the ground) has a low circuit configuration, even when a strong input is applied to the input terminal 101, the voltage between the node Y and the ground may not increase, and the limiter circuit 52 may not operate.

[0043] In contrast, in the amplifier circuit 1 according to the present embodiment, by connecting the limiter circuit 51 between the node Y and the drain terminal d1, when an overvoltage is applied to the input terminal 101, the voltage amplitude of the node X is limited, so that the rapid increase of the voltage (V GD ) between the gate terminal g1 and the drain terminal d1 can be suppressed. Also, even when the impedance of the node Y is low, since the limiter circuit 51 operates according to the magnitude of the voltage between the node Y and the drain terminal d1, the rapid increase of the voltage V GD can be suppressed.

[0044] The configuration in which the limiter circuit 51 is connected to the drain terminal d1 is due to the fact that the amplification circuit 1 is a cascode amplifier, and node X undergoes voltage fluctuations along with the high-frequency signal.

[0045] Since the power supply voltage VDD is always applied to the drain terminal of an FET that is not cascode connected, even if the limiter circuit 51 is connected from the gate terminal to the drain terminal, the voltage at the drain terminal will always be the power supply voltage VDD, and the gate terminal-drain terminal voltage (V) will be affected when an overvoltage is applied. GD This effect of suppressing the sharp increase in ) cannot be achieved.

[0046] Figure 3 is a circuit diagram showing the state when an overvoltage is applied to the amplifier circuit 1 according to Embodiment 1. When an overvoltage (strong input) is applied to the input terminal 101, diodes 511 and 512 become conductive, and a current corresponding to the overvoltage flows between node X and node Y. This current flows to ground via the drain terminal d1 and source terminal s1. As a result, the potential of node X does not become greater than the (positive) on-voltage of the limiter circuit 51 relative to the potential of node Y, and does not become smaller than the (negative) on-voltage of the limiter circuit 51 relative to the potential of node Y. In other words, since the DC level voltage of node X becomes less than or equal to the on-voltage, the FET 11 moves out of the saturation region, and the voltage amplitude at node X becomes extremely small. Therefore, it is possible to avoid applying an overvoltage between node Y and node X, and to suppress deterioration of the structure between the gate terminal g1 and drain terminal d1 of the FET 11. Furthermore, even when the impedance of node Y is low, the limiter circuit 51 operates based on the magnitude of the voltage between node Y and drain terminal d1, so the voltage between gate terminal g1 and drain terminal d1 (V GD This can suppress the sharp increase in ).

[0047] Furthermore, when an overvoltage (strong input) is applied to the input terminal 101, diodes 521 and 522 become conductive, and a current corresponding to the overvoltage flows between node Y and ground. As a result, the potential of node Y does not become greater than the (positive) on-voltage of the limiter circuit 52 relative to ground, nor does it become less than the (negative) on-voltage of the limiter circuit 52. Therefore, the application of an overvoltage between node Y and ground can be avoided, and deterioration of the structure between the gate terminal g1 and source terminal s1 of FET 11 can be suppressed.

[0048] Furthermore, if an overvoltage (high input) is applied to the input terminal 101, diodes 511 and 512 may become conductive, while diodes 521 and 522 may remain non-conductive.

[0049] Figure 4 shows the voltage V when an overvoltage is applied to the amplifier circuit according to Example 1 and the Comparative Example. GD This is a graph showing the waveform. The amplification circuit in the comparative example differs from the amplification circuit 1 in Example 1 only in that the limiter circuit 51 is not present.

[0050] Figure 4 shows the voltage V when an overvoltage (strong input: 25 dBm) is applied to the input terminal 101. GD The waveform is shown. In the comparative example amplifier circuit, the voltage V GD While the voltage amplitude is 4.0V (2.4V to -1.6V), in the amplifier circuit 1 according to Example 1, the voltage V GD The voltage amplitude is limited to 2.8V (1.9V to -0.9V). In other words, the limiter circuit 51 prevents overvoltage from being applied between node Y and node X. Therefore, the amplifier circuit 1 according to Example 1 can suppress the deterioration of the structure between the gate terminal g1 and the drain terminal d1 of the FET 11 compared to the amplifier circuit according to the comparative example.

[0051] The on-voltages of diodes 511 and 512 may be greater than the on-voltages of diodes 521 and 522.

[0052] If diodes 511, 512, 521, and 522 are each composed of multiple diode elements connected in series, then diodes 511 and 512 have a higher on-voltage than diodes 521 and 522. This means that diodes 511 and 512 have a larger number of diode elements connected in series than diodes 521 and 522. Therefore, diodes 511 and 512 can have a smaller capacitance value than diodes 521 and 522. Thus, the capacitance added between the gate terminal g1 and the drain terminal d1 of FET11 can be reduced, thereby suppressing the degradation of the amplification characteristics of FET11.

[0053] Furthermore, the on-voltages of diodes 511 and 512 may be less than or equal to the on-voltages of diodes 521 and 522. In this case, when an overvoltage is applied to the input terminal 101, the limiter circuit 51 will turn on first, followed by the limiter circuit 52.

[0054] In addition, the limiter circuit 52 may be omitted in the amplifier circuit 1 according to this embodiment.

[0055] [2. Configuration of the Amplifier Circuit 2 in Example 2] The circuit configuration of the amplifier circuit 2 according to Embodiment 2 will be described with reference to Figure 5. Figure 5 is a circuit diagram of the amplifier circuit 2 according to Embodiment 2. As shown in the figure, the amplifier circuit 2 includes an input terminal 101, an output terminal 102, FETs 11 and 12, limiter circuits 52 and 53, an LCR parallel resonant circuit 30, capacitors 21, 22 and 23, an inductor 24, resistors 25 and 26, and bias terminals 103 and 104. The amplifier circuit 2 according to this embodiment differs from the amplifier circuit 1 according to Embodiment 1 in that a limiter circuit 53 is placed in place of the limiter circuit 51. Therefore, in the following description of the amplifier circuit 2 according to this embodiment, the same configuration as the amplifier circuit 1 according to Embodiment 1 will be omitted, and the different configurations will be described in detail.

[0056] The limiter circuit 53 includes diodes 531 and 532. Diode 531 is an example of a first diode and has a first anode terminal and a first cathode terminal. Diode 532 is an example of a second diode and has a second anode terminal and a second cathode terminal. The first anode terminal and the second cathode terminal are connected to node Y on a first path connecting the input terminal 101 and the gate terminal g1. The second anode terminal and the first cathode terminal are connected to the gate terminal g2.

[0057] Diode 531 has a first threshold voltage, and when the voltage at node Y relative to the gate terminal g2 becomes greater than or equal to the first threshold voltage (first on-voltage), current flows from the first anode terminal to the first cathode terminal, and the voltage at node Y relative to the gate terminal g2 does not exceed the first threshold voltage (is limited by the first threshold voltage). Diode 532 has a second threshold voltage, and when the voltage at gate terminal g2 relative to node Y becomes greater than or equal to the second threshold voltage (second on-voltage), current flows from the second anode terminal to the second cathode terminal, and the voltage at gate terminal g2 relative to node Y does not exceed the second threshold voltage (is limited by the second threshold voltage). In this embodiment, the first threshold voltage and the second threshold voltage are the same value (denoted as on-voltage), but the first threshold voltage and the second threshold voltage may be different.

[0058] According to the limiter circuit 53, when an overvoltage is applied to the input terminal 101, it is possible to prevent the voltage amplitude between gate terminal g1 and gate terminal g2 from becoming larger than the on-voltage. In other words, the voltage amplitude between gate terminal g1 and gate terminal g2 can always be kept below the on-voltage.

[0059] Furthermore, diode 531 may have a configuration in which multiple first diode elements are connected in series. In this case, the first ON voltage of diode 531 is the sum of the threshold voltages of the multiple first diode elements. Also, the first anode terminal of diode 531 is the anode terminal of the first diode element connected to node Y among the multiple first diode elements, and the first cathode terminal of diode 531 is the cathode terminal of the first diode element connected to gate terminal g2 among the multiple first diode elements.

[0060] Furthermore, diode 532 may have a configuration in which multiple second diode elements are connected in series. In this case, the second ON voltage of diode 532 is the sum of the threshold voltages of the multiple second diode elements. Also, the second anode terminal of diode 532 is the anode terminal of the second diode element connected to the gate terminal g2 among the multiple second diode elements, and the second cathode terminal of diode 532 is the cathode terminal of the second diode element connected to node Y among the multiple second diode elements.

[0061] Furthermore, since the limiter circuit 53 becomes a capacitive circuit during normal operation when no overvoltage is flowing, the closer it is placed to the gate terminal g1, the more likely it is to degrade the amplification characteristics of the FET 11. From this perspective, when the capacitor 21 is placed in the first path, it is preferable that the node Y to which the limiter circuit 53 is connected be placed in the path between the input terminal 101 and the capacitor 21, rather than in the path between the capacitor 21 and the gate terminal g1.

[0062] According to the amplifier circuit 2 of this embodiment, by connecting the limiter circuit 53 between node Y and gate terminal g2, the operation of FET 12 is suppressed by limiting the bias voltage of gate terminal g2 when an overvoltage is applied to the input terminal 101. As a result, the voltage amplitude of node X is limited, and the voltage between gate terminal g1 and drain terminal d1 (V GD This can suppress the rapid increase in () and also, even when the impedance of node Y is low, the limiter circuit 53 operates based on the magnitude of the voltage between node Y and gate terminal g2, so the voltage V GD This can curb the sharp increase.

[0063] The configuration in which the limiter circuit 53 is connected to the gate terminal g2 is due to the fact that the amplification circuit 2 is a cascode amplifier, and node X undergoes voltage fluctuations along with the high-frequency signal.

[0064] Figure 6 is a circuit diagram showing the state when an overvoltage is applied to the amplifier circuit 2 according to Embodiment 2. When an overvoltage (strong input) is applied to the input terminal 101, diodes 531 and 532 become conductive, and a current corresponding to the overvoltage flows between the gate terminal g2 and node Y, and this current flows to ground via capacitor 22. As a result, the potential of the gate terminal g2 does not become greater than the (positive) on-voltage of the limiter circuit 53 relative to the potential of node Y, and does not become smaller than the (negative) on-voltage of the limiter circuit 53 relative to the potential of node Y. In other words, since the DC level voltage of the gate terminal g2 becomes less than or equal to the on-voltage, the FET 12 does not operate, and the voltage amplitude at node X becomes extremely small. Therefore, it is possible to avoid applying an overvoltage between node Y and node X, and to suppress deterioration of the structure between the gate terminal g1 and drain terminal d1 of the FET 11. Furthermore, even when the impedance of node Y is low, the limiter circuit 53 operates based on the magnitude of the voltage between node Y and gate terminal g2, so the voltage V GD This can curb the sharp increase.

[0065] Furthermore, if an overvoltage (high input) is applied to the input terminal 101, diodes 531 and 532 may become conductive, while diodes 521 and 522 may remain non-conductive.

[0066] Note that the on-voltages of diodes 531 and 532 may be greater than the on-voltages of diodes 521 and 522.

[0067] If diodes 531, 532, 521, and 522 are each composed of multiple diode elements connected in series, then diodes 531 and 532 have a higher on-voltage than diodes 521 and 522. Therefore, diodes 531 and 532 have a larger number of diode elements connected in series than diodes 521 and 522. As a result, diodes 531 and 532 can have a smaller capacitance value than diodes 521 and 522. Thus, the capacitance added between gate terminal g1 and gate terminal g2 can be reduced, thereby suppressing the degradation of the amplification characteristics of FETs 11 and 12.

[0068] Furthermore, the on-voltages of diodes 531 and 532 may be less than or equal to the on-voltages of diodes 521 and 522. In this case, when an overvoltage is applied to the input terminal 101, the limiter circuit 53 will turn on first, followed by the limiter circuit 52.

[0069] In addition, the limiter circuit 52 may be omitted in the amplifier circuit 2 according to this embodiment.

[0070] [3 Effects, etc.] As described above, the amplifier circuit 1 according to Embodiment 1 comprises an input terminal 101 and an output terminal 102, an FET 11 having a gate terminal g1, a drain terminal d1 and a source terminal s1, an FET 12 having a gate terminal g2, a drain terminal d2 and a source terminal s2, a diode 511 having a first anode terminal and a first cathode terminal, and a diode 512 having a second anode terminal and a second cathode terminal. The gate terminal g1 is connected to the input terminal 101, the drain terminal d1 is connected to the source terminal s2, the drain terminal d2 is connected to the output terminal 102, the first anode terminal and the second cathode terminal are connected to a first path connecting the input terminal 101 and the gate terminal g1, and the second anode terminal and the first cathode terminal are connected to the drain terminal d1.

[0071] According to this, by connecting a limiter circuit 51 having diodes 511 and 512 between the first path and the drain terminal d1, the voltage amplitude at the drain terminal d1 (node ​​X) is limited when an overvoltage is applied to the input terminal 101, thereby limiting the voltage between the gate terminal g1 and the drain terminal d1 (V GD This can suppress the rapid increase in voltage V. Also, even if the impedance at the connection point (node ​​Y) between the limiter circuit 51 and the first path is low, the limiter circuit 51 operates based on the magnitude of the voltage between node Y and drain terminal d1, so the voltage V GD This can suppress the rapid increase in overvoltage input. Therefore, a cascode-connected amplifier circuit 1 with suppressed overvoltage input can be provided.

[0072] Furthermore, the amplification circuit 2 according to Embodiment 2 comprises an input terminal 101 and an output terminal 102, an FET 11 having a gate terminal g1, a drain terminal d1, and a source terminal s1, an FET 12 having a gate terminal g2, a drain terminal d2, and a source terminal s2, a diode 531 having a first anode terminal and a first cathode terminal, and a diode 532 having a second anode terminal and a second cathode terminal. The gate terminal g1 is connected to the input terminal 101, the drain terminal d1 is connected to the source terminal s2, the drain terminal d2 is connected to the output terminal 102, the first anode terminal and the second cathode terminal are connected to a first path connecting the input terminal 101 and the gate terminal g1, and the second anode terminal and the first cathode terminal are connected to the gate terminal g2.

[0073] According to this, by connecting a limiter circuit 53 having diodes 531 and 532 between the first path and the gate terminal g2, the operation of the FET 12 is suppressed by limiting the bias voltage of the gate terminal g2 when an overvoltage is applied to the input terminal 101. As a result, the voltage amplitude of node X is limited, and the voltage V GD This can suppress the sudden increase in voltage. Also, even when the impedance of node Y is low, the limiter circuit 53 operates based on the magnitude of the voltage between node Y and gate terminal g2, so the voltage V GD This can suppress the rapid increase in overvoltage input. Therefore, a cascode-connected amplifier circuit 2 with suppressed overvoltage input can be provided.

[0074] For example, the amplification circuit 1(2) further includes a capacitor 21 arranged in series with the first path, and the first anode terminal and the second cathode terminal are connected to the path between the input terminal 101 and the capacitor 21 of the first path.

[0075] The limiter circuit 51(53) becomes a capacitive circuit during normal operation when no overvoltage is flowing in, so the closer it is placed to the gate terminal g1, the more likely it is to degrade the amplification characteristics of the FET 11. Therefore, since the limiter circuit 51(53) is connected to the path between the input terminal 101 and the capacitor 21, it can suppress the input of overvoltage without degrading the amplification characteristics of the FET 11.

[0076] For example, the amplifier circuit 1(2) further includes a diode 521 having a third anode terminal and a third cathode terminal, and a diode 522 having a fourth anode terminal and a fourth cathode terminal, the third anode terminal and the fourth cathode terminal being connected to a first path, and the fourth anode terminal and the third cathode terminal being connected to ground.

[0077] According to this, the potential of node Y will not be greater than the (positive) on-voltage of the limiter circuit 52 having diodes 521 and 522 relative to ground, nor will it be less than the (negative) on-voltage of the limiter circuit 52. Therefore, it is possible to avoid applying an overvoltage between node Y and ground, and to suppress the deterioration of the structure between the gate terminal g1 and source terminal s1 of FET 11.

[0078] For example, the amplification circuit 1(2) further includes a capacitor 21 arranged in series with the first path, and the first anode terminal, second cathode terminal, third anode terminal, and fourth cathode terminal are connected to the path between the input terminal 101 and the capacitor 21 of the first path.

[0079] Since the limiter circuits 51(53) and 52 become capacitive circuits during normal operation when no overvoltage is flowing, the closer they are to the gate terminal g1, the more likely they are to degrade the amplification characteristics of the FET 11. Therefore, since the limiter circuits 51(53) and 52 are connected to the path between the input terminal 101 and the capacitor 21, the input of overvoltage can be suppressed without degrading the amplification characteristics of the FET 11.

[0080] For example, the amplification circuit 1(2) further includes a bias terminal 103 connected to the path between the capacitor 21 and the gate terminal g1 of the first path.

[0081] According to this, a capacitor 21 is placed between the bias terminal 103 and node Y to which the limiter circuits 51 (53) and 52 are connected, so that the bias terminal 103 and node Y can be DC-isolated.

[0082] For example, the amplifier circuit 1(2) further includes a capacitor 22 connected between the gate terminal g2 and ground, and a bias terminal 104 connected to a second path connecting the gate terminal g2 and the capacitor 22.

[0083] According to this, FET12 functions as a common-gate type FET, and by placing capacitor 22 between the gate terminal g2 and ground, a bias voltage can be supplied from bias terminal 104 to gate terminal g2 while the gate terminal g2 is connected to high-frequency ground.

[0084] For example, in amplifier circuit 1(2), the on-voltages of diodes 511(531) and 512(532) are greater than the on-voltages of diodes 521 and 522.

[0085] According to this, if diodes 511(531), 512(532), 521, and 522 are each composed of multiple diode elements connected in series, then diodes 511(531) and 512(532) will have a larger number of diode elements connected in series than diodes 521 and 522. Therefore, the capacitance values ​​of diodes 511(531) and 512(532) will be smaller than those of diodes 521 and 522. Thus, the capacitance added between the gate terminal g1 and the drain terminal d1 of FET11 can be reduced, thereby suppressing the degradation of the amplification characteristics of FET11.

[0086] For example, in amplifier circuit 1(2), the on-voltages of diodes 511(531) and 512(532) are less than or equal to the on-voltages of diodes 521 and 522.

[0087] According to this, when an overvoltage is applied to the input terminal 101, the limiter circuit 51 (53) is turned on first, and then the limiter circuit 52 is turned on.

[0088] For example, the amplification circuit 1(2) further includes an LCR parallel resonant circuit 30 connected between the power supply terminal and the drain terminal d2.

[0089] According to this, by adjusting the resonant frequency of the LCR parallel resonant circuit 30 to be near the frequency of the high-frequency signal transmitted by the amplification circuit 1(2), leakage of the high-frequency signal to the power supply terminal side can be suppressed.

[0090] (Other embodiments) The amplification circuit according to the present invention has been described above based on examples, but the amplification circuit according to the present invention is not limited to the above examples. Other embodiments realized by combining any of the components in the above examples, modified examples obtained by applying various modifications to the above examples that a person skilled in the art can conceive of without departing from the spirit of the present invention, and various devices incorporating the above amplification circuit are also included in the present invention.

[0091] For example, in the circuit configuration of the amplification circuit according to the above embodiment, other circuit elements and wiring may be inserted between the paths connecting each circuit element and signal path disclosed in the drawing.

[0092] The characteristics of the amplification circuit described based on the above embodiment are shown below.

[0093] <1> Input terminals and output terminals, A first FET having a first gate terminal, a first drain terminal, and a first source terminal, A second FET having a second gate terminal, a second drain terminal, and a second source terminal, A first diode having a first anode terminal and a first cathode terminal, A second diode having a second anode terminal and a second cathode terminal, The first gate terminal is connected to the input terminal, The first drain terminal is connected to the second source terminal, The second drain terminal is connected to the output terminal. The first anode terminal and the second cathode terminal are connected to a first path connecting the input terminal and the first gate terminal. An amplifier circuit in which the second anode terminal and the first cathode terminal are connected to the first drain terminal.

[0094] <2> Input terminals and output terminals, A first FET having a first gate terminal, a first drain terminal, and a first source terminal, A second FET having a second gate terminal, a second drain terminal, and a second source terminal, A first diode having a first anode terminal and a first cathode terminal, A second diode having a second anode terminal and a second cathode terminal, The first gate terminal is connected to the input terminal, The first drain terminal is connected to the second source terminal, The second drain terminal is connected to the output terminal. The first anode terminal and the second cathode terminal are connected to a first path connecting the input terminal and the first gate terminal. An amplifier circuit in which the second anode terminal and the first cathode terminal are connected to the second gate terminal.

[0095] <3> moreover, The first path includes a first capacitor arranged in series with the first path, The first anode terminal and the second cathode terminal are connected to the path between the input terminal and the first capacitor in the first path. <1> or <2> The amplification circuit described above.

[0096] <4> moreover, A third diode having a third anode terminal and a third cathode terminal, A fourth diode having a fourth anode terminal and a fourth cathode terminal, The third anode terminal and the fourth cathode terminal are connected to the first path. The fourth anode terminal and the third cathode terminal are connected to ground. <1> or <2> The amplification circuit described above.

[0097] <5> moreover, The first path includes a first capacitor arranged in series with the first path, The first anode terminal, the second cathode terminal, the third anode terminal, and the fourth cathode terminal are connected to the path between the input terminal and the first capacitor in the first path. <4> The amplification circuit described above.

[0098] <6> moreover, The first bias terminal is connected to the path between the first capacitor and the first gate terminal of the first path, <5> The amplification circuit described above.

[0099] <7> moreover, A second capacitor connected between the second gate terminal and ground, It includes a second bias terminal connected to a second path connecting the second gate terminal and the second capacitor, <6> The amplification circuit described above.

[0100] <8> The on-voltages of the first and second diodes are greater than the on-voltages of the third and fourth diodes. <4> ~ <7> An amplification circuit as described in any of the following.

[0101] <9> The on-voltages of the first and second diodes are less than or equal to the on-voltages of the third and fourth diodes. <4> ~ <7> An amplification circuit as described in any of the following.

[0102] <10> moreover, It includes an LCR parallel resonant circuit connected between the power terminal and the second drain terminal. <1> ~ <10> An amplification circuit as described in any of the following. [Industrial applicability]

[0103] This invention can be widely used in communication devices such as mobile phones as a power amplification circuit placed in the front-end section of a multiband-compatible device. [Explanation of Symbols]

[0104] 1, 2 Amplifier circuits 11, 12 FETs 21, 22, 23, 31 Capacitors 24, 32 inductors 25, 26, 33 Resistor elements 30 LCR parallel resonant circuit 51, 52, 53 Limiter Circuit 101 Input Terminals 102 Output terminals 103, 104 Bias terminals 511, 512, 521, 522, 531, 532 diodes

Claims

1. Input terminals and output terminals, A first FET having a first gate terminal, a first drain terminal, and a first source terminal, A second FET having a second gate terminal, a second drain terminal, and a second source terminal, A first diode having a first anode terminal and a first cathode terminal, A second diode having a second anode terminal and a second cathode terminal, The first gate terminal is connected to the input terminal, The first drain terminal is connected to the second source terminal, The second drain terminal is connected to the output terminal. The first anode terminal and the second cathode terminal are connected to a first path connecting the input terminal and the first gate terminal. The second anode terminal and the first cathode terminal are connected to the first drain terminal. Amplifier circuit.

2. Input terminals and output terminals, A first FET having a first gate terminal, a first drain terminal, and a first source terminal, A second FET having a second gate terminal, a second drain terminal, and a second source terminal, A first diode having a first anode terminal and a first cathode terminal, A second diode having a second anode terminal and a second cathode terminal, The first gate terminal is connected to the input terminal, The first drain terminal is connected to the second source terminal, The second drain terminal is connected to the output terminal. The first anode terminal and the second cathode terminal are connected to a first path connecting the input terminal and the first gate terminal. The second anode terminal and the first cathode terminal are connected to the second gate terminal. Amplifier circuit.

3. moreover, The first path includes a first capacitor arranged in series, The first anode terminal and the second cathode terminal are connected to the path between the input terminal and the first capacitor in the first path. The amplification circuit according to claim 1 or 2.

4. moreover, A third diode having a third anode terminal and a third cathode terminal, A fourth diode having a fourth anode terminal and a fourth cathode terminal, The third anode terminal and the fourth cathode terminal are connected to the first path. The fourth anode terminal and the third cathode terminal are connected to ground. The amplification circuit according to claim 1 or 2.

5. moreover, The first path includes a first capacitor arranged in series, The first anode terminal, the second cathode terminal, the third anode terminal, and the fourth cathode terminal are connected to the path between the input terminal and the first capacitor in the first path. The amplification circuit according to claim 4.

6. moreover, It includes a first bias terminal connected to the path between the first capacitor and the first gate terminal of the first path, The amplification circuit according to claim 5.

7. moreover, A second capacitor connected between the second gate terminal and ground, It includes a second bias terminal connected to a second path connecting the second gate terminal and the second capacitor, The amplification circuit according to claim 6.

8. The on-voltages of the first and second diodes are greater than the on-voltages of the third and fourth diodes. The amplification circuit according to claim 4.

9. The on-voltages of the first and second diodes are less than or equal to the on-voltages of the third and fourth diodes. The amplification circuit according to claim 4.

10. moreover, It includes an LCR parallel resonant circuit connected between the power terminal and the second drain terminal. The amplification circuit according to claim 1 or 2.

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