Oscillator circuit

Abstract

In an oscillator circuit with a ring oscillator, the waiting time associated with frequency switching is reduced. [Solution] The oscillation circuit 10 includes a plurality of inverters 12A to 12E coupled in a ring shape, a clock generation circuit 13 that generates a clock signal CK0 by cyclically selecting the output signals S1 to S5 of each of the plurality of inverters 12A to 12E, and an oscillation signal S that is synchronized with the clock signal CK0 and has a frequency different from the frequencies of the output signals S1 to S5 of each of the plurality of inverters 12A to 12E. OSC It includes an output circuit 14 that outputs a signal.

Description

[Technical Field]

[0001] The disclosed technology relates to oscillator circuits. [Background technology]

[0002] The following technologies are known regarding oscillation circuits having a ring oscillator. For example, Patent Document 1 describes a semiconductor integrated circuit device that incorporates a pulse generation circuit which forms an internal pulse signal with a desired duty cycle, and includes a PLL circuit that includes a ring oscillator consisting of odd-numbered delay circuits with a CMOS inverter circuit as one delay circuit, a selector that selectively outputs the output signals of each delay circuit, and a logic circuit that receives the output signal of the selector and the oscillation output of the ring oscillator. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 9-246920

[0004] [overview] A ring oscillator is composed of multiple inverters coupled in a ring shape. One way to vary the frequency of the output signal of an oscillator circuit having a ring oscillator is to vary the number of inverters that make up the ring oscillator. Another method is to vary the gain of each inverter by varying the magnitude of the current supplied to each inverter that makes up the ring oscillator. However, with these methods, a relatively long waiting time is required from the start of frequency switching until the frequency stabilizes.

[0005] The disclosed technology aims to reduce the waiting time associated with frequency switching in an oscillator circuit having a ring oscillator.

[0006] The oscillation circuit according to the disclosed technology includes a plurality of inverters connected in a ring, a clock generation circuit that generates a clock signal by cyclically selecting the output signals of each of the plurality of inverters, and an output circuit that outputs an oscillation signal having a frequency different from the frequency of the output signal of each of the plurality of inverters and synchronized with the clock signal.

Brief Description of the Drawings

[0007] [Figure 1] FIG. 1 is a circuit block diagram showing an example of the configuration of an oscillation circuit according to an embodiment of the disclosed technology. [Figure 2] FIG. 2 is a circuit block diagram showing an example of a more detailed configuration of a clock generation circuit and an output circuit according to an embodiment of the disclosed technology. [Figure 3] FIG. 3 is a diagram showing an example of a truth table of a selector according to an embodiment of the disclosed technology. [Figure 4] FIG. 4 is a time chart showing an example of the operation of an oscillation circuit according to an embodiment of the disclosed technology. [Figure 5] FIG. 5 is a time chart showing an example of the operation of an oscillation circuit according to an embodiment of the disclosed technology. [Figure 6A] FIG. 6A is a circuit block diagram showing an example of the output form of a signal in an oscillation circuit according to an embodiment of the disclosed technology. [Figure 6B] FIG. 6B is a circuit block diagram showing an example of the output form of a signal in an oscillation circuit according to an embodiment of the disclosed technology. [Figure 7] FIG. 7 is a circuit block diagram showing an example of the configuration of an oscillation circuit according to another embodiment of the disclosed technology. [Figure 8] FIG. 8 is a circuit block diagram showing an example of a more detailed configuration of a clock generation circuit and an output circuit according to an embodiment of the disclosed technology. [Figure 9] A diagram showing an example of a truth table of a selector according to an embodiment of the disclosed technology. [Figure 10] FIG. 10 is a time chart showing an example of the operation of an oscillation circuit according to an embodiment of the disclosed technology. [Figure 11] Figure 11 is a time chart showing an example of the operation of an oscillator circuit according to an embodiment of the disclosed technology. [Detailed description]

[0008] The embodiments of the disclosed technology will be described below with reference to the drawings. In each drawing, substantially identical or equivalent components or parts are given the same reference numerals.

[0009] [First Embodiment] Figure 1 is a circuit block diagram showing an example of the configuration of an oscillator circuit 10 according to an embodiment of the disclosed technology. The oscillator circuit 10 includes a ring oscillator 11, a clock generation circuit 13, and an output circuit 14. The ring oscillator 11 has a plurality of inverters coupled in a ring shape. The number of inverters constituting the ring oscillator 11 is odd. The output terminal of each inverter is connected to the input terminal of the next stage inverter. The output terminal of the final stage inverter is connected to the input terminal of the first stage inverter. Figure 1 illustrates a configuration in which the ring oscillator 11 has five inverters 12A, 12B, 12C, 12D, and 12E. Note that the number of inverters in the ring oscillator 11 is not particularly limited, as long as it is odd.

[0010] The first-stage inverter 12A outputs output signal S1, which is the inverted logic of output signal S5 of the fifth-stage inverter 12E. Output signal S1 is supplied to the second-stage inverter 12B. The second-stage inverter 12B outputs output signal S2, which is the inverted logic of output signal S1. Output signal S2 is supplied to the third-stage inverter 12C. The third-stage inverter 12C outputs output signal S3, which is the inverted logic of output signal S2. Output signal S3 is supplied to the fourth-stage inverter 12D. The fourth-stage inverter 12D outputs output signal S4, which is the inverted logic of output signal S3. Output signal S4 is supplied to the fifth-stage inverter 12E. The fifth-stage inverter 12E outputs output signal S5, which is the inverted logic of output signal S4. Output signal S5 is supplied to the first-stage inverter 12A.

[0011] Inverters 12A to 12E each function as delay elements. After a finite delay time has elapsed from the input to the first-stage inverter 12A, the fifth-stage inverter 12E outputs the logical negation of the input to the first-stage inverter 12A, which is then input back to the first-stage inverter 12A. As this process is repeated, output signals S1 to S5 each oscillate. The output signals S1 to S5 from inverters 12A to 12E are each supplied to the clock generation circuit 13.

[0012] The clock generation circuit 13 generates a clock signal CK0 with a frequency different from the frequencies of the output signals S1 to S5 by cyclically selecting (extracting) the respective output signals S1 to S5 of the inverters 12A to 12E. In the clock generation circuit 13, the selection order of the output signals S1 to S5 is switchable. The clock generation circuit 13 uses control signal S CTL The selection order of output signals S1 to S5 is switched accordingly. Switching the selection order of output signals S1 to S5 switches the frequency of clock signal CK0. Clock signal CK0 is supplied to output circuit 14.

[0013] The output circuit 14 outputs an oscillation signal S synchronized with the clock signal CK0. OSC This generates the oscillation signal S OSC This is output as the output signal of the oscillation circuit 10. As the selection order of output signals S1 to S5 in the clock generation circuit 13 is switched, the frequency of the clock signal CK0 is switched, and the oscillation signal S OSC The frequency switches. Oscillation signal S OSC The frequency is a non-integer multiple (e.g., 5 / 4 or 5 / 6) of the oscillation frequency of the ring oscillator 11 (the frequency of the output signals S1 to S5).

[0014] Figure 2 is a circuit block diagram showing a more detailed example of the configuration of the clock generation circuit 13 and the output circuit 14. The clock generation circuit 13 includes a counter 20 and a selector 21.

[0015] Counter 20 outputs a count value obtained by counting the number of pulses of the clock signal CK0. The count value is output as a 3-bit digital value. C0 is the first bit (LSB: Least Significant Bit) of the count value, C1 is the second bit of the count value, and C2 is the third bit (MSB: Most Significant Bit) of the count value.

[0016] The counter 20 receives a control signal S supplied from an external source. CTL The count mode is switched accordingly. In the first count mode, counter 20 performs a countdown operation. Specifically, it outputs the count value of the number of pulses of the clock signal CK0 in the order of "100", "011", "010", "001", and "000". The count value after "000" returns to "100". In the second count mode, counter 20 performs a count-up operation. Specifically, it outputs the count value of the number of pulses of the clock signal CK0 in the order of "000", "001", "010", "011", and "100". The count value after "100" returns to "000".

[0017] The selector 21 selects one of the output signals S1 to S5 of the inverters 12A to 12E according to the count value of the counter 20. The clock generation circuit 13 is configured such that the output signal selected by the selector 21 passes through the output node n1 of the clock signal CK0. Specifically, the selector 21 has a plurality of switches SW1, SW2, SW3, SW4, SW5 provided between the output terminals of the inverters 12A to 12E and the output node n1 of the clock signal CK0. Switches SW1 to SW5 are selectively turned ON according to the count value of the counter 20.

[0018] Figure 3 is a diagram showing an example of the truth table of selector 21. When the count value of counter 20 is "000", SW1 is in the ON state, and the output signal S1 of inverter 12A passes through the output node n1 of clock signal CK0. When the count value of counter 20 is "001", SW2 is in the ON state, and the output signal S2 of inverter 12B passes through the output node n1 of clock signal CK0. When the count value of counter 20 is "010", SW3 is in the ON state, and the output signal S3 of inverter 12C passes through the output node n1 of clock signal CK0. When the count value of counter 20 is "011", SW4 is in the ON state, and the output signal S4 of inverter 12D passes through the output node n1 of clock signal CK0. When the count value of counter 20 is "100", SW5 is in the ON state, and the output signal S5 of inverter 12E passes through the output node n1 of clock signal CK0.

[0019] The output circuit 14 is configured to include flip - flop 22. The clock signal CK0 is input to the clock input terminal of flip - flop 22. The data input terminal (D) is connected to the inverted output terminal (Q bar). The oscillation signal S OSC is output from the output terminal (Q). Flip - flop 22 performs a toggle operation that inverts the logic of its output signal, the oscillation signal S OSC every time the clock signal CK0 rises.

[0020] Figures 4 and 5 are time charts showing an example of the operation of the oscillation circuit 10. Figure 4 shows the case where counter 20 operates in the first count mode, and Figure 5 shows the case where counter 20 operates in the second count mode. In Figures 4 and 5, the waveforms of the output signals S1 - S5 of each of inverters 12A - 12E, the clock signal CK0, and the oscillation signal S OSC are shown. In Figures 4 and 5, the horizontal axis represents time.

[0021] Output signal S2 is the logical inverted signal of output signal S1, and its phase lags behind output signal S1 by 1 / 5 of a period. Output signal S3 is the logical inverted signal of output signal S2, and its phase lags behind output signal S2 by 1 / 5 of a period. Output signal S4 is the logical inverted signal of output signal S3, and its phase lags behind output signal S3 by 1 / 5 of a period. Output signal S5 is the logical inverted signal of output signal S4, and its phase lags behind output signal S4 by 1 / 5 of a period.

[0022] In the first counting mode, counter 20 performs a countdown operation. That is, after reset, counter 20 outputs a count value of "100". This turns on switch SW5 of selector 21, and the output signal S5 of inverter 12E is selected. Output signal S5 passes through output node n1 of clock signal CK0. The first pulse of clock signal CK0 is generated as output signal S5 rises.

[0023] As the first pulse of the clock signal CK0 is generated, the counter 20 outputs a count value of "011". This turns on the switch SW4 of the selector 21, and the output signal S4 of the inverter 12D is selected. The output signal S4 passes through the output node n1 of the clock signal CK0. As the rising edge of the output signal S4 occurs, the second pulse of the clock signal CK0 is generated.

[0024] As the second pulse of the clock signal CK0 occurs, the counter 20 outputs a count value of "010". This turns on the switch SW3 of the selector 21, and the output signal S3 of the inverter 12C is selected. The output signal S3 passes through the output node n1 of the clock signal CK0. As the rising edge of the output signal S3 occurs, the third pulse of the clock signal CK0 is generated.

[0025] As the third pulse of the clock signal CK0 occurs, the counter 20 outputs a count value of "001". This turns on the switch SW2 of the selector 21, and the output signal S2 of the inverter 12B is selected. The output signal S2 passes through the output node n1 of the clock signal CK0. As the rising edge of the output signal S2 occurs, the fourth pulse of the clock signal CK0 is generated.

[0026] As the fourth pulse of the clock signal CK0 occurs, the counter 20 outputs a count value of "000". This turns on the switch SW1 of the selector 21, and the output signal S1 of the inverter 12A is selected. The output signal S1 passes through the output node n1 of the clock signal CK0. As the rising edge of the output signal S1 occurs, the fifth pulse of the clock signal CK0 is generated.

[0027] In the clock generation circuit 13, the above operation is repeated. In this way, the counter 20 receives the control signal S CTL When operating in the first count mode accordingly (see Figure 4), the counter 20 performs a countdown operation, and the output signals S1 to S5 of inverters 12A to 12E pass through the output node n1 of the clock signal CK0 in the order S5, S4, S3, S2, S1, S5, ... The clock signal CK0 is a signal that generates a rising edge at each point in time when the output signals S5, S4, S3, S2, and S1 rise in this order.

[0028] The flip-flop 22 that constitutes the output circuit 14 outputs the oscillation signal S, which is its output signal, at each rising edge of the clock signal CK0. OSC This performs a toggle operation that reverses the logic. As a result, the oscillation signal S is output from the output circuit 14. OSC The frequency of this is 5 / 4 times the oscillation frequency of ring oscillator 11.

[0029] Meanwhile, the counter 20 operating in the second counting mode performs a count-up operation. That is, after resetting, the counter 20 outputs a count value of "000". This turns on the switch SW1 of the selector 21, and the output signal S1 of the inverter 12A is selected. The output signal S1 passes through the output node n1 of the clock signal CK0. The first pulse of the clock signal CK0 is generated as the output signal S1 rises.

[0030] As the first pulse of the clock signal CK0 is generated, the counter 20 outputs a count value of "001". This turns on the switch SW2 of the selector 21, and the output signal S2 of the inverter 12B is selected. The output signal S2 passes through the output node n1 of the clock signal CK0. As the rising edge of the output signal S2 is reached, the second pulse of the clock signal CK0 is generated.

[0031] As the second pulse of the clock signal CK0 occurs, the counter 20 outputs a count value of "010". This turns on the switch SW3 of the selector 21, and the output signal S3 of the inverter 12C is selected. The output signal S3 passes through the output node n1 of the clock signal CK0. As the rising edge of the output signal S3 occurs, the third pulse of the clock signal CK0 is generated.

[0032] As the third pulse of the clock signal CK0 occurs, the counter 20 outputs a count value of "011". This turns on the switch SW4 of the selector 21, and the output signal S4 of the inverter 12D is selected. The output signal S4 passes through the output node n1 of the clock signal CK0. As the rising edge of the output signal S4 occurs, the fourth pulse of the clock signal CK0 is generated.

[0033] As the fourth pulse of the clock signal CK0 occurs, the counter 20 outputs a count value of "100". This turns on the switch SW5 of the selector 21, and the output signal S5 of the inverter 12E is selected. The output signal S5 passes through the output node n1 of the clock signal CK0. As the rising edge of the output signal S5 occurs, the fifth pulse of the clock signal CK0 is generated.

[0034] In the clock generation circuit 13, the above operation is repeated. In this way, the counter 20 receives the control signal S CTL When operating in the second count mode accordingly (see Figure 5), the counter 20 performs a count-up operation, and the output signals S1 to S5 of inverters 12A to 12E pass through the output node n1 of the clock signal CK0 in the order S1, S2, S3, S4, S5, S1, ... The clock signal CK0 is a signal that generates a rising edge at each point in time when the output signals S1, S2, S3, S4, and S5 rise in this order.

[0035] The flip-flop 22 that constitutes the output circuit 14 outputs the oscillation signal S, which is its output signal, at each rising edge of the clock signal CK0. OSC This performs a toggle operation that reverses the logic. As a result, the oscillation signal S is output from the output circuit 14. OSC The frequency of this signal is 5 / 6 times the oscillation frequency of the ring oscillator 11 (the frequency of output signals S1 to S5).

[0036] Figures 6A and 6B are circuit block diagrams showing an example of the signal output configuration in the oscillation circuit 10. As shown in Figure 6A, in the oscillation circuit 10, the output signal S5 from the inverter 12E and the oscillation signal S from the output circuit 14 are output. OSC It may be possible to output both. According to the configuration shown in Figure 6A, an output signal S5 with frequency f can be taken from output terminal 16, and an oscillation signal S with frequency 5 / 4f can be taken from output terminal 15. OSC and an oscillation signal S with frequency 5 / 6f OSC It is possible to selectively extract them.

[0037] Furthermore, as shown in Figure 6B, in the oscillation circuit 10, the output signal S5 from the inverter 12E and the oscillation signal S from the output circuit 14 are connected. OSC The output signal S5 has a frequency of f, and the oscillation signal S has a frequency of 5 / 4f. OSC and an oscillation signal S with frequency 5 / 6f OSC This allows for selective extraction. Furthermore, it is possible to use any of the output signals S1 to S4 instead of output signal S5 as the signal with frequency f.

[0038] As described above, the oscillation circuit 10 according to the disclosed technology comprises a plurality of inverters 12A to 12E coupled in a ring shape, a clock generation circuit 13 that generates a clock signal CK0 by cyclically selecting the output signals S1 to S5 of each of the plurality of inverters 12A to 12E, and an oscillation signal S that is synchronized with the clock signal CK0 and has a frequency different from the frequencies of the output signals S1 to S5. OSC It includes an output circuit 14 that outputs a signal.

[0039] According to the oscillator circuit 10 according to an embodiment of the disclosed technology, the oscillator signal S is generated by the clock signal CK0, which is generated by edge extraction of the respective output signals S1 to S5 of the plurality of inverters 12A to 12E. OSC Since the frequency is fixed, it is possible to switch the frequency of the output signal of the oscillation circuit 10 while maintaining a stable oscillation state of the ring oscillator 11. This makes it possible to reduce the waiting time associated with switching frequencies.

[0040] Furthermore, according to the oscillation circuit 10 of this embodiment, the oscillation signal S OSC The frequency of can be a non-integer multiple of the oscillation frequency of the ring oscillator 11. For example, the oscillation signal S OSC The frequency of this can be set to less than 1 or less than 2 times the oscillation frequency of the ring oscillator 11.

[0041] The oscillator circuit 10 according to this embodiment can be applied, for example, to a VCO (Voltage-controlled oscillator) or DCO (Digitally-Controlled Oscillator) block built into a PLL (Phase Locked Loop). For example, by using the output of the oscillator circuit 10 as an output clock whose frequency can be switched in time, spread spectrum can be enabled regardless of the bandwidth of the PLL's open-loop gain.

[0042] [Second Embodiment] Figure 7 is a circuit block diagram showing an example of the configuration of an oscillator circuit 10A according to a second embodiment of the disclosed technology. The oscillator circuit 10A differs from the oscillator circuit 10 according to the first embodiment described above in that the ring oscillator 11 has seven inverters 12A, 12B, 12C, 12D, 12E, 12F, and 12G. The output signals S1 to S7 of inverters 12A to 12G are supplied to a clock generation circuit 13, respectively.

[0043] The clock generation circuit 13 generates a clock signal CK0 with a frequency different from the frequencies of the output signals S1 to S7 by cyclically selecting (extracting) the respective output signals S1 to S7 of the inverters 12A to 12G. In the clock generation circuit 13, the selection order of the output signals S1 to S7 is switchable. The clock generation circuit 13 uses control signal S CTL The selection order of output signals S1 to S7 is switched accordingly. Switching the selection order of output signals S1 to S7 switches the frequency of clock signal CK0. Clock signal CK0 is supplied to output circuit 14.

[0044] The output circuit 14 outputs an oscillation signal S synchronized with the clock signal CK0. OSC This generates the oscillation signal S OSC This is output as the output signal of the oscillation circuit 10A. Oscillation signal S OSC The frequency is a non-integer multiple (e.g., 7 / 6 or 7 / 8) of the oscillation frequency of the ring oscillator 11 (the frequency of the output signals S1 to S7).

[0045] Figure 8 is a circuit block diagram showing a more detailed example of the configuration of the clock generation circuit 13 and the output circuit 14. The clock generation circuit 13 includes a counter 20 and a selector 21.

[0046] Counter 20 outputs a count value obtained by counting the number of pulses of the clock signal CK0. The count value is output as a 3-bit digital value. C0 is the first bit (LSB: Least Significant Bit) of the count value, C1 is the second bit of the count value, and C2 is the third bit (MSB: Most Significant Bit) of the count value.

[0047] The counter 20 receives a control signal S supplied from an external source. CTL The count mode is switched accordingly. In the first count mode, counter 20 performs a countdown operation. Specifically, it counts the pulse count value of the clock signal CK0 in the order of "110", "101", "100", "011", "010", "001", and "000". The count value after "000" returns to "110". In the second count mode, counter 20 performs a count-up operation. Specifically, it counts the pulse count value of the clock signal CK0 in the order of "000", "001", "010", "011", "100", "101", and "110". The count value after "110" returns to "000".

[0048] The selector 21 selects one of the output signals S1 to S7 of the inverters 12A to 12G according to the count value of the counter 20. The clock generation circuit 13 is configured such that the output signal selected by the selector 21 passes through the output node n1 of the clock signal CK0. Specifically, the selector 21 has a plurality of switches SW1, SW2, SW3, SW4, SW5, SW6, SW7 provided between the output terminals of the inverters 12A to 12G and the output node n1 of the clock signal CK0. Switches SW1 to SW7 are selectively turned ON according to the count value of the counter 20.

[0049] Figure 9 shows an example of a truth table for selector 21. When the count value of counter 20 is "101", SW6 is turned on, and the output signal S6 of inverter 12F passes through the output node n1 of clock signal CK0. When the count value of counter 20 is "110", SW7 is turned on, and the output signal S7 of inverter 12G passes through the output node n1 of clock signal CK0. The state of selector 21 when the count value of counter 20 is between "000" and "100" is the same as in the first embodiment described above, so no explanation is given.

[0050] Figures 10 and 11 are time charts showing examples of the operation of the oscillation circuit 10A, respectively. Figure 10 shows the case when the counter 20 operates in the first count mode, and Figure 11 shows the case when the counter 20 operates in the second count mode. Figures 10 and 11 show the output signals S1 to S7 of inverters 12A to 12G, the clock signal CK0, and the oscillation signal S OSC The waveform is shown. In Figures 10 and 11, the horizontal axis represents time.

[0051] In the first counting mode, counter 20 performs a countdown operation. That is, after reset, counter 20 outputs a count value of "110". This turns on switch SW7 of selector 21, and the output signal S7 of inverter 12G is selected. Output signal S7 passes through output node n1 of clock signal CK0. The first pulse of clock signal CK0 is generated as output signal S7 rises.

[0052] As the first pulse of the clock signal CK0 is generated, the counter 20 outputs a count value of "101". This turns on the switch SW6 of the selector 21, and the output signal S6 of the inverter 12F is selected. The output signal S6 passes through the output node n1 of the clock signal CK0. As the rising edge of the output signal S6 occurs, the second pulse of the clock signal CK0 is generated.

[0053] As the second pulse of the clock signal CK0 is generated, the counter 20 outputs a count value of "100". This turns on the switch SW5 of the selector 21, and the output signal S5 of the inverter 12E is selected. The output signal S5 passes through the output node n1 of the clock signal CK0. As the rising edge of the output signal S5 occurs, the third pulse of the clock signal CK0 is generated.

[0054] As the third pulse of the clock signal CK0 occurs, the counter 20 outputs a count value of "011". This turns on the switch SW4 of the selector 21, and the output signal S4 of the inverter 12D is selected. The output signal S4 passes through the output node n1 of the clock signal CK0. As the rising edge of the output signal S4 occurs, the fourth pulse of the clock signal CK0 is generated.

[0055] As the fourth pulse of the clock signal CK0 occurs, the counter 20 outputs a count value of "010". This turns on the switch SW3 of the selector 21, and the output signal S3 of the inverter 12C is selected. The output signal S3 passes through the output node n1 of the clock signal CK0. As the rising edge of the output signal S3 occurs, the fifth pulse of the clock signal CK0 is generated.

[0056] As the fifth pulse of the clock signal CK0 occurs, the counter 20 outputs a count value of "001". This turns on the switch SW2 of the selector 21, and the output signal S2 of the inverter 12B is selected. The output signal S2 passes through the output node n1 of the clock signal CK0. As the rising edge of the output signal S2 occurs, the sixth pulse of the clock signal CK0 is generated.

[0057] As the sixth pulse of the clock signal CK0 occurs, the counter 20 outputs a count value of "000". This turns on the switch SW1 of the selector 21, and the output signal S1 of the inverter 12A is selected. The output signal S1 passes through the output node n1 of the clock signal CK0. As the rising edge of the output signal S1 occurs, the seventh pulse of the clock signal CK0 is generated.

[0058] In the clock generation circuit 13, the above operation is repeated. In this way, the counter 20 receives the control signal S CTL When operating in the first count mode accordingly (see Figure 10), the counter 20 performs a countdown operation, and the output signals S1 to S7 of inverters 12A to 12G pass through the output node n1 of the clock signal CK0 in the order S7, S6, S5, S4, S3, S2, S1, ... The clock signal CK0 is a signal that generates a rising edge at each point in time when the output signals S7, S6, S5, S4, S3, S2, S1 rise in this order.

[0059] The flip-flop 22 that constitutes the output circuit 14 outputs the oscillation signal S, which is its output signal, at each rising edge of the clock signal CK0. OSC This performs a toggle operation that reverses the logic. As a result, the oscillation signal S is output from the output circuit 14. OSC The frequency of this signal is 7 / 6 times the oscillation frequency of ring oscillator 11 (the frequency of output signals S1 to S7).

[0060] Meanwhile, the counter 20 operating in the second counting mode performs a count-up operation. That is, after resetting, the counter 20 outputs a count value of "000". This turns on the switch SW1 of the selector 21, and the output signal S1 of the inverter 12A is selected. The output signal S1 passes through the output node n1 of the clock signal CK0. The first pulse of the clock signal CK0 is generated as the output signal S1 rises.

[0061] As the first pulse of the clock signal CK0 is generated, the counter 20 outputs a count value of "001". This turns on the switch SW2 of the selector 21, and the output signal S2 of the inverter 12B is selected. The output signal S2 passes through the output node n1 of the clock signal CK0. As the rising edge of the output signal S2 is reached, the second pulse of the clock signal CK0 is generated.

[0062] As the second pulse of the clock signal CK0 occurs, the counter 20 outputs a count value of "010". This turns on the switch SW3 of the selector 21, and the output signal S3 of the inverter 12C is selected. The output signal S3 passes through the output node n1 of the clock signal CK0. As the rising edge of the output signal S3 occurs, the third pulse of the clock signal CK0 is generated.

[0063] As the third pulse of the clock signal CK0 occurs, the counter 20 outputs a count value of "011". This turns on the switch SW4 of the selector 21, and the output signal S4 of the inverter 12D is selected. The output signal S4 passes through the output node n1 of the clock signal CK0. As the rising edge of the output signal S4 occurs, the fourth pulse of the clock signal CK0 is generated.

[0064] As the fourth pulse of the clock signal CK0 occurs, the counter 20 outputs a count value of "100". This turns on the switch SW5 of the selector 21, and the output signal S5 of the inverter 12E is selected. The output signal S5 passes through the output node n1 of the clock signal CK0. As the rising edge of the output signal S5 occurs, the fifth pulse of the clock signal CK0 is generated.

[0065] As the fifth pulse of the clock signal CK0 occurs, the counter 20 outputs a count value of "101". This turns on the switch SW6 of the selector 21, and the output signal S6 of the inverter 12F is selected. The output signal S6 passes through the output node n1 of the clock signal CK0. As the rising edge of the output signal S6 occurs, the sixth pulse of the clock signal CK0 is generated.

[0066] As the sixth pulse of the clock signal CK0 occurs, the counter 20 outputs a count value of "110". This turns on the switch SW7 of the selector 21, and the output signal S7 of the inverter 12G is selected. The output signal S7 passes through the output node n1 of the clock signal CK0. As the rising edge of the output signal S7 occurs, the seventh pulse of the clock signal CK0 is generated.

[0067] In the clock generation circuit 13, the above operation is repeated. In this way, the counter 20 receives the control signal S CTL When operating in the second count mode accordingly (see Figure 11), the counter 20 performs a count-up operation, and the output signals S1 to S7 of inverters 12A to 12G pass through the output node n1 of the clock signal CK0 in the order S1, S2, S3, S4, S5, S6, S7, ... The clock signal CK0 is a signal that generates a rising edge at each point in time when the output signals S1, S2, S3, S4, S5, S6, S7 rise in this order.

[0068] The flip-flop 22 that constitutes the output circuit 14 outputs the oscillation signal S, which is its output signal, at each rising edge of the clock signal CK0. OSC This performs a toggle operation that reverses the logic. As a result, the oscillation signal S is output from the output circuit 14. OSC The frequency of this signal is 7 / 8 times the oscillation frequency of the ring oscillator 11 (the frequency of output signals S1 to S7).

[0069] According to the oscillation circuit 10A of the second embodiment, similar to the oscillation circuit 10 of the first embodiment, it is possible to reduce the waiting time associated with switching the frequency of the output signal.

[0070] In the first and second embodiments described above, the oscillation signal S OSC Although an example configuration in which the frequency can be switched has been given, the disclosed technology is not limited to this embodiment. The oscillation signal S output from the output circuit 14 OSC The frequency may be fixed.

[0071] The following additional information is disclosed regarding the embodiments described above. (Note 1) Multiple inverters 12A~12E connected in a ring shape, A clock generation circuit 13 generates a clock signal CK0 by cyclically selecting the output signals S1 to S5 of each of the plurality of inverters 12A to 12E, Oscillation signal S is synchronized with the clock signal CK0 and has a frequency different from the frequencies of the respective output signals S1 to S5 of the plurality of inverters 12A to 12E. OSC An output circuit 14 that outputs, An oscillator circuit 10 including this.

[0072] With the above configuration, it is possible to reduce the waiting time associated with switching the frequency of the output signal of the oscillation circuit 10.

[0073] (Note 2) The oscillation signal S OSC The frequency is a non-integer multiple of the frequencies of the respective output signals S1 to S5 of the plurality of inverters 12A to 12E. The oscillation circuit 10 described in Appendix 1.

[0074] According to the above configuration, for example, the oscillation signal S OSC The frequency can be set to less than 1 or less than 2 times the oscillation frequency of the ring oscillator.

[0075] (Note 3) In the clock generation circuit 13, the selection order of the output signals S1 to S2 of each of the plurality of inverters 12A to 12E can be switched. The oscillation signal S is generated by switching the selection order of the output signals S1 to S5 of each of the plurality of inverters 12A to 12E. OSC The frequency switches. The oscillation circuit described in Appendix 1 or Appendix 2.

[0076] (Note 4) The aforementioned clock generation circuit is A counter 20 that outputs a count value obtained by counting the number of pulses of the clock signal CK0, A selector 21 selects one of the output signals S1 to S5 of each of the plurality of inverters 12A to 12E according to the count value, An oscillator circuit 10 that includes any one of the appendices 1 to 3.

[0077] (Note 5) The clock generation circuit 13 is configured such that the signal selected by the selector 21 from among the output signals S1 to S5 of the plurality of inverters 12A to 12E passes through the output node n1 of the clock signal CK0. The oscillation circuit 10 described in Appendix 4.

[0078] (Note 6) The selector 21 includes a plurality of switches SW1 to SW5 provided between each output terminal of the plurality of inverters 12A to 12E and the output node n1 of the clock signal CK0. The aforementioned switches SW1 to SW5 are selectively turned ON according to the count value. The oscillation circuit 10 described in Appendix 4.

[0079] (Note 7) The output circuit 14 has a flip-flop The oscillation circuit 10 described in any one of the appendices 1 to 6.

[0080] (Note 8) One of the output signals S1 to S5 of each of the plurality of inverters 12A to 12E and the oscillation signal S OSC Both were made capable of outputting. The oscillation circuit 10 described in any one of the appendices 1 to 7.

[0081] (Note 9) One of the output signals S1 to S5 of each of the plurality of inverters 12A to 12E and the oscillation signal S OSC It was made possible to selectively output it. The oscillation circuit 10 described in any one of the appendices 1 to 7. [Explanation of Symbols]

[0082] 10, 10A Oscillator Circuit 11 Ring Oscillator 12A, 12B, 12C, 12D, 12E, 12F, 12G Inverter 13. Clock generation circuit 14 Output Circuit 15, 16 Output terminals 17 Selector 20 counters 21 Selector 22 Flip-flops

Claims

1. Multiple inverters connected in a ring shape, A clock generation circuit that generates a clock signal by cyclically selecting the output signals of each of the aforementioned plurality of inverters, An output circuit that outputs an oscillation signal synchronized with the clock signal and having a frequency different from the frequency of each of the multiple inverters' output signals, An oscillator circuit that includes this component.

2. The frequency of the oscillation signal is a non-integer multiple of the frequency of the output signal of each of the plurality of inverters. The oscillation circuit according to claim 1.

3. In the clock generation circuit, the selection order of the output signals of each of the plurality of inverters can be switched. The frequency of the oscillation signal is switched by switching the selection order of the output signals of each of the plurality of inverters. The oscillation circuit according to claim 1.

4. The aforementioned clock generation circuit is A counter that outputs a count value obtained by counting the number of pulses of the clock signal, A selector that selects one of the output signals of each of the plurality of inverters according to the count value, The oscillator circuit according to claim 1, including the following:

5. The clock generation circuit is configured such that the signal selected by the selector from among the output signals of the plurality of inverters passes through the output node of the clock signal. The oscillator circuit according to claim 4.

6. The selector includes a plurality of switches provided between the output terminals of each of the plurality of inverters and the output node of the clock signal, The aforementioned plurality of switches are selectively turned on according to the count value. The oscillator circuit according to claim 4.

7. The output circuit has a flip-flop The oscillation circuit according to claim 1.

8. Both one of the output signals from each of the plurality of inverters and the oscillation signal are capable of being output. The oscillation circuit according to any one of claims 1 to 7.

9. The output signals of each of the plurality of inverters and the oscillation signal are selectively output. The oscillation circuit according to any one of claims 1 to 7.

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