comparator

Abstract

In a comparator that has the function of supplying a temporary bias current to the differential pair when the output transitions, in addition to a steady bias current, the delay in the timing of the change in the relative magnitudes of the input voltages is suppressed at the timing of generating the temporary bias current. [Solution] The comparator 10 provides a temporary bias current I to the current path of the differential pair, including the input transistors 11 and 12, in accordance with the reversal of the relative magnitudes of the first input voltage V1 and the second input voltage V2 in the fully differential amplifier. B2 The system includes a second current supply circuit 52 that supplies a current. The second current supply circuit includes a first monitor transistor 45 that turns on in response to the voltage at the first node n1, and a second monitor transistor 46 that turns on in response to the voltage at the second node n2 and is connected in series with the first monitor transistor. The second current supply circuit supplies a current generated based on the through-current that occurs when both the first and second monitor transistors are turned on, as a temporary bias current.

Description

Technical Field

[0001] The disclosed technology relates to a comparator.

Background Art

[0002] As technologies related to reducing the power consumption of a comparator, the following technologies are known. For example, Patent Document 1 describes a comparator circuit including a current source that generates a bias current and supplies it to a differential amplifier, a first inverter circuit that inverts a differential voltage from the differential amplifier and outputs an inverted signal, and an adaptive bias current generation circuit. The adaptive bias current generation circuit detects the bias current of the current source, detects the through-current of the first inverter circuit, and based on the detected bias current and the detected through-current, operates the differential amplifier with the bias current during a period when the differential amplifier does not perform a logical determination, and generates an adaptive bias current for operating the differential amplifier using an adaptive bias current obtained by increasing the bias current during a period when the differential amplifier performs a logical determination, and supplies it to the differential amplifier.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] The ideal generation timing of the adaptive bias current is the timing when the magnitude relationship of the input voltages to be compared is switched. However, according to the comparator circuit described in Patent Document 1, the adaptive bias current cannot be generated until the output of the first inverter circuit transitions. Therefore, the generation timing of the adaptive bias current is delayed from the timing when the magnitude relationship of the input voltages is switched. This delay becomes more prominent as the bias current constantly supplied to the differential pair is smaller, so there is also a limit to suppressing the bias current constantly supplied.

[0005] The disclosed technology was developed in view of the above points, and aims to suppress the delay between the timing at which the transient bias current is generated and the timing at which the relative magnitudes of the input voltages are reversed, in a comparator that has the function of supplying a transient bias current to the differential pair when the output transitions, in addition to a steady bias current.

[0006] The comparator relating to the disclosed technology includes a fully differential amplifier having a first input transistor to which a first input voltage to be compared is input, a second input transistor to which a second input voltage to be compared is input, a first load transistor connected to the first input transistor, a second load transistor connected to the second input transistor, and a first current supply circuit that supplies a steady bias current to the current path of the first input transistor and the second input transistor, and a second current supply circuit that supplies a temporary bias current to the current path in accordance with the reversal of the magnitude relationship between the first input voltage and the second input voltage. The second current supply circuit includes a first monitor transistor that turns on in accordance with the voltage of a first node which is the connection point between the first input transistor and the first load transistor, and a second monitor transistor that turns on in accordance with the voltage of a second node which is the connection point between the second input transistor and the second load transistor and is connected in series with the first monitor transistor, and supplies a current generated based on the through-current generated when both the first monitor transistor and the second monitor transistor are turned on as the temporary bias current. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is an equivalent circuit diagram showing an example of the configuration of a comparator according to a first embodiment of the disclosed technology. [Figure 2A] Figure 2A is a waveform diagram obtained by performing an operational simulation on a comparator according to the first embodiment of the disclosed technology. [Figure 2B]Figure 2B is a waveform diagram obtained by performing an operational simulation on a comparator according to the first embodiment of the disclosed technology. [Figure 2C] Figure 2C is a waveform diagram obtained by performing an operational simulation on a comparator according to the first embodiment of the disclosed technology. [Figure 3] Figure 3 is an equivalent circuit diagram showing an example of the comparator configuration for a comparative example. [Figure 4A] Figure 4A is a waveform diagram obtained by performing an operational simulation on the comparator related to the comparative example. [Figure 4B] Figure 4B is a waveform diagram obtained by performing an operational simulation on the comparator related to the comparative example. [Figure 4C] Figure 4C is a waveform diagram obtained by performing an operational simulation on the comparator related to the comparative example. [Figure 5] Figure 5 is an equivalent circuit diagram showing an example of a comparator configuration according to a second embodiment of the disclosed technology. [Figure 6A] Figure 6A is a waveform diagram obtained by performing an operational simulation on a comparator according to a second embodiment of the disclosed technology. [Figure 6B] Figure 6B is a waveform diagram obtained by performing an operational simulation on a comparator according to a second embodiment of the disclosed technology. [Figure 6C] Figure 6C is a waveform diagram obtained by performing an operational simulation on a comparator according to a second embodiment of the disclosed technology. [Figure 7] Figure 7 is an equivalent circuit diagram showing an example of a comparator configuration according to a third embodiment of the disclosed technology. [Figure 8] Figure 8 is an equivalent circuit diagram showing an example of a comparator configuration according to a fourth embodiment of the disclosed technology. [Figure 9] Figure 9 is an equivalent circuit diagram showing an example of a comparator configuration according to a fifth embodiment of the disclosed technology. [Figure 10A] Figure 10A is a waveform diagram obtained by performing an operational simulation on a comparator according to a second embodiment of the disclosed technology. [Figure 10B] Figure 10B is a waveform diagram obtained by performing an operational simulation on a comparator according to a fifth embodiment of the disclosed technology. [Figure 11] Figure 11 is an equivalent circuit diagram showing an example of a comparator configuration according to a sixth embodiment of the disclosed technology. [Figure 12] Figure 12 is a waveform obtained by performing an operational simulation on a comparator according to a sixth embodiment of the disclosed technology. [Detailed Description]

[0008] The embodiments of the disclosed technology will be described below with reference to the drawings. In each drawing, substantially identical or equivalent components or parts are given the same reference numerals.

[0009] [First Embodiment] Figure 1 is an equivalent circuit diagram showing an example of the configuration of a comparator 10 according to a first embodiment of the disclosed technology. The comparator 10 outputs an output voltage V1 according to the relative magnitudes of the input voltages V2. OUT It has the function to output [something].

[0010] Comparator 10 has an N-top type fully differential amplifier. A fully differential amplifier is a differential amplifier in which both the input and output have a differential configuration. The fully differential amplifier has input transistors 11, 12, load transistors 13, 14, output transistors 41, 42, 43, 44, and a first current supply circuit 51 and an output circuit 53.

[0011] n-channel MOSFETs (metal-oxide-semiconductor field-effect transistors) (hereinafter referred to as n-MOS) are used for input transistors 11 and 12, respectively. Input voltage V1 is input to the gate of input transistor 11, and input voltage V2 is input to the gate of input transistor 12. The sources of input transistors 11 and 12 are connected to each other. Input transistor 11 is an example of a first input transistor in the disclosed art, and input transistor 12 is an example of a second input transistor in the disclosed art. Input voltage V1 is an example of a first input voltage in the disclosed art, and input voltage V2 is an example of a second input voltage in the disclosed art.

[0012] The load transistors 13 and 14 each use p-channel type MOSFETs (hereinafter referred to as p-MOS). Load transistor 13 is connected to input transistor 11. More specifically, the source of load transistor 13 is at a high potential (V DD The load transistor 13 is connected to the power line L1 on the ) side, and its gate and drain are connected to the drain of the input transistor 11. The load transistor 13 functions as an active load on the current path of the input transistor 11.

[0013] The load transistor 14 is connected to the input transistor 12. More specifically, the source of the load transistor 14 is connected to the high-potential power line L1, and the gate and drain are connected to the drain of the input transistor 12. The load transistor 14 functions as an active load on the current path of the input transistor 12. The load transistor 13 is an example of a first load transistor in the disclosed art, and the load transistor 14 is an example of a second load transistor in the disclosed art.

[0014] p-MOS transistors are used for output transistors 41 and 42, respectively, while n-MOS transistors are used for output transistors 43 and 44. The source of output transistor 41 is connected to the high-potential power supply line L1, its drain is connected to the drain of output transistor 43, and its gate is connected to the gate of load transistor 13. The source of output transistor 43 is connected to the low-potential power supply line L2.

[0015] Output transistor 42 has its source connected to the high-potential power line L1, its drain connected to the drain of output transistor 44, and its gate connected to the gate of load transistor 14. Output transistor 44 has its source connected to the low-potential power line L2, and its gate connected to its own drain and the gate of output transistor 43. Output transistors 43 and 44 constitute a current mirror circuit.

[0016] The first current supply circuit 51 supplies a steady bias current I to the current path of the differential pair including the input transistors 11 and 12. B1 The first current supply circuit 51 has a current source 30 and transistors 15 and 16. n-MOS transistors are used for transistors 15 and 16. The current source 30 supplies a constant current to transistor 15. The drain of transistor 15 is connected to the current source 30, the source is connected to the low-potential power line L2, and the gate is connected to its own drain and the gate of transistor 16. The drain of transistor 16 is connected to the sources of input transistors 11 and 12. Transistors 15 and 16 constitute a current mirror circuit.

[0017] The output circuit 53 has transistors 23 and 24. Transistor 23 is a p-MOS and transistor 24 is an n-MOS. The source of transistor 23 is connected to the high-potential power line L1, the drain is connected to the drain of transistor 24, and the gate is connected to node n3, which is the connection point of output transistors 41 and 43, and to the gate of transistor 24. The source of transistor 24 is connected to the low-potential power line L2. The drains of transistors 23 and 24 are connected to the output voltage V of comparator 10. OUT This is designated as the output terminal. Transistors 23 and 24 constitute a CMOS (Complementary MOS) inverter.

[0018] The comparator 10 further includes a second current supply circuit 52. The second current supply circuit 52 supplies a temporary bias current I to the current path of the differential pair including the input transistors 11 and 12 in accordance with the reversal of the relative magnitudes of the input voltages V1 and V2. B2 The second current supply circuit 52 has monitor transistors 45, 46 and transistors 47, 48. p-MOS transistors are used for monitor transistors 45, 46, and n-MOS transistors are used for transistors 47, 48, respectively.

[0019] The monitor transistor 45 has its source connected to the high-potential power line L1, its drain connected to the source of monitor transistor 46, and its gate connected to node n1, which is the connection point between input transistor 11 and load transistor 13. Monitor transistor 45 turns on depending on the voltage at node n1.

[0020] Monitor transistor 46 has its source connected to the drain of monitor transistor 45, its drain connected to the drain of transistor 47, and its gate connected to node n2, which is the connection point between input transistor 12 and load transistor 14. Monitor transistor 46 is connected in series with monitor transistor 45 and turns on in response to the voltage at node n2. Monitor transistor 45 is an example of a first monitor transistor in the disclosed art, and monitor transistor 46 is an example of a second monitor transistor in the disclosed art. Node n1 is an example of a first node in the disclosed art, and node n2 is an example of a second node in the disclosed art.

[0021] Transistor 47 has its source connected to the low-potential power line L2, and its gate connected to its drain and the gate of transistor 48. Transistor 48 has its drain connected to the sources of input transistors 11 and 12, and its source connected to the low-potential power line L2. Transistors 47 and 48 constitute a current mirror circuit. The current mirror circuit formed by transistors 47 and 48 generates a mirror current of the through-current that occurs when both monitor transistors 45 and 46 are turned on. The second current supply circuit 52 supplies this mirror current of the through-current as a temporary bias current I B2 It will be supplied as such.

[0022] The comparator 10 according to this embodiment operates as follows: When the input voltage V2 is greater than the input voltage V1, current flows through the input transistor 12 and the load transistor 14, but no current flows through the input transistor 11 and the load transistor 13. As a result, current flows through the output transistors 42 and 44, the output transistor 43 turns on and the output transistor 41 turns off, and the potential of node n3 becomes low level, so the output circuit 53 produces a high output voltage V OUTis output. In the state where V2 > V1, node n1 is at a high level and node n2 is at a low level. Therefore, monitor transistor 45 is in an off state and monitor transistor 46 is in an on state. Accordingly, the bias current I B2 does not flow.

[0023] On the other hand, when the input voltage V2 is smaller than the input voltage V1, current flows through input transistor 11 and load transistor 13, and no current flows through input transistor 12 and load transistor 14. As a result, output transistor 41 is in an on state and output transistor 43 is in an off state, and the potential of node n3 becomes a high level. Therefore, output circuit 53 outputs a low-level output voltage V OUT is output. In the state where V2 < V1, node n1 is at a low level and node n2 is at a high level. Therefore, monitor transistor 45 is in an on state and monitor transistor 46 is in an off state. Accordingly, the bias current I B2 does not flow.

[0024] Input voltage V 1と At the timing when the magnitude relationship between the input voltage V2 changes (that is, the timing of switching from the state where V2 > V1 to the state where V2 < V1 and the timing of switching from the state where V2 < V1 to the state where V2 > V1), instantaneously V1 ≒ V2. In the state where V1 ≒ V2, nodes n1 and n2 are at a level intermediate between the high level and the low level, and both monitor transistors 45 and 46 are in an on state, thereby generating a through current. The current mirror circuit composed of transistors 47 and 48 generates a mirror current of the above through current and supplies this as a temporary bias current I B2 to the current paths of input transistors 11 and 12.

[0025] In this way, at the timing when the magnitude relationship between the input voltage V 1と input voltage V is changed, by additionally supplying a temporary bias current I B2 a steady bias current I B1This makes it possible to suppress the effect while improving responsiveness during output transitions.

[0026] Figures 2A, 2B, and 2C are waveform diagrams obtained by performing operational simulations on the comparator 10 configured as shown in Figure 1, respectively. Figures 2A to 2C show the input voltages V1 and V2, and the output voltage V, respectively. OUT , and steady bias current I B1 and temporary bias current I B2 The combined bias current I B The time course of the bias current is shown. A DC voltage of 1.5V was input as input voltage V1, and a triangular wave with an upper peak of 2V, a lower peak of 1V, and a frequency of 32kHz was input as input voltage V2. Figure 2A shows the steady bias current I B1 This is the case when the magnitude is 5nA, and Figure 2B shows the steady-state bias current I B1 This is the case when the magnitude is 10nA, and Figure 2C shows the steady-state bias current I B1 This is the case when the magnitude is 100 nA.

[0027] Input voltage V 1と At the timing when the relative magnitudes of the input voltages V2 change (when V1 ≈ V2), the combined bias current I B A peak is appearing. Temporary bias current I B2 The combined bias current I is generated at the timing of its generation. B A peak appears. Steady-state bias current I B1 When the magnitude is 5nA (Figure 2A), the combined bias current I B The timing at which the peak appears (i.e., the temporary bias current I B2 The generation timing of the input voltage V1 and V2 is slightly delayed relative to the timing when their relative magnitudes are reversed. The steady-state bias current I B1 When the magnitude is set to 10nA (Figure 2B), the delay is smaller compared to when it is 5nA. Steady-state bias current I B1 When the magnitude is set to 100nA (Figure 2C), the combined bias current I BThe timing at which the peak appears (i.e., the temporary bias current I B2 The generation timing of (V1) precedes the timing at which the relative magnitudes of input voltages V1 and V2 are reversed.

[0028] Figure 3 is an equivalent circuit diagram showing an example of the configuration of comparator 10X according to the comparative example. Comparator 10X according to the comparative example differs from comparator 10 (see Figure 1) according to the embodiment of the disclosed technology described above in that the differential amplifier is single-ended rather than fully differential. In other words, comparator 10X according to the comparative example does not have the output transistors 41-44 that comparator 10 according to the embodiment of the disclosed technology has.

[0029] Furthermore, the comparator 10X in the comparative example has a temporary bias current I B2 The configuration of the second current supply circuit 52X that supplies the current differs from that of the second current supply circuit 52 according to the embodiment of the disclosed technology. The second current supply circuit 52X according to the comparative example has a CMOS inverter 70 composed of transistors 17 and 18, and a current mirror circuit composed of transistors 19 and 20.

[0030] In the comparative example comparator 10X, when the relative magnitudes of input voltages V1 and V2 are reversed, the output voltage level of the CMOS inverter 70 switches. At this time, both transistors 17 and 18 momentarily turn on, which generates a through-current. The current mirror circuit composed of transistors 19 and 20 generates a mirror current of the above through-current, which is then converted into a temporary bias current I B2 This is used to supply current to the current paths of input transistors 11 and 12.

[0031] Figures 4A, 4B, and 4C are waveform diagrams obtained by performing operational simulations on comparator 10X, which is a comparative example of the configuration shown in Figure 3. Figures 4A to 4C show the input voltages V1 and V2, and the output voltage V, respectively. OUT , and steady Bias current I B1and temporary bias current I B2 The combined bias current I B The time course of the bias current is shown. A DC voltage of 1.5V was input as input voltage V1, and a triangular wave with an upper peak of 2V, a lower peak of 1V, and a frequency of 32kHz was input as input voltage V2. Figure 4A shows the steady bias current I B1 This is the case when the magnitude is 5nA, and Figure 4B shows the steady-state bias current I B1 This is the case when the magnitude is 10nA, and Figure 4C shows the steady-state bias current I B1 This is the case when the magnitude is 100 nA.

[0032] According to the comparative example comparator 10X, the combined bias current I B The timing at which the peak appears is significantly delayed compared to the timing at which the relative magnitudes of input voltages V1 and V2 are reversed. According to the comparator 10X in the comparative example, the bias current I B2 This is because it does not generate. Furthermore, according to the comparative example comparator 10X, because it is a single-ended configuration, the output voltage V OUT The response time differs significantly depending on whether the transition is from a high level to a low level or from a low level to a high level.

[0033] On the other hand, according to the comparator 10 of the disclosed embodiment, since it includes a fully differential amplifier, it can provide high responsiveness to input voltages V1 and V2 that occur at nodes n1 and n2. A temporary bias current I is based on the through-current of monitor transistors 45 and 46 that monitor the potentials of nodes n1 and n2, which have high responsiveness to the input voltages V1 and V2. B2 By generating the bias current I B2 This makes it possible to suppress delays in the generation timing.

[0034] According to the comparator 10 of the disclosed technology embodiment, the steady-state bias current I B1 When the magnitude is 5nA, the bias current I B2The delay time is the steady-state bias current I in the comparator 10X of the comparative example. B1 The bias current I when the magnitude is 100nA B2 Shorter than the delay time. That is, according to the comparator 10 according to the embodiment of the disclosed technology, the transient bias current I B2 While maintaining the effect of suppressing the delay time, a steady bias current I B1 Since the size can be reduced, it is possible to achieve even lower power consumption.

[0035] Furthermore, according to the comparator 10 of this embodiment, the output voltage V OUT This makes it possible to reduce the response time difference between transitions from high level to low level and transitions from low level to high level.

[0036] [Second Embodiment] Figure 5 is an equivalent circuit diagram showing an example of the configuration of a comparator 10A according to a second embodiment of the disclosed technology. The comparator 10A according to the second embodiment has a configuration that adds two monitor transistors 61 and 62 to the comparator 10 according to the first embodiment (see Figure 1). p-MOS transistors are used for monitor transistors 61 and 62, respectively.

[0037] The monitor transistor 61 has its source connected to the high-potential power line L1, its drain connected to the source of monitor transistor 62, and its gate connected to node n2. Monitor transistor 61 turns on depending on the voltage at node n2.

[0038] Monitor transistor 62 has its source connected to the drain of monitor transistor 61, its drain connected to the drain of transistor 47, and its gate connected to node n1. Monitor transistor 62 is connected in series with monitor transistor 61 and turns ON in response to the voltage at node n1. Monitor transistor 62 is an example of a third monitor transistor in the disclosed art, and monitor transistor 61 is an example of a fourth monitor transistor in the disclosed art.

[0039] When both monitor transistors 45 and 46 are turned on, a first-system through-current is generated, and when both monitor transistors 61 and 62 are turned on, a second-system through-current is generated. The current mirror circuit, composed of transistors 47 and 48, generates a mirror current, which is the sum of the first-system and second-system through-currents. The second current supply circuit 52A according to the second embodiment supplies this mirror current as a temporary bias current I B2 It will be supplied as such.

[0040] In the configuration shown in Figure 5, the monitor transistor 45 that monitors the potential of node n1 in the first system is positioned on the higher potential side relative to the monitor transistor 46 that monitors the potential of node n2. In this case, the monitor transistor 61 that monitors the potential of node n2 in the second system is positioned on the higher potential side relative to the monitor transistor 62 that monitors the potential of node n1. On the other hand, although not shown in the figure, if the monitor transistor that monitors the potential of node n2 in the first system is positioned on the higher potential side relative to the monitor transistor that monitors the potential of node n1, then the monitor transistor that monitors the potential of node n1 in the second system is positioned on the higher potential side relative to the monitor transistor that monitors the potential of node n2.

[0041] Figures 6A, 6B, and 6C are waveform diagrams obtained by performing an operation simulation on the comparator 10A according to the second embodiment of the configuration shown in Figure 5. Figures 6A to 6C show the input voltages V1 and V2, and the output voltage V, respectively.OUT , and steady bias current I B1 and temporary bias current I B2 The combined bias current I B The time course of the bias current is shown. A DC voltage of 1.5V was input as input voltage V1, and a triangular wave with an upper peak of 2V, a lower peak of 1V, and a frequency of 32kHz was input as input voltage V2. Figure 6A shows the steady-state bias current I B1 This is the case when the magnitude is 5nA, and Figure 6B shows the steady-state bias current I B1 This is the case when the magnitude is 10nA, and Figure 6C shows the steady-state bias current I B1 This is the case when the magnitude is 100 nA.

[0042] According to the comparator 10A of the second embodiment, similar to the comparator 10 of the first embodiment, the temporary bias current I B2 It is possible to suppress the delay in the timing of generation relative to the timing when the relative magnitudes of input voltages V1 and V2 are reversed.

[0043] Furthermore, by generating through-currents in two systems using monitor transistors, and reversing the relative positions of the monitor transistor monitoring the potential of node n1 and the monitor transistor monitoring the potential of node n2 between the first and second systems, the output voltage V OUT This makes it possible to further reduce the response time difference between transitions from high level to low level and transitions from low level to high level.

[0044] [Third Embodiment] Figure 7 is an equivalent circuit diagram showing an example of the configuration of comparator 10B according to a third embodiment of the disclosed technology. Comparator 10B according to the third embodiment differs from comparator 10 according to the first embodiment (see Figure 1) in that the fully differential amplifier is of the P-top type. That is, in comparator 10A according to the third embodiment, p-MOS transistors are used for input transistors 11 and 12, respectively, and n-MOS transistors are used for load transistors 13 and 14 and monitor transistors 45 and 46, respectively. For the other transistors, transistors with opposite polarity to those in comparator 10 according to the first embodiment are used.

[0045] According to the comparator 10B of the third embodiment, the comparator according to the first embodiment Similar to Ta10, the temporary bias current I B2 It is possible to suppress the delay in the timing of generation relative to the timing when the relative magnitudes of input voltages V1 and V2 are reversed.

[0046] [Fourth Embodiment] Figure 8 is an equivalent circuit diagram showing an example of the configuration of a comparator 10C according to the fourth embodiment of the disclosed technology. The comparator 10C according to the fourth embodiment differs from the comparator 10A according to the second embodiment (see Figure 5) in that the fully differential amplifier is of the P-top type. That is, in the comparator 10C according to the fourth embodiment, p-MOS transistors are used for input transistors 11 and 12, respectively, and n-MOS transistors are used for load transistors 13 and 14 and monitor transistors 45, 46, 61, and 62, respectively. For the other transistors, transistors with the opposite polarity to those used in the comparator 10A according to the second embodiment are also used.

[0047] According to the comparator 10C of the fourth embodiment, similar to the comparator 10 of the first embodiment, the temporary bias current I B2It is possible to suppress the delay in the timing of the generation of the input voltages V1 and V2 when the relative magnitudes of the input voltages V1 and V2 are reversed. Also, similar to the comparator 10A of the second embodiment, the output voltage V OUT This makes it possible to further reduce the response time difference between transitions from high level to low level and transitions from low level to high level.

[0048] [Fifth Embodiment] Figure 9 is an equivalent circuit diagram showing an example of the configuration of a comparator 10D according to a fifth embodiment of the disclosed technology. The comparator 10D according to the fifth embodiment differs from the comparator 10A according to the second embodiment (see Figure 5) in that it has a resistor element 80 that limits the first system of through-current generated when both monitor transistors 45 and 46 are turned on, and the second system of through-current generated when both monitor transistors 61 and 62 are turned on. Specifically, one end of the resistor element 80 is connected to the power line L1, and the other end is connected to the source of the monitor transistors 45 and 61.

[0049] Figure 10A is a waveform diagram obtained by performing an operational simulation on comparator 10A (see Figure 5) according to the second embodiment of the disclosed technology. Figure 10B is a waveform diagram obtained by performing an operational simulation on comparator 10D (see Figure 9) according to the fifth embodiment of the disclosed technology. Figures 10A and 10B show input voltages V1, V2, and output voltage V, respectively. OUT , and steady bias current I B1 and temporary bias current I B2 The combined bias current I B The time progression is shown. In addition, waveforms are shown for each case where the gate threshold voltage of the transistors constituting comparators 10A and 10D is at the upper limit, lower limit, and midpoint of the tolerance range.

[0050] According to the comparator 10A of the second embodiment, which does not have a resistive element to limit the through-current, the temporary bias current I B2The magnitude becomes excessive, and as a result, the combined bias current I B The magnitude of becomes excessive. On the other hand, according to the comparator 10D of the fifth embodiment having a resistive element 80 that limits the through-current, the temporary bias current I can be controlled without affecting the response time. B2 This makes it possible to significantly suppress the combined bias current I B This allows for optimization of the size.

[0051] [Sixth Embodiment] Figure 11 is an equivalent circuit diagram showing an example of the configuration of a comparator 10E according to a sixth embodiment of the disclosed technology. The comparator 10E according to the sixth embodiment differs from the comparator 10D according to the fifth embodiment (see Figure 9) in that the resistance element that limits the through-current is a variable resistor element 81. The resistance value of the variable resistor element 81 can be adjusted by an external control signal.

[0052] Figure 12 is a waveform diagram obtained by performing an operational simulation on the comparator 10E according to the sixth embodiment of the disclosed technology. Figure 12 shows input voltages V1, V2, and output voltage V OUT , and steady bias current I B1 and temporary bias current I B2 The combined bias current I B The time progression is shown. Furthermore, waveforms are shown for the cases where the gate threshold voltage of the transistor constituting the comparator 10E is at the upper limit, lower limit, and intermediate limit of the tolerance range. According to the comparator 10E of the sixth embodiment, which has a variable resistor element 81 that limits the through-current, the combined bias current I B Not only can the size be optimized, but by adjusting the resistance value of the variable resistor element 81, it is possible to suppress variations in bias current or response time caused by variations in the transistor's threshold voltage.

[0053] With regard to the first to fourth embodiments described above, the following additional information is disclosed. (Note 1) The first input transistor 11 to which the first input voltage V1 to be compared is input, The second input transistor 12 to which the second input voltage V2 to be compared is input, The first load transistor 13 connected to the first input transistor 11, The second load transistor 14 connected to the second input transistor 12, A steady bias current I is applied to the current paths of the first input transistor 11 and the second input transistor 12. B1 A first current supply circuit 51 that supplies, A fully differential amplifier having, A temporary bias current I is introduced into the current path in accordance with the change in the relative magnitudes of the first input voltage V1 and the second input voltage V2. B2 A second current supply circuit 52 that supplies, Includes, The second current supply circuit 52 is, A first monitor transistor 45 that turns on in accordance with the voltage at the first node n1, which is the connection point between the first input transistor 11 and the first load transistor 13, The system includes a second monitor transistor 46 connected in series with the first monitor transistor 45, which turns on in response to the voltage at the second node n2, which is the connection point between the second input transistor 12 and the second load transistor 14, The current generated based on the through-current that occurs when both the first monitor transistor 45 and the second monitor transistor 46 are turned on is the temporary bias current I. B2 To supply as Comparator 10.

[0054] (Note 2) The second current supply circuit 52 includes a current mirror circuit that generates a mirror current of the through-current. Comparator 10 as described in Appendix 1.

[0055] (Note 3) The second current supply circuit 52A is, A third monitor transistor 62 that turns on in accordance with the voltage of the first node n1, It includes a fourth monitor transistor 61 which is connected in series with the third monitor transistor 62 and turns on in response to the voltage of the second node n2, The current generated based on the current obtained by combining the first through-current generated when both the first monitor transistor 45 and the second monitor transistor 46 are turned on, and the second through-current generated when both the third monitor transistor 62 and the fourth monitor transistor 61 are turned on, is called the temporary bias current I. B2 It will be supplied as, The first monitor transistor 45 is positioned on the higher potential side relative to the second monitor transistor 46, and the fourth monitor transistor 61 is positioned on the higher potential side relative to the third monitor transistor 62. Comparator 10A as described in Appendix 1 or Appendix 2.

[0056] (Note 4) The second current supply circuit 52A is, A third monitor transistor 62 that turns on in accordance with the voltage of the first node n1, It includes a fourth monitor transistor 61 which is connected in series with the third monitor transistor 62 and turns on in response to the voltage of the second node n2, The current generated based on the current obtained by combining the first through-current generated when both the first monitor transistor 45 and the second monitor transistor 46 are turned on, and the second through-current generated when both the third monitor transistor 62 and the fourth monitor transistor 61 are turned on, is called the temporary bias current I. B2 It will be supplied as, The second monitor transistor 46 is positioned on the higher potential side relative to the first monitor transistor 45, and the third monitor transistor 62 is positioned on the higher potential side relative to the fourth monitor transistor 61. The comparator described in Appendix 1 or Appendix 2.

[0057] (Note 5) The system further includes a resistive element that limits the through-current of the first system and the through-current of the second system. The comparator described in Appendix 3 or Appendix 4.

[0058] (Note 6) The aforementioned resistive element is a variable resistive element. The comparator according to claim 5. [Explanation of Symbols]

[0059] 10, 10A, 10B, 10C, 10X comparators 11, 12 input transistors 13, 14 Load transistors 30 current source 41, 42, 43, 44 Output transistors 45, 46, 61, 62 Monitor transistors 51 1st current supply circuit 52, 52A, 52X 2nd current supply circuit 53 Output Circuit

Claims

1. The first input transistor to which the first input voltage to be compared is input, The second input transistor to which the second input voltage to be compared is input, The first load transistor connected to the first input transistor, The second load transistor connected to the second input transistor, A first current supply circuit that supplies a steady bias current to the current paths of the first input transistor and the second input transistor, A fully differential amplifier having, A second current supply circuit supplies a temporary bias current to the current path in accordance with the reversal of the relative magnitudes of the first input voltage and the second input voltage, Includes, The second current supply circuit is, A first monitor transistor that turns on in accordance with the voltage at the first node, which is the connection point between the first input transistor and the first load transistor, The system includes a second monitor transistor connected in series with the first monitor transistor, which turns on in response to the voltage at a second node, which is the connection point between the second input transistor and the second load transistor. The current generated based on the through-current that occurs when both the first monitor transistor and the second monitor transistor are turned on is supplied as the temporary bias current. comparator.

2. The second current supply circuit includes a current mirror circuit that generates a mirror current of the through-current. The comparator according to claim 1.

3. The second current supply circuit is, A third monitor transistor that turns on in accordance with the voltage of the first node, It includes a fourth monitor transistor that turns on in response to the voltage of the second node and is connected in series with the third monitor transistor, The current generated based on the combined current of the first through-current generated when both the first monitor transistor and the second monitor transistor are turned on, and the second through-current generated when both the third monitor transistor and the fourth monitor transistor are turned on, is supplied as the temporary bias current. The first monitor transistor is positioned on the higher potential side relative to the second monitor transistor, and the fourth monitor transistor is positioned on the higher potential side relative to the third monitor transistor. The comparator according to claim 1.

4. The second current supply circuit is, A third monitor transistor that turns on in accordance with the voltage of the first node, It includes a fourth monitor transistor that turns on in response to the voltage of the second node and is connected in series with the third monitor transistor, The current generated based on the combined current of the first through-current generated when both the first monitor transistor and the second monitor transistor are turned on, and the second through-current generated when both the third monitor transistor and the fourth monitor transistor are turned on, is supplied as the temporary bias current. The second monitor transistor is positioned on the higher potential side relative to the first monitor transistor, and the third monitor transistor is positioned on the higher potential side relative to the fourth monitor transistor. It is being done The comparator according to claim 1.

5. The system further includes a resistive element that limits the through-current of the first system and the through-current of the second system. The comparator according to claim 3 or claim 4.

6. The aforementioned resistive element is a variable resistive element. The comparator according to claim 5.

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