Indication device

Abstract

To provide a display device that improves manufacturing yield without reducing transparency. [Solution] The display device includes a first conductive layer, a first insulating layer on the first conductive layer, a first transparent conductive layer and a second transparent conductive layer on the first insulating layer, an oxide semiconductor layer on the first transparent conductive layer and the second transparent conductive layer in contact with the first transparent conductive layer and the second transparent conductive layer, a second insulating layer on the oxide semiconductor layer, and a second conductive layer on the second insulating layer, wherein the first transparent conductive layer and the second transparent conductive layer are located on the same layer, and the oxide semiconductor layer is superimposed on the first conductive layer and the second conductive layer.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, progress has been made in the development of transparent displays that allow the background of one side to be seen from the other side (see Patent Document 1). Users can see images, figures, or characters displayed on the transparent display from either side. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2021-092702 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] In transparent displays, oxide semiconductor layers are sometimes used as the channel region for thin-film transistors (TFTs). However, the transistor characteristics of thin-film transistors using oxide semiconductor layers are susceptible to the influence of the back channel region of the oxide semiconductor layer. For example, if the back channel region of the oxide semiconductor layer is damaged by the formation of source and drain electrodes on the oxide semiconductor layer, the thin-film transistor will exhibit depletion-type transistor characteristics. Therefore, in transparent displays, there is a demand not only for increasing the aperture ratio to improve transparency, but also for improving manufacturing yield.

[0005] One of the objectives of one embodiment of the present invention is to provide a display device that improves manufacturing yield without reducing transparency, in view of the above-mentioned problems. [Means for solving the problem]

[0006] A display device according to one embodiment of the present invention includes a first conductive layer, a first insulating layer on the first conductive layer, a first transparent conductive layer and a second transparent conductive layer on the first insulating layer, an oxide semiconductor layer on the first transparent conductive layer and the second transparent conductive layer in contact with the first transparent conductive layer and the second transparent conductive layer, a second insulating layer on the oxide semiconductor layer, and a second conductive layer on the second insulating layer, wherein the first transparent conductive layer and the second transparent conductive layer are located on the same layer, and the oxide semiconductor layer is superimposed on the first conductive layer and the second conductive layer. [Brief explanation of the drawing]

[0007] [Figure 1] This is a perspective view illustrating the overview of a display device according to one embodiment of the present invention. [Figure 2] Figure 1 is a schematic cross-sectional view showing the cross-sectional structure of the display device as cut along line A1-A2. [Figure 3] This is a schematic plan view illustrating the configuration of an array substrate for a display device according to one embodiment of the present invention. [Figure 4] This is a circuit diagram showing the configuration of the pixel circuit of a display device according to one embodiment of the present invention. [Figure 5] This is a timing chart of four pixels in a display device according to one embodiment of the present invention. [Figure 6] This is a schematic cross-sectional view showing the pixel configuration in an array substrate of a display device according to one embodiment of the present invention. [Figure 7] This is a flowchart showing a method for manufacturing an array substrate of a display device according to one embodiment of the present invention. [Figure 8] This is a schematic cross-sectional view showing a method for manufacturing an array substrate of a display device according to one embodiment of the present invention. [Figure 9] This is a schematic cross-sectional view showing a method for manufacturing an array substrate of a display device according to one embodiment of the present invention. [Figure 10] This is a schematic cross-sectional view showing a method for manufacturing an array substrate of a display device according to one embodiment of the present invention. [Figure 11] This is a schematic cross-sectional view showing a method for manufacturing an array substrate of a display device according to one embodiment of the present invention. [Figure 12] It is a cross-sectional schematic view showing a method for manufacturing an array substrate of a display device according to an embodiment of the present invention. [Figure 13] It is a cross-sectional schematic view showing a method for manufacturing an array substrate of a display device according to an embodiment of the present invention. [Figure 14] It is a cross-sectional schematic view showing a method for manufacturing an array substrate of a display device according to an embodiment of the present invention. [Figure 15] It is a cross-sectional schematic view showing a method for manufacturing an array substrate of a display device according to an embodiment of the present invention. [Figure 16] It is a cross-sectional schematic view showing the configuration of pixels in an array substrate of a display device according to an embodiment of the present invention. [Figure 17] It is a cross-sectional schematic view showing a method for manufacturing an array substrate of a display device according to an embodiment of the present invention. [Figure 18] It is a cross-sectional schematic view showing the configuration of pixels in an array substrate of a display device according to an embodiment of the present invention. [Figure 19] It is a flowchart showing a method for manufacturing an array substrate of a display device according to an embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0008] Hereinafter, each embodiment of the present invention will be described with reference to the drawings and the like. However, the present invention can be implemented in various modes without departing from the gist thereof, and is not to be construed as being limited to the description content of the embodiments exemplified below. Also, regarding the drawings, for the sake of clearer explanation, the width, thickness, shape, etc. of each part may be schematically represented compared to the actual mode, but these schematic diagrams are just examples and do not limit the interpretation of the present invention. Furthermore, in this specification and each figure, the same or similar elements as those described with respect to the already shown figure may be denoted by the same reference numerals, and duplicate explanations may be omitted. Note that in this specification and the like, ordinal numbers are for convenience of distinguishing components, parts, etc., and do not indicate priority or order.

[0009] In this invention, when multiple films are formed by processing a single film, these multiple films may have different functions and roles. However, these multiple films originate from a film formed as the same layer in the same process, and have the same layer structure and the same material. Therefore, these multiple films are defined as existing in the same layer. Furthermore, when multiple films are formed by processing a single film, they may be described separately as -1, -2, etc., in this specification, etc.

[0010] In this specification, expressions such as "above" and "below" describe the relative positional relationship between the structure of interest and other structures. In this specification, in a side view, the direction from the first substrate (described later) toward the pixel electrode is defined as "above," and the opposite direction is defined as "below." In this specification and the claims, when describing a manner in which one structure is placed on top of another structure, unless otherwise specified, the expression "above" includes both cases: when one structure is placed directly above another structure so as to be in contact with it, and when another structure is placed above another structure via yet another structure.

[0011] Furthermore, in this specification, bottom gate drive refers to a system where the on / off state is controlled by a gate electrode located below the semiconductor layer. Furthermore, in this specification, top gate drive refers to a system where the on / off state is controlled by a gate electrode located above the semiconductor layer. Furthermore, in this specification, dual gate drive refers to a system where the on / off state is controlled by inputting the same control signal to gate electrodes located above and below the semiconductor layer.

[0012] <First Embodiment> A display device 10 according to one embodiment of the present invention will be described with reference to Figures 1 to 15.

[0013] [1. Configuration of the display device 10] Figure 1 shows a perspective view of a display device 10 according to one embodiment of the present invention. The display device 10 includes a display panel 102, a light source 104, and a first transparent substrate 151A and a second transparent substrate 151B that sandwich the display panel 102. The display panel 102 is provided with an array substrate 150, a liquid crystal layer (not shown) between the array substrate 150 and the opposing substrate 152, a gate drive circuit 28, and a source drive circuit 38. In the following description, one direction of the plane in the display panel 102 shown in Figure 1 is referred to as the D1 direction, the direction perpendicular to the D1 direction is referred to as the D2 direction, and the direction perpendicular to the D1-D2 plane is referred to as the D3 direction.

[0014] The array substrate 150 and the opposing substrate 152 are light-transmitting. Preferably, the array substrate 150 and the opposing substrate 152 are transparent to visible light. The opposing substrate 152 is positioned in the D3 direction so as to face the array substrate 150. The array substrate 150 and the opposing substrate 152 are bonded together by a sealing material 154 while facing each other with a gap between them. A liquid crystal layer (not shown) is provided in the gap between the array substrate 150 and the opposing substrate 152.

[0015] The display panel 102 includes a display area 12 and a peripheral area 14. The peripheral area 14 is located outside the display area 12. Multiple pixels (PIX) are arranged in the row and column directions within the display area 12. Here, the row direction refers to the direction parallel to the D1 direction, and the column direction refers to the direction parallel to the D2 direction. The display area 12 has m pixels arranged in the row direction and n pixels arranged in the column direction. The values ​​of m and n are set appropriately according to the vertical and horizontal display resolutions. Gate wiring (sometimes called scan signal lines) is arranged in the D1 direction within the display area 12, and source wiring (sometimes called data signal lines) is arranged in the D2 direction.

[0016] A gate drive circuit 28 and a source drive circuit 38 are provided in the peripheral region 14. Figure 1 shows an embodiment in which the gate drive circuit 28 and the source drive circuit 38 are provided as integrated circuits (ICs) and mounted on the array substrate 150 using the COG (Chip on Glass) method. The gate drive circuit 28 and the source drive circuit 38 are not limited to the embodiment shown, and may be mounted using the COF (Chip on Film) method or formed by thin-film transistors on the array substrate 150.

[0017] The peripheral region 14 includes a gate wiring region 32, a common wiring region 22, and a source wiring region 42. The gate wiring region 32 is an area where a pattern is formed by wiring connecting the gate drive circuit 28 and the gate wiring arranged in the display region 12. The common wiring region 22 is an area where a pattern is formed by common wiring. Circuit-wise, the common wiring region 22 is used as wiring that applies a common voltage to the common electrode provided on the opposing substrate 152. The source wiring region 42 is an area where a pattern is formed by wiring connecting the source drive circuit 38 and the data signal lines arranged in the display region 12. Details of the gate wiring, common wiring, and source wiring will be described later.

[0018] The light source 104 is provided along the D1 direction. The light source 104 is composed of, for example, light-emitting diodes (LEDs) arranged along the D1 direction. However, the structure of the light source 104 is not limited to light-emitting diodes and may include optical components such as reflectors, diffusers, or lenses. The light source 104 and the light emission control circuit 110 that controls the light source 104 may be provided as separate components independent of the display panel 102. Furthermore, the timing of light emission of the light source 104 may be controlled by the light emission control circuit 110 which is synchronized with the gate drive circuit 28 and the source drive circuit 38. The light emission control circuit 110 that controls the light source 104 may be provided as a separate component, like the light source 104, separate from the display panel 102, mounted on the array substrate 150 as an individual component, or incorporated into the gate drive circuit 28 or the source drive circuit 38.

[0019] The first transparent substrate 151A and the second transparent substrate 151B are provided so as to sandwich the display area 12 and the peripheral area 14. The first transparent substrate 151A and the second transparent substrate 151B function as protective members for the display panel 102. As will be described in detail later, the first transparent substrate 151A and the second transparent substrate 151B also function as light guide plates that introduce light emitted from the light source 104 into the display panel 102.

[0020] Figure 2 is a schematic cross-sectional view showing the cross-sectional structure of the display device 10 shown in Figure 1, cut along the line A1-A2. As shown in Figure 2, a first transparent substrate 151A is provided on the array substrate 150 side of the display panel 102, and a second transparent substrate 151B is provided on the opposing substrate 152 side. Glass substrates or plastic substrates are used as the first transparent substrate 151A and the second transparent substrate 151B. Preferably, the first transparent substrate 151A and the second transparent substrate 151B have refractive indices equivalent to those of the array substrate 150 and the opposing substrate 152. The array substrate 150 and the first transparent substrate 151A are bonded together with a transparent adhesive (not shown). Similarly, the opposing substrate 152 and the second transparent substrate 151B are bonded together with a transparent adhesive (not shown).

[0021] The array substrate 150 and the opposing substrate 152 are facing each other with a liquid crystal layer 153 in between. Because the array substrate 150 is larger than the opposing substrate 152, a portion of the peripheral region 14 in the -D2 direction is exposed from the opposing substrate 152. Drive circuits such as the source drive circuit 38 are mounted on the array substrate 150. In addition, a flexible printed circuit 34 is attached to the peripheral edge of the array substrate 150.

[0022] The light source 104 is positioned adjacent to one end face of either the first transparent substrate 151A or the second transparent substrate 151B. Figure 2 shows a configuration in which the light source 104 is positioned along one end face of the second transparent substrate 151B. Although Figure 2 shows a configuration in which the light source 104 is attached to the array substrate 150, the configuration for positioning the light source 104 is not limited to this, and other configurations are possible as long as the mounting position can be fixed. For example, the light source 104 may be supported by a housing surrounding the display panel 102.

[0023] The light source 104 is positioned along the first end face 15C of the second transparent substrate 151B. The light source 104 irradiates light L onto the first end face 15C of the second transparent substrate 151B. The light source 104 is sometimes called an edge light source because it emits light L toward the first end face 15C. The first end face 15C of the second transparent substrate 151B facing the light source 104 becomes the light incident surface.

[0024] Light L incident on the first end face 15C of the second transparent substrate 151B propagates away from the first end face 15C (direction D2) while being reflected by the second plane 15B of the second transparent substrate 151B and the first plane 15A of the first transparent substrate 151A. The display device 10 is in the atmosphere. The refractive index of the air, which is the medium outside the first transparent substrate 151A (e.g., in the -D3 direction) and outside the second transparent substrate 151B (e.g., in the D3 direction), is smaller than the refractive index of the first transparent substrate 151A and the second transparent substrate 151B. When light L that has propagated through the first transparent substrate 151A or the second transparent substrate 151B reaches the first plane 15A of the first transparent substrate 151A or the second plane 15B of the second transparent substrate 151B, it undergoes total internal reflection if the angle of incidence is greater than the critical angle. In this way, the totally reflected light L propagates in the direction of D2 while being reflected by the first plane 15A and the second plane 15B.

[0025] The liquid crystal layer 153 is formed of polymer-dispersed liquid crystal. The liquid crystal layer 153 is controlled to alternate between a scattering state and a non-scattering state for each pixel PIX (see Figure 1). Light L propagating while reflecting off the first plane 15A and the second plane 15B is scattered at least partially by pixels in which the liquid crystal layer 153 is controlled to a scattering state. Scattered light LA ​​and LB, whose incident angles are smaller than the critical angle, are emitted to the outside from the first plane 15A and the second plane 15B, respectively. The emitted scattered light LA ​​and LB are observed by the observer. The array substrate 150, the opposing substrate 152, the first transparent substrate 151A, and the second transparent substrate 151B are translucent, i.e., transparent to visible light. Since the liquid crystal layer 153 controlled to a non-scattering state is transparent, the areas other than those from which scattered light LA ​​and LB are emitted are transparent. Therefore, the observer can view the back side through the display panel 102.

[0026] Figure 3 is a schematic plan view illustrating the configuration of the array substrate 150 of a display device 10 according to one embodiment of the present invention. As shown in Figure 3, the array substrate 150 includes a display area 12 and a peripheral area 14.

[0027] The display area 12 includes multiple pixels PIX arranged in a matrix. As will be described in detail later, each of the multiple pixels PIX includes multiple transistors and liquid crystal elements.

[0028] The peripheral region 14 is provided so as to surround the display region 12. The peripheral region 14 refers to the area on the array substrate 150 from the display region 12 to the edge of the array substrate 150. In other words, the peripheral region 14 is the area on the array substrate 150 other than the display region 12 (i.e., the area outside the display region 12).

[0029] In addition to the gate drive circuit 28 and source drive circuit 38, the peripheral region 14 is provided with a gate wiring region 32, a source wiring region 42, common wiring 16 and 18, a common wiring region 22, terminal sections 26 and 36, flexible printed circuits 24 and 34, and various test circuits. The terminal sections 26 and 36 are arranged along one side of the array substrate 150.

[0030] A flexible printed circuit board 24 is connected to the terminal section 26. The flexible printed circuit board 24 supplies various signals to the gate drive circuit 28, common wiring 16 and 18, ESD protection circuit 59, and QD pad 56. The gate drive circuit 28 is connected to multiple gate wirings, and each of the multiple gate wirings is electrically connected to each of the multiple pixels PIX in the display area 12. The gate wiring area 32 is an area where multiple gate wirings are provided, but the detailed arrangement of the multiple gate wirings is omitted in Figure 3. The number of gate wirings connected to the two gate drive circuits 28 corresponds to the number of rows of pixels PIX in the display area 12. Although the gate wiring area 32 is shown as being provided separately from the display area 12, in reality, the gate wirings and pixels PIX are electrically connected.

[0031] A flexible printed circuit 34 is connected to the terminal section 36. The flexible printed circuit 34 supplies a video signal to the source drive circuit 38. The source drive circuit 38 is connected to multiple source wires, and each of the multiple source wires is electrically connected to each of the multiple pixels PIX in the display area 12. The source wire area 42 is an area where multiple source wires are provided, but the detailed arrangement of the multiple source wires is omitted in Figure 3. The number of source wires connected to the eight source drive circuits 38 shown in Figure 3 corresponds to at least three times the number of rows of pixels PIX in the display area 12. Hereinafter, the case where the number of source wires is four times the number of rows of pixels PIX in the display area 12 will be described. Although the source wire area 42 is shown as being provided separately from the display area 12, in reality, the source wires and pixels PIX are electrically connected.

[0032] Between the gate wiring area 32 and the display area 12, a common wiring 18, an ESD protection circuit 46, a gate inspection circuit 48, and an inspection line 54 are provided. Between the source wiring area 42 and the display area 12, a common wiring 18, an ESD protection circuit 46, a source inspection circuit 52, and an inspection line 54 are provided. The inspection line 54 is connected to the ESD protection circuit 58 and the QD pad 56. The common wiring 18 is also connected to the ESD protection circuit 59.

[0033] The common wiring 16 is provided so as to surround the peripheral region 14 on the array substrate 150, and signals are supplied from the two flexible printed circuits 24. The common wiring 16 is also electrically connected to the mesh-like common wiring region 22.

[0034] [2. Pixel PIX Configuration] [2-1. Circuit Configuration] Figure 4 is a circuit diagram showing the configuration of a pixel circuit of a display device 10 according to one embodiment of the present invention. Figure 4 shows the pixel circuits of four pixels PIX1 to PIX4 included in the display device 10. In the display device 10 shown in Figure 4, an ON voltage is supplied simultaneously to four gate wirings GL1 to GL4, and the four pixels PIX arranged in the column direction can be charged simultaneously by four source wirings SL1 to SL4. This makes it possible to make one horizontal period longer than the horizontal period of line sequential charging. In other words, the time required to scan all pixel lines arranged in the display area 12 can be reduced to 1 / 4. Therefore, a sufficient charging period for pixels PIX1 to PIX4 can be ensured in high-speed drive panels such as transparent displays and large panels. Hereinafter, pixels PIX1 to PIX4 will be referred to as "pixel PIX" unless they are distinguished from each other. Similarly, gate wirings GL1 to GL4 and source wirings SL1 to SL4 will be referred to as "gate wiring GL" or "source wiring SL" unless they are distinguished from each other.

[0035] The four pixels PIX1 to PIX4 are arranged in the column direction (D2 direction). Each of the four pixels PIX1 to PIX4 is electrically connected to each of the four gate lines GL1 to GL4. In addition, each of the four pixels PIX1 to PIX4 is electrically connected to each of the four source lines SL1 to SL4. Each of the four pixels PIX1 to PIX4 is connected to the capacitive line CW.

[0036] Each pixel circuit (PIX) includes a transistor (Tr), a liquid crystal element (LE), and a retaining capacitor (C). The gate of the transistor (Tr) is connected to the gate wiring (GL), the source of the transistor (Tr) is connected to the source wiring (SL), and the drain of the transistor (Tr) is connected to one electrode of the liquid crystal element (LE) (pixel electrode) and one electrode of the retaining capacitor (C). The other electrode of the liquid crystal element (LE) is a common electrode located on the opposing substrate (152). The other electrode of the retaining capacitor (C) is connected to the capacitance wiring (CW).

[0037] The transistor Tr has the function of controlling the writing time of the video signal supplied from the source wiring SL to the pixels PIX by switching between an on state and an off state. By turning the transistor Tr on, the potential corresponding to the video signal supplied from the source wiring SL can be written to the retaining capacitor C electrically connected to the transistor Tr. Conversely, by turning the transistor Tr off, the potential held in the retaining capacitor C can be retained.

[0038] Figure 5 shows the timing chart of four pixels PIX1 to PIX4 in a display device 10 according to one embodiment of the present invention. Normally, an ON voltage is supplied to the gate wiring GL one row at a time, sequentially charging the pixel rows aligned in the D2 direction with the same source wiring SL. In contrast, in this embodiment, an ON voltage is supplied to four gate wirings GL simultaneously in one horizontal period, causing each of the transistors Tr of the four pixels PIX1 to PIX4 to be turned ON at the same time. In this state, video signals are supplied simultaneously to different source wirings SL1 to SL4. This makes it possible to drive the four pixels PIX1 to PIX4 aligned in the D2 direction simultaneously.

[0039] [2-2. Structure] Figure 6 is a schematic cross-sectional view showing the configuration of pixels PIX in an array substrate 150 of a display device 10 according to one embodiment of the present invention. As shown in Figure 6, the array substrate 150 includes a support substrate 200, conductive layers 202-1 and 202-2, an insulating layer 204, transparent conductive layers 206-1 and 206-2, an oxide semiconductor layer 208, an insulating layer 210, a conductive layer 212, a planarizing layer 214, a conductive layer 216, an insulating layer 218, and a transparent conductive layer 220. Conductive layers 202-1 and 202-2 are provided on the support substrate 200. The insulating layer 204 includes insulating layers 204a and 204b and is provided so as to cover conductive layers 202-1 and 202-2. The insulating layer 204 is also provided with a contact hole CH1 through which the conductive layer 202-2 is exposed. Transparent conductive layers 206-1, 206-2, and 206-3 are provided on the insulating layer 204. Transparent conductive layer 206-3 is in direct contact with conductive layer 202-2 via a contact hole CH1. Oxide semiconductor layer 208 is in contact with transparent conductive layers 206-1 and 206-2 and is provided on the insulating layer 204 and transparent conductive layers 206-1 and 206-2. Insulating layer 210 includes insulating layers 210a and 210b and is provided to cover transparent conductive layers 206-1, 206-2, and 206-3, as well as oxide semiconductor layer 208. Conductive layer 212 is superimposed on conductive layer 202-1 and oxide semiconductor layer 208 and is provided on the insulating layer 210. The planarization layer 214 is provided on top of the insulating layer 210 and the conductive layer 212, superimposed on the conductive layers 202-1 and 202-2, the transparent conductive layer 206-3, the oxide semiconductor layer 208, and the conductive layer 212. The planarization layer 214 also has an opening OP through which the insulating layer 210 is exposed. The conductive layer 216 is provided on top of the planarization layer 214. The insulating layer 218 is provided on top of the insulating layer 210, the planarization layer 214, and the conductive layer 216. At the opening OP, the insulating layers 210 and 218 are provided with a contact hole CH3 through which the transparent conductive layer 206-2 is exposed. The transparent conductive layer 220 is provided on top of the insulating layer 218 at the opening OP. The transparent conductive layer 220 is in contact with the transparent conductive layer 206-2 via the contact hole CH3.

[0040] The conductive layer 202-1 functions as the gate electrode. The transparent conductive layers 206-1 and 206-2 function as the source electrode and drain electrode, respectively. Note that the functions of the source electrode and drain electrode may be interchangeable. Although not shown in the diagram, the conductive layer 212 is electrically connected to the conductive layer 202-1 via a contact hole and functions as the back gate electrode. A portion of the insulating layer 204 (the region overlapping with the gate electrode) and a portion of the insulating layer 210 (the region overlapping with the back gate electrode) function as the gate insulating layer. In other words, the conductive layer 202-1, a portion of the insulating layer 204, the transparent conductive layers 206-1 and 206-2, the oxide semiconductor layer 208, a portion of the insulating layer 210, and the conductive layer 212 are components of the transistor Tr.

[0041] The conductive layer 202-2 functions as a signal line (scan signal line or data signal line). The transparent conductive layer 206-3 functions as a connecting electrode that electrically connects the two conductive layers 202-2. In other words, conductive layers 202-2 and 206-3 are components of the wiring that controls the pixel PIX.

[0042] The transparent conductive layer 220 functions as a pixel electrode. The transparent conductive layer 220 is in direct contact with the transparent conductive layer 206-2, which functions as a drain electrode.

[0043] The conductive layer 216 functions as a capacitive wiring CW (see Figure 4). Furthermore, the conductive layer 216 also functions as a light-shielding layer.

[0044] A pixel PIX is generally divided into an aperture region where a transparent conductive layer 220 is provided in an opening OP through which a planarization layer is opened, and a wiring region where a transistor Tr and wiring are provided. In this embodiment, the transparent conductive layer 220 in the aperture region is in direct contact with the transparent conductive layer 206-2 extending from the wiring region without the need for opaque wiring. Therefore, since light transmission is maintained even in the region near the boundary between the wiring region and the aperture region, the aperture ratio of the pixel PIX is improved. In addition, the source electrode (transparent conductive layer 206-1) and drain electrode (transparent conductive layer 206-2) of the transistor Tr are provided below the oxide semiconductor layer 208. The manufacturing method of the array substrate 150 will be described later, but since the oxide semiconductor layer 208 is not affected by the formation of the source electrode and drain electrode, damage to the back channel portion of the oxide semiconductor layer 208 is significantly reduced.

[0045] [2-3. Materials] As the support substrate 200, a rigid substrate that is translucent and not flexible, such as a glass substrate, quartz substrate, or sapphire substrate, can be used. If the array substrate 150 needs to be flexible, a flexible substrate such as a polyimide substrate, acrylic substrate, siloxane substrate, or fluororesin substrate can be used as the support substrate 200. In this case, to improve the heat resistance of the support substrate 200, a flexible substrate with impurities introduced into it can also be used as the support substrate.

[0046] Furthermore, rigid or flexible substrates similar to the support substrate 200 can be used as the support substrate for the opposing substrate 152, the first transparent substrate 151A, and the second transparent substrate 151B. In any case, since the display device 10 is a transparent display, the support substrate for the array substrate 150, the support substrate for the opposing substrate 152, the first transparent substrate 151A, and the second transparent substrate 151B are light-transmitting.

[0047] As the conductive layers 202-1 and 202-2, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), or their alloys or compounds are used. The conductive layers 202-1 and 202-2 may have a single-layer structure or a laminated structure.

[0048] As the insulating layer 204, silicon nitride (SiN y ), silicon oxynitride (SiN x O y ), aluminum nitride (AlN x ), or aluminum oxynitride (AlN x O y ), etc., nitrides, or silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), or aluminum oxynitride (AlO[[ID=2​​​​​​​​​​​​​​​​​​​​​​​

[0050] As the oxide semiconductor layer 208, an oxide semiconductor having semiconductor properties can be used. The oxide semiconductor layer 208 is translucent. As the oxide semiconductor layer 208, an oxide semiconductor containing two or more metals including indium (In) can be used. Specifically, as the oxide semiconductor layer 208, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) can be used. In this case, an oxide semiconductor having a composition ratio of In:Ga:Zn:O = 1:1:1:4 may be used. The oxide semiconductor layer 208 may be amorphous or crystalline.

[0051] The same material as the insulating layer 204 can be used for the insulating layer 210. More specifically, an oxide is used as the insulating layer 210a, which is similar to the oxide semiconductor layer 208, and a nitride is used as the insulating layer 210b, which is similar to the conductive layer 212.

[0052] The same material as that used for conductive layers 202-1 and 202-2 can be used for conductive layer 212.

[0053] As the planarization layer 214, an organic insulating material such as polyimide resin, acrylic resin, epoxy resin, silicone resin, fluororesin, or siloxane resin can be used.

[0054] The same material as that used for conductive layers 202-1 and 202-2 can be used for conductive layer 216.

[0055] A nitride similar to that used for the insulating layer 204 can be used as the insulating layer 218.

[0056] As the transparent conductive layer 220, the same material as that used for the transparent conductive layers 206-1, 206-2, and 206-3 can be used.

[0057] [3. Method for manufacturing the array substrate 150] The manufacturing method of the array substrate 150 will be described with reference to Figures 7 to 15. Figure 7 is a flowchart showing the manufacturing method of the array substrate 150 of the display device 10 according to one embodiment of the present invention. Figures 8 to 15 are schematic cross-sectional views showing the manufacturing method of the array substrate 150 of the display device 10 according to one embodiment of the present invention. As shown in Figure 7, the manufacturing method of the array substrate 150 includes steps S100 to S180. Steps S100 to S180 will be described below with reference to Figures 8 to 15, but the manufacturing method of the array substrate 150 is not limited thereto.

[0058] In step S100, a conductive film is deposited on the support substrate 200 using sputtering, and then the conductive film is patterned using photolithography. This forms conductive layers 202-1 and 202-2 on the support substrate 200 (see Figure 8). Conductive layers 202-1 and 202-2 are the same layer formed from a single conductive film. That is, conductive layers 202-1 and 202-2 are located in the same layer.

[0059] In step S110, an insulating layer 204 is deposited so as to cover the conductive layers 202-1 and 202-2, and then a contact hole CH1 penetrating the insulating layer 204 is formed using photolithography (see Figure 9). The insulating layer 204 is deposited, for example, using CVD. Since the contact hole CH1 is formed on top of the conductive layer 202-2, the conductive layer 202-2 is exposed in the contact hole CH1.

[0060] In step S120, a transparent conductive film is deposited on the insulating layer 204 using sputtering, and then the transparent conductive film is patterned using photolithography. This forms transparent conductive layers 206-1, 206-2, and 206-3 on the insulating layer 204 (see Figure 10). Transparent conductive layers 206-1, 206-2, and 206-3 are the same layer formed from a single transparent conductive film. That is, transparent conductive layers 206-1, 206-2, and 206-3 are located on the same layer. Note that transparent conductive layer 206-3 is formed to overlap with contact hole CH1, and therefore is in contact with conductive layer 202-2 via contact hole CH1.

[0061] In step S120, the transparent conductive layers 206-1, 206-2, and 206-3 are subjected to annealing. This causes the transparent conductive layers 206-1, 206-2, and 205-3 to crystallize.

[0062] In step S130, an oxide semiconductor film is deposited so as to cover the transparent conductive layers 206-1, 206-2, and 206-3. The oxide semiconductor film is deposited, for example, by sputtering. Then, the transparent conductive film is patterned into a predetermined shape using photolithography. This forms an oxide semiconductor layer 208 that is in contact with the transparent conductive layers 206-1 and 206-2 (see Figure 11).

[0063] In step S130, the oxide semiconductor layer 208 is subjected to annealing. Oxygen vacancies may be generated in the oxide semiconductor layer 208 due to patterning. The annealing treatment can repair the oxygen vacancies in the oxide semiconductor layer 208. For example, the annealing treatment conditions are, but are not limited to, an air atmosphere, a temperature of 300 to 450°C, and a holding time of 1 to 2 hours. The oxide semiconductor layer 208 may also crystallize as a result of the annealing treatment.

[0064] In step S140, an insulating layer 210 is deposited so as to cover the transparent conductive layers 206-1, 206-2, and 206-3 and the oxide semiconductor layer 208, and then contact holes (not shown) penetrating the insulating layers 204 and 210 are formed using photolithography. The insulating layer 210 is deposited, for example, using CVD. Furthermore, a conductive film is deposited on the insulating layer 210 using sputtering, and then the conductive film is patterned using photolithography. This forms a conductive layer 212 on the insulating layer 210 (see Figure 12). The conductive layer 212 is superimposed on the conductive layer 202-1 and the oxide semiconductor layer 208. Although not shown, the conductive layer 212 is also in contact with the conductive layer 202-1 through contact holes formed in the insulating layers 204 and 210.

[0065] In step S150, a planarization film is formed on the insulating layer 210 so as to cover the conductive layer 212, and then the planarization film is patterned using photolithography. This forms a planarization layer 214 having an opening OP in which the insulating layer 210 is exposed (see Figure 13).

[0066] In step S160, a conductive film is deposited on the planarization layer 214 and the insulating layer 210 using sputtering, and then the conductive film is patterned using photolithography. This forms a conductive layer 216 on top of the planarization layer 214 (see Figure 14).

[0067] In step S170, an insulating layer 218 is deposited so as to cover the insulating layer 210, the planarization layer 214, and the conductive layer 216, and then a contact hole CH3 is formed through the insulating layers 204, 210, and 218 using photolithography (see Figure 15). The contact hole CH3 is formed within the opening OP, and the transparent conductive layer 206-2 that is in contact with the oxide semiconductor layer 208 extending to the opening OP is exposed in the contact hole CH3.

[0068] Next, a transparent conductive film is deposited on the insulating layer 218 using sputtering, and then the transparent conductive film is patterned using photolithography. This forms a transparent conductive layer 220 on the insulating layer 218, and the array substrate 150 shown in Figure 6 is manufactured. The transparent conductive layer 220 is formed within the opening OP and is in contact with the transparent conductive layer 206-2 via the contact hole CH3.

[0069] As described above, in the display device 10 according to this embodiment, the drain electrode (transparent conductive layer 206-2) and the pixel electrode (transparent conductive layer 220) of the transistor Tr formed on the array substrate 150 are in direct contact without the use of opaque wiring. As a result, the aperture ratio of the pixel PIX is improved, and the transparency of the display device 10 is improved. Furthermore, in the manufacturing method of the array substrate 150, the formation of the source electrode (transparent conductive layer 206-1) and drain electrode (transparent conductive layer 206-2) of the transistor Tr takes place before the formation of the oxide semiconductor layer 208. Therefore, there is no damage to the oxide semiconductor layer 208 due to the formation of the source electrode and drain electrode, and damage to the back channel portion of the oxide semiconductor layer 208 is significantly reduced. Consequently, the display device 10 according to this embodiment can improve manufacturing yield without reducing transparency.

[0070] <Second Embodiment> In this embodiment, an array substrate 150A, which is different from the array substrate 150, will be described with reference to Figures 16 and 17. In the following, when the array substrate 150A has the same configuration as the array substrate 150, the description of the configuration of the array substrate 150A may be omitted.

[0071] Figure 16 is a schematic cross-sectional view showing the configuration of pixels PIX in an array substrate 150A of a display device 10 according to one embodiment of the present invention. As shown in Figure 16, the array substrate 150A includes a support substrate 200, conductive layers 202-1 and 202-2, an insulating layer 204, transparent conductive layers 206-1, 206-2, and 206-3, an oxide semiconductor layer 208, an insulating layer 210, conductive layers 212-1 and 212-2, a planarization layer 214, a conductive layer 216, an insulating layer 218, and a transparent conductive layer 220. The insulating layer 210 is provided with a contact hole CH2 through which the transparent conductive layer 206-1 is exposed. The conductive layer 212-1 is superimposed on the conductive layer 202-1 and the oxide semiconductor layer and is provided on the insulating layer 210. The conductive layer 212-2 is provided on the insulating layer 210. The conductive layer 212-2 is in contact with the transparent conductive layer 206-1 via the contact hole CH2.

[0072] Conductive layers 212-1 and 212-2 are identical layers formed from a single film. That is, conductive layers 212-1 and 212-2 are located in the same layer. Although not shown, conductive layer 212-1 is electrically connected to conductive layer 202-1 via a contact hole and functions as a back gate electrode. Conductive layer 212-2 functions as a signal line. That is, conductive layer 212-2, together with conductive layers 202-2 and 206-3, is a component of the wiring that controls the pixel PIX. Since conductive layer 212-2 has lower resistance than transparent conductive layer 206-1, using conductive layer 212-2 as wiring can reduce wiring resistance.

[0073] Here, with reference to Figure 17, the manufacturing method of the array substrate 150A will be described. Figure 17 is a schematic cross-sectional view showing the manufacturing method of the array substrate 150A according to one embodiment of the present invention. The array substrate 150A can be manufactured using the same manufacturing method as the array substrate 150, that is, according to the flowchart in Figure 7.

[0074] In step S140 of this embodiment, an insulating layer 210 is formed to cover the transparent conductive layers 206-1, 206-2, and 206-3 and the oxide semiconductor layer 208. Then, contact holes (not shown) penetrating the insulating layers 204 and 210, and a contact hole CH2 penetrating the insulating layer 210 are formed using photolithography (see Figure 17). The transparent conductive layer 206-1 is exposed in the contact hole CH2. The contact hole CH2 penetrating the insulating layer 210 is formed simultaneously with the contact holes penetrating the insulating layers 204 and 210. However, since the contact hole CH2 is formed in superimposition with the transparent conductive layer 206-1, the transparent conductive layer 206-1 functions as an etch stop layer, and the insulating layer 204 is not etched in the contact hole CH2.

[0075] Furthermore, in step S140 of this embodiment, a conductive film is deposited on the insulating layer 210 using sputtering, and then the conductive film is patterned using photolithography. This forms conductive layers 212-1 and 212-2 on the insulating layer 210. Although not shown, conductive layer 212-1 is in contact with conductive layer 202-1 through contact holes formed in the insulating layers 204 and 210. Conductive layer 212-2 is in contact with transparent conductive layer 206-1 through contact hole CH2. Thus, in this embodiment, conductive layers 212-1 and 212-2, which are formed as the same layer, can be electrically connected to conductive layers or transparent conductive layers of different layers through contact holes of different depths.

[0076] As described above, in the display device 10 according to this embodiment, the drain electrode (transparent conductive layer 206-2) and the pixel electrode (transparent conductive layer 220) of the transistor Tr formed on the array substrate 150A are in direct contact without the use of opaque wiring. As a result, the aperture ratio of the pixel PIX is improved, and the transparency of the display device 10 is improved. Furthermore, by using the conductive layer 212-2, which is formed as the same layer as the back gate electrode (conductive layer 212-1), as wiring, the wiring resistance can be reduced. Moreover, in the manufacturing method of the array substrate 150, the formation of the source electrode (transparent conductive layer 206-1) and drain electrode (transparent conductive layer 206-2) of the transistor Tr is performed before the formation of the oxide semiconductor layer 208. Therefore, there is no damage to the oxide semiconductor layer 208 due to the formation of the source electrode and drain electrode, and damage to the back channel portion of the oxide semiconductor layer 208 is significantly reduced. Thus, in the display device 10 according to this embodiment, the manufacturing yield can be improved without reducing transparency.

[0077] <Third Embodiment> In this embodiment, array substrate 150B, which is different from array substrates 150 and 150A, will be described with reference to Figures 18 and 19. In the following, when array substrate 150B has the same configuration as array substrates 150 and 150A, the description of the configuration of array substrate 150B may be omitted.

[0078] Figure 18 is a schematic cross-sectional view showing the configuration of pixels PIX in an array substrate 150B of a display device 10 according to one embodiment of the present invention. As shown in Figure 18, the array substrate 150B includes a support substrate 200, a conductive layer 202-1, an insulating layer 204, transparent conductive layers 206-1, 206-2, and 206-3, an oxide semiconductor layer 208, an insulating layer 210, conductive layers 212-2 and 212-3, an insulating layer 222, a conductive layer 224, a planarization layer 214, a conductive layer 216, an insulating layer 218, and a transparent conductive layer 220. The insulating layer 210 is provided with a contact hole CH2-1 in which the transparent conductive layer 206-1 is exposed and a contact hole CH2-2 in which the transparent conductive layer 206-3 is exposed. The conductive layers 212-2 and 212-3 are provided on top of the insulating layer 210. The conductive layer 212-2 is in contact with the transparent conductive layer 206-1 via a contact hole CH2-1. The conductive layer 212-3 is in direct contact with the transparent conductive layer 206-3 via a contact hole CH2-2. The insulating layer 222 is provided to cover the conductive layers 212-2 and 212-3. The conductive layer 224 is superimposed on the conductive layer 202-1 and the oxide semiconductor layer 208 and is provided on top of the insulating layer 222. At the opening OP, the insulating layers 210, 222, and 218 are provided with a contact hole CH3 through which the transparent conductive layer 206-2 is exposed.

[0079] Conductive layers 212-2 and 212-3 are identical layers formed from a single film. That is, conductive layers 212-2 and 212-3 are located in the same layer. Conductive layers 212-2 and 212-3 function as signal lines. In other words, conductive layers 212-2 and 212-3 are components of the wiring that controls the pixels (PIX). Since conductive layers 212-2 and 212-3 have lower resistance than transparent conductive layers 206-1 and 206-3, using conductive layers 212-2 and 212-3 as wiring can reduce wiring resistance. Although not shown, conductive layer 224 is electrically connected to conductive layer 202-1 via a contact hole and functions as a back gate electrode.

[0080] A nitride similar to that used for insulating layer 204 can be used for insulating layer 222.

[0081] The same material as that used for conductive layer 202-1 can be used for conductive layer 224.

[0082] Now, with reference to Figure 19, the method for manufacturing the array substrate 150B will be described. Figure 19 is a cross-sectional view showing the method for manufacturing the array substrate 150B according to one embodiment of the present invention. As shown in Figure 19, the method for manufacturing the array substrate 150B includes step S145 after step S140 in the flowchart shown in Figure 7.

[0083] In step S140 of this embodiment, an insulating layer 210 is formed to cover the transparent conductive layers 206-1, 206-2, and 206-3 and the oxide semiconductor layer 208, and then contact holes CH2-1 and CH2-2 penetrating 210 are formed using photolithography. The transparent conductive layers 206-1 and 206-3 are exposed in the contact holes CH2-1 and CH2-2, respectively. Furthermore, a conductive film is formed on the insulating layer 210 using sputtering, and then the conductive film is patterned using photolithography. This forms conductive layers 212-2 and 212-3 on the insulating layer 210. Conductive layer 212-2 is in contact with transparent conductive layer 206-1 via contact hole CH2-1. Conductive layer 212-3 is in contact with transparent conductive layer 206-3 via contact hole CH2-2.

[0084] In step S145 of this embodiment, an insulating layer 222 is formed to cover conductive layers 212-2 and 212-3, and then contact holes are formed through the insulating layers 204, 210, and 222 using photolithography. The conductive layer 202-1 is exposed through the contact holes. Furthermore, a conductive film is formed on the insulating layer 222 using sputtering, and then the conductive film is patterned using photolithography. This forms a conductive layer 224 on the insulating layer 222. The conductive layer 224 is superimposed on the conductive layer 202-1 and the oxide semiconductor layer 208. The conductive layer 224 is also in contact with the conductive layer 202-1 through the contact holes formed in the insulating layers 204, 210, and 222.

[0085] As described above, in the display device 10 according to this embodiment, the drain electrode (transparent conductive layer 206-2) and the pixel electrode (transparent conductive layer 220) of the transistor Tr formed on the array substrate 150B are in direct contact without the use of opaque wiring. As a result, the aperture ratio of the pixel PIX is improved, and the transparency of the display device 10 is improved. Furthermore, by using conductive layers 212-2 and 212-3 as wiring, the wiring resistance can be reduced. Moreover, in the manufacturing method of the array substrate 150, the formation of the source electrode (transparent conductive layer 206-1) and drain electrode (transparent conductive layer 206-2) of the transistor Tr takes place before the formation of the oxide semiconductor layer 208. Therefore, there is no damage to the oxide semiconductor layer 208 due to the formation of the source electrode and drain electrode, and damage to the back channel portion of the oxide semiconductor layer 208 is significantly reduced. Thus, in the display device 10 according to this embodiment, the manufacturing yield can be improved without reducing transparency.

[0086] While preferred embodiments have been described above, this disclosure is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various modifications are possible without departing from the spirit of this disclosure. Any modifications made without departing from the spirit of this disclosure will naturally fall within the technical scope of this disclosure. Furthermore, the embodiments described above can be combined as appropriate, as long as they do not contradict each other. Moreover, any other effects and benefits that differ from those brought about by the embodiments described above, if they are clear from the description herein or can be easily predicted by a person skilled in the art, will naturally be considered to be brought about by the present invention. [Explanation of symbols]

[0087] 10: Display device, 10A: First main surface, 12: Display area, 14: Peripheral area, 15A: First plane, 15B: Second plane, 15C: First end face, 16: Common wiring, 18: Common wiring, 20A: First main surface, 22: Common wiring area, 24: Flexible printed circuit, 26: Terminal section, 28: Gate drive circuit, 32: Gate wiring area, 34: Flexible printed circuit, 36: Terminal section, 38: Source drive circuit, 42: Source wiring area, 46: ESD protection circuit, 48: Gate inspection circuit, 52: Source inspection circuit, 54: Inspection line, 56: QD pad, 58: ESD protection circuit, 59: ESD protection circuit, 102: Display panel, 104: Light source, 109: Data signal line, 110: Light emission control circuit, 150, 150A, 150B: Array substrate, 151A: First transparent substrate, 151B: Second transparent substrate, 152: Opposing substrate, Liquid crystal layer: 153, 154: Sealing material, 200: Support substrate, 202-1, 202-2, 212, 212-1, 212-2, 212-3, 216, 224: Conductive layer, 204, 204a, 204b, 210, 210a, 210b, 218, 222: Insulating layer, 206-1, 206-2, 206-3, 220: Transparent conductive layer, 208: Oxide semiconductor layer, 214: Planarization layer, C: Holding capacitance, CL: Common wiring, CW: Capacitive wiring, ESD: Common wiring, GL: Gate wiring, PIX: Pixel, SL: Source wiring

Claims

1. A first conductive layer and The first insulating layer on the first conductive layer, A first transparent conductive layer and a second transparent conductive layer on the first insulating layer, On the first transparent conductive layer and the second transparent conductive layer, an oxide semiconductor layer in contact with the first transparent conductive layer and the second transparent conductive layer, A second insulating layer on the oxide semiconductor layer, The second conductive layer on the second insulating layer, The first transparent conductive layer and the second transparent conductive layer are located in the same layer. A display device in which the oxide semiconductor layer is superimposed on the first conductive layer and the second conductive layer.

2. moreover, A planarization layer located on the second conductive layer and having a first opening, A transparent pixel electrode having a region located at the first aperture, The display device according to claim 1, wherein the transparent pixel electrode is in direct contact with the second transparent conductive layer through a second opening provided in the second insulating layer.

3. Furthermore, it includes a third conductive layer located in the same layer as the second conductive layer, The display device according to claim 1, wherein the third conductive layer is in direct contact with at least one of the first transparent conductive layer and the second transparent conductive layer through a second opening provided in the second insulating layer.

4. Furthermore, it includes a fourth conductive layer located in a different layer from the second conductive layer, The display device according to claim 1, wherein the fourth conductive layer is in direct contact with at least one of the first transparent conductive layer and the second transparent conductive layer through a second opening provided in the second insulating layer.

5. The display device according to claim 4, wherein the second conductive layer is located above the fourth conductive layer.

6. moreover, A fifth conductive layer formed as the same layer as the first conductive layer, The present invention includes a third transparent conductive layer located in the same layer as the first transparent conductive layer and the second transparent conductive layer, The display device according to claim 1, wherein the third transparent conductive layer is in direct contact with the fifth conductive layer through a third opening provided in the first insulating layer.

7. The display device according to claim 6, wherein the fifth conductive layer is a signal line.

8. The display device according to any one of claims 1 to 7, wherein each of the first transparent conductive layer and the second transparent conductive layer is crystalline.

9. The display device according to any one of claims 1 to 7, wherein the oxide semiconductor layer is crystalline.

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