Power factor correction circuit
The power factor correction circuit addresses surge voltages and EMI noise in totem-pole type PFC circuits by discharging output capacitance during the dead time and controlling leg switching sequences to minimize voltage stress and noise.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-09-30
- Publication Date
- 2026-04-09
AI Technical Summary
Totem-pole type PFC circuits experience large surge voltages between the drain and source of switching elements during the first switching of each half-cycle, exceeding the voltage rating of the elements and generating significant EMI noise.
A power factor correction circuit with a high-frequency leg and a commercial leg, incorporating a discharge circuit to discharge output capacitance during the dead time at the start of a half-cycle, and controlling the commercial leg to turn on before the high-frequency leg, thereby suppressing surge voltages and EMI noise.
Surge voltages and EMI noise are effectively suppressed, ensuring reliable operation and reduced stress on switching elements.
Smart Images
Figure 2026061381000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a power factor improvement circuit having a high-frequency leg and a commercial leg.
Background Art
[0002] A power factor improvement circuit having a high-frequency leg and a commercial leg is called a totem-pole bridgeless PFC (Totem-Pole Bridgeless PFC) circuit. The commercial leg is composed of a pair of switching elements connected in series that perform a switching operation at the frequency of the input AC voltage. The high-frequency leg is composed of another pair of switching elements connected in series that perform a switching operation at a frequency higher than the frequency of the input AC voltage. Such a power factor improvement circuit can suppress switching losses and stress generated in the switching elements by the switching elements of the high-frequency leg performing ZVS (Zero Voltage Switching) turn-on, and can achieve high efficiency (for example, refer to Non-Patent Document 1).
Prior Art Documents
Non-Patent Documents
[0003]
Non-Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] However, in totem-pole type PFC circuits, the large surge voltage generated between the drain and source of the switching elements during the first switching of each half-cycle can exceed the voltage rating of the switching elements. Furthermore, large surge voltages simultaneously generate significant EMI noise.
[0005] One aspect of the present invention provides a power factor correction circuit that can suppress the surge voltage generated between the drain and source of a switching element during the first switching of each half-cycle. [Means for solving the problem]
[0006] A power factor correction circuit according to one aspect of the present invention comprises a high-frequency leg connected to an AC voltage via an inductor and a commercial leg directly connected to the AC voltage. The power factor correction circuit converts the AC voltage to a DC voltage by controlling the commercial leg to turn on and off at the frequency of the AC voltage, and the high-frequency leg to turn on and off at a frequency higher than the frequency of the AC voltage. The power factor correction circuit includes a discharge circuit for discharging the output capacitance of the commercial leg. After discharging the output capacitance by the discharge circuit during the dead time at the start of a half-cycle, the power factor correction circuit turns on the commercial leg before the high-frequency leg. [Effects of the Invention]
[0007] According to one aspect of the present invention, surge voltage generated between the drain and source of a switching element during the first switching of each half-cycle can be suppressed, thereby suppressing EMI noise. [Brief explanation of the drawing]
[0008] [Figure 1] This diagram shows the circuit configuration of an embodiment of the power factor correction circuit. [Figure 2] This figure shows the AC voltage, inductor current, and drive signal. [Figure 3] This diagram shows the current path of the inductor current iL. [Figure 4] This diagram shows the charge and discharge operation at the start of a half-cycle. [Figure 5] This diagram shows the surge voltage associated with charging and discharging operations. [Figure 6] This diagram shows the operation of the discharge circuit. [Figure 7] This is a diagram showing an example of a discharge circuit configuration. [Modes for carrying out the invention]
[0009] The embodiments of the present invention will now be described in detail with reference to the figures. In the following embodiments, components that have the same function are denoted by the same reference numerals and their descriptions are omitted as appropriate.
[0010] The power factor correction circuit 1 of this embodiment is a totem-pole type PFC circuit that converts an AC voltage Vin to a DC voltage Vo. Referring to Figure 1, the power factor correction circuit 1 comprises an inductor L, a high-frequency leg 11, a commercial-frequency leg 12, and a capacitor Co.
[0011] The high-frequency leg 11 comprises a pair of high-frequency upper switching elements SW1 (hereinafter referred to as high-frequency upper SW1) and a high-frequency lower switching element SW2 (hereinafter referred to as high-frequency lower SW2) connected in series. The connection point between the high-frequency upper SW1 and the high-frequency lower SW2 of the high-frequency leg 11 is connected to an AC voltage Vin via an inductor L.
[0012] The commercial leg 12 comprises a pair of commercial-powered switching elements SW3 (hereinafter referred to as commercial-powered SW3) and commercial-powered switching elements SW4 (hereinafter referred to as commercial-powered SW4) connected in series. The connection point between commercial-powered SW3 and commercial-powered SW4 of the commercial leg 12 is directly connected to the AC voltage Vin.
[0013] In the power factor correction circuit 1, both ends of the high-frequency leg 11 and both ends of the commercial-voltage leg 12 are connected in parallel to both ends of the capacitor Co, and a DC voltage Vo is obtained from the capacitor Co.
[0014] The power factor improvement circuit 1 includes a control circuit 20. The control circuit 20 generates and outputs respective drive signals (gate signals) G3 and G4 for on / off controlling the commercial upper SW3 and the commercial lower SW4 at the frequency of the AC voltage Vin. The drive signals G3 and G4 are supplied to the gate terminals of the commercial upper SW3 and the commercial lower SW4. The control circuit 20 generates and outputs respective drive signals (gate signals) G1 and G2 for on / off controlling the high-frequency upper SW1 and the high-frequency lower SW2 at a frequency higher than the frequency of the AC voltage Vin. The drive signals G1 and G2 are supplied to the gate terminals of the high-frequency upper SW1 and the high-frequency lower SW2.
[0015] FIG. 2 shows the inductor current i in the positive half-cycle of the AC voltage Vin ,
[0017] , , ,
[0016] and the drive signals G1 to G4. FIG. 3 shows the current path of the inductor current i in the positive half-cycle. Referring to FIG. 2, the control circuit 20 controls the commercial upper SW3 to be in the off state and the commercial lower SW4 to be in the on state respectively in the positive half-cycle. L Referring to FIG. 2, in the positive half-cycle, the control circuit 20 controls the commercial upper SW3 to be in the off state and the commercial lower SW4 to be in the on state respectively.
[0016] In the positive half-cycle, the control circuit 20 complementarily on / off controls the high-frequency upper SW1 and the high-frequency lower SW2 at a frequency higher than the frequency of the AC voltage Vin. When the high-frequency lower SW2 turns on from the off state (dead time) of the high-frequency upper SW1 and the high-frequency lower SW2, as shown in FIG. 3(a), it becomes the excitation period in which the inductor L is charged. Next, when the high-frequency lower SW2 turns off and the high-frequency upper SW1 turns on across the dead time, as shown in FIG. 3(b), it becomes the regeneration period in which the inductor L is discharged. After that, if the high-frequency upper SW1 continues to be on even after the timing when the current of the inductor L becomes zero, as shown in FIG. 3(c), the polarity of the current is reversed and it becomes the reverse current period. When the high-frequency upper SW1 turns off during this reverse current period, as shown in FIG. 3(d), the body diode of the high-frequency upper SW2 conducts. By turning on the high-frequency lower SW2 at this timing, ZVS (zero voltage switching) turn-on is realized.
[0016] In the positive half-cycle, the control circuit 20 complementarily on / off controls the high-frequency upper SW1 and the high-frequency lower SW2 at a frequency higher than the frequency of the AC voltage Vin. When the high-frequency lower SW2 turns on from the off state (dead time) of the high-frequency upper SW1 and the high-frequency lower SW2, as shown in FIG. 3(a), it becomes the excitation period in which the inductor L is charged. Next, when the high-frequency lower SW2 turns off and the high-frequency upper SW1 turns on across the dead time, as shown in FIG. 3(b), it becomes the regeneration period in which the inductor L is discharged. After that, if the high-frequency upper SW1 continues to be on even after the timing when the current of the inductor L becomes zero, as shown in FIG. 3(c), the polarity of the current is reversed and it becomes the reverse current period. When the high-frequency upper SW1 turns off during this reverse current period, as shown in FIG. 3(d), the body diode of the high-frequency upper SW2 conducts. By turning on the high-frequency lower SW2 at this timing, ZVS (zero voltage switching) turn-on is realized.
[0017] The high-frequency upper SW1, high-frequency lower SW2, commercial upper SW3, and commercial lower SW4 are composed of switching elements such as GaN devices and SiC (Silicon Carbide) devices (for example, field-effect transistors (MOSFETs: metal-oxide-semiconductor field-effect transistors)). Therefore, there are parasitic capacitances in the high-frequency upper SW1, high-frequency lower SW2, commercial upper SW3, and commercial lower SW4. Among these parasitic capacitances, the output capacitance Coss is charged and discharged between 0V and the DC voltage Vo during the switching operation.
[0018] Figure 4(a) shows the charging state of the output capacitance Coss at the dead time at the start of the positive half-cycle. The output capacitances Coss of the high-frequency lower SW2 and commercial lower SW4 are charged to the DC voltage Vo. The high-frequency lower SW2 and commercial lower SW4 are turned on from the state where the output capacitance Coss is charged to the DC voltage Vo.
[0019] When the high-frequency lower SW2 in the high-frequency leg 11 is first turned on, as shown by the solid-line arrow in Figure 4(b), the output capacitance Coss of the high-frequency lower SW2 is short-circuited and discharged, and the output capacitance Coss of the high-frequency upper SW1 is directly charged from the DC voltage Vo. Since the charging and discharging current of the high-frequency leg 11 is steep, that is, di / dt is large, the drain-source voltage Vds of the high-frequency upper SW1 is a large surge voltage (L s di / dt) generated by the parasitic inductance existing in the current path. Subsequently, ringing occurs in the drain-source voltage VdS of the high-frequency upper SW1 due to the resonance of the output capacitance Coss and the parasitic inductance.
[0020] As shown by the dotted-line arrow in Figure 4(b), the output capacitance Coss of the commercial upper SW3 is charged and the output capacitance Coss of the commercial lower SW4 is discharged. Since the charging and discharging current of the commercial leg 12 passes through the inductor L, di / dt is relatively small, and no large surge voltage occurs in the drain-source voltage Vds of the commercial upper SW3.
[0021] When the commercial-under SW4 of commercial leg 12 is first turned on, the output capacitance Coss of the commercial-under SW4 is short-circuited and discharged, as shown by the solid arrow in Figure 4(c), and the output capacitance Coss of the commercial-upper SW3 is directly charged from the DC voltage Vo. Because the charge / discharge current of commercial leg 12 is steep, i.e., di / dt is large, the drain-source voltage Vds of the commercial-upper SW3 undergoes a large surge voltage (L) due to the parasitic inductance present in the current path, as shown in Figure 5(b). s di / dt) occurs. Commercially, the drain-source voltage Vds of SW3 subsequently rings due to resonance between the output capacitance Coss and the parasitic inductance.
[0022] As shown by the dotted arrows in Figure 4(c), the output capacitance Coss of the high-frequency upper SW1 is charged, and the output capacitance Coss of the high-frequency lower SW1 is discharged. Since the charge / discharge current of the high-frequency leg 11 is mediated through the inductor L, the di / dt is relatively small, and no large surge voltage occurs in the drain-source voltage Vds of the high-frequency upper SW1. Thus, regardless of whether the high-frequency leg 11 or the commercial leg 12 is turned on first from the dead time at the start of the half-cycle, a large surge voltage will occur.
[0023] Therefore, the power factor correction circuit 1 of this embodiment includes a discharge circuit 13 for discharging the output capacitance Coss. The discharge circuit 13 includes a series circuit consisting of an upper discharge switch SW5 and a discharge resistor DR connected between the drain and source of the upper commercial SW3 of the commercial leg 12, and a series circuit consisting of a lower discharge switch SW6 and a discharge resistor DR, respectively, connected between the drain and source of the lower commercial SW4 of the commercial leg 12.
[0024] The on / off states of the discharge upper switch SW5 and the discharge lower switch SW6 are controlled by control signals G5 and G6 from the control circuit 20, respectively. The control circuit 20 discharges the charged output capacity Coss of either the commercial upper switch SW3 or the commercial lower switch SW4 by turning on either the discharge upper switch SW5 or the discharge lower switch SW6 during the dead time at the start of the half-cycle. The discharge resistor DR is provided for adjusting the discharge time constant (τ=CR).
[0025] Referring to Figure 6, the control circuit 20 turns on the discharge switch SW6 during the dead time at the start of the positive half-cycle to discharge the output capacitance Coss, and then turns on the commercial power SW4 first. That is, the control circuit 20 discharges the output capacitance Coss of the commercial power SW4, which is charged during the dead time at the start of the positive half-cycle, and then starts switching the commercial power leg 12 (commercial power SW4) before the high-frequency leg 11 (high-frequency power SW2). As a result, there is no discharge current of the output capacitance Coss when the commercial power leg 12 (commercial power SW4) is first turned on, so di / dt becomes small, and the generation of surge voltage (Ldi / dt) can be suppressed, as shown in Figure 6.
[0026] Referring to Figure 6, the control circuit 20 turns on the discharge switch SW5 during the dead time at the start of the negative half-cycle to discharge the output capacitance Coss, and then turns on the commercial power SW3 first. In other words, the control circuit 20 discharges the output capacitance Coss of the commercial power SW3, which is charged during the dead time at the start of the negative half-cycle, and then starts switching the commercial leg 12 (commercial power SW3) before the high-frequency leg 11 (high-frequency power SW1). As a result, there is no discharge current of the output capacitance Coss when the commercial leg 12 (commercial power SW4) is first turned on, so di / dt becomes small and the generation of surge voltage (Ldi / dt) can be suppressed.
[0027] Referring to Figure 7(a), the discharge-up switch SW5 can be configured with the light-receiving section of photorelay PR5, and the discharge-down switch SW6 can be configured with the light-receiving section of photorelay PR6. The control circuit 20 turns on the light-emitting diodes of photorelays PR5 and PR6 by setting the control signals G5 and G6 to high levels, thereby turning on the light-receiving sections (MOSFETs) of photorelays PR5 and PR6. Photorelays PR5 and PR6 can transmit the control signals G5 and G6 to the discharge-up switch SW5 and discharge-down switch SW6 respectively while maintaining electrical isolation from the control circuit 20. When using photorelays PR5 and PR6, there is no need to add a gate driver or power supply for the discharge circuit.
[0028] Referring to Figure 7(b), when switching elements such as MOSFETs are used as the upper discharge switch SW5 and the lower discharge switch SW6, the on / off state can be controlled by transmitting control signals G5 and G6, respectively, via photocouplers PC5 and PC6. The light-receiving part of photocoupler PC5, which controls the on / off state of the upper discharge switch SW5, utilizes the voltage from the bootstrap circuit 14, eliminating the need for additional gate drivers or power supplies for the discharge circuit.
[0029] Furthermore, the power factor correction circuit 1 of this embodiment only needs to be equipped with a commercial leg 12, and can also be used in an interleaved configuration with multiple high-frequency legs 11.
[0030] (summary) (1) Each embodiment of the present invention comprises a power factor correction circuit 1, which includes a high-frequency leg 11 connected to an AC voltage Vin via an inductor L, and a commercial leg 12 directly connected to the AC voltage Vin. The power factor correction circuit 1 includes a discharge circuit 13 for discharging the output capacitance Coss of the commercial leg 12. The power factor correction circuit 1 discharges the output capacitance Coss by the discharge circuit 13 during the dead time at the start of the half-cycle, and then turns on the commercial leg 12 before the high-frequency leg 11.
[0031] According to the power factor correction circuit 1 described in (1) above, surge voltages generated between the drain and source of the switching elements (high frequency upper SW1, high frequency lower SW2, commercial power upper SW3, commercial power lower SW4) during the first switching of each half-cycle can be suppressed, thereby suppressing EMI noise.
[0032] (2) In the power factor correction circuit 1 described in (1) above, the discharge circuit 13 is a series circuit consisting of a discharge resistor DR and a discharge switch (discharge upper SW5, discharge lower SW6) connected between the high-potential side terminal (drain) and the low-potential side terminal (source) of the switching element (commercial upper switch SW3, commercial lower switch SW4) of the commercial leg 12.
[0033] According to the power factor correction circuit 1 described in (2) above, the discharge time constant (τ=CR) when discharging the output capacitance Coss can be adjusted.
[0034] (3) In the power factor correction circuit 1 described in (2) above, the discharge switch is the light receiving part of the photorelay.
[0035] According to the power factor correction circuit 1 described in (3) above, there is no need to add a gate driver or power supply for the discharge circuit.
[0036] Although the present invention has been described above with reference to specific embodiments, it goes without saying that these embodiments are merely examples and can be modified and implemented without departing from the spirit of the present invention. [Explanation of Symbols]
[0037] 1. Power Factor Correction Circuit 11 High-frequency legs 12 Commercial Legs 13 Discharge circuit 14 Bootstrap Circuit 20 Control circuits C1, Co capacitor Coss output capacity D1 diode L Inductor SW1 High-Frequency Switching Element SW2 High-Frequency Switching Element SW3 Commercial Switching Element SW4 Commercial Switching Element SW5 Discharge Up Switch SW6 Discharge Down Switch Vin AC voltage Vo DC voltage
Claims
1. A power factor correction circuit comprising a high-frequency leg connected to an AC voltage via an inductor and a commercial leg directly connected to the AC voltage, wherein the commercial leg is switched on and off at the frequency of the AC voltage and the high-frequency leg at a frequency higher than the frequency of the AC voltage, thereby converting the AC voltage to a DC voltage, The system includes a discharge circuit for discharging the output capacity of the aforementioned commercial leg, A power factor correction circuit that discharges the output capacitance by the discharge circuit during the dead time at the start of the half-cycle, and then turns on the commercial leg before the high-frequency leg.
2. The power factor correction circuit according to claim 1, wherein the discharge circuit is a series circuit consisting of a discharge resistor and a discharge switch connected between the high-potential terminal and the low-potential terminal of the switching element of the commercial leg.
3. The power factor correction circuit according to claim 2, wherein the discharge switch is the light receiving part of a photorelay.