Image sensor

Abstract

The present invention provides an image sensor that allows the output of any one or more pixels to be selected and output to an output line. [Solution] The image sensor comprises a first photoelectric conversion unit, a second photoelectric conversion unit, a first floating diffusion unit, a second floating diffusion unit, a first transistor, a second transistor, a first output unit that outputs a first signal and a second signal, a second output unit that outputs a third signal and a fourth signal, and an output line on which a first binning process is performed using the first signal output from the first output unit and the third signal output from the second output unit, and a second binning process is performed using the second signal output from the first output unit and the fourth signal output from the second output unit.

Description

Technical Field

[0001] The present invention relates to an imaging device.

Background Art

[0002] Conventionally, an imaging device that uses a part of pixels as an element for detecting the focus of an image formed by an imaging lens has been known (for example, Patent Document 1). The values of the signals output from the pixels used for focus detection and the pixels used for imaging are different.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] According to a first aspect of the present invention, the image sensor comprises a first photoelectric conversion unit that converts light into electric charge, a second photoelectric conversion unit that converts light into electric charge, a first floating diffusion unit to which the charge converted by the first photoelectric conversion unit is transferred, a second floating diffusion unit to which the charge converted by the second photoelectric conversion unit is transferred, a transistor for electrically connecting the first floating diffusion unit and a first supply unit to which a first voltage is supplied, the first transistor for discharging the charge from the first floating diffusion unit, the second transistor for electrically connecting the second floating diffusion unit and a second supply unit to which a second voltage lower than the first voltage and a third voltage lower than the second voltage are supplied, the second transistor for discharging the charge from the second floating diffusion unit, and a third transistor including a gate portion electrically connected to the first floating diffusion unit, the output unit comprising a first signal based on the charge transferred from the first photoelectric conversion unit to the first floating diffusion unit, and the first transistor The device comprises: a first output unit that outputs a second signal based on the charge of the first floating diffusion unit when charge is discharged from the first floating diffusion unit to the first supply unit; a second output unit having a fourth transistor including a gate unit electrically connected to the second floating diffusion unit, wherein the second transistor outputs a third signal based on the charge of the second floating diffusion unit when charge is discharged from the second floating diffusion unit to the second supply unit to which the third voltage is supplied; and a fourth signal based on the charge of the second floating diffusion unit when charge is discharged from the second floating diffusion unit to the second supply unit to which the second voltage is supplied; and an output line on which a first binning process is performed using the first signal output from the first output unit and the third signal output from the second output unit, and a second binning process is performed using the second signal output from the first output unit and the fourth signal output from the second output unit. [Brief explanation of the drawing]

[0005] [Figure 1] A schematic cross-sectional view showing the configuration of the imaging device. [Figure 2] A plan view of the image sensor as seen from the imaging surface side. Figure 2(a) is an overall view of the image sensor, and Figure 2(b) is a magnified view of a part of it. [Figure 3] A schematic diagram of a portion of the pixels of an image sensor and the readout circuit. [Figure 4] Circuit diagram of the control unit for the image sensor. [Figure 5] A timing chart showing an example of the image sensor's operation. [Figure 6] Cross-sectional view of the image sensor. [Figure 7] Cross-sectional view of the imaging pixel and the focus detection pixel. [Modes for carrying out the invention]

[0006] (Embodiment of an imaging device) Figure 1 is a schematic cross-sectional view showing the configuration of an imaging device using an image sensor according to the first embodiment. The imaging device 1 comprises an imaging optical system 2, an image sensor 3, a control unit 4, a lens movement unit 5, and a display unit 6.

[0007] The imaging optical system 2 forms an image of the subject on the imaging surface of the image sensor 3. The imaging optical system 2 consists of lens 2a, focusing lens 2b, and lens 2c. Focusing lens 2b is a lens used to adjust the focus of the imaging optical system 2. Focusing lens 2b is configured to be movable in the optical axis Z direction.

[0008] The lens movement unit 5 has an actuator (not shown). The lens movement unit 5 moves the focusing lens 2b in the optical axis Z direction using this actuator. The image sensor 3 captures an image of the subject and outputs a signal. The image sensor 3 has imaging pixels and AF pixels (focus detection pixels). The imaging pixels output a signal (image signal) used for image generation. The AF pixels output a signal (focus detection signal) used for focus detection. The control unit 4 controls each part, such as the image sensor 3. The control unit 4 generates image data by performing image processing on the image signal output by the image sensor 3. The control unit 4 records the image data on a recording medium (not shown) or displays an image based on the image data on the display unit 6. The control unit 4 can also be interpreted as a generation unit that generates an image based on the image signal. The display unit 6 is a display device having a display element such as a liquid crystal panel.

[0009] Furthermore, the control unit 4 performs focus detection processing necessary for autofocus (AF) of the imaging optical system 2 using a known phase difference detection method. Specifically, the control unit 4 detects the focus position of the focusing lens 2b so that the image from the imaging optical system 2 is formed on the imaging surface of the image sensor 3. Based on a pair of focus detection signals output from the image sensor 3, the control unit 4 detects the amount of image shift between the first and second images. Based on the detected amount of image shift, the control unit 4 calculates the amount of deviation (defocus amount) between the current position of the focusing lens 2b and the focus position. Focus adjustment is performed automatically by driving the focusing lens 2b according to the defocus amount.

[0010] (Embodiment of the image sensor) Figure 2(a) is a view of the image sensor 3 of an embodiment of the present invention, seen from the imaging surface side, that is, from the -Z side in Figure 1. The image sensor 3 has a plurality of pixels 30 arranged in the x and y directions in Figure 2. Although partially omitted in Figure 2, the pixels 30 may be arranged in large numbers, for example, 1000 or more, in both the x and y directions. In the region where multiple pixels 30 are arranged (imaging region), a horizontal control unit HC is provided at the left end of the figure, and a vertical control unit VC is provided at the top end of the figure. The horizontal control unit HC and the vertical control unit VC together are also called the control unit CU.

[0011] (Pixel block configuration) The image sensor 3 has multiple pixel blocks BC. In Figure 2, one pixel block BC has multiple pixels 30 arranged in the x and y directions within the region enclosed by the boundary line BB shown by the dashed line. The region enclosed by the boundary line BB constitutes one pixel block BC. Within each pixel block BC, the multiple pixels 30 are connected to one output line and one readout unit, as will be described later. Note that the multiple pixels 30 within each pixel block BC may be connected to multiple output lines and multiple readout units. In Figure 2, hatching is applied to the area corresponding to one pixel block BC for ease of explanation. However, each region enclosed by the dashed boundary line BB is a pixel block BC. Multiple pixels 30 are divided and arranged within multiple pixel blocks BC.

[0012] In the example shown in Figure 2, a total of 16 pixels 30, arranged 4 in the x-direction and 4 in the y-direction, constitute one pixel block BC. The number of pixels arranged in the x-direction and y-direction within one pixel block BC is not limited to 4; it could be 6, 8, or other numbers. The number of pixels arranged in the x-direction and y-direction may also be different. Furthermore, the outer shape of the pixel block BC is not limited to the rectangle shown in Figure 2, but may be any shape that encloses multiple pixels 30. In this case, the shape of the boundary line BB is not a simple straight line, but rather a shape formed by multiple straight lines bending and connecting.

[0013] Figure 2(b) is a magnified view of two pixel blocks BC1 and BC2, which are adjacent in the x-direction, from the pixel block BC shown in Figure 2(a). As shown in Figure 2(b), each of the multiple pixels 30 is provided with one of three color filters having different spectral characteristics, such as R (red), G (green), and B (blue). The R color filter mainly transmits light in the red wavelength range, the G color filter mainly transmits light in the green wavelength range, and the B color filter mainly transmits light in the blue wavelength range. Each pixel has different spectral characteristics depending on the color filter it is fitted with. The pixels 30 include pixels sensitive to red (R) light (hereinafter referred to as R pixels R), pixels sensitive to green (G) light (hereinafter referred to as G pixels G), and pixels sensitive to blue (B) light (hereinafter referred to as B pixels B). These pixels 30 are arranged in a so-called Bayer array. G pixels Gb are G pixels positioned in the same y-direction as B pixels B, and G pixels Gr are G pixels positioned in the same y-direction as R pixels R.

[0014] Pixel block BC1 has four G pixels Gb, four G pixels Gr, four R pixels R, and four B pixels B arranged in a Bayer array. These pixels 30 are all imaging pixels Gb, Gr, R, and B (hereinafter collectively referred to as imaging pixels 30c) used to capture the optical image formed on the imaging surface of the image sensor 3.

[0015] Pixel block BC2 has an arrangement of pixels 30 inside that is almost the same as pixel block BC1, but some of the pixels in the locations where pixel B is located in pixel block BC1 are replaced with special pixels Z1 and Z2 (collectively called special pixels ZZ), which are different from the aforementioned imaging pixels 30c.

[0016] Special pixels ZZ are, for example, AF pixels, and their configuration will be described later. The special pixel ZZ is not limited to an AF pixel, and may also be a pixel whose sensitivity differs from any of the aforementioned imaging pixels 30c. Furthermore, it may be a pixel having a color filter whose spectral characteristics differ from any of the aforementioned imaging pixels 30c.

[0017] The pixel block BC2 includes at least one special pixel ZZ as a plurality of pixels 30 and has a plurality of imaging pixels 30c. At least one pixel block BC among the plurality of pixel blocks BC is composed of at least one special pixel ZZ and a plurality of imaging pixels 30c like the pixel block BC2. All of the plurality of pixel blocks BC of the imaging device 3 may be composed of pixel blocks BC2 including special pixels ZZ. At least one of the plurality of pixel blocks BC of the imaging device 3 may be a pixel block BC2 including a special pixel ZZ, and the other pixel blocks BC may all be pixel blocks BC composed of imaging pixels 30c.

[0018] From the vertical control unit VC shown in Fig. 2(a), vertical selection lines VS1 to VS8 (collectively also referred to as vertical selection lines VS) connected to a selection unit TV (shown in Fig. 3) provided in each pixel 30 extend in the y direction. From the horizontal control unit HC, horizontal selection lines HS1 to HS4 (collectively also referred to as horizontal selection lines HS) connected to a selection unit TH2 (shown in Fig. 3) provided in each imaging pixel 30c extend in the x direction. From the horizontal control unit HC, a special horizontal selection line ZS connected to a selection unit of each of the special pixels Z1 and Z2 also extends in the x direction. From the horizontal control unit HC, reset voltage lines HR1 to HR4 (collectively also referred to as reset voltage lines HR) connected to a reset unit provided in each pixel 30 extend in the x direction.

[0019] As shown in Fig. 2(b), each of the vertical selection lines VS1 to VS8 is shared by a plurality of pixels 30 arranged in the y direction, and each of the horizontal selection lines HS1 to HS4 is shared by a plurality of imaging pixels 30c arranged in the x direction. The special horizontal selection line ZS is shared by a plurality of special pixels ZZ arranged in the x direction. Each of the reset voltage lines HR1 to HR4 is shared by a plurality of pixels 30 arranged in the x direction.

[0020] Figure 3 shows an overview of the electrical circuits for four pixels 30 (arranged two vertically and two horizontally) within the region PB enclosed by a dashed line in the lower right of the pixel block BC2 shown in Figure 2(b). As shown within region PB in Figure 2(b), the top left is a G pixel Gb, the top right is a special pixel Z2, the bottom left is an R pixel R, and the bottom right is a G pixel Gr. The four pixels (Gb, Z2, R, Gr) are all basically 4-transistor CMOS image sensors, but as will be described later, the configuration of the so-called selection transistors differs from that of a normal 4-transistor CMOS image sensor.

[0021] In each pixel (Gb, Z2, R, Gr), the photoelectric conversion unit, the photodiode PD, converts incident light into electricity to generate charge, and temporarily stores the generated charge. The transfer transistor TX transfers the charge stored in the photodiode PD to the floating diffusion (FD) region FD where capacitance CC is formed, based on a transfer signal sent to its gate from a transfer control line (not shown). The amplification transistor TA outputs a signal corresponding to the charge generated in the photodiode PD when the voltage generated in the FD region FD by the transferred charge is applied to its gate.

[0022] The power supply voltage VDD is applied to the input side (drain) of the amplification transistor TA. A reset transistor TR is provided to reset the FD region FD to a predetermined voltage. The input side (drain) of the reset transistor TR is connected to the reset voltage line HR3 or HR4, and a predetermined voltage, described later, is supplied from the horizontal control unit HC via the reset voltage line HR.

[0023] The output side (source side) of the amplification transistor TA for each pixel (Gb, Z2, R, Gr) is connected to the input side of the vertical selection transistor TV. A vertical selection line VS7 or VS8 is connected to the gate of the vertical selection transistor TV, and the vertical selection transistor TV is controlled to conduct or not conduct by a control signal sent from the vertical control unit VC shown in Figure 2(a).

[0024] The output side of the vertical selection transistor TV for the image pixels (Gb, R, Gr) is connected to the input side of the horizontal selection transistor TH1. In other words, the vertical selection transistor TV and the horizontal selection transistor TH1 are arranged in series. The gate of the horizontal selection transistor TH1 is connected to the horizontal selection line HS3 or HS4, and the control signal sent from the horizontal control unit HC shown in Figure 2(a) causes the horizontal selection transistor TH1 to conduct or not conduct. In the imaging pixels (Gb, R, Gr) of the image sensor 3 of the embodiment, the amplification transistor TA, the vertical selection transistor TV, and the horizontal selection transistor TH1 can be interpreted as an output unit, either as a single unit or individually.

[0025] On the other hand, in the special pixel Z2, the output side of the vertical selection transistor TV is connected to the input side of the special horizontal selection transistor TH2. The gate of the special horizontal selection transistor TH2 is connected to the special horizontal selection line ZS, and the special horizontal selection transistor TH2 becomes conductive or non-conductive according to the control signal sent from the horizontal control unit HC shown in Figure 2(a). The amplification transistor TA, vertical selection transistor TV, and special horizontal selection transistor TH2 of the special pixel Z2 of the image sensor 3 in this embodiment can be interpreted as an output unit, either as a whole or individually.

[0026] The output sections of the horizontal selection transistors TH1 for the imaging pixels (Gb, R, Gr) in pixel block BC2, and the output sections of the special horizontal selection transistors TH2 for the special pixel Z2 in pixel block BC2, are both connected to a single output line RW. The output line RW is connected to a readout unit that reads the signal from the pixel 30. The readout unit includes, for example, an ADC (analog-to-digital converter) that converts the analog signal output from the pixel 30 into a digital signal. The output line RW is also connected to a current source CS that supplies current to each pixel 30.

[0027] The control unit CU controls the voltage of the control signals to the vertical selection line VS and the horizontal selection line HS, thereby outputting the signals (output of the amplification transistor TA) of any one or more pixels (Gb, Z2, R, Gr) in the pixel block BC2 to the output line RW. The readout unit reads the signals of the pixels (Gb, Z2, R, Gr) in the pixel block BC2.

[0028] Figure 4 is a circuit diagram included in the horizontal control unit HC. Figure 4 shows a portion of the circuit included in the horizontal control unit HC, a portion of the multiple pixels 30, a portion of the horizontal selection line HS, the special horizontal selection line ZS, and a portion of the reset voltage line HR connected to the pixels 30 in the aforementioned pixel blocks BC1 and BC2.

[0029] Each horizontal selection line HS is connected to selection line changeover switches SS1 to SS4 (collectively referred to as selection line changeover switches SS) in the horizontal control unit HC. The selection line changeover switches SS allow each horizontal selection line HS to be switched between either a high-voltage line SH supplied with a high voltage such as the power supply voltage VDD, or a low-voltage line SL supplied with a low voltage such as the ground voltage GND.

[0030] For example, when horizontal selection line HS1 is connected to high-voltage line SH, the horizontal selection transistor TH1 in the pixel 30 to which horizontal selection line HS1 is connected becomes conductive. When horizontal selection line HS1 is connected to low-voltage line SL, the horizontal selection transistor TH1 becomes non-conductive. The special horizontal selection line ZS is connected to a special changeover switch SZ in the horizontal control unit HC. The special changeover switch SZ allows the special horizontal selection line ZS to be switched between connecting to either the high-voltage line SH or the low-voltage line SL. For example, when the special horizontal selection line ZS is connected to the high-voltage line SH, the horizontal selection transistor TH2 in the pixel 30 to which the special horizontal selection line ZS is connected becomes conductive. When the special horizontal selection line ZS is connected to the low-voltage line SL, the horizontal selection transistor TH2 becomes non-conductive.

[0031] On the other hand, each reset voltage line HR is connected to reset line selector switches SR1 to SR4 (collectively referred to as reset line selector switches SR) in the horizontal control unit HC. The reset line selector switches SR allow each reset voltage line HR to be switched between one of the following: a first voltage line RR1 to which a first voltage such as the power supply voltage VDD is supplied; a second voltage line RR2 to which a second voltage closer to the board voltage than the first voltage is supplied; or a third voltage line RR3 to which a third voltage closer to the board voltage than the second voltage is supplied.

[0032] The horizontal control unit HC applies either the first voltage, the second voltage, or the third voltage to the input side of the reset transistor TR in each pixel 30 via the reset voltage line HR. The selection line switch SS, the special switch SZ, and the reset line switch SR can all be constructed using semiconductor switches, such as MOS transistor circuits.

[0033] Although not shown in the diagram, the vertical control unit VC also contains a changeover switch, similar to the horizontal control unit HC shown in Figure 4, which switches the voltage applied to each vertical selection line VS. The switching of each of these switches, i.e., the voltage signals sent to the vertical selection line VS, the horizontal selection line HS, the special horizontal selection line ZS, and the reset voltage line HR, can be controlled by the control circuit within the control unit CU. Furthermore, the control unit (CU) can also control the movement of the changeover switch based on instructions from various devices and equipment on which the image sensor is mounted.

[0034] Although not shown in the diagram, the gates of the transfer transistor TX and reset transistor TR within each pixel 30 shown in Figure 3 are connected to control lines similar to the horizontal selection line HS or vertical selection line VS, as in conventional CMOS image sensors. The control unit CU can then control the conduction state of the transfer transistor TX and reset transistor TR for each row of pixels 30 arranged in the x-direction or column in the y-direction using these control lines.

[0035] Alternatively, the transfer transistor TX and reset transistor TR may be controlled for each pixel 30. For this purpose, for example, each control line may consist of two control lines, one horizontal and one vertical, and each of the transfer transistor TX and reset transistor TR may be composed of two transistors arranged in series. Then, either the horizontal control line or the vertical control line can be connected to the gates of each of the two transistors.

[0036] In the image sensor 3 of this embodiment, as will be described later, the signals of any number of pixels 30 within a single pixel block BC connected to a single readout unit can be summed and read out via the output line RW and the readout unit (binning readout). Binning readout allows the image sensor 3 to be easily applied to low-resolution modes that output image data with fewer pixels than the total number of pixels of the image sensor. In binning readout, two or more pixels 30 within a single pixel block BC are combined and read out by the readout unit, which smooths out the noise mixed into the signal of each pixel 30, thus allowing for the acquisition of a less noisy image.

[0037] It is preferable that the multiple pixels 30 that are summed up during reading by the reading unit are pixels of the same color. Therefore, the vertical control unit VC and the horizontal control unit HC control the voltage of the control signals to the vertical selection line VS and the horizontal selection line HS to select two or more pixels 30 of the same color within a single pixel block BC, and output their signals (outputs of the amplification transistor TA) to the output line RW.

[0038] (Operation of readout pixels and clipping pixels) When reading a signal, if an abnormal value is output to the readout unit, such as when the signal voltage at the input side of the readout unit falls below a predetermined value, excessive current may flow to the current source CS connected to the output line RW in the pixel block BC, or to the readout unit itself, potentially damaging the current source CS or the readout unit. To prevent this, the image sensor 3 of this embodiment can suppress excessive current as follows. Specifically, when reading out any one or more readout pixels within a single pixel block BC, any other pixel 30 within the same pixel block BC is designated as a clipping pixel, and the signals of the readout pixel and the clipping pixel are added together and read out, thereby suppressing excessive current.

[0039] By reading the combined signal from the clipping pixel, the lower limit of the combined readout signal voltage is clipped to the value from the clipping pixel, preventing it from falling below that value. This eliminates the risk of damage to the readout unit or current source CS. Clipping pixels function solely as pixels that output a constant signal for clipping, and therefore do not need to be pixels of the same color as the readout pixels.

[0040] The following describes the readout operation of the light intensity signal during imaging in the image sensor 3 of this embodiment. First, as an example, we will explain assuming that the readout pixel is the G pixel (imaging pixel) Gb located in the upper left of Figure 3, and the clipping operation pixel is the R pixel (imaging pixel) R located in the lower left of Figure 3. However, as will be described later, any other pixel 30 may be selected as the readout pixel and clipping operation pixel.

[0041] Prior to exposure operations such as imaging or focus detection, the control unit CU, including the horizontal control unit HC, controls the reset line switching switch SR to connect each reset voltage line HR to the first voltage line RR1 to which the first voltage is supplied. The control unit CU then turns on the reset transistor TR and transfer transistor TX of each pixel 30, resetting the FD region and photodiode PD to the first voltage mentioned above.

[0042] Subsequently, the control unit CU deactivates the transfer transistor TX, and exposure is performed on the photodiode PD on the image sensor 3 for imaging or focus detection. After exposure, the signal based on the charge generated in the photodiode PD by exposure is read out using so-called correlated double sampling. The control unit CU applies high-level voltages to the horizontal selection lines HS3 and HS4, and the vertical selection line VS7, causing the vertical selection transistor TV and horizontal selection transistor TH1 of the readout pixel Gb and clipping pixel R, respectively, to conduct. As a result, the outputs of the amplification transistors TA of the readout pixel Gb and clipping pixel R are output to the output line RW and summed up.

[0043] The following explanation will also refer to the timing chart shown in Figure 5. In the timing chart shown in Figure 5, the horizontal axis represents time, and TX and TR represent the voltage of the control signal input to the gates of the transfer transistor TX and reset transistor TR of each pixel 30. For example, since each transistor in each pixel 30 is of the nMOS type, in Figure 5, when the control signal is at a high level (e.g., power supply voltage), the transistor to which the control signal is input becomes conductive, and when the control signal is at a low level (e.g., ground voltage), the transistor to which the control signal is input becomes non-conductive. In Figure 5, the HR voltage represents the voltage supplied to the reset voltage line HR connected to each pixel 30, and the FD voltage represents the voltage in the FD region of each pixel 30.

[0044] At time t0, when the read operation begins, the control unit CU supplies a low-level control signal to the gates of both the transfer transistor TX and the reset transistor TR of the read pixel Gb and the clipping pixel R. The control unit CU also supplies a first voltage VC1 to the reset voltage line HR of both the read pixel Gb and the clipping pixel R. Although the FD region FD of the readout pixel Gb and the clipping pixel R is reset to the first voltage during the reset operation described above, the voltage of the FD region FD at time t0 is uncertain due to the influence of noise and other factors.

[0045] Next, the control unit CU applies a high-level voltage to the gate of the reset transistor TR of the readout pixel Gb between time t1 and time t2, resetting the FD region FD of the readout pixel Gb to the first voltage VC1. As a result, the first voltage VC1 is applied to the gate of the amplification transistor TA in the readout pixel Gb, and the amplification transistor TA outputs an amplified signal based on this, i.e., a so-called dark signal that does not reflect the charge accumulated in the photodiode PD. This output is output to the output line RW via the vertical selection transistor TV and the horizontal selection transistor TH1.

[0046] On the other hand, for the clipping pixel R, the control unit CU applies a high-level signal to the gate of the reset transistor TR from time t1 onward, supplying a second voltage VC2 to the reset voltage line HR connected to the clipping pixel R. As a result, the FD region FD of the clipping pixel R is reset to the second voltage VC2. Consequently, the second voltage VC2 is applied to the gate of the amplification transistor TA within the clipping pixel R, and the amplification transistor TA outputs an amplified signal based on this. This output is then output to the output line RW via the vertical selection transistor TV and the horizontal selection transistor TH1.

[0047] In the image sensor 3 of this embodiment, the signal from the readout pixel Gb and the signal from the clipping operation pixel R are summed together as so-called source binning. Therefore, the voltage of the signal finally read out from the readout unit is approximately equal to the higher of the two voltage signals that would have been obtained if the two signals had been read out separately from the readout unit. Therefore, the second voltage VC2 applied to the reset transistor TR of the clipping pixel R is set as follows: That is, the second voltage VC2 is set such that the output voltage value of the readout section when only the clipping pixel R is connected does not exceed the expected value of the output voltage value of the readout section when only the readout pixel Gr that outputs the dark signal is connected.

[0048] Specifically, since the amplification transistor TA for each pixel 30 is of the nMOS type, the second voltage VC2 is set to a voltage lower than the first voltage VC1 (closer to the ground voltage). However, if the voltage is too low, the function of clipping the output signal will be lost, so it is best to set the voltage to about 20-60% of the first voltage VC1, using the ground voltage as a reference. The control unit (CU) commands the readout unit to read the signal. In this state, the voltage applied to the input of the readout unit is converted from analog to digital, and dark sampling is performed.

[0049] Next, the control unit CU applies a high-level voltage to the gate of the transfer transistor TX of the readout pixel Gb between time t3 and time t4, transferring the charge in the photodiode PD generated by photoelectric conversion to the FD region. Meanwhile, at time t3, the voltage supplied to the reset voltage line HR connected to the clipping operation pixel R is changed to a third voltage VC3. As a result, the FD region FD of the clipping operation pixel R is reset to the third voltage VC3.

[0050] At time t4, the control unit CU commands the readout unit to read the signal. In this state, the voltage applied to the input of the readout unit is converted from analog to digital, and signal sampling is performed. The third voltage VC3 is also set as follows: The third voltage VC3 is set so that the output voltage value of the readout section, assuming only the clipping pixel R is connected, does not exceed the assumed value of the output voltage of the readout section, assuming only the readout pixel Gr is connected.

[0051] Specifically, the third voltage VC3 should be lower than the second voltage VC2, and ideally be about 30-70% of the second voltage VC2, using the ground voltage as a reference. Furthermore, if the amplification transistor TA within each pixel 30 is of the pMOS type, the relative heights of the first, second, and third voltages described above will be reversed.

[0052] The readout unit calculates the difference between the signal sampling and dark sampling results described above and outputs it as the readout result of the light intensity signal from the readout pixel Gb. Therefore, the readout signal obtained by dark sampling can be interpreted as a correction signal for correcting the readout signal obtained by signal sampling. The output read out by the readout unit within each pixel block BC is output from the image sensor 3 via an output control circuit (not shown).

[0053] (Selection of readout pixels and clipping pixels) Next, the selection operation of readout pixels and clipping pixels, which is performed by the control unit CU controlling the signal levels of the vertical selection line VS, the horizontal selection line HS, and the special horizontal selection line ZS, will be explained with reference to Figures 2(b) and 3.

[0054] First, we will explain the case where, within the pixel block BC2 shown in Figure 2(b), all G pixels Gb are used as readout pixels, and the two R pixels R connected to the horizontal selection line HS4 located at the bottom of the pixel block BC2 are selected as clipping pixels. In this case, the control unit CU supplies a high-level voltage to conduct the vertical selection transistors TV to the vertical selection lines VS5 and VS7 connected to the four G pixels Gb and the two R pixels R, and supplies a high-level voltage to conduct the horizontal selection transistors TH1 to the horizontal selection lines HS1, HS3, and HS4 connected to these pixels.

[0055] On the other hand, low-level voltages are supplied to the horizontal selection line HS2, the special horizontal selection line ZS, and the vertical selection lines VS6 and VS8, which are not connected to these pixels. As a result, within each pixel block BC2, only the signals from the four G pixels Gb, which are the readout pixels, and the two R pixels R connected to the horizontal selection line HS4, can be connected to the output line RW and read out by the readout unit.

[0056] In other words, in the correlated double sampling readout described above, the four G pixels Gb are used as readout pixels, and the two R pixels R connected to the horizontal selection line HS4 are used as clipping pixels for the readout. Specifically, the reset voltage lines HR1 and HR3 connected to the reset section of the four G pixels Gb are always supplied with the first voltage VC1, and the reset transistor TR and transfer transistor TX are supplied with a high-level voltage at predetermined timings (predetermined timings for the readout pixels) as shown in Figure 5.

[0057] The reset voltage line HR4 connected to the reset section of the two R pixels R connected to the horizontal selection line HS4 sequentially applies the first voltage VC1, the second voltage VC2, and the third voltage VC3 at predetermined timings (predetermined timings for the clipping pixels) as shown in Figure 5. In addition, a high-level voltage is applied to the reset transistor TR of the two R pixels R connected to the horizontal selection line HS4 at predetermined timings. This allows binning readout to be performed within pixel block BC2, using two R pixels (R) as clipping pixels and four G pixels (Gb) as readout pixels.

[0058] In the readout operation described above, by applying a low-level voltage to the horizontal selection line HS1, it is also possible to perform binning readout by using the two G pixels Gb connected to the horizontal selection line HS3 within the pixel block BC2 as readout pixels and the two R pixels R as clipping operation pixels. Furthermore, by applying a low-level voltage to the vertical selection line VS5, it is possible to perform binning readout by using one G pixel Gb connected to the horizontal selection line HS3 and the vertical selection line VS7 within the pixel block BC2 as the readout pixel and one R pixel R as the clipping operation pixel.

[0059] You can also select pixels of the same color for both the readout pixel and the clipping operation pixel. For example, within pixel block BC2, a high-level voltage is applied only to the vertical selection line VS5, a low-level voltage is applied to the other vertical selection lines VS, a high-level voltage is applied to the horizontal selection lines HS1 and HS3, and a low-level voltage is applied to the horizontal selection lines HS2 and HS4. This allows only the signals of the two G pixels Gb connected to the vertical selection line VS5 to be connected to the output line RW. This is an example where one G pixel Gb is the readout pixel and the other G pixel Gb is the clipping operation pixel, and the horizontal control unit HC controls the signal levels supplied to the reset voltage line HR and the horizontal selection line HS as follows.

[0060] According to the timing chart in Figure 5, the first voltage VC1 is always supplied to the reset voltage line HR1. Meanwhile, the first voltage VC1, second voltage VC2, and third voltage VC3 are sequentially supplied to the reset voltage line HR3 according to the timing, and a high-level voltage is supplied to the gates of the reset transistor TR and the transfer transistor TX as appropriate according to the timing. This allows reading to be performed with the G pixel Gb connected to the reset voltage line HR1 as the readout pixel and the G pixel Gb connected to the reset voltage line HR3 as the clipping operation pixel.

[0061] In the above example of readout, we described an example where the G pixel Gb was used as the readout pixel, but it is also possible to use the G pixel Gr, R pixel R, B pixel B, or special pixel ZZ as the readout pixel in the same way. In that case, the clipping pixel can also be a pixel of the same color as the read pixel, or a pixel of a different color from the read pixel.

[0062] When using a special pixel ZZ as a readout pixel or clipping pixel, a high-level voltage is applied to the special horizontal selection line ZS connected to the special pixel ZZ, instead of the horizontal selection line HS mentioned above, in order to output the signal of the special pixel ZZ to the output line RW. In pixel block BC2 shown in Figure 2(b), some of the B pixels B, which are highly sensitive to blue light, are replaced by special pixels Z1 and Z2. However, the readout operation from B pixels B in pixel block BC2 can be performed in almost the same way as the readout operation from G pixels Gr described above.

[0063] For example, when reading a signal using two B pixels as readout pixels and two special pixels Z1 and Z2 as clipping pixels, a high-level voltage is applied to the horizontal selection line HS1, the special horizontal selection line ZS, and the vertical selection lines VS6 and VS8. A low-level voltage is then applied to the other horizontal selection lines HS and vertical selection lines VS.

[0064] This allows only the signals from the two B pixels B and the two special pixels Z1 and Z2 to be connected to the output line RW. Then, as in the example above, a predetermined voltage is applied to the reset voltage line HR, etc., so that the two B pixels B become the readout pixels and the two special pixels Z1 and Z2 become the clipping pixels, and the correlated double sampling described above is performed.

[0065] In this case, instead of the special horizontal selection line ZS, a high-level voltage can be applied to the horizontal selection line HS2, and a predetermined voltage can be applied to the reset voltage line HR2 according to the timing shown in Figure 5, thereby allowing the two G pixels Gr connected to the horizontal selection line HS2 to be used as clipping pixels.

[0066] Furthermore, the horizontal selection line HS3, which is arranged in parallel with the special horizontal selection line ZS, is not connected to the special horizontal selection transistor TH2 in the special pixels Z1 and Z2. Therefore, when reading the signal from pixel B in pixel block BC2, no matter what signal the horizontal control unit HC sends to the horizontal selection line HS3, the signal read from pixel B will not be mixed with the signals from special pixels Z1 and Z2. However, since the horizontal selection line HS3 is also shared by other pixel blocks BC, such as pixel block BC1 which is adjacent to pixel block BC2 in the x-direction, it is preferable to apply a signal to the horizontal selection line HS3 that is suitable for reading out in other pixel blocks BC.

[0067] Similarly, the special pixel ZZ can be used as the readout pixel, and the other imaging pixels 30c can be used as the clipping pixels to read out the signal from the special pixel ZZ. For example, when reading out special pixel Z2 within region PB as the readout pixel and G pixel Gr within region PB as the clipping operation pixel, a high-level voltage is applied to the vertical selection line VS8, the horizontal selection line HS4, and the special horizontal selection line ZS. Then, a low-level voltage is applied to the other vertical selection lines VS and horizontal selection lines HS.

[0068] This allows only the signals from the special pixel Z2 and the G pixel Gr within region PB to be connected to the output line RW. Then, similar to the example above, a predetermined voltage is applied to the reset voltage line HR, etc., so that the special pixel Z2 in region PB becomes the readout pixel and the G pixel Gr in region PB becomes the clipping operation pixel, and the above-mentioned correlated double sampling is performed.

[0069] The above describes the reading of signals from pixels 30 in pixel block BC2, but the same applies to other pixel blocks BC. The signals from each pixel 30 in each pixel block BC are output to the output line RW provided in each pixel block BC and read out by the readout unit. In addition, in the reading of pixel blocks other than pixel block BC2, the vertical selection line VS, horizontal selection line HS, and special horizontal selection line ZS may be shared by multiple pixel blocks BC. For example, horizontal selection lines HS1 to HS4 may be connected to each pixel 30 of other pixel blocks BC that are aligned in the x-direction with respect to pixel block BC2, as in pixel block BC1. Also, vertical selection lines VS5 to VS8 may be connected to each pixel 30 of other pixel blocks BC that are aligned in the y-direction with respect to pixel block BC2.

[0070] The order in which the signals from the special pixel ZZ and the imaging pixels (Gb, Gr, R, B) are read out is arbitrary. For example, the control unit CU first selects the special pixel ZZ via the vertical selection line VS and the horizontal selection line HS, and the readout unit reads out its output signal. After that, the control unit CU selects the imaging pixels (Gb, Gr, R, B) and the readout unit reads out their output signals.

[0071] Since the number of special pixels ZZ (2 pixels, Z1 and Z2) in pixel block BC is less than the number of imaging pixels 30c (14 pixels in total, Gb, Gr, R, and B), the time required to read out the signals from the special pixels ZZ is shorter than the time required to read out the signals from the imaging pixels. In other words, the signals from the special pixels ZZ can be read out faster than the signals from the imaging pixels 30c. For example, if the special pixels ZZ are AF pixels, the signal from the special pixels ZZ is read out before the signals from the imaging pixels (Gb, Gr, R, and B), allowing the control unit 4 to perform focus detection at high speed. Alternatively, two readout units may be provided in a single pixel block BC. By connecting the two readout units to a single output line RW, each of the two readout units may read out the signal from the special pixel ZZ and the signals from the imaging pixels (Gb, Gr, R, B). This allows the readout units to read out the signals from the special pixel ZZ and the imaging pixels (Gb, Gr, R, B) under optimal readout gain and other conditions.

[0072] In the binning readout between the readout pixel and the clipping pixel described above, no high-level signal (transfer signal) is applied to the gate of the transfer transistor TX in the clipping pixel. Therefore, the photodiode PD in the pixel used as the clipping pixel stores the charge (photoelectric signal) generated by exposure. Therefore, after the readout using the combination of readout pixels and clipping pixels described above is completed, at least one of the pixels used as the clipping pixel can be used as the readout pixel to read out its signal.

[0073] In the above embodiment, the voltage applied to the reset section (reset transistor TR) of the clipping operation pixel may be one of two types: a first voltage VC1 and a second voltage VC2. Correspondingly, the voltage source connected to the reset voltage line HR by the reset line switching switch SR in the horizontal control unit HC may be one of two types: a first voltage line RR1 and a second voltage line RR2 to which a second voltage closer to the substrate voltage than the first voltage is supplied.

[0074] In this case, for the clipping operation pixel shown in Figure 5, the HR voltage (the voltage supplied to the reset voltage line HR connected to the clipping operation pixel) should be the first voltage VC1 from time t0 to time t1, and the second voltage VC2 from time t1 onward. In this case, the second voltage VC2 should be approximately 20-40% of the first voltage VC1, with the ground voltage as the reference.

[0075] In the above embodiment, of the pixels 30 that are read out by summing them up through source binning readout, the readout pixels can be interpreted as first pixels. On the other hand, the clipping operation pixels can be interpreted as second pixels. Furthermore, the FD region (FD) of each pixel 30 can be interpreted as an accumulation area, as the charge converted photoelectrically by the photodiode PD is transferred and stored there. The FD region (FD) of the readout pixel (first pixel) can also be interpreted as the first accumulation area, and the FD region (FD) of the clipping operation pixel (second pixel) can also be interpreted as the second accumulation area.

[0076] Furthermore, in the above embodiments, the pixels 30 read out by summing them up using source binning may be set to only a number of readout pixels, without using clipping pixels. This can be achieved by not selecting the pixels used as clipping pixels in the readout example described above. Specifically, during correlated double sampling, the clipping pixels may not be selected using the vertical selection line VS, the horizontal selection line HS, and the special horizontal selection line ZS, or signals to control various reset voltages and reset transistors TR may not be sent to the clipping pixels at predetermined timings.

[0077] In this case, any one or more of the multiple pixels 30 that are read out together can be interpreted as the first pixel, and any one or more of the pixels other than the first pixel can be interpreted as the second pixel. Furthermore, the voltage generated in the FD region FD of the first pixel to which the charge generated by the photodiode PD is transferred can be interpreted as the first voltage, and the voltage generated in the FD region FD of the second pixel to which the charge generated by the photodiode PD is transferred can be interpreted as the second voltage.

[0078] Figure 6 shows a cross-section of the pixel 30 portion of the image sensor 3 in this embodiment. Note that Figure 6 shows only a portion of the cross-section of the image sensor 3 as a whole. The z-directions shown in Figure 6 are the same as the directions shown in Figure 1. The image sensor 3 is a so-called back-illuminated image sensor. The image sensor 3 converts light incident from the plane of the paper into photoelectric power. The image sensor 3 comprises a first semiconductor substrate 7 and a second semiconductor substrate 8.

[0079] As described above, the image sensor 3 has multiple pixels 30. Each pixel 30 includes an upper part 30x provided on the first semiconductor substrate 7 and a lower part 30y provided on the second semiconductor substrate 8. The upper part 30x of each pixel includes one microlens 74, one color filter 73, one light-receiving part 31 of a photodiode PD, etc.

[0080] The first semiconductor substrate 7 comprises a light-receiving layer 71 including a light-receiving portion 31 of a photodiode PD contained in the upper part 30x of a pixel, and a wiring layer 72 on which transistors such as a transfer transistor TX and an amplification transistor TA are formed. The light-receiving layer 71 is located on the opposite side (back side) of the first semiconductor substrate 7 from the wiring layer 72. Multiple light-receiving portions 31 are arranged in a two-dimensional manner on the light-receiving layer 71. The upper part 30x of the pixel includes a light-receiving section 31, which converts incident light into photoelectric energy, and can therefore be interpreted as an imaging section. The second semiconductor substrate 8 contains a vertical selection transistor TV, a horizontal selection transistor TH1, a special horizontal selection transistor TH2, a vertical selection line VS, a horizontal selection line HS, a special horizontal selection line ZS, a readout section, a current source CS, and other components located in the lower part 30y of the pixel.

[0081] Multiple bumps 75 are arranged on the surface of the wiring layer 72. Multiple bumps 76 corresponding to the multiple bumps 75 are arranged on the surface of the second semiconductor substrate 8 facing the wiring layer 72. The multiple bumps 75 and the multiple bumps 76 are joined to each other. The first semiconductor substrate 7 and the second semiconductor substrate 8 are electrically connected via the multiple bumps 75 and the multiple bumps 76, that is, the first semiconductor substrate 7 and the second semiconductor substrate 8 are stacked. Furthermore, since the readout unit that reads signals from multiple pixels 30 is located on the second semiconductor substrate 8, it can also be interpreted as being stacked on the imaging unit located on the first semiconductor substrate 7.

[0082] The configurations of the circuit elements placed on the first semiconductor substrate 7 and the second semiconductor substrate 8 described above are merely examples, and some of these components may be placed on either the first semiconductor substrate 7 or the second semiconductor substrate 8. A light-receiving layer 71 including the light-receiving portion 31 of the photodiode PD, a transfer transistor TX, an amplification transistor TA, and a vertical selection transistor TV, a horizontal selection transistor TH2, a horizontal selection transistor TH1, a special horizontal selection transistor TH2, horizontal selection lines HS3, HS4, and a special horizontal selection line ZS may be formed on the first semiconductor substrate 7, and a readout section and a current source CS may be arranged on the second semiconductor substrate 8. The vertical control unit VC and the horizontal control unit HC may be placed on either the first semiconductor substrate 7 or the second semiconductor substrate 8. However, if many circuit elements are placed on the first semiconductor substrate 7, it becomes impossible to secure sufficient area or volume for placing the light-receiving unit 31 on the first semiconductor substrate 7. Therefore, it is preferable to place the reading unit and current source CS on the second semiconductor substrate 8.

[0083] Each of the 30 pixels has a color filter 73 that is matched to the spectral sensitivity characteristics of that pixel. Furthermore, a color filter 73 is also placed in the special pixel ZZ among the pixels 30. If the special pixel ZZ is an AF pixel, the color filter G is provided as the color filter 73. The color filter 73 provided in the special pixel ZZ may be a filter that transmits the entire wavelength range of incident light. Also, the color filter 73 provided in the special pixel ZZ may be a color filter 73 with different spectral characteristics from any of the color filters 73 placed in the imaging pixels 30c.

[0084] If the special pixel ZZ is a pixel for receiving infrared light, the color filter 73 will have high transmittance of infrared light and low transmittance of visible light. If the special pixel ZZ is a pixel for receiving visible light, the color filter 73 will have high transmittance across the entire wavelength range of visible light.

[0085] Furthermore, the sensitivity of the special pixel ZZ may be made different from that of the imaging pixel 30c by making the average transmittance of the color filter 73 of the special pixel ZZ different from that of the color filter 73 of the imaging pixel 30c. Here, average transmittance refers to the average transmittance for all wavelengths of light that the light receiving unit 31 converts photoelectrically. The sensitivity of the special pixel ZZ may be made different from that of the imaging pixel 30c by making the area of ​​the light-receiving portion 31 of the special pixel ZZ different from the area of ​​the light-receiving portion 31 of the imaging pixel 30c, or by changing the conditions for ion implantation into the light-receiving portion 31.

[0086] Figure 7 shows an example where the special pixel ZZ is an AF pixel. In Figure 7, the second semiconductor substrate 8 is omitted from the cross-sectional view of the image sensor 3 shown in Figure 6. Special pixel Z1 has a light-shielding portion 75R at the boundary between the color filter 73 and the first semiconductor substrate 7, which shields the right side of the light-receiving portion 31. On the other hand, special pixel Z2 has a light-shielding portion 75L at its boundary, which shields the left side of the light-receiving portion 31.

[0087] Of the light incident on the special pixel Z1, the light LL that is incident at an angle in the -x direction with respect to the direction PL perpendicular to the incident surface of the image sensor 3 is blocked by the light-shielding portion 75R. On the other hand, of the light incident on the special pixel Z2, the light LR that is incident at an angle in the +x direction with respect to the direction PL perpendicular to the incident surface of the image sensor 3 is blocked by the light-shielding portion 75L. As a result, the special pixels Z1 and Z2 become less sensitive to light incident from different incident directions, and conversely, their sensitivity to light incident from different incident directions becomes relatively higher.

[0088] When this image sensor 3 is applied to the imaging device shown in Figure 1, the special pixels Z1 and Z2 become elements that are highly sensitive to light passing through different positions on the pupil plane of the imaging optical system 2, and therefore function as pixels for detecting image plane phase difference focus. Furthermore, the positions in which the light-shielding portions 75R and 75L are provided are not limited to the boundary between the color filter 73 and the first semiconductor substrate 7, but can be provided anywhere between the microlens 74 and the first semiconductor substrate 7.

[0089] In the above embodiments of the image sensor, the arrangement of each pixel 30 is not necessarily limited to a Bayer arrangement. Furthermore, the horizontal selection line HS and the special horizontal selection line ZS may extend in the direction of the short side of the image sensor 3 rather than the direction of the long side, and the vertical selection line VS may extend in the direction of the long side of the image sensor 3 rather than the direction of the short side. Furthermore, the horizontal selection line HS, special horizontal selection line ZS, and vertical selection line VS that control the signal output of each pixel 30 do not necessarily have to extend in the horizontal (x-direction) and vertical (y-direction) directions. Also, the horizontal selection line HS, special horizontal selection line ZS, and vertical selection line VS do not necessarily have to be shared by multiple pixels 30.

[0090] Furthermore, the signal output from the special pixel ZZ is often smaller than the signal output from the imaging pixel 30c due to the presence of light-shielding sections 75R and 75L. Therefore, the special pixel ZZ may incorporate an amplification circuit that increases the signal output by, for example, about twice. Alternatively, the value may be increased by adding an offset to the output signal from the special pixel ZZ.

[0091] In the above embodiment, the total number of imaging pixels 30c and B pixels B within each pixel block BC varies depending on whether or not special pixels ZZ are included in that pixel block BC. Therefore, when performing the binning readout described above, the magnitude of the summation signal of the pixel block BC may also vary depending on whether or not that pixel block BC includes special pixels ZZ.

[0092] Therefore, in order to prevent fluctuations in this summing signal, a correction circuit may be provided that increases or decreases the summing signal of the pixel block BC containing special pixels ZZ according to the number of special pixels ZZ contained in the pixel block BC. This correction circuit may be provided within the pixel block BC, or within the image sensor 3 other than the pixel block BC. Alternatively, instead of providing the correction circuit within the image sensor 3, this correction may be performed in the control unit 4.

[0093] For example, in the example shown in Figure (b), pixel block BC1 does not contain any special pixels ZZ, but contains four each of G pixels Gb, G pixels Gr, B pixels B, and R pixels R. On the other hand, pixel block BC2 contains two special pixels ZZ (Z1, Z2), four each of G pixels Gb, G pixels Gr, and R pixels R, but only two B pixels B. Therefore, when performing binning readout of B pixels B in pixel block BC2, the summation signal is multiplied by (4 / 2). This makes the summation signal when binning readout of B pixels B approximately equal for pixel block BC1 and pixel block BC2.

[0094] (Effects of the image sensor embodiment) (1) The image sensor 3 of the above embodiment has a first pixel and a second pixel. The first pixel has a photodiode (first photoelectric conversion unit) PD that converts light into electricity to generate charge, an FD region (first storage unit) FD that stores the charge generated by the photodiode PD, and a select transistor (first output unit) TH1 that outputs a first signal based on the voltage of the FD region FD. The second pixel has a photodiode (second photoelectric conversion unit) PD that converts light into electricity to generate charge, an FD region (second storage unit) FD that stores the charge generated by the photodiode PD, and a select transistor (second output unit) TH1 or TH2 that outputs a second signal based on the voltage of the FD region FD. The image sensor 3 of the above embodiment further includes an output line RW to which the first pixel selection transistor TH1 and the second pixel selection transistor TH1 or TH2 are connected and to which the first signal and the second signal are output, and a control unit CU that can control the voltage of the FD region FD of the first pixel to a first voltage and control the voltage of the FD region FD of the second pixel to a second voltage or a first voltage different from the first voltage. This configuration has the effect of allowing the output of any one or more pixels 30 from among the multiple pixels connected to the output line RW to be selected and output to the output line RW.

[0095] (2) Furthermore, the control unit CU can also control the second storage unit to a second voltage while the first output unit outputs the first signal. This prevents excessive current from being generated in the current source IS even when the first signal is an abnormal value exceeding a predetermined range, thereby preventing damage to the image sensor 3.

[0096] Although various embodiments and modifications have been described above, the present invention is not limited to these. Furthermore, each embodiment and modification may be applied individually or in combination. Other embodiments conceivable within the scope of the technical idea of ​​the present invention are also included within the scope of the present invention.

[0097] The disclosures of the following priority application are incorporated herein by reference. Japanese Patent Application No. 2018-185635 (filed September 28, 2018) [Explanation of symbols]

[0098] 1: Imaging device, 2: Imaging lens, 3: Image sensor, 4: Control unit (generation unit), 5: Lens movement unit, 7: First semiconductor substrate, 8: Second semiconductor substrate, BC, BC1, BC2: Pixel block, HC: Horizontal control unit, VC: Vertical control unit, CU: Control unit, Pixel 30, Gr, Gb: G pixel, R: R pixel, B: B pixel, Z1, Z2: Special pixel, VS, VS1~HS8: ​​Vertical selection line, HS, HS1~HS4: Horizontal selection line, ZS: Special horizontal selection line, HR, HR1~HR4: Reset voltage line, PD: Photodiode, TX: Transfer transistor, TR: Reset transistor, TA: Amplifier transistor, TV: Vertical selection transistor, TH1: Horizontal selection transistor, TH2: Special horizontal selection transistor, RW: Readout line, ADC: Readout unit, 31: Photosensitive unit, 73: Color filter

Claims

[Claim 1] A first photoelectric conversion unit that converts light into electric charge, A second photoelectric conversion unit that converts light into electric charge, A first floating diffusion unit to which the charge converted in the first photoelectric conversion unit is transferred, The second floating diffusion unit to which the charge converted in the second photoelectric conversion unit is transferred, A transistor for electrically connecting the first floating diffusion unit and the first supply unit to which the first voltage is supplied, comprising a first transistor for discharging the charge from the first floating diffusion unit, A transistor for electrically connecting the second floating diffusion unit and a second supply unit to which a second voltage lower than the first voltage and a third voltage lower than the second voltage are supplied, the second transistor for discharging the charge from the second floating diffusion unit, An output unit having a third transistor including a gate portion electrically connected to the first floating diffusion unit, the first output unit outputting a first signal based on the charge transferred from the first photoelectric conversion unit to the first floating diffusion unit and a second signal based on the charge of the first floating diffusion unit when the charge is discharged from the first floating diffusion unit to the first supply unit by the first transistor, An output unit having a fourth transistor including a gate portion electrically connected to the second floating diffusion unit, the second output unit outputting a third signal based on the charge of the second floating diffusion unit when charge is discharged from the second floating diffusion unit to the second supply unit to which the third voltage is supplied, and a fourth signal based on the charge of the second floating diffusion unit when charge is discharged from the second floating diffusion unit to the second supply unit to which the second voltage is supplied, An output line on which a first binning process is performed using the first signal output from the first output unit and the third signal output from the second output unit, and a second binning process is performed using the second signal output from the first output unit and the fourth signal output from the second output unit. An image sensor equipped with the following features.

Images