Reduced Header Signal Information Test System and Method

Abstract

This invention provides a signal processing test system and a signal processing test method that facilitate the efficient, effective, and flexible implementation of different types of test procedures in a test system. [Solution] The signal processing test method comprises a step 810 of selecting a signal processing mode from a header inclusion mode, a reduced header training mode, and a reduced header mode; a step 820 of executing a signal processing information determination process according to the result of the step of selecting the signal processing mode; and a step 830 of executing modulation / demodulation-related processing according to the result of the signal processing information determination process. In the reduced header mode, processing is performed on the communication signal. Header information is not initially readily available in the communication signal itself, and demodulation parameter information is advantageously derived / developed / extrapolated from other information in the communication signal.

Description

Technical Field

[0001] [Related Applications] This application claims the benefit and priority of Provisional Application No. 63 / 512,605, filed July 7, 2023, entitled "Techniques for Headerless Demodulation of Signals" (Attorney Docket No.: ATSY-0138-00.00US). The provisional application is hereby incorporated by reference in its entirety.

[0002] Embodiments of the present disclosure relate to the fields of signal processing and electronic testing.

Background Art

[0003] Electronic systems and devices have made significant contributions to the development of modern society and have facilitated improvements in productivity and cost reduction in information analysis and communication in various business, scientific, educational, and entertainment applications. To address the increasing demand for communicating more information, new communication devices and communication protocols have been implemented. Appropriate transmission and processing of signals for transmitting information (e.g., modulation, demodulation, etc.) are essential for accurate information communication between electronic devices. As more information is communicated and new communication protocols are developed, more time and resources have been required to test the ability of components to appropriately participate in information communication, resulting in a decrease in the productivity and an increase in the cost of the overall test system and test operations.

[0004] Furthermore, as communication components and protocols evolve and change, testing to ensure accurate signal transmission and processing tends to become complex and problematic. Addressing changing communication protocol requirements in conventional ways leads to more complex test patterns (e.g., individually, patterns become larger, and collectively, more of these patterns are needed), often resulting in undesirable prolongation of test time. To cope with the increasing volume of information and new communication protocol requirements, more electronic resources associated with testing (e.g., test scan chain components, wave generation components, additional information storage capacity, etc.) have also traditionally been required. However, memory space and other resources in integrated circuits are typically limited, which consequently leads to a concentration of resource allocation towards normal operation (e.g., mission mode operation, non-test operation, end-use operation, etc.) and functions. However, allocating this limited space to test resources for relatively infrequent test operations and making them dedicated to those test resources tends to be costly and inefficient, and / or an undesirable allocation of resources. For example, providing adequate time and resources to properly test the implementation of a new communication protocol within a device under test (DUT) using automated test systems (ATEs) has traditionally been impractical and / or impossible. [Overview of the Initiative]

[0005] The embodiments presented in this disclosure facilitate the flexible implementation of different types of test procedures in a test system. The embodiments described herein enable efficient and effective component-based testing of communication systems and methods where the resources supporting the components are limited. In practice, embodiments of this disclosure can provide cost savings for device manufacturers by ensuring that communication devices are thoroughly tested without adding additional electronic resources that are not required by the communication devices for normal operation.

[0006] In some embodiments, a reduced-header communication signal processing test method comprises the steps of: performing autocorrelation of cyclic prefixes in a signal, wherein the signal is configured according to a communication protocol; identifying the start timing of symbols in the signal based on the results of the autocorrelation, wherein the symbols are defined by the communication protocol and include orthogonal frequency division modulation (OFDM) symbols; determining initial coarse frequency error correction based on the results of the autocorrelation; setting up a set of bins for the signal, wherein the set of bins includes a pilot bin and a data bin, wherein the set of bins corresponds to a set of subcarriers associated with the signal, the pilot bin includes a corresponding pilot subcarrier in the set of subcarriers, and the data bin corresponds to a data subcarrier in the set of subcarriers; extracting identification information for the pilot bin according to the definition of the pilot subcarrier as defined by the communication protocol; setting ideal constellation values ​​and ideal symbol values ​​for the pilot bin and the data bin; and determining other demodulation parameter values ​​based on the results of the ideal constellation values ​​and ideal symbol values ​​for the pilot bin and the data bin.

[0007] In another embodiment, the signal processing test system comprises a load board configured to be coupled with a plurality of devices under test (DUTs); a controller configured to direct the testing of the plurality of DUTs, wherein the controller has a test mode selection module operable to select between a plurality of test modes, wherein one of the plurality of test modes is associated with reduced header communication signal test processing applied to a signal; and test electronics configured to test the plurality of DUTs under the control of the controller. The test electronics is coupled to the load board, wherein the test electronics has a demodulation information determination module operable to collect information associated with a demodulation operation, wherein the demodulation operation includes determining signal processing information based on information in the payload portion of the signal; and a demodulation module operable to perform a demodulation operation based on information received from the demodulation information determination module.

[0008] In another embodiment, the signal processing test method comprises the steps of: selecting a signal processing mode from a header inclusion mode, a reduced header training mode, and a reduced header mode; performing a signal processing information determination process according to the result of the step of selecting the signal processing mode; and performing modulation / demodulation-related processing according to the result of the signal processing information determination process. [Brief explanation of the drawing]

[0009] The accompanying drawings incorporated herein and forming part thereof are included for illustrative purposes of illustrating the principles of this disclosure and are not intended to limit this disclosure to any specific implementation shown in the accompanying drawings. Unless otherwise indicated, these drawings are not to scale.

[0010] [Figure 1A] This is a block diagram of an exemplary test environment or system according to embodiments of the present disclosure.

[0011] [Figure 1B]This is a block diagram of an exemplary radio frequency (RF) integrated circuit device or DUT according to embodiments of the present disclosure.

[0012] [Figure 1C] This is a block diagram of an exemplary test environment or system according to embodiments of the present disclosure.

[0013] [Figure 2A] This is an exemplary block diagram of a DUT according to an embodiment of the present disclosure.

[0014] [Figure 2B] This is a block diagram of an exemplary automated test system (ATE) according to an embodiment of the present disclosure.

[0015] [Figure 3A] This is a flowchart of an exemplary multimode modulation / demodulation parameter determination method, including a novel reduction header processing method, according to an embodiment of the present disclosure.

[0016] [Figure 3B] This is a block diagram of an exemplary multimode modulation / demodulation parameter determination system according to an embodiment of the present disclosure.

[0017] [Figure 4A] This is a block diagram illustrating an exemplary PDU communication frame or packet according to an embodiment of the present disclosure.

[0018] [Figure 4B] This is a block diagram of an exemplary PDU communication frame or packet in different communication protocol / model layers according to embodiments of the present disclosure.

[0019] [Figure 4C] Embodiments of this disclosure include various exemplary data packets, including the organization and configuration of information within a PPDU.

[0020] [Figure 4D]A data packet diagram including various exemplary compilations and configurations of information (``packets'') according to embodiments of the present disclosure.

[0021] [Figure 4E] A block diagram of different exemplary signal physical layer protocol data unit (PPDU) compilations / configurations for each IEEE 802.11-based wireless network protocol / standard according to embodiments of the present disclosure.

[0022] [Figure 5A] A block diagram of an exemplary signal configuration according to embodiments of the present disclosure.

[0023] [Figure 5B] A block diagram of an exemplary frequency spectrum of subcarriers and corresponding bins according to embodiments of the present disclosure.

[0024] [Figure 5C] A graph block diagram of an exemplary transmission scheme of OFDM symbol tones / signals according to embodiments of the present disclosure.

[0025] [Figure 5D] A block diagram of an exemplary OFDM symbol payload part transmission using reduced header information according to embodiments of the present disclosure.

[0026] [Figure 5E] A block diagram of various exemplary subcarrier configuration allocations according to embodiments of the present disclosure.

[0027] [Figure 6A] A block diagram of some exemplary constellation maps associated with signal communication according to embodiments of the present disclosure.

[0028] [Figure 6B] A block diagram of some exemplary constellation map errors associated with signal communication according to embodiments of the present disclosure.

[0029] [Figure 7] This is a logical flowchart of an exemplary test mode selection process according to an embodiment of the present disclosure.

[0030] [Figure 8] This is a block diagram of an exemplary reduced header mode test process according to an embodiment of the present disclosure.

[0031] [Figure 9A] This is a block diagram illustrating exemplary autocorrelation graph results according to embodiments of the present disclosure.

[0032] [Figure 9B] This is a block diagram illustrating an exemplary autocorrelation process according to an embodiment of the present disclosure.

[0033] [Figure 10] This is a flowchart illustrating an exemplary equalizer value determination process according to an embodiment of the present disclosure.

[0034] [Figure 11A] This is a flowchart illustrating an exemplary ideal pilot tone determination process according to an embodiment of the present disclosure.

[0035] [Figure 11B] This is an exemplary simulated channel response graph according to embodiments of the present disclosure, in the presence of a signal with a full header or a signal with a non-blind known stimulus.

[0036] [Figure 11C] This is a graph showing the positions of several exemplary pilot bin frequency responses according to embodiments of the present disclosure.

[0037] [Figure 12A] This is a flowchart of an exemplary interpolation process, including iterative updating / re-determination of equalization values ​​in a bin, according to embodiments of the present disclosure.

[0038] [Figure 12B] This is an exemplary graph of the results of an interpolation process, including iterative updating / re-determination of equalization values ​​within a bin, according to embodiments of the present disclosure.

[0039] [Figure 12C] This is a flowchart of an exemplary interpolation process, including iterative updating / re-determination of equalization values ​​in a bin, according to embodiments of the present disclosure. [Figure 12D] This is a flowchart of an exemplary interpolation process, including iterative updating / re-determination of equalization values ​​in a bin, according to embodiments of the present disclosure.

[0040] [Figure 12E] This is a block diagram of an exemplary subcarrier bin configuration 1291 according to an embodiment of the present disclosure.

[0041] [Figure 12F] This is a block diagram illustrating exemplary signal information processing operation according to an embodiment of the present disclosure.

[0042] [Figure 12G] This is a block diagram illustrating exemplary signal information processing operation according to an embodiment of the present disclosure.

[0043] [Figure 12H] This is a block diagram illustrating exemplary signal information processing operation according to an embodiment of the present disclosure.

[0044] [Figure 12I] This is a block diagram of the equalizer value list 1293 associated with bins of OFDM values ​​within a burst or frame.

[0045] [Figure 12J] This is a flowchart of the average equalizer processing 1500 according to some embodiments of the present disclosure.

[0046] [Figure 13A]This is an exemplary graph of the frequency response of a bandwidth containing multiple bins / subcarriers according to embodiments of the present disclosure.

[0047] [Figure 13B] This is an exemplary graph of the frequency response of a bandwidth containing multiple bins / subcarriers according to embodiments of the present disclosure.

[0048] [Figure 14A] This is a flowchart illustrating an exemplary enhanced equalizer processing according to an embodiment of the present disclosure.

[0049] [Figure 14B] This is a block diagram of some exemplary signal information processing operations according to embodiments of the present disclosure.

[0050] [Figure 15] This is a flowchart illustrating an exemplary current data bin label reassignment process according to an embodiment of the present disclosure.

[0051] [Figure 16] This is a flowchart illustrating an exemplary reference signal training mode test process with a reduced header according to an embodiment of the present disclosure.

[0052] [Figure 17] This is a block diagram of an exemplary ideal waveform for 802.11ax at 20 MHz according to embodiments of the present disclosure.

[0053] [Figure 18] This is a graph of an ideal IQ waveform specifically for an exemplary payload when the input parameter HeaderlessDemod is set to a training mode (e.g., HeaderlessDemodTraining and Execute, etc.) according to embodiments of the present disclosure.

[0054] [Figure 19] This is a graph of an ideal signal specifically for the extracted payload, as exemplified by the embodiments of this disclosure.

[0055] [Figure 20] This is a graph of the demodulated payload-specific signal according to an embodiment of the present disclosure.

[0056] [Figure 21] This is a flowchart illustrating an exemplary header mode test process according to an embodiment of the present disclosure.

[0057] [Figure 22] This is a block diagram of an exemplary electronic system that may be used as a platform for implementing and controlling the method according to embodiments of the present disclosure.

[0058] [Figure 23] This is a block diagram of a reduced header processing module 2300, which is an exemplary algorithm according to an embodiment of the present disclosure.

[0059] [Figure 24] This is a block diagram of an exemplary algorithm interpolation module according to an embodiment of the present disclosure.

[0060] [Figure 25] This is an extended version of the enhanced equalizer module and reassignment module, which are exemplary algorithms.

[0061] [Figure 26] This is a block diagram of a training module processing module, which is an exemplary algorithm according to an embodiment of the present disclosure.

[0062] [Figure 27] This is a block diagram of a pilot bin ideal value module, which is an exemplary algorithm according to an embodiment of the present disclosure.

[0063] [Figure 28] This is a block diagram of an iterative interpolation module, which is an exemplary algorithm according to an embodiment of the disclosure.

[0064] [Figure 29] This is a block diagram of an exemplary test method according to an embodiment of the present disclosure.

[0065] [Figure 30] This is a block diagram of an exemplary reduced header mode test process according to an embodiment of the present disclosure. [Modes for carrying out the invention]

[0066] Preferred embodiments of the Disclosure, illustrated in the accompanying drawings, are described in detail here. While the Disclosure is described in conjunction with these preferred embodiments, it will be understood that this is not intended to limit the Disclosure to these embodiments. On the contrary, the Disclosure is intended to include alternatives, modifications, and equivalents that may fall within the spirit and scope of the Disclosure as defined by the accompanying claims. Furthermore, the following detailed description of the Disclosure includes numerous specific details to provide a full understanding of the Disclosure. However, it will be apparent to those skilled in the art that the Disclosure can be implemented without these specific details. In other examples, well-known methods, procedures, components, and circuits are not described in detail so as not to unnecessarily obscure aspects of the Disclosure.

[0067] The presented systems and methods include efficient and effective approaches to handling modulation / demodulation in various scenarios, including situations where properly handling signal modulation / demodulation would otherwise be difficult (e.g., due to limited functionality / resources within the device, or economic unfeasibility). In some embodiments, a communication signal is demodulated without relying on several demodulation parameters contained within the signal that would be utilized differently in conventional approaches. In some exemplary implementations, a "reduced header information demodulation decision" process is performed on the communication signal. Within this communication signal, header information (e.g., preamble information, channel estimation-related information, reference information, etc.) is not initially readily available within the communication signal itself, and demodulation parameter information is favorably derived / developed / extrapolated from other information within the communication signal. By reducing the header size, devices under test (DUTs) with limited resources can be tested efficiently, thereby reducing the cost and complexity of the test.

[0068] With the above in mind, embodiments of this disclosure enable efficient and effective signal processing component testing. In some embodiments, when a signal is transmitted to or by a Device Under Test (DUT), an automated test instrument (ATE) system performs a "reduced header information demodulation" process. This process is performed in the test environment on the payload portion of information, where demodulation parameter information would normally be contained within other parts of the communication protocol. Demodulation parameter information is otherwise not readily available to the DUT. The results of upconverting and downconverting the signal within the DUT are captured for post-processing according to the "reduced header information demodulation" process and transmitted to the ATE. In some exemplary implementations, the reduced header information demodulation process is implemented by a computer algorithm running on a workstation associated with the ATE. The payload portion is communicated in accordance with the payload specification of the communication protocol, and information and data related to demodulation parameters specified by other parts of this protocol are not contained in this signal. In some exemplary implementations, this signal specifically contains less header / preamble information associated with the communication protocol than would otherwise normally be contained in the signal.

[0069] Figure 1A is a block diagram of an exemplary test environment or test system 100A according to embodiments of the present disclosure. Test system 100A is included in several embodiments of a signal processing test system. The test environment or test system 100A includes an automated test equipment (ATE) 110A and devices under test (DUTs) (e.g., 120A, 130A, etc.). The ATE 110A includes a controller 111A, test electronics 114A, a test or load board 119A, and a user interface (not shown). In some embodiments, the controller 111A is configured to direct the testing of multiple DUTs (e.g., DUTs 120A, 130A, etc.). The test electronics 114A is configured to test multiple DUTs. The controller 111A is coupled to the test electronics 114A and the test board or load board 119A. The load board 119A is configured to communicate with the test electronic equipment 114A and multiple devices under test (e.g., DUT120A, DUT130A, etc.).

[0070] In some exemplary implementations, the controller 111A includes a test mode selection module 112A. The test mode selection module selects between 1) reduced header signal processing test mode processing, 2) reference signal training mode test processing with reduced header, and 3) header test mode processing. Additional characteristics / features and operations of these modes are presented in other parts of this specification. Test electronics 114A is communicatively coupled to the controller 111A. It is understood that various factors may be used when making a mode selection. For example, one part of the DUT test may be performed in one mode, and another part of the DUT test may be performed in another mode. In some embodiments, the header test mode is selected for one burst (e.g., a burst with few OFDM symbols in the payload), and the reduced header signal processing test mode processing is selected for another burst (e.g., a burst with many OFDM symbols in the payload).

[0071] The test electronics 114A includes a demodulation information determination module 115A and a demodulation module 117A, which are coupled to communicate with each other. The demodulation information determination module 115A collects information associated with the demodulation operation, including the determination of signal processing information that would otherwise not be included in the reduced header information. The demodulation module 117A performs the demodulation operation based on the information received from the demodulation information determination module 115A. In some embodiments, the test electronics 114A directs the testing of the DUTs and includes resources allocated to each DUT. In some implementations, the test electronics 114A may include a field-programmable gate array (FPGA). Additional characteristics / features and operations of the test mode selection module 112A and the demodulation information determination module 115A are presented in other parts of this specification.

[0072] In some embodiments, the test mode selection module 112A selects a reduced header signal processing test process, and the demodulation information determination module 115A determines the signal processing information associated with the demodulation operation, which is otherwise not included in the header portion of the signal associated with the demodulation operation.

[0073] Various information associated with the DUT test (e.g., test mode selection, test results, preliminary analysis results, reconstitution test information, test instructions, etc.) is communicated between the test instrument 110A and the user test interface. In some exemplary implementations, the user test interface includes a processing unit, memory, and user input / output components (e.g., display, keyboard, etc.). The memory can store test-related information, the processing unit can process the information, and the user input / output components can communicate information with the user.

[0074] In some embodiments, the DUT (e.g., 120A, 130A, etc.) is considered a signal processing component. DUT 120A may be configured for final implementation in an end-use device 190A. In some embodiments, DUT 120A is configured for final end-use implementation in a communication device or system (e.g., a mobile phone, an Internet of Things (IoT) device, or a device conforming to the IEEE 802.11 wireless network protocol / standard, etc.). Device 190A includes a transceiver 191A, a signal processing core 192A, a processor / microcontroller 193A, memory storage 195A (e.g., ROM / RAM, etc.), and an I / O interface 194A (e.g., digital interface pins, etc.). The signal processing core 192A includes an analog signal processing component 172A, a baseband component 172A, registers 173A, and a cache 174A. When DUT120A is integrated into device 190A, it may have access to other resources and functions (e.g., memory / storage 195, processor / microcontroller 193A, etc.), but these resources are typically unavailable to DUT120A during testing prior to its integration into device 190A.

[0075] DUT120A is primarily associated with performing analog operations. In some exemplary implementations, DUT120 is a radio frequency (RF) integrated circuit chip. In some embodiments, DUT120A is associated with performing communication operations. DUT120A may be configured to perform transceiver operations and analog signal processing, etc.

[0076] In some embodiments, the DUT is an RF component that performs various modes of communication signal transmission and reception operations (including performing upconversion and downconversion operations on the signal). In the transmission activity, the carrier frequency generated by the local oscillator is multiplied by the baseband modulation signal, thereby combining the modulation information (e.g., in the form of a modulation signal, I and Q signals, etc.) and upconverting it to an RF signal. In the transmission activity, the carrier frequency generated by the local oscillator is multiplied by the baseband modulation signal, thereby combining the modulation information (e.g., in the form of a modulation signal, I and Q signals, etc.) and upconverting it to an RF signal. It is understood that the DUT may have various interface configurations (e.g., analog, digital, etc.) for coupling with the baseband component. The RF component is equipped with filtering capabilities to satisfy spectral mask requirements (e.g., it may perform parts such as interpolation in the analog and digital domains). In some embodiments, the novel test systems and methods presented herein receive information based on captured samples of communication signals that are upconverted and transmitted and communication signals that are downconverted and received. The novel ability to accurately process payload symbols containing reduced header information allows testing of DUTs with limited memory resources to store captured samples that would otherwise be overloaded by samples from larger header portions.

[0077] Figure 1B is a block diagram of two exemplary radio frequency (RF) integrated circuit DUTs according to embodiments of the present disclosure. DUT 150A includes mixer 151A, mixer 152A, amplifier 153A, amplifier 154A, mixer 181A, mixer 182A, adder component 183A, amplifier 184A, and local oscillator 155A. Mixer 151A is coupled to amplifier 153A, and mixer 152A is coupled to amplifier 154A. Mixers 181A and 182A are coupled to adder component 183A, which is coupled to amplifier 184A. Local oscillator 155A is coupled to mixer 151A, mixer 152A, mixer 181A, and mixer 182A. The local oscillator provides common-mode signals to mixers 151A and 181A, and also provides quadrature signals shifted by 90 degrees to mixers 152A and 182A. The radio frequency (RF) input signal 157A is supplied to mixers 151A and 152A. Amplifiers 153A and 154A provide analog output signals 158A to the baseband component. The analog input signal 188A from the baseband component is supplied to mixers 181A and 182A, which in turn supply the input to adder component 183A. Adder component 183A combines the common-mode portion of the signal and the quadrature-phase portion of this signal and transfers the result to amplifier 184A. Amplifier 184A provides the RF output signal 187A.

[0078] The DUT150B includes mixers 151B and 152B, amplifiers 153B and 154B, mixers 181B and 182B, adder component 183B, amplifier 184B, local oscillator 155B, and digital RF data component 159B. Mixer 151B is coupled to amplifier 153B, and mixer 152B is coupled to amplifier 154B. Local oscillator 155B is coupled to mixers 151B, 152B, 181B, and 182B. The local oscillator provides common-mode signals to mixers 151B and 181B, and also provides 90-degree phase-shifted quadrature signals to mixers 152B and 182B. Radio frequency (RF) input signals 157B are supplied to mixers 151B and 152B. The outputs of amplifiers 153B and 154B are coupled to a digital RF data component 159B. The digital RF data component 159B provides a digital output signal 158B to the baseband component. The digital input signal 188B from the baseband component is fed to mixers 181B and 182B, which in turn provide input to an adder component 183B. The adder component 183B combines the in-phase portion and the orthogonal-phase portion of the signal and transfers the result to amplifier 184B. Amplifier 184B provides an RF output signal 187B.

[0079] It is understood that various test approaches exist. Different types of DUTs may exist with various configurations. In some embodiments, the DUT may be configured as a more complete device / system (e.g., integrated system, circuit board level, etc.) closer to the final end-use configuration. Figure 1C is a block diagram of an exemplary test environment or test system 100C according to some embodiments. The exemplary test environment or test system 100C is similar to the exemplary test environment or test system 100A, except that the device circuit board 190C is being tested as a DUT similar to DUT 190A.

[0080] The test environment or test system 100C in Figure 1C includes an automated test instrument (ATE) 110C and a device under test (DUT) (e.g., 190C, 199C, etc.). The ATE 110C includes a controller 111C, a test mode selection module 112C, test electronics 114C, a demodulation information module 115C, a demodulation module 117C, a test or load board 119C, and a user interface (not shown). In some exemplary implementations, device 190C includes a transceiver 191C, a signal processing core 192C, a processor / microcontroller 193C, memory storage 195C (e.g., ROM / RAM, etc.), and an I / O interface 194C (e.g., ATE digital interface pins, etc.). In some embodiments, the DUT 199C is an end-use product (e.g., a mobile phone, a device compliant with the IEEE 802.11 wireless network protocol / standard, etc.). Part of the testing of the DUT (e.g., DUT190C, DUT199C, etc.) relates to the testing of analog components within the DUT (e.g., RF chips, RF processors, etc.).

[0081] As DUT configurations approach end-use device levels, utilizing the proposed approaches (e.g., reduced header demodulation) offers several advantages. The choice between modes (e.g., full header mode, reduced header mode) allows for flexible testing and a potential reduction in overall test time. As DUT configurations approach end-use levels, reduced header demodulation offers several further benefits. When the goal is to directly test analog components within the DUT, reduced-length test pattern streams that are more relevant to the analog components can be used. Enabling isolated testing of analog components reduces the risk of test results being compromised by other components. This ability to isolate tests also facilitates "splitting" the test, or testing different parts of the DUT at different times, which in turn helps simplify debugging challenges, etc.

[0082] In some embodiments, the DUT may include multiple test functions. Figure 2A is a block diagram of an exemplary DUT200 according to an embodiment of the present disclosure. It is understood that DUT200 is similar to DUT120A. DUT200 includes a boundary scan register 210, a core 220, and a test access port 270. The boundary scan register 210 includes multiple boundary cancels (BSCs). The boundary cancels are similar to boundary cancel 215. Boundary cancel 215 includes multiplexers (MUX) 211 and 214, and flip-flops 212 and 213. MUX211 is coupled to flip-flop 212, which is coupled to flip-flop 213, and as a result, flip-flop 213 is coupled to MUX214. Based on the shift DR signal, MUX211 can select and transfer any of the normal operation data inputs, or transfer the scan test data input as a scan-out signal, and also transfer it to flip-flop 212 for latching in response to the clock DR. In response to the update DR signal, flip-flop 212 is updated with the information.

[0083] MUX214 selects and transfers either data in or from flip-flop 213 based on a mode control signal. Core 220 includes scan chain area A, scan chain area B, and scan chain area C. Scan chain area A includes a combinational circuit and multiple scan cancels (SCs) coupled together in a scan chain configuration. The combinational circuit performs its normal function during mission mode operation. The scan cancels can function as both sequential circuits during mission mode operation and can also support test operations (e.g., scan-in, capture, scan-out, etc.) during test mode operation. Test information may be communicated from one scan cancel to another in the scan chain. It is understood that the DUT may also include flip-flops that are not part of the scan chain and flip-flops dedicated to scan chain operation. Scan cancel (SC) 270 includes a multiplexer 271 and a flip-flop 272. Based on the scan enable signal, the MUX271 can select either mission mode operation data input or scan test data input in response to the clock and reset signals and transfer it to the flip-flop 272. The information is then output from the flip-flop 272 to other mission mode operation circuits and other scan chain components.

[0084] The test access port (TAP) 230 includes a TAP controller coupled to the test reset input, a test clock input, a test mode input, MUX233, an instruction register, a bypass register, and an identification information register coupled to MUX232. MUX232 is coupled to MUX225, an additional capture memory 231, a test block, and a boundary scan register. MUX233 is coupled to the instruction register, MUX232, and a test data output. The test data input is coupled to the boundary scan register, a debug block, a test block, scan chain A, scan chain B, and scan chain C. The DUT200 may be compatible with various standards (e.g., JTAG, IEEE1149.1, etc.).

[0085] Typically, the DUT lacks sufficient memory resources (e.g., scan test chain resources, capture memory resources, and waveguide generation resources) to easily support testing of various functions (e.g., communication functions, demodulation operations, etc.) without the novel approaches presented herein. Integrating a large amount of dedicated circuitry and other components for testing into the analog signal processing component presents significant problems and challenges (e.g., limited chip space and relatively high cost due to the limited number of times components can be tested). In some embodiments, with respect to a DUT that primarily performs analog signal processing during normal non-test operation, the signal is processed and transferred to other components in the system without the need to "store" intermediate or final results in the analog DUT. The analog processing component does not include the many more normal operation components (e.g., memory capacity, flip-flops in the scan chain, etc.) available for dual normal / test operation. Problems and challenges related to the "lack" of memory capacity available for test operations (e.g., capture, scan chain, etc.) are exacerbating with advancements in technology and communication protocols.

[0086] Figure 2B is a block diagram of an exemplary automated test system (ATE) 250 according to an embodiment of the present disclosure. The automated test system 250 includes a digital test function module 251, an arbitrary waveform generation module 252, an arbitrary waveform digitization (AWD) sequencer 253, a DC resource 254, and a time measurement resource 255, all of which are coupled to a master clock 257. The digital test function module 251 includes a vector memory coupled to a real-time comparator (coupled to full memory), and a drive formatter and edge timing components. The edge timing components are coupled to a receive formatter coupled to a digital capture memory. Pin electronics are coupled to the drive formatter, receive formatter, MUX time measurement, and DC test unit.

[0087] The arbitrary waveform generation module 252 includes an arbitrary waveguide generation (AWG) component coupled to an AWG sequencer component, a waveform source memory, and an amplifier / filter coupled to the resulting SFG and MUX. The MUX is coupled to a DC offset component, test head #1, and test head #2. The arbitrary waveform digitization (AWD) sequencer 253 includes a waveguide digitizer coupled to a multimode modulation / demodulation parameter determination module, a digitizer sequencer, a waveform capture memory, and an amplifier / filter coupled to the MUX. The MUX is coupled to test head #1 and test head #2. The DC resource 254 includes a DC data memory and a time measurement resource module 255 including a time measurement unit / time interval analyzer.

[0088] In some embodiments, there are insufficient memory resources (e.g., capture memory resources, waveguide generation resources, etc.) to easily support testing of various functions (e.g., communication functions, demodulation operations, etc.). As more functions are integrated and DUTs and communication protocols become more complex, testing DUTs has consequently become more complex, increasing the demand for more capable test systems. The demand to test numerous DUTs simultaneously and in parallel further complicates testing. While ATE test resources can be substantial, they are not infinite, and allocating resources for all different test activities is costly and impractical, thus complicating the allocation of test resources. As a result, conventional test systems, on an individual DUT basis, do not have enough memory available for some activities (e.g., arbitrary waveguide generation, etc.).

[0089] The novel systems and methods described herein enable ATE systems to perform tests on the modulation and demodulation performance of DUTs that would otherwise be impractical or impossible. Furthermore, the novel systems and methods improve the performance of ATE systems. Test efficiency is improved through a reduction in the need for large test patterns associated with long header information (e.g., those that would otherwise be time-consuming, inefficient, and prone to errors). The amount of ATE resources (e.g., memory resources) required to handle large test patterns is also reduced.

[0090] Figure 3A is a flowchart of an exemplary multimode modulation / demodulation parameter determination method 300, including reduced header processing, according to an embodiment of the present disclosure. The multimode modulation / demodulation parameter determination method 300 is included in several embodiments of signal processing test methods. In one exemplary implementation, the multimode modulation / demodulation parameter determination method 300 relates to test operations within a radio frequency (RF) component (e.g., upconversion operation, downconversion operation, initial front-end transmission operation, initial front-end reception operation, etc.). The multimode modulation / demodulation parameter determination method 300 readily addresses effective testing of the performance of RF components in modulation and demodulation of communication signals using reduced header information.

[0091] In block 310, the test mode selection process is performed. This process enables flexible and efficient responses to various test scenarios. For example, multiple test modes are available, along with the ability to effectively address different demodulation challenges, such as communication bursts associated with very long header sections. Further explanation of the test mode selection process operation is provided in other parts of this specification (e.g., the explanation of the test mode selection process shown in Figure 7).

[0092] In block 320 of Figure 3A, the demodulation information determination process is performed. In some embodiments, various types of demodulation information (e.g., timing information, frequency error, equalization value, etc.) are determined based on reduced header mode operation. In some exemplary implementations, the demodulation information is determined without conventional reliance on header information. Additional descriptions of the demodulation information determination process operation are presented in other parts of this specification (e.g., blocks 730, 740, 750, 800, 1600, etc.). In block 330, full demodulation is performed. In some embodiments, full demodulation includes determining various parameters associated with demodulation. These parameters may include, among other things, the full equalizer value, frequency error value and sampling clock error, and error vector amplitude (EVM). Additional descriptions of the full demodulation operation are presented in other parts of this specification.

[0093] In some embodiments, full demodulation is performed from the perspective of the DUT. In some exemplary implementations, the DUT is a radio frequency (RF) integrated circuit (e.g., similar to DUTs 150A and 150B), and full demodulation is the demodulation that produces the output signal of the DUT (158A, 158B). It is understood that additional demodulation may be performed on the output signal of the DUT, which is not considered part of full demodulation. In some exemplary implementations, additional demodulation operations (e.g., FFT, data bit decoding, etc.) may be performed on the communication signal by backend baseband digital signal processing, but are not considered part of full demodulation from the perspective of the radio frequency (RF) integrated circuit DUT. In other embodiments, additional demodulation operations (e.g., FFT, data bit decoding, etc.) may be performed on the communication signal by backend baseband digital signal processing, but are considered part of full demodulation (e.g., from the perspective of a different DUT (e.g., 190C, 199C, etc.)).

[0094] Figure 3B is a block diagram of an exemplary multimode modulation / demodulation parameter determination test environment. The multimode modulation / demodulation parameter determination test environment includes a test system 390 (e.g., ATE110A, 110C, etc.) and a DUT391 (e.g., DUT120A, 150A, 150B, etc.). The test system 390 directs the testing of the DUT391, in which various types of signal processing tests are performed. In some embodiments, the test system 390 provides simulated test information to the DUT391 and receives captured test information (e.g., associated with real in-phase (I) signals, virtual quadrature-phase (Q) signals, etc.). With respect to EVM, it is understood that the test system 390 can direct testing of both transmitter RF output characteristics and receiver RF input characteristics. The DUT391 performs operations associated with the receiver module 341A, carrier demodulation module 342A, transmission module 341B, and carrier modulation module 342B. The test system 390 includes a multimode modulation / demodulation parameter determination module 370 and a control module 371. The test system 390 performs operations associated with the cyclic prefix removal module 344, the fast Fourier transform (FFT) module 345, the equalization module 346, and the message decoder module 347. In some embodiments, parts of the operation of the carrier demodulation module 342A are performed within the test system 390. The receiver module 341 performs various activities associated with the initial reception of a communication (e.g., carrier bandpass filtering, synchronous operation, automatic gain control, etc.).

[0095] The carrier demodulation module 342A performs various operations associated with the demodulation of the carrier frequency (e.g., demodulation based on a local oscillator, 90-degree tuned demodulation to the in-phase (I) / "real" signal component and the quadrature (Q) / "virtual" component, etc.). Similarly, the carrier modulation module 341B performs various operations associated with the modulation of the carrier frequency. In some embodiments, the operations associated with the receiving module 341A, the carrier demodulation module 342A, the transmission module 341B, and the carrier modulation module 341B are performed by the transceiver component and the analog processing component (e.g., 191A, 172A, etc.).

[0096] The multimode modulation / demodulation parameter determination module 370 in Figure 3B verifies various modulation / demodulation parameters. In some embodiments, the multimode modulation / demodulation parameter determination module 370 performs a multimode modulation / demodulation parameter determination method. In some exemplary implementations, the multimode modulation / demodulation parameter determination method is similar to method 300. The multimode modulation / demodulation parameter determination module 370 receives input from the test system 390. In some embodiments, this input indicates the selection of a test mode. The operation by the multimode modulation / demodulation parameter determination module 370 may be performed within the test system 390.

[0097] The cyclic prefix removal module 344 removes cyclic prefixes added to these signals (e.g., in the transmission source). The Fast Fourier Transform (FFT) module 345 converts these signals into signals corresponding to a discrete Fourier series configuration. The equalization module 346 performs equalization operations on these signals based on information received (e.g., inverse estimates). The multimode modulation / demodulation parameter determination module 370 performs data decoding operations (e.g., QAM demodulation / desampling operations, parallel-to-serial conversion, and MUX operations).

[0098] The message decoder module 347 performs various demodulation operations. In some embodiments, the message decoder module 347 outputs a stream of data corresponding to the unprocessed transmitted data. In some exemplary implementations, the message decoder module 347 decodes data symbols (e.g., QAM demodulation / desampling of data constellation point information, and parallel-to-serial multiplexing (MUX) to concatenate logical bits corresponding to the constellation point information).

[0099] The communicated information is organized into "blocks" of information corresponding to parts of the signal communication (e.g., header, payload, or body). In some exemplary implementations, the information blocks are communicated according to a protocol (e.g., a communication protocol, network protocol, storage protocol, etc.) that includes definitions of the blocks and the organization and configuration of the information. In some embodiments, this information includes a header portion and a data / payload portion. In some embodiments, the communication protocol organizes the information according to the communication protocol layer, with the header portion containing supplementary information associated with the protocol layer (e.g., signal processing-related parameters, constants, metadata, etc.), and the data payload portion containing data / information from another protocol layer.

[0100] Furthermore, the communication protocol layer is organized into a communication protocol layer hierarchy. It is understood that several layers may exist within the communication protocol layer hierarchy. In some exemplary implementations, the protocol layer is organized from a layer concerning the configuration of user / host application information / data to a layer concerning the configuration of information about actual transmission / reception on the physical communication medium, with multiple layers in between. In some embodiments, these layers are referred to as higher or lower relative to their relative positions within the hierarchy. The layer concerning the configuration of user / host application information / data is referred to as the upper layer, and the layer concerning the configuration of information about actual transmission / reception on the physical communication medium is referred to as the lower layer. In some exemplary implementations, the layer concerning the configuration of user / host application information / data is referred to as the lower layer, and the layer concerning the configuration of information about actual transmission / reception on the physical communication medium is referred to as the upper layer.

[0101] The header portion is information transmitted before the payload portion. It is understood that some protocols have different designations (e.g., preamble, header, etc.) for information transmitted before the data / payload portion. In an effort to avoid confusion, as referred to herein, header information includes information received in the preamble portion of a signal, information received in the header portion of a signal, and combinations of information received in both the preamble and header portions of a signal.

[0102] In some embodiments, signals are structured according to protocol data units (PDUs) of a communication protocol. In some exemplary implementations, a PDU is a single unit of information communicated (e.g., transmitted, received, etc.) between similar entities (e.g., entities considered at similar protocol levels, network peer entities, etc.). A PDU includes information associated with a header portion / section and a portion of information associated with a data / payload portion or section. The data / payload portion may be considered a service data unit (SDU). In some exemplary implementations, a service data unit is a unit of information that has passed between a higher communication protocol level (e.g., a level closer to the user / host application level, etc.) and a lower communication protocol level (e.g., a level closer to the physical communication level, etc.) in order to be provided / encapsulated by a lower communication protocol level. It is understood that the payload portion of the first communication protocol layer may include information configured within the second communication protocol layer as header information of the second communication protocol layer and payload information of the second communication protocol layer (e.g., from the perspective of the first communication protocol layer, etc.). The first communication protocol layer is a higher communication protocol layer, and the second communication protocol layer is a lower communication protocol layer.

[0103] The novel approach described is understood to be flexible in that it can be configured for implementations involving various communication protocols. In some embodiments, the novel approach described is compatible with IEEE 802.11-based wireless network protocol standards (e.g., 802.11 a / b / g / n / ac / ax / be, etc.). In other embodiments, the novel approach described is compatible with Wi-Fi®-based wireless network protocols / standards (e.g., Wi-Fi 4, 5, 6, 7, etc.). The novel approach described may also be compatible with communication layer models / suites (e.g., Open System Interconnection (OSI), Internet Communication Suite, Transmission Control Protocol / Internet Protocol (TCP / IP), etc.). The basic frame structure / configuration of an 802.11-based burst includes a header portion, followed by a data / payload portion (including OFDM symbols).

[0104] Figure 4A is a block diagram of an exemplary PDU401A frame or packet according to several embodiments. The PDU401A is configured according to a communication protocol. The PDU401A includes a header portion / section 402A and a data / payload portion 403A. The header portion / section 402A and the data / payload portion / section 403A contain information organized within fields. It is understood that the PDU401A can be considered as a communication frame and a communication packet, etc. It is understood that the communication information may be composed using other fields not shown (e.g., tail portions / sections at the end of the PDU, etc.).

[0105] Figure 4B is a block diagram of exemplary PDU frames or packets in different communication protocol / model layers according to embodiments of the present disclosure. PDU 401B is a block diagram of an exemplary frame in a second communication protocol layer 409A. In some exemplary implementations, the communication configuration (or “frame”) 401B includes a header portion / section 402B and a data / payload portion 403B. PDU 401C is a block diagram of an exemplary frame in a first communication protocol layer 409B. In some exemplary implementations, the communication configuration (or “frame”) 401C includes a header portion / section 402C and a data / payload portion 403C.

[0106] Information "moves" from layer to layer within the communication protocol hierarchy and is processed according to the requirements of each layer. This processing often involves adding or removing header information associated with the layer. Whether header information is added or removed is typically determined by whether the overall direction is higher or lower in the communication protocol hierarchy. In some embodiments, when a PDU from a higher level moves to a lower level to create a "new" PDU at a lower level, header information associated with the lower level is added. In some embodiments, an upper-layer PDU is considered a lower-level service data unit (SDU) encapsulated (e.g., wrapped inside) by a lower-level PDU. Payload section 403C includes SDU 404C (also known as PDU 401B from layer 409A) and, together with header section 402C, is encapsulated to form a "new" PDU 401C.

[0107] Whether communication information / signals include or do not include reduced header information depends on the perspective of the communication protocol layer. From the perspective of one communication protocol layer, if communication / signals lack some or substantially all header information, the communication / signals may be considered reduced header / headerless; on the other hand, from the perspective of another communication protocol layer, communication information may be considered to include or have a header. In some exemplary implementations, a payload section 403C containing an SDU404C (also known as a PDU401B) is considered headerless even if the SDU404C contains header information in the header section 402B from the PDU401B. In some embodiments, if the header section 402C is missing (e.g., not added to this information), the communication signal is also considered headerless. In some embodiments, the data / payload portion 403C contains the communication configuration PPDU401B (and consequently, the header portion / section 402B and the data / payload portion 403B).

[0108] The reduced header information demodulation process described herein operates on the payload portion of a PDU. In some exemplary implementations, the payload portion of a PDU is considered “headerless” from the perspective of the communication protocol layer associated with the PDU. In some exemplary implementations, the reduced header information demodulation process operates on information that is headerless from the perspective of a first communication protocol layer 409B (this information includes data payload section 303C information, but not information from header section 402C). Payload information (e.g., 403C) is considered “headerless” from the perspective of a protocol layer (e.g., 409B), but the payload information includes “header” information (e.g., 402B) from another protocol layer.

[0109] It is understood that a communication protocol layer may have multiple sublayers. These sublayers have different functions and perform different operations associated with their respective communication protocol layers. Figure 4C includes various exemplary organization and configuration (also called "frames") of information within a PPDU by several embodiments.

[0110] Communication configuration 410A is a block diagram of an exemplary frame according to several embodiments. Communication configuration 410A is compatible with a Physical Protocol Data Unit (PDU) frame. Frame 410A includes a header portion / section 420A and a data / payload portion 430A. The header portion / section 420A and the data / payload portion / section 430A contain information organized within the fields.

[0111] Communication configuration 410B is a block diagram of an exemplary frame according to several embodiments. Frame 410B is compatible with a Physical Layer Protocol Data Unit (PPDU). Frame 410B includes a header portion / section 420B and a data / payload portion / section 430B. In some embodiments, the header portion / section 420B includes a preamble field 421B and a signaling field 422B.

[0112] Frame 410C is a block diagram of exemplary communication information organization and configuration (also called a “frame”) according to several embodiments. Frame 410C is compatible with Physical Layer Protocol Data Units (PPDUs). Frame 410C includes a header portion / section 420C and a data / payload portion / section 430C. In some embodiments, the data / payload portion / section 430C includes packets 430C and 450C. Packet 440C includes a packet header portion / section 441C and a packet data / payload portion / section 442C. Packet 450C includes a packet header portion / section 451C and a packet data / payload portion / section 452C.

[0113] Frame 410D is a block diagram of exemplary communication information organization and configuration (also called a “frame”) according to several embodiments. Frame 410D is compatible with Physical Layer Protocol Data Units (PPDUs). Frame 410D includes a header portion / section 420D and a data / payload portion / section 430D. In some embodiments, the header section 420D includes a preamble field 421D and a physical header 422D.

[0114] In some exemplary implementations, the data / payload portion / section 430D includes a physical layer service data unit (SDU) 440D (also known as MPDU) and a physical layer service data unit (SDU) 450D (also known as MPDU). The physical layer service data unit (SDU) 440D includes a MAC layer PDU (MPDU). The MPDU 440D includes a MAC header portion / section 441DD and a MAC data / payload portion / section 442D. The MPDU 450D includes a MAC header portion / section 451DD and a MAC data / payload portion / section 452D. In some embodiments, the medium access control (MAC) layer protocol data unit (PDU) is a physical layer service data unit (SDU).

[0115] Figure 4D includes exemplary organization and configuration of information according to several embodiments. The communication configuration or frame 410F is a block diagram of an exemplary frame according to several embodiments. Frame 410F is compatible with frame configuration or physical layer protocol data unit (PPDU) configuration. Frame 410F includes a header portion / section 420F and a data / payload portion / section 430F. In some embodiments, the header portion / section 420F includes a preamble field 421F and a signaling field 422F. The data / payload portion / section 430F includes orthogonal frequency division multiplexed OFDM symbols 441F, 442F through 448F. It is understood that modulated forms of OFDM symbols at lower protocol levels may include header information associated with multiple higher protocol levels. OFDM symbols are configured for communication within the physical layer of the communication protocol, and some of the OFDM symbols include header information from protocol layers (e.g., link layer, transport layer, etc.), even though they are considered headerless payload data from a physical layer perspective.

[0116] Figure 4E is a block diagram of several exemplary signal-to-physical layer protocol data unit (PPDU) configurations (also called "frames") for different IEEE 802.11-based wireless network protocols / standards. A PPDU includes a physical layer header portion and a physical layer data portion. The header portion includes various training fields, including a reference training symbol, and the signal field (SIG) includes rate, length, and parity information. It is understood that the size of the header portion increases significantly when the configuration of new IEEE 802.11-based communication protocols changes (e.g., when a new version is released).

[0117] The PPDU451 conforms to the IEEE 802.11a / g communication protocol, and its header includes a legacy short training field (L-STF), a legacy long training field (L-LTF), and a legacy signaling field (L-SIG). On the other hand, the PPDU452 conforms to the IEEE 802.11n high-throughput (HT) communication protocol, and its header includes a legacy short training field (L-STF), a legacy long training field (L-LTF), a legacy signaling field (L-SIG), a high-throughput signaling field (SIG), a high-throughput short training field (STF), and one to four high-throughput long training fields (HT LTF). The PPDU453 conforms to the IEEE 802.11ac ultra-high throughput (VHT) communication protocol, and its header includes a legacy short training field (L-STF), a legacy long training field (L-LTF), a legacy signaling field (L-SIG), an ultra-high throughput signaling field A (SIG-A), an ultra-high throughput short training field (STF), 1 to 8 ultra-high throughput long training fields (VHT LTF), and an ultra-high throughput signaling field B (SIG-B).

[0118] Additionally, PPDU454 conforms to the IEEE 802.11ax High Efficiency (HE) communication protocol, and its header includes a legacy short training field (L-STF), a legacy long training field (L-LTF), a legacy signaling field (L-SIG), a repeating non-HT signaling field (RL-SIG), a high efficiency signaling field A (SIG-A), a high efficiency short training field (STF), and 1 to 8 high efficiency long training fields (VHT LTF). Finally, PPDU455 is compliant with IEEE 802.11be(HET) and is an extremely high-throughput communication protocol. Its header includes a legacy short training field (L-STF), a legacy long training field (L-LTF), a legacy signaling field (L-SIG), a repeating legacy signaling field (RL-SIG), a universal signaling field (U-SIG), an extremely efficient signaling field (EHT-SIG), an extremely efficient short training field (EHT-STF), and an extremely efficient long training field (EHT-LFT). The duration of the EHT-LFT symbol is determined by the GI+LFT size.

[0119] In some embodiments, the reduced header information demodulation test system and method according to this disclosure are compatible with a subcarrier communication approach. In some exemplary implementations, the subcarrier communication approach includes multiple tones organized within a communication channel. These tones may be organized and configured in accordance with the IEEE 802.11 radio network protocol / standard.

[0120] There are at least two aspects of evolving communication protocol standards that pose significant challenges to test operations. The first aspect is that the header portion and corresponding header information increase with the new protocol standard, meaning that more information is required for sampling and capturing during testing. The second aspect is that increased bandwidth leads to an increase in the sampling rate. In some exemplary implementations, a DUT requires 400 samples to test a signal conforming to OFDM802.11a and between 15,360 and 24,320 samples to test a signal conforming to OFDM802.11be. As previously shown, many communication DUTs have limited resources for test operations (e.g., memory, scan test cells, etc.), and the increased information required for testing (e.g., associated with sampling for capture, etc.) overloads these limited resources. The limited resources become filled with information about the header portion and therefore cannot handle proper testing of the payload portion. The reduced header information demodulation test system and method according to this disclosure overcome these challenges and, advantageously, enable proper testing of the payload portion. Furthermore, storing information associated with waveforms (e.g., the output of an AWG component) places less load on the memory of the DUT and ATE systems.

[0121] It is understood that different power levels can be assigned to different RUs, and that RUs can be assigned across various carrier bandwidths. More tones / subcarriers exist within the layer than tones assigned to user data communications. Some tones / subcarriers may be used for control operations (e.g., pilot, guard / null space, etc.). It is understood that RUs and tones may be organized and configured according to the IEEE 802.11 radio network protocol / standard.

[0122] Figure 5A is a block diagram of exemplary signal configurations according to several embodiments. Tones are arranged at different levels based on the number of tones contained within a resource unit (RU). In some exemplary implementations, resource units are used to represent groups of subcarriers (e.g., tones, etc.) used in communication (e.g., downlink transmission, uplink transmission, etc.). For example, level 510 contains 37 RUs (1A to 37A) with each RU containing 26 tones, level 520 contains 16 RUs (1B to 16B) with each RU containing 52 tones, level 530 contains 8 RUs (1C to 8C) with each RU containing 106 tones, level 540 contains 4 RUs (1D to 4D) with each RU containing 242 tones, level 550 contains 2 RUs (1E and 2E) with each RU containing 484 tones, and level 570 contains 1 RU (1F) with 996 tones.

[0123] In some embodiments, the subcarrier is associated with a frequency bandwidth or range. The frequency bandwidth is defined by the communication protocol (e.g., IEEE 802.11 wireless network protocol / standard). In other embodiments, the reference signal is associated with a predetermined, defined, known characteristic. Each received reference signal characteristic is determined and compared with a corresponding predetermined, defined characteristic.

[0124] Figure 5B is a block diagram of an exemplary frequency spectrum of subcarriers and corresponding bins according to embodiments of the present disclosure. Each frequency bin corresponds to a subcarrier. User subcarriers and corresponding bins are distributed throughout the spectrum (e.g., user 1 subcarrier, user 2 subcarrier, etc.). This block diagram also shows the subcarrier location / space with respect to a reference tone / signal (e.g., pilot tone, etc.) in some embodiments. Data bins exist between the pilot bins. At both ends of the spectrum are subcarriers / bins that act as guard subcarriers (e.g., to help mitigate interference from other spectra). In some exemplary implementations, a non-pilot tone null subcarrier exists at the center carrier frequency value.

[0125] Figure 5C is a graph block diagram of an exemplary transmission of an OFDM symbol tone / signal according to an embodiment of the present disclosure. This transmission includes OFDM symbols 0, 1, and 2 concatenated within a “burst” frame sequence over the time domain. One OFDM burst contains an OFDM symbol. An OFDM symbol contains n data bitstreams from 1 to subcarrier 1, each assigned through N bins. One modulated subcarrier is equal to one point in frequency and time. An IFFT creates an OFDM waveform from the OFDM subcarriers. One OFDM symbol includes a guard interval in addition to the IFFT OFDM waveform.

[0126] The novel approach makes it possible to determine the start of OFDM symbols 0, 1, and 2 based on information within the OFDM symbols in the payload portion of the "burst" frame, without relying on information from the header portion of the "burst" frame. It is understood that the novel approach described herein is compatible with implementations in various communication protocols (e.g., OFDM protocol, OFDMA protocol, etc.).

[0127] Figure 5D is a block diagram of an exemplary OFDM symbol payload partial transmission using reduced header information according to an embodiment of the present disclosure. As previously shown, header information (e.g., preamble information, reference information, etc.) is often used to correct issues associated with communication (e.g., equalization, etc.). OFDM symbol payload partial transmission 505 includes OFDM symbols 501, 502, and 503. OFDM symbols 501, 502, and 503 are configured within a loop pattern. In some embodiments, the payload data is configured without preamble training. For example, the start of OFDM symbol 501 loops around to the end of the OFDM symbol 503 reference symbol. This pattern is considered continuous (e.g., no start, no end, etc.). OFDM symbol 502 includes a cyclic prefix portion 502A and an end portion 502B at the start of OFDM symbol 502. The cyclic prefix portion 502A is a copy of the end portion 502B. OFDM symbol 501 includes a cyclic prefix portion and an end portion 501B. OFDM symbol 503 includes a cyclic prefix portion 503A at the beginning of OFDM symbol 503 and an end portion.

[0128] Figure 5E is a block diagram of various exemplary subcarrier configuration assignments according to embodiments of the present disclosure. Dots or circles represent various subcarriers within the communication bandwidth. Filled dark circles represent pilot subcarrier signals, and unfilled circles represent other subcarrier signals (e.g., data subcarriers, null subcarriers, etc.). The Y-axis corresponds to the frequency values ​​of the various subcarriers, and the X-axis represents the transmission of subcarriers over time. Different pilot subcarrier configurations (e.g., block, comb, scattering, etc.) may be implemented to address different conditions or concerns. While pilot signals provide valuable information regarding the operation of the DUT, designating all subcarriers as pilots for the entire duration would not enable the communication of other data. Therefore, pilot subcarrier configuration is often a trade-off between different objectives. In configuration 591, all subcarriers within the bandwidth are intermittently used as pilot subcarriers, providing indication of all subchannel conditions. In configuration 592, intermittent subcarriers within the bandwidth are used as pilot subcarriers that continuously provide indications of the subchannel conditions of those subcarriers. In configuration 593, one pilot subcarrier information is transmitted continuously, while other pilot subcarrier information is intermittent with respect to frequency and time. The pilot subcarrier signal is a reference signal with characteristics (e.g., BPSK modulation) that are resistant to misinterpretation due to communication conditions (e.g., channel conditions, equipment vibration differences, etc.).

[0129] Various subcarrier configurations are predetermined (e.g., known by the ATE). Subcarrier configuration protocols may be publicly known (e.g., according to published industry standards, IEEE 802-11 protocols, etc.) or privately known (e.g., through private interpretations of industry standards, confidential configurations, trade secrets, etc.). Subcarrier configuration information can be used by the ATE to implement various novel reduced header systems and methods that are accessible and presented in other parts of this specification. In some embodiments, the subcarrier configuration is used to extract information (e.g., related to timing, frequency errors, ideal values, equalizers, etc.) from the payload portion of the communication. In some exemplary implementations, this information is extracted from the complex payload portion without relying on the availability of header information.

[0130] The intention is to accurately transmit the information within the original data stream. In some embodiments, exemplary data streams are shown in Figure 5C. The data is modulated according to several constellation maps in the process being communicated. Errors or deviations from ideal values ​​in each constellation map are often associated with communication challenges (e.g., inappropriate channel characteristics, frequency response characteristics, scattering, fading, power loss with distance, etc.). Figure 6A is a block diagram of several exemplary constellation maps associated with signal communication according to embodiments of the present disclosure. Block dots indicate symbols at ideal locations (e.g., ideal I and Q maps). Constellation map 610 is a BPSK map with 2 possible symbols and 1 information bit / symbol. Constellation map 620 is a QPSK map with 4 possible symbols and 2 information bits / symbol. Constellation map 630 is a 16QAM map with 16 possible symbols and 4 information bits / symbol. It is understood that various other QAM configurations (e.g., 64QAM, 256QAM, 1024QAM, etc.) may exist.

[0131] Figure 6B is a block diagram of several exemplary constellation map errors associated with signal communication according to several embodiments. The constellation map includes ideal symbol locations, shown as filled black dots (e.g., 640, 650, 670, 680, etc.), and symbol locations associated with transmitted signals, shown as hollow dots (e.g., 641, 642, 674, etc.). The constellation map shows ideal or reference vector 690 and effort vectors 671 and 672.

[0132] Figure 7 is a flowchart of an exemplary test mode selection process 700 according to embodiments of the present disclosure. The test mode selection process 700 provides a flexible and adaptable selection among test modes (e.g., header inclusion mode, reduced header training mode, reduced header mode; etc.). The test mode selection process 700 enables the ATE to perform various test scenarios with different test characteristics and functions. In some embodiments, this selection enables "backward" compatibility with legacy test approaches and also enables the implementation of novel test approaches described herein that would otherwise be impractical or impossible in legacy test approaches.

[0133] In block 710, a selection trigger is received. The selection trigger may be based on a communication protocol or the overall test approach, etc. There may be a request to perform several tests on the DUT using a signal with a full header, and then another signal with a reduced header. There may be a request to obtain a statistical sample of the DUT's full header processing capability, and then increase the overall throughput using the reduced header. For example, first, test whether the header information portion is properly processed / stored in a limited chip memory, and then in a second "run," verify whether the payload is processed / stored correctly.

[0134] In block 720, the test mode is determined based on the received trigger information. The capabilities of the different available test modes are considered in 720 in response to the selection trigger. In some embodiments, the selection trigger may indicate that the first DUT does not have enough memory to handle testing a communication burst containing larger header information. In some embodiments, if the DUT fails the first test run, the failure indication acts as a trigger to perform a second test run using a different test mode.

[0135] In block 730, reduced header mode test processing is selected. In some embodiments, the DUT does not have sufficient resources (e.g., memory, etc.) to efficiently perform demodulation tests. If the communication protocol specifies relatively large header information that exceeds the DUT's ability to respond appropriately to the test scenario, in 730, reduced header mode test processing may be selected to overcome the challenges associated with large amounts of header information.

[0136] In block 740, a reduced header reference signal mode test process is selected. In some embodiments, the reduced header reference signal mode test process is selected as a secondary test. In some exemplary implementations, the reduced header mode test process is selected for a first test run on the DUT, and the reduced header reference signal mode test is selected for a second test run. By performing the second test run using a different test mode, any anomalies that were not captured by the first test run can be identified. The anomalies may be due to test characteristics of the first test mode that the second test mode may not be affected by.

[0137] In block 750, a header mode test process is selected. In some embodiments, the header mode test process can produce more reliable results for certain complex test scenarios. In test scenarios requiring very high QAM demodulation, the results of the header mode test process may be more reliable than the reduced header mode test process and the reduced header with reference signal mode test process. The reduced header mode test process 800 is included in the demodulation decision process (e.g., similar to block 320).

[0138] Figure 8 is a block diagram of an exemplary reduced header mode test process 800 according to an embodiment of the present disclosure. In some embodiments, the reduced header mode test process 800 is included in a reduced header communication signal processing test method. The reduced header mode test process is used when reference signal information is reduced / unavailable. In some exemplary implementations, there is no reference signal for comparison to the capture (e.g., for fault determination / calculation, etc.). The reduced header mode test process is used when the receiving component (e.g., DUT, etc.) reduces information about the received signal (e.g., reduced modulation-related information, header information, preamble information, signal configuration information, etc.). In some exemplary implementations, the reduced header (information) does not include various fields of information (e.g., short training field, long training field, sync field, header field, signal field, service field, modulation selection bit / field, rate field, etc.). In other exemplary implementations, some of these fields are included in the reduced header (information). The received information is less than what would otherwise be available in normal field / non-test conditions.

[0139] In block 810, a reduced header mode test processing instruction is accessed (e.g., headerless without a reference signal). In some exemplary implementations, the reduced header mode test processing instruction is based on a selection of reduced header mode test processing (e.g., similar to the selection in block 710). This selection may be based on various conditions (e.g., the DUT does not have sufficient resources to handle testing communications with full header information, it is desirable to have a smaller test pattern for testing payloads containing reduced header information, it is desirable to have multiple test runs with different test characteristics, etc.).

[0140] In block 820, a reduction header demodulation information determination process is performed. In some embodiments, the reduction header demodulation information determination process determines the information to be used in testing the modulation / demodulation operation (e.g., signal processing operation). In some exemplary implementations, the reduction header demodulation information determination process includes blocks 821, 822, 823, 824, 825, and 826.

[0141] In block 821, autocorrelation of cyclic prefixes within a signal is performed. In some embodiments, this signal is a loop signal (e.g., similar to the signal in Figure 5D). This signal is constructed according to a communication protocol. In some exemplary implementations, this communication protocol corresponds to the communication protocol standard in the IEEE 802.11 series of wireless network protocols / standards. In some embodiments, a peak lookup function is performed on the autocorrelation results.

[0142] In block 822, the start timing of symbols within this signal is identified based on the autocorrelation results from block 821. These symbols are defined by the communication protocol. These symbols may include orthogonal frequency division modulation (OFDM) symbols. In some exemplary implementations, the start and end positions / timings of symbols relative to each other are identified (e.g., here one OFDM symbol starts and ends relative to the start and end of another OFDM symbol).

[0143] In block 823, the initial coarse frequency error correction is determined based on the autocorrelation results from block 821. The difference between phase and coarse frequency error may also be determined from the analysis of peaks in the autocorrelation results. In some embodiments, the difference in peak position from the expected peak position may indicate the phase difference and the corresponding frequency error. In some exemplary implementations, the initial coarse frequency error correction is determined by the process described with reference to Figures 9A and 9B. As described in other parts of this specification, the initial coarse frequency error correction may be the average of each individual frequency error correction.

[0144] In block 824, a set of bins is established for this signal, which includes a pilot bin and a data bin. The set of bins corresponds to a set of subcarriers associated with this signal, with the pilot bin corresponding to the pilot subcarrier within the set of subcarriers, and the data bin corresponding to the data subcarrier within the set of subcarriers. In some exemplary implementations, a Fast Fourier Transform (FFT) operation is performed on a portion of the signal associated with the OFDM symbol, and the result is used to establish the set of bins.

[0145] In block 825, pilot bin identification information is extracted according to the definition of pilot subcarriers as defined by the communication protocol. In some embodiments, pilot bin identification includes identifying the position of the pilot bin relative to each other and to other bins in the set of bins. It is understood that the identification information and definitions of the configuration and position of subcarriers (e.g., pilot subcarriers, data subcarriers, null subcarriers, etc.) relative to each other may vary (as presented, for example, in the descriptions of Figures 5A to 5E, in other parts of this specification, etc.).

[0146] In block 826, ideal constellation values ​​and ideal symbol values ​​are set for the pilot bin and data bin. In some embodiments, interpolation is used to set the ideal constellation values ​​and ideal symbols for the data bin. It is understood that various types of interpolation (e.g., linear, least-squares regression, iterative update / re-determination, etc.) are compatible with and can be easily implemented in the reduced header mode test process 800. Additional descriptions of the interpolation process operation are presented in other parts of this specification (e.g., descriptions of processes 1200A and 1200B, etc.).

[0147] In block 827, other demodulation parameter values ​​are determined based on the results of the ideal constellation and ideal symbol values ​​of the pilot bin and data bin (e.g., based on the results of block 826). In some embodiments, the equalizer value from the first bin is first applied to the second bin and then updated based on the results of block 826. In some exemplary implementations, the first and second bins are adjacent or adjacent to each other. The configuration of the first and second bins in relation to their proximity to each other may be defined by a communication protocol (e.g., industry standards, IEEE 802.11-based communication protocols, etc.).

[0148] In some embodiments, after the reduction header demodulation information determination process from block 820 is performed, the operation proceeds to block 830, where an exemplary full demodulation is performed. This full demodulation is similar to that of block 330. In some embodiments, the full demodulation is similar to some aspects of conventional demodulation analysis. After the information from block 820 becomes available, the process may proceed with full demodulation determination information similar to conventional information that would otherwise not be available from the reduction header signal.

[0149] Figure 9A is a block diagram of exemplary autocorrelation graph results from several embodiments. In some exemplary implementations, the autocorrelation is related to a cyclic prefix within an OFDM symbol (e.g., similar to the one shown in Figure 5D). The peaks in the graph are the locations of the resulting autocorrelation of the signal containing the cyclic prefix and the delayed version of this signal. The Y-axis is the normalized correlation (unitless) incrementing by 0.1, and the X-axis is the samples (unitless) with an increment of 1000 samples per grid width.

[0150] In some exemplary implementations, a reduction header demodulation information determination process (e.g., block 820) is performed. Autocorrelation is performed on the loop signal, and peak indications are generated at the locations of OFDM symbols in this signal (e.g., results similar to those in Figures 9A, 9B, etc.). The autocorrelation provides timing-related information and coarse frequency error information. The timing of the connected boundaries of OFDM symbols in the loop signal is determined based on the peaks in the autocorrelation results. Portions of the signal associated with different OFDM symbols are identified based on the peak lookup in the autocorrelation results (e.g., the start and end of OFDM symbols). The start and end of OFDM symbols are similar to the start and end of OFDM symbols 0, 1, and 2 in Figure 5C. The phase and coarse frequency error differences can also be determined from the analysis of the peaks in the autocorrelation results.

[0151] Figure 9B is a block diagram of an exemplary autocorrelation process according to an embodiment of the present disclosure. OFDM symbol 910A includes a cyclic prefix 911A and a corresponding termination portion 912A. Copy OFDM symbol 920B includes a cyclic prefix 921B and a corresponding termination portion 922B. Copy OFDM symbol 920B is a copy of OFDM symbol 910A. The copy of OFDM symbol 920B is shifted in the time domain by a time amount corresponding to the Fast Fourier Transform or FFT size, etc. Autocorrelation is performed during the shift so that an autocorrelation peak 930 is detected when the cyclic prefix 921B aligns with the termination portion 912A in the time domain. The autocorrelation peak 930 has both amplitude and phase. If there is no coarse frequency error, the phase is zero. If a non-zero phase exists, there is a coarse frequency error. The coarse frequency error is defined as D theta divided by dt, where D theta is equal to the phase. dt is the amount of time from the start of an OFDM symbol to the end of an OFDM symbol (excluding cyclic prefixes).

[0152] The lower part of Figure 9B includes a block diagram of the frequency domain spectrum, including the local oscillator spectrum, signal spectrum, and other spectra (e.g., frequency response, digitizer, and other components that introduce other out-of-band spectra). In some exemplary implementations, a local oscillator is present, while in other exemplary implementations, the local oscillator may be absent or located elsewhere. In some embodiments, coarse frequency error correction can obtain a response close to the true frequency error. In some exemplary implementations, coarse frequency error correction avoids substantial EVM rise (e.g., below the EVM associated with any residual frequency error when the spectrum is not clean). Timing information associated with OFDM symbols and coarse frequency error correction enables reliable subsequent extraction of ideal symbols. Extraction of ideal symbol values ​​and retrieval of captured values ​​provides information about frequency domain analysis (e.g., after FFT) as described in other parts of this specification. Equalizer values ​​are described in other parts of this specification (e.g., in processes 1200A and 1200B).

[0153] Referring to both Figures 9A and 9B, in some embodiments, the coarse frequency error of each individual peak in Figure 9A (e.g., corresponding to the peaks in OFDM symbol 0, OFDM symbol 1, OFDM symbol 2, etc.) is determined in the same way as the error frequency determination of OFDM symbol 910A. The resulting individual frequency error is averaged over multiple peaks (e.g., peaks in Figure 9A). In some embodiments, the resulting individual frequency error is averaged over multiple peaks within the payload portion of a burst or frame. Based on the average frequency error value, an average frequency error correction is determined. The average frequency error correction is applied to the waveform (e.g., the payload portion of a burst or frame, etc.).

[0154] An FFT operation is performed on each portion of the signal associated with OFDM symbols 0, 1, and 2 to generate channel bandwidth subcarriers (e.g., similar to subcarrier bins 1 through N in Figure 5C). While the values ​​of the subcarriers within each bin (along with different OFDM symbols, etc.) may change over time, the position of each bin within the bandwidth remains fixed and defined by the communication protocol. Since the position of the pilot bins is set by this communication protocol, the subcarriers associated with each pilot bin are easily identifiable. This communication protocol also specifies that BPSK modulation is used for the pilot subcarriers, and that BPSK analysis, as described elsewhere in this specification, is used to determine the ideal values ​​of the pilot subcarriers within each pilot bin.

[0155] For the pilot bin and data bin, ideal constellation and ideal symbol values ​​are set (for example, in block 826, etc.), which includes determining equalizer values. In some exemplary implementations, equalizers are set for the pilot subcarriers and data subcarriers associated with each pilot bin and data bin.

[0156] Figure 10 is a flowchart of an exemplary equalizer value determination process 1000 according to embodiments of the present disclosure. In some embodiments, the equalizer value is obtained from the results of analyzing the frequency responses in the pilot bin and data bin. The equalizer value (e.g., pilot bin, data bin, etc.) is the reciprocal of the respective frequency response value. In some embodiments, this is for OFDM symbols available in the capture and is then averaged. It is understood that the equalizer value determination and interpolation processes described herein are applicable to both magnitude correction and phase correction. The interpolation process 1000 is included in some embodiments of reduced header mode test processes (e.g., process 800, etc.).

[0157] In block 1010, the equalizer value is determined for the pilot subcarrier at the pilot bin position based on the ideal pilot tone constellation value. In some embodiments, the frequency response is based on the difference between the ideal pilot tone constellation value and the received / captured pilot tone value. Further explanation of the determination of the equalizer value is presented in other parts of this specification (e.g., the description of process 1100 shown in Figure 11).

[0158] In block 1020, equalizer values ​​are determined for the data subcarriers at the data bin locations based on ideal data tone constellation values. The determination of equalizer values ​​at the data bin locations is based on the results of the equalizer values ​​in the step of determining the equalizer values ​​at the pilot bin locations. In some exemplary implementations, the equalizer values ​​determined for the data subcarriers at the data bin locations are based on interpolation between the equalizer values ​​from block 1010 for the pilot subcarriers at the pilot bin locations.

[0159] In some embodiments, setting the ideal constellation and symbol values ​​of the pilot bins (for example, in block 826) includes performing an ideal pilot tone determination process. The ideal pilot tone determination process sets the ideal constellation and symbol values ​​of the pilot bins. Other processes (e.g., interpolation) are used to set the ideal constellation and symbol values ​​of the data bins.

[0160] Figure 11A is a flowchart of an exemplary ideal pilot tone determination process 1100 according to embodiments of the present disclosure. In some exemplary implementations, ideal pilot tone values ​​are obtained for an ideal pilot tone constellation point and ideal symbol. In block 1110, the determination of the coarse frequency error is completed. In some embodiments, the results of an autocorrelation peak search function process are used in the determination of the coarse frequency error. The compensation value is the difference between the expected frequency of the pilot bin as defined by the communication protocol standard and the received or captured frequency of the pilot bin.

[0161] In block 1120, coarse frequency error is compensated. In some embodiments, compensating for coarse frequency error involves adjusting the captured pilot bin subcarrier signal value by a compensation value. The compensation value is equal in magnitude and in the negative number of coarse error values. For example, if the captured pilot bin subcarrier signal is 2.4499 GHz with a frequency error 100 kHz below the expected value, the compensation is to add 100 kHz to 2.4499 GHz for a value of 2.45 GHz. If the captured pilot bin subcarrier signal is 2.4501 GHz with a frequency error 100 kHz above the expected value, the compensation is to subtract 100 kHz from 2.4501 GHz for a value of 2.45 GHz.

[0162] In block 1130, the pilot tone value of the signal is acquired. In some embodiments, the pilot tone is modulated according to a two-phase-shift keying BPSK protocol. In some exemplary implementations, the pilot tone is relatively unaffected by noise. The BPSK signal is more susceptible to noise due to its lower constellation density in the IQ plane. A small amount of noise can cause, for example, a 1024QAM constellation type symbol error, while the same amount of noise does not cause a symbol error in the BPSK constellation plane. There is an increasing inverse exponential relationship between the logarithmic bit error rate value and the signal-to-noise ratio in decibels. As the QAM value increases, the probability that errors focus on a different constellation type relative to the signal-to-noise ratio (BPSK error probability is the same as QPSK) increases. In some exemplary implementations, a signal-to-noise ratio (SNR) of approximately 13 dB is required for BPSK / QPSK signals to have a symbol error rate of 10e-6, while achieving the same for 256QAM signals requires, for example, an SNR of approximately 28 dB.

[0163] In block 1140, a determination is made as to whether a re-estimation of the frequency error is appropriate / necessary. If so, the fine-tuning of the frequency error is performed in block 1145; otherwise, block 1150 is executed. If the user selects "LowSNR" for FrequencyEstimationMethod, processing proceeds to block 1145. If "HighSNR" is selected for FrequencyEstimationMethod, processing skips to block 1050.

[0164] In block 1145, if the result of the decision in block 1040 is positive, a re-estimation process of the frequency error using the ideal pilot tone and / or data bin values ​​from block 1130 is optionally performed. In some embodiments, the re-estimation provides a more accurate frequency error estimate by also using the ideal pilot tone and / or data bin values.

[0165] In block 1050, an ideal pilot tone value is returned. In some embodiments, the ideal pilot tone value is associated with an ideal pilot bin value and an ideal pilot subcarrier value (e.g., an ideal pilot subcarrier symbol value). Using the returned ideal pilot tone value, a more accurate estimation of the frequency error can be achieved.

[0166] The novel approach presented overcomes numerous challenges in demodulation using reduced header information. Figure 11B is an exemplary graph of simulated channel response in several embodiments, when a signal with a full header or a signal with a non-blind known stimulus is present. This non-blind known stimulus may be similar to the PayloadOnlyIdealIQWaveform discussed elsewhere in this specification. As shown in Figure 11B, in some embodiments, the system can easily obtain a known channel response for all subcarriers used. However, conventionally, challenges arise when only the system has a pilot tone to obtain the initial frequency response. The Y-axis represents the magnitude (dB) from 7.0 dB to 1.0 dB, incrementing by 1.0 dB, and the X-axis represents the subcarrier frequency from 1000.0 Hz to 1000.0 Hz, incrementing by 50 Hz.

[0167] Figure 11C is a graph showing the positions of exemplary pilot bin frequency responses in several embodiments. Known pilot bin frequency responses are not very popular compared to otherwise unknown data bin frequency responses. In some embodiments, interpolation is performed to set intermediate data bin frequency response values ​​between the pilot bins. It is understood that the frequency responses for the data bins shown in Figure 11C are not known until interpolation is performed. The Y-axis is the magnitude (dB) from 7.0 dB to 1.0 dB, incrementing by 1.0 dB, and the X-axis is the subcarrier frequency from 1000.0 Hz to 1000.0 Hz, incrementing by 50 Hz.

[0168] Figure 12A is a flowchart of an exemplary interpolation process 1200A, including iterative updating / re-determining of equalization values ​​in a bin, according to embodiments of the present disclosure. Interpolation process 1200A is included in several embodiments of a reduced-header communication signal processing test method. Exemplary interpolation process 1200A with iterative updating / re-determining of equalization values ​​provides more accurate interpolation of equalization values ​​than conventional linear and conventional least-squares interpolation, which have fewer iterations. Having a more accurate equalization rate enables more accurate demodulation operation for the DUT and corresponding test processing of those operations. This approach enables testing of DUTs that would otherwise be difficult to handle / demodulate in a test environment, such as full frames or packets with full header information. Interpolation process 1200A with iterative updating / re-determining of equalization values ​​in a bin is understood to be applicable to both magnitude correction and phase correction.

[0169] In block 1201 of Figure 12A, a new equalizer value for the pilot tone is determined. In some embodiments, the equalizer value is based on pilot two-phase shift keying (BPSK), such as an ideal / known or easily extractable pilot signal value. The BPSK analysis of this signal has only two constellation points, as opposite portions of the X axis shown in the exemplary constellation map 610. Assuming that there is a relatively large distance between constellation points in the BPSK compared to other constellation maps (e.g., 620, 630, etc.), the probability of misrepresenting the received signal value to an incorrect ideal constellation point is small. In addition, the probability of very high noise adding confusion to the determination of the appropriate constellation point is small. Thus, the difference between the received or captured signal value and the ideal constellation point provides a reliable indication channel response. The reciprocal of the channel response is equal to the equalizer value.

[0170] In block 1202, a determination is made as to whether the next bin is a data bin. In some embodiments, the next bin is assumed to be a data bin if it does not have the characteristics of a pilot bin or a null bin. The next bin is assumed to be a data bin if it is not one of the previously identified pilot bins and has some transmitted signal characteristics (e.g., as opposed to null bins which are not expected to have transmitted signal characteristics).

[0171] In block 1203, the new equalizer value is applied to the data bin. In some embodiments, applying the new equalizer from an adjacent bin provides a more accurate estimation of the preliminary equalizer value for the current data bin. Applying the preliminary new equalizer from an adjacent bin to the current data bin provides a reasonable initial correction to the corresponding subcarrier value for the current bin.

[0172] In block 1204, the ideal data subcarrier signal values ​​are extracted for the data bin. In some embodiments, the ideal data subcarrier signal values ​​are based on the relationship between multiple results in block 1203 to known expected values ​​according to the communication protocol standard. By using these results in block 1203, the possibility of misidentifying the appropriate corresponding ideal constellation point value is significantly reduced compared to other conventional approaches.

[0173] In block 1205, a new equalizer value is set based on the ideal signal value of the data subcarrier. By setting a new equalizer value for the current data bin based on the ideal signal value of the data subcarrier from block 1204, more accurate interpolation results are provided. This more accurate estimation of appropriate equalizer values ​​allows for the avoidance, and in many cases the reversal, of challenges related to frequency response errors.

[0174] Figure 12B is a graph showing the results of interpolation processing, including iterative updating / re-determination of equalization values ​​within bins, according to embodiments of the present disclosure. The graph includes a display of the relationships between associated subcarriers within various bins and communication bandwidths. The graph also provides an example of a scheme, in which the novel iterative interpolation approach described enables precise tuning for efficient testing of DUT demodulation performance. The Y-axis represents magnitude (dB) from 7.5dB to 4.0dB, incrementing by 0.5dB, and the X-axis represents subcarrier frequencies from 1012.0Hz to 975.0Hz, incrementing by 1.0Hz.

[0175] Figures 12C and 12D are flowcharts of an exemplary interpolation process 1200B using iterative updating / re-determination of equalized values ​​in a bin, according to embodiments of the present disclosure. Interpolation process 1200B is included in several embodiments of the reduced header communication signal processing test method. In some embodiments, interpolation process 1200B is similar to interpolation process 1200A. Furthermore, using iterative updating / re-determination of equalized value interpolation process 1200B provides more accurate interpolation of equalized values ​​than interpolation processes with fewer iterations, such as conventional linear or conventional least-squares interpolation. It is understood that interpolation process 1200B using iterative updating / re-determination of equalized values ​​in a bin is applicable to both magnitude correction and phase correction.

[0176] Process 1200B performs functions related to the analysis of pilot bins. In block 1207, one of the pilot bins is selected and assigned to the label of the current pilot bin. In block 1210, ideal values ​​are extracted for the current pilot bin, and the extraction of ideal values ​​for the current pilot bin is based on two-phase shift keying (BPSK) analysis. In block 1215, pilot equalizer values ​​based on the ideal values ​​of the current pilot bin from block 1210, and known capture values ​​for the current pilot bin are extracted. In block 1217, the pilot equalizer is inserted into the list of equalizers associated with bins in the burst or frame package.

[0177] This process performs the following functions related to the analysis of the data bins: In block 1220, one of the data bins adjacent to the current pilot bin is selected, and the label of the current data bin is assigned to this data bin. In block 1221, the label of the current equalizer is assigned to the pilot equalizer value. In block 1225, the current equalizer value is applied to the current data bin. In block 1230, an ideal constellation value is extracted for the current data bin. In block 1235, a new equalizer value is extracted based on the ideal constellation value from block 1230 and the known capture value of the current data bin. In block 1237, the new equalizer is inserted into the list of equalizers associated with bins in the burst or frame package.

[0178] This process includes checking for subsequent bins that are not data bins (e.g., pilot bins, null bins, etc.). In block 1240, it is determined whether the next bin in the set of bins is another pilot bin. In block 1241, the label of the current pilot bin is reassigned to another pilot bin. In block 1242, it is determined whether the next bin in the set of bins is another data bin. In block 1243, the next bin is skipped (e.g., the result in the block indicates that the next bin is not a data bin, etc.). In some embodiments, if a null bin exists between a pilot bin and a data bin, this process "skips" the null bin and analyzes the next data bin or pilot.

[0179] This process also includes the possibility of handling special circumstances (e.g., handling data bins at the bandwidth edge, resuming analysis in subsequent pilot bins). In block 1245, if the next bin in the set of bins is another data bin, it is checked whether the next bin is a bandwidth edge bin. If proceeding to blocks 1250 and 1270, it is understood that null bins are skipped. In block 1250, if this check is negative, a new equalizer is applied to the next bin in the data bin. In block 1270, if this check is positive, enhanced equalizer processing is performed. In block 1261, it is determined whether the iteration of the current bin corresponds to the last bin (e.g., in a burst or frame package). If the current bin is the last bin, processing proceeds to block 1262; otherwise, processing proceeds to block 1290. In block 1290, the current pilot bin label reassignment process is performed. In block 1262, an averaging and equalization process is performed.

[0180] In some embodiments, process 1200B proceeds until all bins within the bandwidth have been processed. This process may proceed in the frequency bin / subcarrier increasing direction, the frequency bin / subcarrier decreasing direction, or both. In some embodiments, a pilot is selected as the initial pilot, and this process proceeds toward frequency bin / subcarrier decrease. When the pilot reaches the lowest frequency bin / subcarrier in the bandwidth, it returns to the initial pilot, and this process proceeds toward frequency bin / subcarrier increasing until the pilot reaches the highest frequency bin / subcarrier in the bandwidth. In some embodiments, a full demodulation process (e.g., blocks 230, 830, etc.) is performed based on the results of interpolation process 1200B.

[0181] Figure 12E is a block diagram of an exemplary subcarrier bin configuration 1291 according to an embodiment of the present disclosure. Dots or circles represent various subcarriers (also known as transmission spectra within the communication bandwidth). Filled dark circles represent pilot subcarrier bins, also known as pilot bins, and unfilled circles represent data subcarrier bins (also known as data bins). It is understood that the subcarrier bin configuration may include other subcarriers (not shown). The Y-axis corresponds to the frequency values ​​of the various subcarriers, and the X-axis represents the transmission of subcarriers over time.

[0182] The subcarrier bin configuration 1291 is understood to represent a subcarrier communication burst or frame and its corresponding OFDM symbol according to some embodiments of the present disclosure. A row of bins corresponds to a bin within each OFDM symbol. The bins are also tracked in rows of bins (e.g., bin row 0, bin row 4, bin row 9, bin row 14, etc.). The organization of OFDM symbols contained in the subcarrier bin configuration 1291 can vary. In some embodiments, each row is associated with a different OFDM symbol. In some exemplary implementations, OFDM symbols are in a loop that is repeated within the subcarrier bin configuration (e.g., similar to the payload portion 505) (e.g., OFDM symbol 4501 is repeated as 501A, 501B, 501C, 501D, etc.). The subcarrier bin configuration 1291 is related to the subcarrier bin configuration, but there are also equalization values ​​associated with each bin (e.g., the equalizer associated with the bin in column 0, the equalizer associated with the bin in column 9, the equalizer associated with the bin in column 19, etc.). These bins include 1274D, 1274H, 1271J, and in the enlarged view section, 1271A, 1272A, 1273A, 1274A, 1271B, 1272B, 1273B, 1274B, 1271C, 1271E, 1272E, 1273E, 1274E, 1271F, 1272F, 1273F, 1274F, and 1271G.

[0183] In some embodiments, the equalizer values ​​associated with the bins are determined according to interpolation process 1200B. Figures 12F, 12G, and 12H are flowcharts illustrating exemplary implementations of interpolation process 1200B according to some embodiments of the present disclosure. It is understood that the blocks in Figures 12F, 12G, and 12H (e.g., 1210B in Figure 12F, block 1210E in Figure 12G, block 1210K in Figure 12H, etc.) are different iterations of the respective processing blocks in Figures 12C and 12D (e.g., block 1210 in Figure 12C, etc.).

[0184] Figure 12F is a block diagram of an exemplary signal information processing operation according to an embodiment of the present disclosure. Several bins exist, including pilot bin 1271A, data bin 1272A, data bin 1273A, and pilot bin 1271B. The process begins at pilot bin 1271A in block 1210A, where an ideal constellation value associated with pilot bin value 1281A (also known as the ideal pilot bin value) is extracted for pilot bin 1271A. In block 1215A, pilot equalizer 1282A is extracted. In block 1220A, pilot equalizer 1282A is applied to data bin 1272A. In block 1230A, an ideal constellation value 1283A for the data in data bin 1272A is extracted. In block 1235A, a new equalizer 1284A is extracted. In block 1250A, the new equalizer 1284A is applied to data bin 1273A. In block 1230AA (for example, this process returns to another iteration such as block 1230), the ideal constellation value 1285A for the data in data bin 1273A is extracted. In block 1235AA, the new equalizer 1287A is extracted. This process proceeds to other blocks (not shown) and continues (for example, the new equalizer is applied to the next data bin). In block 1240A, it is determined whether the next bin is a pilot bin. If this process encounters another pilot (for example, pilot bin 1271B), it returns and performs another iteration of block 1210 (for example, in Figure 12G).

[0185] Figure 12G is a block diagram of an exemplary signal information processing operation according to an embodiment of the present disclosure. Several bins exist, including pilot bin 1271B, data bin 1272B, data bin 1273B, and pilot bin 1271C. The process begins at pilot bin 1271B in block 1210B, where an ideal constellation value associated with pilot bin value 1281B (also known as the ideal pilot bin value) is extracted for pilot bin 1271B. In block 1215B, pilot equalizer 1282B is extracted. In block 1220B, pilot equalizer 1282B is applied to data bin 1272B. In block 1230B, an ideal constellation value 1283B for the data in data bin 1272B is extracted. In block 1235B, a new equalizer 1284B is extracted. In block 1250B, the new equalizer 1284B is applied to data bin 1273B. In block 1230BB (for example, this process returns to another iteration such as block 1230), the ideal constellation value 1285B for the data in data bin 1273B is extracted. In block 1235BB, the new equalizer 1287B is extracted. This process proceeds to other blocks (not shown) and continues (for example, the new equalizer is applied to the next data bin). In block 1240B, it is determined whether the next bin is a pilot bin. If this process encounters another pilot (for example, pilot bin 1271C), it returns and performs another iteration of block 1210.

[0186] This process continues for the other bins in the OFDM symbol in a similar manner, as shown in Figures 12F and 12G. Referring to Figure 12E, this process continues to find the equalizer associated with bin 1274D. Thus, this process determines the equalizer value for each bin in equalizer column 0 in Figure 12E. This process returns to the next column and begins again with bin 1271E.

[0187] Figure 12H is a block diagram of an exemplary signal information processing operation according to an embodiment of the present disclosure. Several bins exist, including pilot bin 1271E, data bin 1272E, data bin 1273E, and pilot bin 1271F. The process begins at pilot bin 1271E in block 1210E, where an ideal constellation value associated with pilot bin value 1281E (also known as the ideal pilot bin value) is extracted for pilot bin 1271E. In block 1215E, pilot equalizer 1282E is extracted. In block 1220E, pilot equalizer 1282E is applied to data bin 1272E. In block 1230E, an ideal constellation value 1283E for the data in data bin 1272E is extracted. In block 1235E, a new equalizer 1284E is extracted. In block 1250E, the new equalizer 1284E is applied to data bin 1273E. In block 1230EE (for example, this process returns to another iteration such as block 1230), the ideal constellation value 1285E for the data in data bin 1273E is extracted. In block 1235EE, the new equalizer 1287E is extracted. This process proceeds to other blocks (not shown) and continues (for example, the new equalizer is applied to the next data bin). In block 1240E, it is determined whether the next bin is a pilot bin. If this process encounters another pilot (for example, pilot bin 1271F), it returns and performs another iteration of block 1210.

[0188] This process continues in a similar manner for other bins of OFDM symbols (e.g., in bursts, frames, etc.). Referring to Figure 12E, bin 1274H in the second column is moved up and back to bin 1271J in the next column. If an equalization value for a burst has been extracted, this process proceeds to averaging. Referring again to Figure 12D, the averaging process is performed in block 1290. The averaging process is performed based on the equalization value in a list of equalizers (developed, for example, in blocks 1217, 1237, etc.). Figure 12I is a block diagram of the list of equalizer values ​​1293 associated with bins of OFDM values ​​in a burst or frame. These bins correspond to the bins in Figure 12E, and the equalizer values ​​correspond to exemplary implementations of the interpolation process 1200B (shown, for example, in Figures 12F, 12G, 12H, etc.). Referring to Figure 12F, in block 1215A, the equalizer 1282A is extracted from the pilot bin 1271A. According to the interpolation process 1200B, in block 1217, the equalizer 1282A is inserted into a list (e.g., equalizer value list 1293). It is understood that equalizer values ​​can be inserted into a list stored in memory.

[0189] Figure 12J is a flowchart of the average equalizer processing 1500 according to some embodiments of the present disclosure. The average equalizer processing 1500 provides an opportunity for overall improved handling of frequency errors and equalization corrections. In some embodiments, this averaging can help avoid overcorrection due to outliers or aberrations in a particular bin. In some exemplary implementations, this averaging can help provide smooth results over time (e.g., in the transverse direction, etc.) and across multiple subcarrier frequencies (e.g., in the vertical OFDM symbol direction, etc.). In some exemplary implementations, the average equalizer processing 1500 is included in block 1262.

[0190] In block 1510, equalizer values ​​are accessed. In some embodiments, an equalizer value list 1293 is accessed. In some exemplary implementations, the accessed equalizer values ​​are associated with OFDM symbols in a communication burst or frame. Equalizer values ​​may be accessed from memory or other mechanisms.

[0191] In block 1520, the average equalization value is determined. It is understood that the average equalization value may be relevant to different averaging purposes. Referring to both Figures 12J and 12I, the average equalization value may correspond to the average of the equalization values ​​in the rows of the equalizer value list 1293 (e.g., bin row 0, bin row 5, etc.). The average equalization value may correspond to the average of the equalization values ​​in the columns of the equalizer value list 1293 (e.g., equalizer column 0, equalizer column 9, etc.). The average equalization value may correspond to the average of the equalization values ​​in a burst or frame (e.g., burst or frame 1291, etc.).

[0192] In block 1530, the average equalizer value is applied to the subcarriers within the bin of OFDM symbols. In some embodiments, applying the average equalizer to the subcarriers leads to residual error mitigation capabilities. It is understood that the average equalizer value can be applied in various configurations. A first average equalizer value for a first row of subcarriers can be applied to the corresponding subcarrier in the first row, and a second average equalizer value for a second row of subcarriers can be applied to the corresponding subcarrier in the second row. A first average equalizer value for a first column of subcarriers can be applied to the corresponding subcarrier in the first column, and a second average equalizer value for a second column of subcarriers can be applied to the corresponding subcarrier in the second column. The average equalizer value can be applied to the subcarriers within the bin of OFDM symbols in bursts, frames, etc.

[0193] It is understood that various forms of interpolation are compatible with the novel approaches presented. In some embodiments, the accuracy of the interpolation approach may vary. Figure 13A is an exemplary graph of the frequency response of a bandwidth containing multiple bins / subcarriers according to an embodiment of the present disclosure. Different bin / subcarrier values ​​are indicated by filled dots (e.g., 5071A, 5072, 5073, 5074, 5075, 5076, 5077, 5078, 5079, etc.). In Figure 13A, the pilot bins are associated with dots 5071A, 5073, 5075, 5077, and 5079, and the data bins are associated with the remaining dots (e.g., 5072, 5074, 5076, 5078, etc.), and linear interpolation is used to estimate the frequency response and the corresponding equalizer. The estimation is reasonable, but there is a deviation from the true value.

[0194] Figure 13B is an exemplary graph of the frequency response of a bandwidth containing multiple bins / subcarriers according to embodiments of the present disclosure. The frequency response, bandwidth, multiple bins / subcarriers, and corresponding signals in Figure 13B are similar to those in Figure 13A. In Figure 13B, the pilot bins are associated with dots 5071A, 5073, 5075, 5077, and 5079, and the data bins are associated with the remaining dots (e.g., 5072, 5074, 5076, 5078, etc.) and iterative interpolation (e.g., similar to 1200B used to estimate the frequency response and corresponding equalizer). In some embodiments, the iterative interpolation is similar to interpolation with iterative updating / re-determination of equalization values ​​within the bins (e.g., shown in Figures 12A, 12C, 12D, etc.). Iterative interpolation yields values ​​very close to the true values. For example, the deviation between the interpolated values ​​and true values ​​in Figure 13B is much smaller than in Figure 13A. In some exemplary implementations, no symbol errors occur when extracting constellation information, and the iterative interpolated values ​​are the same as the true values.

[0195] In some implementations, the frequency lines are fairly flat or nearly linear for most of the bins / subcarriers in the large central portion of the bandwidth, but challenges begin to emerge towards the edges (due to, for example, filter performance / limitations). In the central portion (the filled-in dot between 5073 and 5077), the frequency is fairly flat or just a small ripple within the range 5091. Assuming the bin / subcarrier frequency responses are relatively flat or close to each other (e.g., 5073 is relatively close to 5074, etc.), an equalizer value from one serves as a relatively good initial equalizer value for the other. As the frequency reaches the lower and upper boundaries or edges of the bandwidth (e.g., 5071A, 5072, 5078, 5079, etc.), the frequency response range (e.g., 5092A, 5093, etc.) begins to decline rapidly. In some embodiments, as the frequency decreases, the magnitude of the change in the response increases downwards. In some embodiments, the processing traverses bins / subcarriers closer to the edge, and this difference is added to the estimated equalizer value. The estimated equalizer used for bin / subcarrier 5071B includes the equalizer from bin / subcarrier 5072, which is added to the adjusted value 5092B (equal to the difference 5092A between the equalizers of bin / subcarrier 5073 and bin / subcarrier 5072) to provide an initial estimate of 5071B. For the purposes of the graph, the estimate 5071B is shown associated with a virtual bin / subcarrier 5071B that is relatively close to bin / subcarrier 5071A (similar to how bin / subcarrier 5073 is relatively close to bin / subcarrier 5074), and serves as a relatively good initial equalizer for the other.

[0196] Figure 14A is a flowchart of an exemplary enhanced equalizer processing according to an embodiment of the present disclosure. Enhanced equalizer processing can be implemented to handle special or specific data bin scenarios. In some exemplary implementations, the data bins are located at the edge of the bandwidth, and as a result, the difference between equalization values ​​can vary more significantly between bins. Therefore, relying solely on equalizer values ​​from previous bins may not be sufficiently reliable. In some embodiments, adjustment by enhanced equalizer processing provides more reliable interpolation and estimation of appropriate equalizer values.

[0197] In block 1470, if the result of checking whether the next bin (e.g., from block 1245) is a bandwidth edge bin is positive, an enhanced equalizer process is performed. The enhanced equalizer process is the same as the enhanced equalizer process performed in block 1270. In block 1471, a delta equalizer value is set based on the current equalizer value and the new equalizer value. The delta equalizer value is the difference between the current equalizer value and the new equalizer value. In block 1472, the new equalizer value is added to the delta equalizer value, and the enhanced equalizer value label is assigned to this additional result. Adding the new equalizer value to the delta equalizer value provides a result that is much closer to the true equalizer value of the next bin. In block 1447, the enhanced equalizer is applied to the next data bin. Using the enhanced equalizer value provides a more reliable estimate of the appropriate equalizer value for the next data bin. Therefore, if the enhanced equalizer is applied to demodulating the next data bin

[0198] Figure 14B is a block diagram of exemplary signal information processing operation according to an embodiment of the present disclosure. Several bins exist, including data bins 7071, 7072, and 7073. The processing begins with data bin 7071, and in block 1430R, an ideal constellation value 7081 is extracted for data bin 7071. In block 1435T, a new equalizer 7082 is extracted and applied to data bin 7071. In block 1445U, the data equalizer 7082 is applied to data bin 7072. In block 1430V, an ideal constellation value 7083 for the data in data bin 7072 is extracted. In block 1435W, a new equalizer 7084 is extracted and applied to data bin 7072. In block 1445X, a new / delta equalizer 7085 (e.g., a new equalizer 7084 plus a delta equalizer value similar to 5092B in Figure 13B) is applied to databin 7073. In block 1430Y (e.g., this process returns to another iteration such as block 1430R), the ideal constellation value 7087 for the data in databin 7073 is extracted. In block 1435Z, a new equalizer 7089 is extracted and applied to databin 7073.

[0199] Figure 15 is a flowchart of an exemplary current databin label reassignment process according to an embodiment of the present disclosure. The block diagram of the current databin label reassignment process is the same as the block diagram of the current databin label reassignment process in block 1290. In block 1590, the current databin label reassignment process is executed. The current databin label reassignment process 1590 includes the following operations: In block 1591, the next databin is reassigned to the label of the current databin, and the next databin becomes known as the current bin. In block 1592, if this confirmation is negative, the new equalizer value is reassigned to the label of the current equalizer value, and the new equalizer value becomes known as the current equalizer value. In block 1595, if this confirmation is positive, the enhanced equalizer value is reassigned to the label of the current equalizer value, and the enhanced equalizer value becomes known as the current equalizer value.

[0200] In some embodiments, full demodulation (e.g., blocks 230, 830, etc.) is performed based on the results of interpolation (e.g., 1200A, 1200B, etc.). In some embodiments, the execution of full demodulation is performed in the same manner as in the usual method (e.g., in the same manner as in a non-test environment, in the same manner as using full header information, etc.). The execution of full demodulation is the same as demodulation in a real-world field environment. The execution of full modulation is the same as the execution of modulation when the associated header / preamble information is available in the signal transmission. In some exemplary implementations, the execution of full modulation includes determining full equalizer values, precisely setting frequency errors, and sampling clock errors, etc. In some embodiments, all result parameters required to test the RF WiFi component / device are determined.

[0201] It is understood that other interpolation processes may be implemented. In some embodiments, linear or polynomial fitted responses or interpretations are implemented. In some exemplary implementations, if device capture potentially gives larger-than-expected erroneous values ​​to some interpolated bins (e.g., potentially leading to larger channel response interpolation errors as a result), iterative interpolation (e.g., 1200A, 1200B, etc.) is selected and implemented instead of linear or polynomial interpolation. In some embodiments, interpolation pilot positions are not widely popular.

[0202] Figure 16 is a flowchart of an exemplary reference signal training mode test process 1600 with a reduced header according to an embodiment of the present disclosure. In the reference signal training mode test process with a reduced header, a known ideal payload signal is extracted from a complete Wi-Fi signal. The ideal payload signal (e.g., PayloadOnlyIdealIQWaveform) does not have header information or reduced header information. The ideal payload signal is reconstructed to the DUT. In some embodiments, a demodulator may be trained using an ideal waveform to provide an ideal payload portion (e.g., mainly data, data only, etc.) of a packet with or without reduced header information. A clean capture with a low EVM is used to train the modulator to generate the ideal payload portion. This approach also enables testing of DUTs that would otherwise not be able to easily handle / demodulate full frames or packets with full header information.

[0203] This process involves developing an ideal waveform based on information within the signal header. In block 1610, a reference signal mode test processing instruction with a reduced header is accessed. In block 1620, a reduced header demodulation information determination process is performed based on the reference signal training. In block 1630, the training process is performed. In block 1640, the ideal waveform, including the training sequence, is demodulated. In block 1641, the complete packet of the ideal waveform is accessed. In block 1642, the complete packet of the ideal waveform is demodulated. In block 1643, the payload portion of the ideal waveform is generated based on the demodulation of the ideal waveform of the complete packet. In some embodiments, the payload waveform is an ideal waveform specifically for the payload (e.g., an IQ waveform).

[0204] This process includes demodulation testing based on the use of an ideal waveform. In block 1650, reduced header demodulation is performed using the payload portion of the ideal waveform. Reduced header demodulation may be headerless demodulation performed using the headerless payload portion of the ideal waveform. In block 1651, the ideal waveform of the payload portion is used as a reference, loaded into the tester stimulus, and used as the source for the DUT. In block 1652, ideal reference trace processing is performed. In some embodiments, ideal reference trace processing includes defining the constellation points of the ideal demodulated signal. In block 1653, ideal subcarrier type per symbol processing is performed. In some embodiments, the input parameter IdealReferenceTrace defines the constellation points of the ideal demodulated signal, and the parameter IdealSubcarrierTypePerSymbol defines the subcarrier type of each element of the ideal reference trace. In some exemplary implementations, IdealReferenceTrace is a composite array whose length is twice the length of IdealSubcarrierTypePerSymbol.

[0205] In block 1680, full demodulation is performed. In some embodiments, full demodulation is similar to some aspects of conventional demodulation analysis. After the information from block 1650 becomes available, processing may proceed with full demodulation decision information similar to conventional information that would otherwise not be available from the reduced header signal.

[0206] Figure 17 is a screenshot of an exemplary 802.11ax 20MHz ideal waveform graphical user interface (GUI) according to embodiments of the present disclosure. The waveform in the GUI is a complete packet including the header and data portions. In some embodiments, training includes a complete burst to generate an ideal signal dedicated to the payload. The Y-axis is amplitude (unitless), incrementing by 0.2, and the X-axis is time (uS), incrementing by 2000.

[0207] Figure 18 is a screenshot of the graphical user interface (GUI) for an exemplary payload-only ideal IQ waveform when the input parameter HeaderlessDemod is set to training, according to several embodiments. The HeaderlessDemodTraining and Execute options are used to implement the development and creation of an ideal IQ waveform for payloads only. This graph is provided by the PayloadOnlyIdealIQWaveform operation. Waveform 1810 is the waveform of a complete packet including the header and data payload portions of the communication, and waveform 1820 is the waveform of the data payload-only portion of the communication. In waveform 1810, the Y axis is amplitude (volts) incrementing by 0.5, and the X axis is time (uS) incrementing by 2000. In waveform 1820, the Y axis is amplitude (volts) incrementing by 2.0, and the X axis is time (uS) incrementing by 2000.

[0208] Figure 19 is a screenshot of a graph of an exemplary extracted payload-only ideal signal according to an embodiment of the present disclosure. Figure 19 shows some of the operational characteristics of block 1653, for example, the input parameter IdealReferenceTrace defines the constellation points of the ideal demodulated signal, and the parameter IdealSubcarrierTypePerSymbol defines the subcarrier type of each element of the ideal reference trace. In some exemplary implementations, IdealReferenceTrace is a composite array whose length is twice the length of IdealSubcarrierTypePerSymbol. The Y-axis is amplitude (volts) incrementing by 0.5, and the X-axis is time (uS) incrementing by 2000.

[0209] Figure 20 is a screenshot of a graph of the demodulated payload-only signal in the GUI according to an embodiment of the present disclosure. To perform headerless demodulation using an ideal payload-only waveform, the input parameters for headerless demodulation are training-based (e.g., setting DoHeaderlessDemod and BurstSearchEnable to false). The Y-axis is amplitude (volts) incrementing by 0.5, and the X-axis is time (uS) incrementing by 2000.

[0210] Figure 21 is a flowchart of an exemplary header-mode test process 2100 according to an embodiment of the present disclosure. In block 2110, a header-mode test process instruction is accessed. In some embodiments, the header-mode test instruction is accessed from memory contained within the ATE system. In block 2120, parameter information determination processing is performed. These parameters are associated with frequency offset, timing information, and equalization, etc. These parameters are used within the demodulation communication system. In block 2125, demodulation parameter information is extracted from the header. The structure of this information is defined by the communication protocol. This information is extracted from fields in the header (e.g., short training field, long training field, signal field, etc.). In block 2130, full demodulation is performed.

[0211] Much of the explanation is presented with reference to public communication protocols. It is understood that this novel system and method presented is readily applicable to protocols that are not publicly known (e.g., not privately established by a test entity, not established by a DUT manufacturer, not secretly communicated to an ATE entity, etc.). Multiple types of modulation (e.g., BPSK, QPSK, etc.) may be assigned to subcarriers, ideal values ​​may be set, and as a result, become "known" to the ATE. Signals and corresponding information may be configured according to various types of protocols (e.g., public, private, etc.). Various values ​​(e.g., timing, frequency error, equalizer, EVM, performance value, modulation value, demodulation value, etc.) may be set based on captured information in comparison to ideal values. These values ​​may be applied to other signals (e.g., adjacent subcarriers, etc.). The configuration or organization of subcarriers within a bandwidth (e.g., relative to each other, within a frequency bin, etc.) may be set and become known to the ATE. The novel iterative interpolation system and method presented may be used to determine information about various signals (e.g., pilot subcarriers, data subcarriers, etc.). Therefore, it is understood that the novel systems and methods presented are applicable to a wide variety of different test scenarios and conditions. In several exemplary implementations, the novel systems and methods are readily applicable to protocols with predetermined characteristics and definitions (e.g., modulation definitions, configuration definitions, etc.).

[0212] Figure 22 is a block diagram of an exemplary electronic system 2200 that may be used as a platform for implementing and controlling a method in several embodiments. In some embodiments, the electronic system 2200 is a workstation that runs algorithms associated with the novel systems and methods presented herein. The electronic system 2200 may be contained within an ATE system (e.g., ATE110A, ATE110C, etc.). The electronic system 2200 may be a “server” computer system. The electronic system 2200 includes a central processing unit 2210, system memory 2215, bulk memory 2225 (e.g., hard drive, external memory, etc.), input / output (I / O) devices 2230, communication components / ports 2240, and bus 2250. When executed by one or more processors (e.g., a central processing unit), it is understood that one or more non-temporary computer-readable media (e.g., system memory 2215, bulk memory 2225, etc.) stores instructions causing one or more processors to perform the operations of the methods and processes described in other parts of this Spec. (e.g., methods 300, 700, 1000, 1100, 1200A, 1200B, 1590, 1600, etc.).

[0213] Bus 2250 is configured to connect other components (e.g., the central processing unit 2210, system memory 2215, bulk memory 2225, input / output (I / O) devices 2230, communication components / ports 2240, etc.) and to enable communication of information between these components. The central processing unit 2210 is configured to process information and instructions. System memory 2221 (e.g., read-only memory (ROM), random access memory (RAM), etc.) and bulk memory 2225 are configured to store information and instructions for the central processing unit complex 2215. I / O devices 2230 can communicate information to the system (e.g., the central processing unit 2210, memory 2225, etc.). I / O devices 2230 may be any suitable device for communicating information and / or commands to an electronic system (e.g., a keyboard, buttons, joystick, microphone, touch sensor digitizer panel, display component, light-emitting diode (LED), display, etc.). Communication port 2240 is configured to exchange / communicate information with an external device / network (not shown). Communication port 940 may have various configurations (e.g., RS-232 port, general-purpose asynchronous receiver transmitter (UART), USB port, infrared transceiver, Ethernet® port, IEEE13394, synchronous port, etc.) and can communicate with an external network.

[0214] In some embodiments, the methods and processes described in other parts of this specification are implemented by algorithms executed on a workstation (e.g., electronic system 2200). Algorithms for accessing information (e.g., retrieving from memory, downloading from a network, etc.) are readily implemented for some of the operations of the methods and processes (e.g., 810, block 1610, etc.). Embodiments performing full demodulation blocks (e.g., 330, 830, 1680, etc.), which may be similar to conventional demodulation methods and processes, can be implemented using algorithms similar to conventional algorithms. It is understood that the algorithm modules described herein are represented in pseudocode that can be readily translated for implementation in various programming languages.

[0215] Figure 23 is a block diagram of a reduced header processing module 2300, which is an exemplary algorithm according to an embodiment of the present disclosure. The reduced header processing module 2300 relates to the implementation of block 820 of method 800. The reduced header processing module 2300 includes an autocorrelation module 2310 (block 821), a coarse frequency error estimation module 2320 (block 823), a timing module 2330 (block 822), a bin set setting module 2350 (block 824), a pilot bin identification module 2360 (block 825), and an ideal pilot bin setting module 2370 (block 826). The autocorrelation module 2310 relates to the implementation of block 821. The coarse frequency error estimation module 2320 relates to the implementation of block 823. The timing module 2330 relates to the implementation of block 822. The bin set setting module 2350 relates to the implementation of block 824. The pilot bin identification module 2360 relates to the implementation of block 825. The ideal pilot bin setting module 2370 is related to the implementation of block 826. The other demodulation parameter determination module 2380 is related to the implementation of block 827.

[0216] Figure 24 is a block diagram of an exemplary algorithm interpolation module 2400 according to an embodiment of the present disclosure. The interpolation module 2400 relates to the implementation of the iterative interpolation process 1200B. The interpolation module 2400 includes a pilot bin identification module 2410, an ideal pilot bin value extraction module 2420, an adjacent data bin selection module 2430, a module 2430 for applying the current equalizer to the data bin, a module 2440 for extracting the ideal value of the current data bin, a module 2450 for determining and applying a new equalizer value, a module 2460 for determining whether the subsequent bin is a data bin, a module 2480 for checking whether the next bin is an edge data bin, a module 2485 for applying a normal new equalizer, an enhanced equalizer module 2490, and a reassignment module 2495. Figure 25 shows an extended version of the exemplary enhanced equalizer module 2490 and reassignment module 2495.

[0217] These modules within the interpolation module 2400 relate to the implementation of blocks within the interpolation process 1200B. The pilot bin identification module 2410 relates to the implementation of block 1207. The ideal pilot bin value extraction module 2420 relates to the implementation of blocks 1210 and 1215. The adjacent data bin selection module 2430 relates to the implementation of block 1220. The module 2430 that applies the current equalizer to the data bin relates to the implementation of block 1225. The module 2440 that extracts the ideal value for the current data bin relates to the implementation of block 1230. The module 2450 that determines and applies the new equalizer value relates to the implementation of blocks 1235 and 1237. The module 2460 that determines whether the subsequent bin is a data bin relates to the implementation of blocks 1240-1243. The module 2480 that checks whether the next bin is an edge data bin relates to the implementation of block 1245. Module 2485, which applies a standard new equalizer, is related to the implementation of block 1250. The enhanced equalizer module 2490 is related to the implementation of block 1270. The average equalization module 2941 is related to the implementation of blocks 1262 and 1500. The reallocation module 2495 is related to the implementation of blocks 1290 and 1590.

[0218] Figure 26 is a block diagram of a training module processing module 2600, which is an exemplary algorithm according to an embodiment of the present disclosure. The training module processing module 2600 includes a module 2610 that completes the demodulation training sequence of an ideal waveform and a reduced header ideal payload reference demodulation module 2620. The training module processing module 2600 relates to the implementation of block 1620. The module 2610 that completes the demodulation training sequence of an ideal waveform relates to the implementation of block 1630.

[0219] Figure 27 is a block diagram of a pilot bin ideal value module 2700, which is an exemplary algorithm according to an embodiment of the present disclosure. The pilot bin ideal value module 2700 relates to the implementation of block 1100. The pilot bin ideal value module 2700 includes a coarse frequency error estimation module 2710, a frequency error compensation module, an ideal pilot bin value extraction module 2730, a decision re-estimation module 2740, a re-estimation module 2745, and a return module 2750. The coarse frequency error estimation module 2710 relates to the implementation of block 1110. The frequency error compensation module 2720 relates to the implementation of block 1120. The ideal pilot bin value extraction module 2730 relates to the implementation of block 1130. The decision re-estimation module 2740 relates to the implementation of block 1140. The re-estimation module 2745 relates to the implementation of block 1145. The return module 2750 relates to the implementation of block 1150.

[0220] Figure 28 is a block diagram of an exemplary algorithm, an iterative interpolation module 2800, according to an embodiment of the present disclosure. The iterative interpolation module 2800 is related to the implementation of process 1200A. The iterative interpolation module 2800 includes an ideal pilot bin setting module 2810, a module 2820 for determining whether a subsequent bin is a data bin, a module 2830 for applying a new equalizer to a data bin, a module 2840 for extracting ideal values ​​for a data bin, and a module 2850 for setting new equalizer values. The ideal pilot bin setting module 2810 is related to the implementation of block 1201. The module 2820 for determining whether a subsequent bin is a data bin is related to the implementation of block 1202. The module 2830 for applying a new equalizer to a data bin is related to the implementation of block 1203. The module 2840 for extracting ideal values ​​for a data bin is related to the implementation of block 1204. The module 2850 for setting new equalizer values ​​is related to the implementation of block 1205.

[0221] Figure 29 is a block diagram of a test method 2900 according to an embodiment of the present disclosure. In block 2910, the reduced header payload test pattern is transmitted to the DUT. In block 2910, the DUT is instructed to perform modulation / demodulation operations on the reduced header payload test pattern and to capture the results. Capture information is received and multimode modulation / demodulation parameter determination processing is performed. Capture information is received and multimode modulation / demodulation parameter determination processing is performed.

[0222] Figure 30 is a block diagram of an exemplary reduced header mode test process 3000 according to an embodiment of the present disclosure. The reduced header mode test process 3000 is included in a reduced header communication signal processing method. The reduced header mode test process is used when reference signal information is reduced / unavailable. In some exemplary implementations, reference signal information (e.g., reference symbols, etc.) that would otherwise be included in the header portion or preamble portion (e.g., included in the short training field, long training field, etc.) is unavailable. The reduced header mode test process is used when the receiving component (e.g., DUT, etc.) reduces information about the received signal (e.g., reduced modulation-related information, header information, preamble information, signal configuration information, etc.). The received information is less than what would otherwise be available in normal field / non-test conditions.

[0223] In block 3010, a reduced header mode test processing instruction is accessed (e.g., headerless without a reference signal). In some exemplary implementations, the reduced header mode test processing instruction is based on a selection of reduced header mode test processing (e.g., similar to the selection in block 710). This selection may be based on various conditions (e.g., the DUT does not have sufficient resources to handle testing communications with full header information, it is desirable to have a smaller test pattern for testing payloads containing reduced header information, it is desirable to have multiple test runs with different test characteristics, etc.).

[0224] In block 3020, a reduction header demodulation information determination process is performed. In some embodiments, the reduction header demodulation information determination process determines the information to be used in testing the modulation / demodulation operation (e.g., signal processing operation). In some exemplary implementations, the reduction header demodulation information determination process includes blocks 3021, 3022, 3023, 3024, 3025, and 3026.

[0225] In block 3021, a characteristic or feature of the signal associated with the payload portion of the information is identified. This characteristic or feature provides indication of timing information (e.g., start time, end time, etc.) (e.g., correlation, association with this indication, etc.). This characteristic or feature may be contained within the payload portion of the signal (e.g., cyclic prefix, other configurations, etc.). In some exemplary implementations, analysis of this characteristic or feature (e.g., autocorrelation analysis, comparative analysis, etc.) provides results from which timing information can be derived (e.g., identifiable correlation peaks, identifiable magnitude configurations in these results, identifiable phase configurations in these results, etc.). In some embodiments, the timing information is associated with a symbol contained in the payload portion. In some embodiments, this symbol is detectable in physical layer channel communication after modulation and before demodulation (e.g., after data encoding and IFFT in the modulation operation, and before FFT and data decoding in the demodulation operation, etc.). The symbol may be an OFDM symbol and an OFDMA symbol, etc. In some embodiments, this signal is a loop signal (e.g., similar to the signal in Figure 5D, etc.). This signal is constructed according to a communication protocol (e.g., publicly known, privately predetermined, etc.).

[0226] In block 3022, the start timing of a symbol in this signal is identified based on the result from block 3021. This symbol is defined by the communication protocol. In other implementations, the start and end positions / timings of symbols relative to each other are identified (for example, here one symbol starts and ends relative to the start and end of another symbol).

[0227] In block 3023, the initial coarse frequency error correction is determined based on the results from block 3021. The difference between the phase and coarse frequency errors may also be determined from an analysis of the characteristics or features of the signal associated with the information payload portion. In some embodiments, the difference between the expected value and the analyzed value may represent the phase difference and the corresponding frequency error. The expected value may be defined by a definition in the communication protocol, or derived from a definition in the communication protocol.

[0228] In block 3024, a set of bins is established for this signal, and this set of bins includes a pilot bin and a data bin. The set of bins corresponds to a set of subcarriers associated with this signal, the pilot bin corresponds to a pilot subcarrier within the set of subcarriers, and the data bin corresponds to a data subcarrier within the set of subcarriers. In some exemplary implementations, a Fast Fourier Transform (FFT) operation is performed on a portion of the signal associated with a symbol, and the result is used to establish the set of bins.

[0229] In block 3025, pilot bin identification information is extracted according to the definition of the pilot subcarrier as defined by the communication protocol. In some embodiments, pilot bin identification includes identifying the position of the pilot bin relative to each other and to other bins in the set of bins. It is understood that the identification information and definitions of the configuration and position of subcarriers (e.g., pilot subcarrier, data subcarrier, null subcarrier, etc.) relative to each other may vary (as presented, for example, in the descriptions of Figures 5A to 5E, and in other parts of this specification). In some embodiments, the pilot signal is a special BPSK subcarrier signal that is more susceptible to symbol errors than the transmitted data symbols, and this relative resilience allows for reliable determination of faults in the pilot symbols (e.g., symbol errors, frequency errors, etc.) and reliable determination of equalizer values.

[0230] In block 3026, ideal constellation values ​​and ideal symbol values ​​are set for the pilot bin and data bin. In some embodiments, interpolation is used to set the ideal constellation values ​​and ideal symbols for the data bin. It is understood that various types of interpolation (e.g., linear, least-squares regression, iterative update / re-determination, etc.) are compatible with and can be easily implemented in the reduced header mode test process 3000.

[0231] In block 3010, other demodulation parameter values ​​are determined based on the results of the ideal constellation and ideal symbol values ​​of the pilot bin and data bin (e.g., based on the results of block 826). In some embodiments, the equalizer value from the first bin is first applied to the second bin and then updated based on the results of block 826. In some exemplary implementations, the first and second bins are adjacent or adjacent to each other. The configuration of the first and second bins in relation to their proximity to each other may be defined by a communication protocol (e.g., industry standards, IEEE 802.11-based communication protocols, etc.).

[0232] In some embodiments, after the reduction header demodulation information determination process from block 3020 is performed, the operation proceeds to block 3030, where an exemplary full demodulation is performed. This full demodulation is similar to that of block 330. The full demodulation is similar to several aspects of conventional demodulation analysis. After the information from block 3020 becomes available, the process may proceed with full demodulation determination information similar to conventional information that would otherwise not be available from the reduction header signal.

[0233] Header mode test processing (e.g., blocks 750, 2100, etc.) performs modulation and demodulation tests using information within the header portion of a communication burst or frame. Header mode test processing uses the header portion information to set timing and reference values ​​for comparison with pilot values. In some embodiments, header test processing performs conventional testing of communication information and implements header test processing using conventional algorithms.

[0234] While this disclosure has been described in conjunction with preferred embodiments, it should be understood that this is not intended to limit the disclosure to these embodiments. On the contrary, this disclosure is intended to include alternatives, modifications, and equivalents. This specification is not intended to be exhaustive, nor to limit the disclosure to the precise form disclosed, and obviously, many modifications and variations are possible.

[0235] The novel test approaches presented herein offer a flexible and adaptable selection among test modes (e.g., header inclusion mode, reduced header training mode, reduced header mode, etc.). Furthermore, the novel modes disclosed herein support efficient and effective testing of the demodulation performance of a communication DUT without relying on header information to perform demodulation. In some embodiments, the reduced header mode enables the demodulation of communication signals (e.g., bursts, in packets, etc.) that are composed with less header information than would otherwise typically be included according to the communication protocol.

[0236] The proposed novel approach facilitates flexible determination of timing, frequency offset, channel response and clock error, fine-tuning frequency error, sampling clock error, IQ gain and phase imbalance, and error vector amplitude (EVM) based on variations in the amount of physical layer communication protocol header information (e.g., from full header information to no header information attached only to the data / payload portion). The proposed novel approach enables efficient and effective testing of demodulation components and functions (including improved overall test performance, e.g., reduced time and cost). The proposed novel approach facilitates significant savings in test time and financial resources. 1. In some embodiments, the reduced header communication signal processing test method is The step involves performing autocorrelation of cyclic prefixes within a signal, where the signal is configured according to a communication protocol. A step of identifying the start timing of symbols in the signal based on the results of the autocorrelation, wherein the symbols are defined by the communication protocol and include orthogonal frequency division modulation (OFDM) symbols. The step of determining initial coarse frequency error correction based on the results of the autocorrelation described above. The step of setting up a set of bins for the signal, wherein the set of bins includes a pilot bin and a data bin, wherein the set of bins corresponds to a set of subcarriers associated with the signal, the pilot bin corresponds to a pilot subcarrier in the set of subcarriers, and the data bin corresponds to a data subcarrier in the set of subcarriers. Steps to extract identification information of the pilot bin in accordance with the definition of the pilot subcarrier as defined by the communication protocol. The steps include setting ideal constellation values ​​and ideal symbol values ​​for the pilot bin and the data bin, and The step of determining other demodulation parameter values ​​based on the results of the ideal constellation values ​​and ideal symbol values ​​of the pilot bin and the data bin. It is equipped with. 2. The method according to item 1, wherein the signal is a loop signal containing payload data without preamble training reference symbols. 3. The aforementioned step of identification is The step of performing a peak search function on the results of the autocorrelation, and The step of associating the results of the peak search function with the indication of the start timing of the symbol. Having, The method described in item 1 or 2. 4. The aforementioned communication protocol is one of the methods described in items 1 to 3, corresponding to one of the IEEE 802.11 series wireless network communication protocols / standards. 5. The signal includes a physical layer payload portion of a protocol data unit that lacks physical layer header information, wherein the configuration of the physical layer payload portion of the protocol data unit conforms to the configuration specifications of a communication protocol standard corresponding to one of the IEEE 802.11 series wireless network protocols / standards, as described in any of items 1 to 4. 6. The step of setting the ideal constellation value and ideal symbol value of the pilot bin is: The stage to complete the determination of the coarse frequency error. Steps to compensate for the aforementioned coarse frequency error A step of obtaining an ideal pilot tone value in the signal, wherein the ideal pilot tone value includes the ideal constellation value and the ideal symbol value of the pilot bin and the corresponding pilot subcarrier. At the stage of determining whether the user has selected "Low SNR" for the aforementioned Frequency Estimation Method, if so, it is appropriate to re-estimate the frequency error. If the result of the above determination is positive, the step is to perform the reestimation of the fine-tuning frequency error using the pilot tone and / or data bin values ​​in the signal. The steps of applying the aforementioned fine-tuning frequency error to the signal, and The step of returning the ideal pilot tone value, where the ideal pilot tone value includes the ideal constellation value and the ideal symbol value of the pilot bin and the corresponding pilot subcarrier. Having, The method described in any of items 1 through 5. 7. The step of setting the ideal constellation values ​​and ideal symbol values ​​for the pilot bin and the data bin is: A step of determining the equalizer value of the pilot subcarrier in the pilot bin based on an ideal pilot tone constellation value, and Steps to determine the equalizer value of the data subcarrier at the data bin location based on the ideal data tone constellation value. Having, The methods described in items 1 to 7. 8. The method according to item 7, wherein the equalizer value of the pilot bin and the equalizer value of the data bin are the reciprocals of their respective channel response values. 9. The method according to item 7 or 8, wherein the determination of the equalizer value of the data bin includes interpolation between the equalizer values ​​of the pilot bin. 10. The step of setting the ideal constellation values ​​and ideal symbol values ​​for the pilot bin and the data bin is: The step of selecting one of the aforementioned pilot bins and assigning the label of the current pilot bin to the aforementioned one of the pilot bins. The step of extracting the ideal value of the current pilot bin, where the step of extracting the ideal value of the current pilot bin is based on two-phase shift keying (BPSK) analysis. Steps to extract pilot equalizer values ​​based on the ideal value of the current pilot bin and the known capture value of the current pilot bin. The step of inserting the aforementioned pilot equalizer into the equalizer list. The step of selecting one of the data bins adjacent to the current pilot bin and assigning that one of the data bins to the label of the current data bin. The step of assigning the label of the current equalizer value to the pilot equalizer value. Steps to apply the current equalizer value to the current data bin. Steps to extract ideal constellation values ​​from the current data bin. Steps to extract new equalizer values ​​based on the ideal constellation values ​​and known capture values ​​of the current databin. Steps to insert the new equalizer into the equalizer list. The step of determining whether the next bin in the set of bins is another one of the pilot bins. If the above determination is positive, the next step is to reassign the label of the current pilot bin to one of the other pilot bins. Determining whether the next bin in the set of bins is another one of the data bins If the next bin in the set of bins is another one of the data bins, checking whether the next bin is a bandwidth edge bin If the check is negative, applying the new equalizer value to the next bin If the check is positive, performing enhanced equalizer processing Determining whether the iteration of the current bin corresponds to the last bin Performing averaging equalization processing, and Performing current data bin label re - assignment processing having The method according to any one of items 1 to 9. 11. The enhanced equalizer processing includes setting a delta equalizer value based on the current equalizer value and the new equalizer value adding the new equalizer value to the delta equalizer value and assigning a label of the enhanced equalizer value to the result of the addition, and applying the enhanced equalizer value to the next bin including The method according to any one of items 1 to 10. 12. The current data bin label re - assignment processing includes re - assigning the next data bin to the label of the current data bin, where the next data bin becomes known as the current bin if the check is negative, re - assigning the new equalizer value to the label of the current equalizer value, where the new equalizer value becomes known as the current equalizer value, and if the check is positive, re - assigning the enhanced equalizer value to the label of the current equalizer value, where the enhanced equalizer value becomes known as the current equalizer value including The method described in any of items 1 through 10. 13. In some embodiments, the signal processing test system is configured to be coupled with a load board that is coupled with multiple devices under test (DUTs). A controller configured to direct the testing of the plurality of DUTs, wherein the controller has a test mode selection module that is operable to select between a plurality of test modes, wherein one of the plurality of test modes is associated with reduced header communication signal test processing applied to a signal, and Test electronic equipment configured to test the plurality of DUTs under the control of the controller, wherein the test electronic equipment is coupled to the load board, wherein the test electronic equipment is A demodulation information determination module capable of collecting information associated with a demodulation operation, wherein the demodulation operation includes determining signal processing information based on information in the payload portion of the signal, and A demodulator capable of performing demodulation operations based on information received from the aforementioned demodulation information determination module. Having, It is equipped with. 14. The signal processing test system according to item 13, wherein the test mode selection module is operable to select the mode associated with the reduced header communication signal test processing, and further, the demodulation information determination module determines signal processing information associated with the demodulation operation of the signal, the signal processing information not otherwise included in the header portion of the signal. 15. The demodulation information determination module is operable to determine signal processing information associated with a plurality of pilot tone subcarriers and a plurality of non-pilot tone subcarriers in the signal, and the configuration of the plurality of pilot tone subcarriers and the plurality of non-pilot tone subcarriers otherwise conforms to a communication protocol standard corresponding to one of the IEEE 802.11 series wireless network protocols / standards, as described in item 13 or 14 of the signal processing test system. 16. The demodulation information determination module is operable to perform a reduced header communication signal processing test method, wherein the reduced header communication signal includes a payload portion that is repeatedly transmitted within a loop, and the reduced header communication signal does not have a complete set of header training reference symbols specified in the communication protocol, as described in any of items 13 to 15. 17. In some embodiments, the signal processing test method comprises the steps of: selecting a signal processing mode from a header inclusion mode, a reduced header training mode, and a reduced header mode; performing a signal processing information determination process according to the result of the step of selecting the signal processing mode; and performing modulation / demodulation-related processing according to the result of the signal processing information determination process. 18. The aforementioned reduced header training mode is: Demodulating an ideal waveform including the training sequence, and Performing ideal headerless demodulation using the payload-dedicated portion of the aforementioned ideal waveform. Performing a training process that includes, Using the results of the aforementioned ideal headerless demodulation, perform complete demodulation of another payload waveform. including, The signal processing test method described in item 17. 19. The aforementioned reduced header mode is, The autocorrelation of cyclic prefixes within a signal, where the signal is configured according to a communication protocol. Identifying the start timing of symbols in the signal based on the results of the autocorrelation, where the symbols are defined by the communication protocol and include orthogonal frequency division modulation (OFDM) symbols. Based on the results of the autocorrelation described above, the initial coarse frequency error correction is determined. Setting up a set of bins for the signal, wherein the set of bins includes a pilot bin and a data bin, wherein the set of bins corresponds to a set of subcarriers associated with the signal, the pilot bin corresponds to a pilot subcarrier in the set of subcarriers, and the data bin corresponds to a data subcarrier in the set of subcarriers. Extracting identification information of the pilot bin in accordance with the definition of the pilot subcarrier as defined by the communication protocol. Setting ideal constellation values ​​and ideal symbol values ​​for the pilot bin and the data bin, and Determining other demodulation parameter values ​​based on the results of the ideal constellation values ​​and ideal symbol values ​​of the pilot bin and the data bin. including, The signal processing test method described in item 17 or 18. 20. The signal processing test method according to any one of items 17 to 19, wherein the header inclusion mode includes obtaining demodulation information from a header contained in the signal.

[0237] In some embodiments, one or more non-temporary computer-readable media store instructions that, when executed by one or more processors of the ATE, cause one or more processors to perform any of the actions in items 1 to 12 and 17 to 20.

[0238] In short, the disclosed technology overcomes the limitations of conventional systems and methods by enabling accurate demodulation of the payload portion of a communication in accordance with the communication protocol, without relying on header information otherwise specified for use by the communication protocol. In some embodiments, the reduced header implementation includes a training mode in which an ideal demodulated payload waveform is extracted from a complete ideal waveform (including, for example, header information), and the ideal demodulated payload waveform is used for demodulating the received or captured signal. In some embodiments, pilot bins / subcarriers are identified in the payload portion of the loop communication signal, and ideal pilot bin values ​​are set. Autocorrelation and peak search functions of the cyclic prefix are used to identify the start of symbols (e.g., transmission symbols, OFDM symbols, etc.). Pilot bins / subcarriers within a symbol and the corresponding ideal pilot bin / subcarrier values ​​are identified (e.g., by performing BPSK analysis, etc.) and, as a result, used to set equalizer values. The equalizer values ​​are applied to adjacent data bins, and new interpolated equalizer values ​​for this data bin are developed. This process iteratively applies equalizer values ​​from the previous data bin equalizer to the subsequent data bin until it encounters another pilot bin, developing a new equalizer for the subsequent data bin.

[0239] At least one technical advantage of the disclosed technology is the ability to perform demodulation testing on a DUT, which would otherwise be impractical or impossible due to limited resources. The ability of a memory-limited DUT to handle newer communication protocols can be tested. The novel reduced-header demodulation processing presented provides efficient and effective demodulation of the data payload portion of a communication signal (e.g., previously unavailable without full header information). Despite the limited test-related resources the DUT possesses that would otherwise hinder demodulation testing, the novel reduced-header system and method presented enables demodulation testing of the DUT by appropriately implementing and analyzing the demodulation of the payload portion of the communication signal. Numerous demodulation-related parameters (e.g., timing, frequency offset, channel response, clock error, etc.) can be determined using the payload portion of the signal, without relying on header information. In addition, the smaller capture size associated with the reduced-header payload signal, and the corresponding test patterns, reduce the number of ATE uploads and demodulation processes. Test efficiency is improved by reducing the need for large test patterns associated with long header information (for example, patterns that would otherwise be time-consuming, inefficient, and prone to errors).

[0240] Any combination of any claim element described in any of the claims in any form and / or any element described herein is included within the scope intended for this disclosure and protection.

[0241] The descriptions of various embodiments are presented for illustrative purposes only and are not intended to be exhaustive or limitful to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

[0242] Aspects of the present embodiment can be embodied as a system, method, or computer program product. Accordingly, aspects of the present disclosure can take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects (generally all of which may be referred to herein as a "module," "system," or "computer"). In addition, any and all hardware and / or software technologies, processes, functions, components, engines, modules, or systems described in the present disclosure can be implemented as a single circuit or a set of multiple circuits. Furthermore, aspects of the present disclosure can take the form of a computer program product embodied in one or more computer-readable media having computer-readable program code embodied thereon.

[0243] Any combination of one or more computer-readable media may be utilized. The computer-readable media may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this specification, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

[0244] Aspects of this disclosure are described above with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block illustrated in the block diagrams and / or flowcharts, and combinations of blocks illustrated in the block diagrams and / or flowcharts, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general-purpose computer, a dedicated computer, or other programmable data processing device to generate a machine. When executed via the processor of a computer or other programmable data processing device, these instructions enable the implementation of the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams. Such processors may, without limitation, be general-purpose processors, dedicated processors, application-specific processors, or field-programmable gate arrays.

[0245] The flowcharts and block diagrams in the drawings illustrate the architecture, functionality, and operation of possible implementations of the systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. Note that in some alternative implementations, the functions shown in the blocks may be performed in a different order than shown in the diagram. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may be executed in reverse order depending on the functions involved. Note that each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, may be implemented by a dedicated hardware-based system or a combination of dedicated hardware and computer instructions that performs a specified function or operation. While the foregoing descriptions relate to embodiments of the present disclosure, other and further embodiments of the present disclosure may be conceived without departing from their basic scope, and their scope is determined by the following claims.

[0246] Embodiments of the present disclosure have been described in this manner. Although the present disclosure has been described in particular embodiments, it should be understood that the present disclosure should not be construed as being limited by such embodiments, but rather should be construed in accordance with the following claims. According to this specification, the following items are also disclosed: [Item 1] A method for testing reduced header communication signal processing, The step involves performing autocorrelation of cyclic prefixes within a signal, where the signal is configured according to a communication protocol; A step of identifying the start timing of symbols in the signal based on the results of the autocorrelation, wherein the symbols are defined by the communication protocol and include orthogonal frequency division modulation (OFDM) symbols; A step in which initial coarse-frequency error correction is determined based on the results of the autocorrelation; The step of setting up a set of bins for the signal, wherein the set of bins includes a pilot bin and a data bin, wherein the set of bins corresponds to a set of subcarriers associated with the signal, the pilot bin corresponds to a pilot subcarrier in the set of subcarriers, and the data bin corresponds to a data subcarrier in the set of subcarriers; A step of extracting identification information of the pilot bin in accordance with the definition of the pilot subcarrier as defined by the communication protocol; The steps of setting ideal constellation values ​​and ideal symbol values ​​for the pilot bin and the data bin; and The step of determining other demodulation parameter values ​​based on the results of the ideal constellation values ​​and ideal symbol values ​​of the pilot bin and the data bin. A method that includes [a certain feature]. [Item 2] The method according to item 1, wherein the signal is a loop signal containing payload data without preamble training reference symbols. [Item 3] The aforementioned step of identification is The step of performing a peak search function on the results of the autocorrelation; and The step of associating the results of the peak search function with the indication of the start timing of the symbol. Having, The method described in item 2. [Item 4] The aforementioned communication protocol is the method described in item 1, which corresponds to one of the IEEE 802.11 series wireless network communication protocols / standards. [Item 5] The signal includes a physical layer payload portion of a protocol data unit that lacks physical layer header information, wherein the configuration of the physical layer payload portion of the protocol data unit conforms to the configuration specifications of a communication protocol standard that otherwise corresponds to one of the IEEE 802.11 series wireless network protocols / standards, as described in item 1. [Item 6] The step of setting the ideal constellation value and ideal symbol value of the pilot bin is: The stage to complete the determination of the coarse frequency error; A step to compensate for the aforementioned coarse frequency error; A step of obtaining an ideal pilot tone value in the signal, wherein the ideal pilot tone value includes the ideal constellation value and the ideal symbol value of the pilot bin and the corresponding pilot subcarrier; At the stage of determining whether the user has selected "LowSNR" for aFrequencyEstimationMode, if so, reestimating the frequency error is appropriate; If the result of the judgment is positive, the step is to perform the reestimation of the fine-tuning frequency error using the pilot tone and / or data bin values ​​in the signal; The step of applying the aforementioned fine-tuning frequency error to the signal; and The step of returning the ideal pilot tone value, where the ideal pilot tone value includes the ideal constellation value and the ideal symbol value of the pilot bin and the corresponding pilot subcarrier. Having, The method described in item 1. [Item 7] The step of setting the ideal constellation values ​​and ideal symbol values ​​for the pilot bin and the data bin is: A step of determining the equalizer value of the pilot subcarrier in the pilot bin based on an ideal pilot tone constellation value; and Steps to determine the equalizer value of the data subcarrier at the data bin location based on the ideal data tone constellation value. Having, The method described in item 1. [Item 8] The method according to item 7, wherein the equalizer value of the pilot bin and the equalizer value of the data bin are the reciprocals of their respective channel response values. [Item 9] The method according to item 7, wherein the determination of the equalizer value of the data bin includes interpolation between the equalizer values ​​of the pilot bin. [Item 10] The step of setting the ideal constellation values ​​and ideal symbol values ​​for the pilot bin and the data bin is: The step of selecting one of the aforementioned pilot bins and assigning the label of the current pilot bin to the aforementioned one of the pilot bins; The step of extracting the ideal value of the current pilot bin, where the step of extracting the ideal value of the current pilot bin is based on two-phase shift keying (BPSK) analysis; A step of extracting pilot equalizer values ​​based on the ideal value of the current pilot bin and the known capture value of the current pilot bin; The step of inserting the aforementioned pilot equalizer value into the equalizer list; A step of selecting one of the data bins adjacent to the current pilot bin, and assigning that one of the data bins to the label of the current data bin; The step of assigning the label of the current equalizer value to the pilot equalizer value; The step of applying the current equalizer value to the current data bin; A step of extracting ideal constellation values ​​from the current data bin; A step of extracting new equalizer values ​​based on the ideal constellation values ​​and known capture values ​​of the current databin; The step of inserting the new equalizer value into the equalizer list; A step of determining whether the next bin in the set of bins is another one of the pilot bins; If the above determination is positive, the next step is to reassign the label of the current pilot bin to one of the other pilot bins; A step of determining whether the next bin in the set of bins is another one of the data bins; If the next bin in the set of bins is another of the data bins, the next step is to determine whether the next bin is a bandwidth edge bin; If the confirmation is negative, the next step is to apply the new equalizer value to the next bin; If the above confirmation is positive, the next step is to perform enhanced equalizer processing; The stage of determining whether the iteration of the current bin corresponds to the last bin; The stage of performing averaging and equalization; and The stage where the current data bin label reassignment process is performed. Having, The method described in item 1. [Item 11] The enhanced equalizer processing described above is: Setting the delta equalizer value based on the current equalizer value and the new equalizer value; Adding the new equalizer value to the delta equalizer value and assigning the enhanced equalizer value label to the additional result; and Apply the enhanced equalizer value to the next bin. including, The method described in item 10. [Item 12] The aforementioned data bin label reassignment process is performed as follows: The next data bin is to be reassigned to the label of the current data bin, where the next data bin is known as the current bin; If the above confirmation is negative, the new equalizer value is reassigned to the label of the current equalizer value, where the new equalizer value is known as the current equalizer value; and If the above confirmation is positive, the enhanced equalizer value is reassigned to the label of the current equalizer value, where the enhanced equalizer value is known as the current equalizer value. including, The method described in item 10. [Item 13] A load board configured to connect with multiple devices under test (DUTs); A controller configured to direct the testing of the plurality of DUTs, wherein the controller has a test mode selection module that is operable to select between a plurality of test modes, wherein one of the plurality of test modes is associated with reduced header communication signal test processing applied to a signal; and Test electronic equipment configured to test the plurality of DUTs under the control of the controller, wherein the test electronic equipment is coupled to the load board, wherein the test electronic equipment is A demodulation information determination module capable of collecting information associated with a demodulation operation, wherein the demodulation operation includes determining signal processing information based on information in the payload portion of the signal; and A demodulator capable of performing demodulation operations based on information received from the aforementioned demodulation information determination module. Having, A signal processing test system equipped with the following features. [Item 14] The signal processing test system according to item 13, wherein the test mode selection module is operable to select the test mode associated with the reduced header communication signal test processing, and further, the demodulation information determination module determines signal processing information associated with the demodulation operation of the signal, the signal processing information not otherwise included in the header portion of the signal. [Item 15] The demodulation information determination module is operable to determine signal processing information associated with a plurality of pilot tone subcarriers and a plurality of non-pilot tone subcarriers in the signal, and the configuration of the plurality of pilot tone subcarriers and the plurality of non-pilot tone subcarriers otherwise conforms to a communication protocol standard corresponding to one of the IEEE 802.11 series wireless network protocols / standards, as described in item 13. [Item 16] The demodulation information determination module is operable to perform a reduced header communication signal processing test method, wherein the reduced header communication signal includes a payload portion that is repeatedly transmitted within a loop, and the reduced header communication signal does not have a complete set of header training reference symbols specified in the communication protocol, as described in item 13. [Item 17] A step in selecting a signal processing mode from among header inclusion mode, reduced header training mode, and reduced header mode; A step of performing a signal processing information determination process according to the result of the step of selecting a signal processing mode; and A step in which modulation / demodulation-related processing is performed according to the results of the signal processing information determination process. A signal processing test method comprising the following: [Item 18] The aforementioned reduced header training mode is: Demodulating an ideal waveform including the training sequence; and Performing ideal headerless demodulation using the payload-dedicated portion of the aforementioned ideal waveform. Performing a training process that includes; and Using the results of the aforementioned ideal headerless demodulation, perform complete demodulation of another payload waveform. including, The signal processing test method described in item 17. [Item 19] The aforementioned reduced header mode is, The autocorrelation of cyclic prefixes within a signal, where the signal is configured according to a communication protocol; Identifying the start timing of symbols in the signal based on the results of the autocorrelation, where the symbols are defined by the communication protocol and include orthogonal frequency division modulation (OFDM) symbols; Determining initial coarse-frequency error correction based on the results of the aforementioned autocorrelation; Setting up a set of bins for the aforementioned signal, wherein the set of bins includes a pilot bin and a data bin, wherein the set of bins corresponds to a set of subcarriers associated with the aforementioned signal, the pilot bin corresponds to a pilot subcarrier in the set of subcarriers, and the data bin corresponds to a data subcarrier in the set of subcarriers; Extracting identification information of the pilot bin in accordance with the definition of the pilot subcarrier as defined by the communication protocol; Setting ideal constellation values ​​and ideal symbol values ​​for the pilot bin and the data bin; and Determining other demodulation parameter values ​​based on the results of the ideal constellation values ​​and ideal symbol values ​​of the pilot bin and the data bin. including, The signal processing test method described in item 17. [Item 20] The signal processing test method described in item 17, wherein the header inclusion mode includes obtaining demodulation information from a header contained within the signal.

Claims

1. A load board configured to connect with multiple devices under test (DUTs); A controller configured to instruct the testing of the plurality of DUTs, wherein the controller has a test mode selection module that is operable to select between a plurality of test modes, wherein one of the plurality of test modes is associated with reduced header communication signal test processing applied to the signal; and A test electronic device configured to test the plurality of DUTs under the control of the controller, wherein the test electronic device is coupled to the load board, wherein the test electronic device is Demodulation information determination module capable of collecting information associated with a demodulation operation, wherein the demodulation operation includes determining signal processing information based on information in the payload portion of the signal; and A demodulator capable of performing demodulation operations based on information received from the aforementioned demodulation information determination module. Having, A signal processing test system equipped with the following features.

2. The signal processing test system according to claim 1, wherein the test mode selection module is operable to select the test mode associated with the reduced header communication signal test processing, and further, the demodulation information determination module determines signal processing information associated with the demodulation operation of the signal, the signal processing information is otherwise not included in the header portion of the signal.

3. The signal processing test system according to claim 1, wherein the demodulation information determination module is operable to determine signal processing information associated with a plurality of pilot tone subcarriers and a plurality of non-pilot tone subcarriers in the signal, and the configuration of the plurality of pilot tone subcarriers and the plurality of non-pilot tone subcarriers otherwise conforms to a communication protocol standard corresponding to one of the IEEE 802.11 series wireless network protocols / standards.

4. The signal processing test system according to claim 1, wherein the demodulation information determination module is operable to perform a reduced header communication signal processing test method, the reduced header communication signal includes a payload portion that is repeatedly transmitted within a loop, and the reduced header communication signal does not have a complete set of header training reference symbols specified in the communication protocol.

5. The step of selecting a signal processing mode from among header inclusion mode, reduced header training mode, and reduced header mode; A step of performing a signal processing information determination process according to the result of the step of selecting a signal processing mode; and A step in which modulation / demodulation-related processing is performed according to the results of the signal processing information determination process. A signal processing test method comprising the following:

6. The aforementioned reduced header training mode is: Demodulating an ideal waveform including the training sequence; and Performing ideal headerless demodulation using the payload-dedicated portion of the aforementioned ideal waveform. Performing a training process that includes; and Using the results of the aforementioned ideal headerless demodulation, perform complete demodulation of another payload waveform. including, The signal processing test method according to claim 5.

7. The aforementioned reduced header mode is, The autocorrelation of cyclic prefixes within a signal, where the signal is configured according to a communication protocol; Identifying the start timing of symbols in the signal based on the results of the autocorrelation, where the symbols are defined by the communication protocol and include orthogonal frequency division modulation (OFDM) symbols; Determining initial coarse-frequency error correction based on the results of the aforementioned autocorrelation; Setting up a set of bins for the aforementioned signal, wherein the set of bins includes a pilot bin and a data bin, wherein the set of bins corresponds to a set of subcarriers associated with the aforementioned signal, the pilot bin corresponds to a pilot subcarrier in the set of subcarriers, and the data bin corresponds to a data subcarrier in the set of subcarriers; Extracting identification information of the pilot bin in accordance with the definition of the pilot subcarrier as defined by the communication protocol; Setting ideal constellation values ​​and ideal symbol values ​​for the pilot bin and the data bin; and Determining other demodulation parameter values ​​based on the results of the ideal constellation values ​​and ideal symbol values ​​of the pilot bin and the data bin. including, The signal processing test method according to claim 5.

8. The signal processing test method according to claim 5, wherein the header inclusion mode includes obtaining demodulation information from a header contained in the signal.

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