Indication device

Abstract

A display device according to one embodiment of this specification includes a substrate including a display area, an optical area disposed within the display area and including a through-hole, and a non-display area surrounding the display area, a plurality of insulating layers disposed on the substrate, at least one dam disposed on the plurality of insulating layers, and at least one connection prevention portion disposed on the plurality of insulating layers and positioned closer to the through-hole than at least one dam, wherein a first trench is disposed in a portion of the plurality of insulating layers that overlap with at least one connection prevention portion in the optical area. [Effect] Therefore, it is possible to prevent cracks generated from external interference in the optical domain from propagating.

Description

Technical Field

[0001] This specification relates to a display device, and more particularly, provides a display device capable of blocking a crack propagation path in an area where a camera or a sensor is disposed.

Background Art

[0002] As the information age progresses, the field of display devices for visually displaying electrical information signals has been rapidly developing, and research has continued to develop performance such as thinning, weight reduction, and low power consumption for various display devices.

[0003] Typical display devices include a liquid crystal display (LCD), a field emission display (FED), an electro-wetting display (EWD), and an organic light emitting display (OLED).

[0004] The field emission display represented by the organic light emitting display is a self-emitting display device. Unlike the liquid crystal display, it does not require a separate light source and can be manufactured in a lightweight and thin form. In addition, the field emission display is not only advantageous in terms of power consumption by low voltage driving, but also excellent in hue reproduction, response speed, viewing angle, and contrast ratio (CR), and is expected to be utilized in various fields.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The problem to be solved in one embodiment of this specification is to provide a display device capable of preventing cracks generated from external interference from propagating in an area where a camera or a sensor is disposed.

[0006] The problem to be addressed in other embodiments of this specification is to provide a display device that can ensure product yield and reliability performance.

[0007] The problems described herein are not limited to those mentioned above, and other problems not mentioned can be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0008] A display device according to one embodiment of this specification includes a substrate including a display area, an optical area disposed within the display area and including a through-hole, and a non-display area surrounding the display area, a plurality of insulating layers disposed on the substrate, at least one dam disposed on the plurality of insulating layers, and at least one connection prevention portion disposed on the plurality of insulating layers and positioned closer to the through-hole than at least one dam, wherein a first trench is disposed in a portion of the plurality of insulating layers that overlap with at least one connection prevention portion in the optical area.

[0009] Specific details of other embodiments are included in the detailed description and drawings.

[0010] In one embodiment of this specification, a display device can prevent the penetration of moisture and oxygen from entering through a through-hole by forming multiple connection prevention parts around the through-hole. The prevention parts can cut the connection of the organic common layer, i.e., the light-emitting layer, of the light-emitting element arranged on the front of the display panel, thereby blocking the movement path of moisture and oxygen.

[0011] In one embodiment of this specification, the display device can be configured to prevent the organic insulating layer of the sealing layer from overflowing into the camera hole by arranging multiple dams near multiple connection prevention sections. The multiple dams can prevent contamination of the camera hole area and interference with the camera positioned in the through-hole that may occur when the organic insulating layer overflows into the camera hole.

[0012] In one embodiment of this specification, a display device can prevent crack propagation by cutting away a portion of the multiple inorganic insulating layers superimposed on the multiple connection prevention parts to form trenches, thereby blocking the path through which cracks propagate even if cracks occur in through holes.

[0013] The effects described herein are not limited to those exemplified above, and a wider variety of effects are included within this specification. [Brief explanation of the drawing]

[0014] [Figure 1] This is a block diagram of a display device according to one embodiment of this specification. [Figure 2] This is a cross-sectional view along line II-II' in Figure 1. [Figure 3] This is a plan view showing an enlarged view of area A in Figure 1. [Figure 4] This is a plan view showing an enlarged view of area B in Figure 3. [Figure 5] This is a cross-sectional view along line V-V' in Figure 4. [Figure 6a] This is an enlarged cross-sectional view showing area C in Figure 5 according to one embodiment of this specification. [Figure 6b] This is a cross-sectional view of a display device according to another embodiment of this specification. [Figure 6c] This is a cross-sectional view of a display device according to another embodiment of this specification. [Figure 6d] This is a cross-sectional view of a display device according to another embodiment of this specification. [Figure 6e] This is a cross-sectional view of a display device according to another embodiment of this specification. [Figure 7a] This is a cross-sectional view of a display device according to another embodiment of this specification. [Figure 7b] This is a cross-sectional view of a display device according to another embodiment of this specification. [Figure 7c] This is a cross-sectional view of a display device according to another embodiment of this specification. [Figure 7d] This is a cross-sectional view of a display device according to another embodiment of this specification.

Best Mode for Carrying Out the Invention

[0015] The advantages and features of this specification, and the method for achieving them, will become clear by referring to the embodiments described in detail below together with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below, and can be embodied in various different shapes. Merely, these embodiments are provided so that the disclosure of this specification becomes complete, and to fully inform those with ordinary knowledge in the technical field to which this specification pertains of the scope of one embodiment of this specification.

[0016] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are exemplary, so the embodiments of this specification are not limited to the matters illustrated. Throughout the specification, the same reference numerals refer to the same components. Also, when explaining one embodiment of this specification, if it is determined that a specific explanation of related known technology may muddy the gist of one embodiment of this specification, the detailed explanation thereof is omitted. When terms such as "including", "having", "being made" as mentioned in this specification are used, other parts can be added as long as "only" is not used. When a component is expressed in the singular, it includes the case of including a plurality unless otherwise explicitly stated.

[0017] When interpreting components, it is interpreted to include an error range even without a separate explicit description.

[0018] When it is an explanation about the positional relationship, for example, when the positional relationship between two parts is described such as "on ~", "above ~", "below ~", "next to ~", etc., one or more other parts may be located between the two parts as long as "immediately" or "directly" is not used.

[0019] An element or layer being referred to as "on" another element or layer includes both the case where there is another layer or another element immediately above or intervening between the other element.

[0020] Furthermore, while terms such as "first," "second," etc., are used to describe a variety of components, these components are not limited by these terms. These terms are simply used to distinguish one component from another. Therefore, the first component referred to below may also be the second component within the technical concept of this specification.

[0021] Throughout the specification, the same reference numeral refers to the same component.

[0022] The area and thickness of each component shown in the drawings are provided for illustrative purposes only, and the embodiments described herein are not necessarily limited to the area and thickness of the components shown.

[0023] The features of each of the various embodiments described herein can be combined or combined with one another, either partially or as a whole, enabling a variety of technically diverse interoperability and drive, and each embodiment may be implemented independently of the others or together in relation to one another.

[0024] Hereinafter, an embodiment of this specification will be described with reference to the drawings.

[0025] Figure 1 is a block diagram of a display device according to one embodiment of this specification.

[0026] Referring to Figure 1, the display device 100 in one embodiment of this specification may include a video processing unit 151, a timing controller 152, a data drive unit 153, a gate drive unit 154, and a display panel DP.

[0027] At this time, the video processing unit 151 can output data signals DATA and data enable signals DE supplied from an external source. In addition to the data enable signal DE, the video processing unit 151 can output one or more of the following signals: vertical synchronization signal, horizontal synchronization signal, and clock signal.

[0028] The timing controller 152 receives a data signal DATA from the video processing unit 151 along with a drive signal including a data enable signal DE or a vertical synchronization signal, a horizontal synchronization signal, and a clock signal. The timing controller 152 can output a gate timing control signal GDC for controlling the operation timing of the gate drive unit 154 and a data timing control signal DDC for controlling the operation timing of the data drive unit 153 based on the drive signal.

[0029] Furthermore, the data drive unit 153 can sample the data signal DATA supplied from the timing controller 152 in response to the data timing control signal DDC supplied from the timing controller 152, latch it, convert it to a gamma reference voltage, and output it. The data drive unit 153 can output the data signal DATA through data wiring DL1 to DLn.

[0030] Furthermore, the gate drive unit 154 can output a gate signal while shifting the gate voltage level in response to the gate timing control signal GDC supplied from the timing controller 152. The gate drive unit 154 can output a gate signal through gate wiring GL1 to GLm.

[0031] The display panel DP can display images by having pixels P emit light in response to data signals DATA and gate signals supplied from the data drive unit 153 and the gate drive unit 154. The detailed structure of pixels P is explained in detail in Figure 2.

[0032] The display panel DP may include a display area DA, an optical area OA located within the display area DA and including a through-hole TH, and a non-display area NDA surrounding the display area DA.

[0033] The display area DA is the area on the display panel DP where the video is displayed.

[0034] The display area DA may contain a number of pixels P and circuits for driving the number of pixels P. The number of pixels P is the smallest unit constituting the display area DA, and a display element may be placed in each of the number of pixels P. For example, an organic light-emitting element including an anode, light-emitting layer, and cathode may be placed in each of the number of pixels P, but is not limited to this. The circuits for driving the number of pixels P may include driving elements and wiring, etc. For example, the circuits may consist of thin-film transistors, storage capacitors, gate wiring, data wiring, etc., but is not limited to this.

[0035] The optical area (OA) is located within the display area (DA) and is the area where the through-holes (TH) are positioned. The display panel (DP) has the through-holes (TH) positioned within the display area (DA), reducing the bezel area (Non-display area, NDA) and maximizing the display area (DA). Products with a design that maximizes the display area (DA) can maximize user immersion and be aesthetically more appealing.

[0036] The through-hole TH may be formed to correspond to an optical electronic device such as a camera or light sensor.

[0037] The through-holes TH may be two, as shown in Figure 1, but are not limited to this and can be arranged in various ways. For example, one or two holes may be arranged inside the display area DA, with a camera in the first hole and a distance sensing sensor or face recognition sensor and a wide-angle camera in the second hole.

[0038] The NDA (Non-Display Area) is an area where video is not displayed.

[0039] The non-display area NDA may be bent and not visible from the front, or may be hidden by a case (not shown), and is also called the bezel area.

[0040] In Figure 1, the non-display area NDA is shown to surround the rectangular display area DA. However, the shape and arrangement of the display area DA and the non-display area NDA are not limited to the example shown in Figure 1. That is, the display area DA and the non-display area NDA may be in a shape suitable for the design of the electronic device equipped with the display device 100. For example, exemplary shapes of the display area DA may be pentagonal, hexagonal, circular, elliptical, etc.

[0041] Various wiring and circuits for driving the organic light-emitting elements of the display area DA may be arranged in the non-display area NDA. For example, link wiring, GIP (Gate-In-Panel) wiring, or drive ICs such as gate drive unit 154 and data drive unit 153 may be arranged in the non-display area NDA for transmitting signals to numerous subpixels and circuits of the display area DA, but are not limited to these.

[0042] The display device 100 may further include a variety of additional elements for generating a variety of signals or driving pixels within the display area DA. Additional elements for driving pixels may include inverter circuits, multiplexers, electrostatic discharge (ESD) circuits, etc. The display device 100 may also include additional elements associated with functions other than pixel driving. For example, the display device 100 may further include additional elements that provide touch sensing functionality, user authentication functionality (e.g., fingerprint recognition), multi-level pressure sensing functionality, tactile feedback functionality, etc. The aforementioned additional elements may be located in external circuits connected to the non-display area (NDA) and / or the linking interface.

[0043] In the following, Figure 2 will be referenced for a more detailed explanation of the cross-sectional structure of the display area DA of the display device 100.

[0044] Figure 2 is a cross-sectional view showing the cross-sectional structure of a single pixel arranged in a display area according to one embodiment of this specification.

[0045] An embodiment of the display device 100 according to this specification may include a substrate 110, a first buffer layer 111, a first thin-film transistor TR1, a second thin-film transistor TR2, a first gate insulating layer 112a, a first interlayer insulating layer 113a, a second buffer layer 114, a second gate insulating layer 112b, a second interlayer insulating layer 113b, a connecting electrode CE, a first planarization layer 115a, a second planarization layer 115b, an auxiliary electrode 145, a bank 116a, a spacer 116b, an anode 121, a light-emitting layer 122, a cathode 123, a sealing layer 117, and a touch sensing unit.

[0046] The substrate 110 serves to support and protect the components of the flexible display device that are positioned on top of it.

[0047] The substrate 110 is a structure for supporting various components included in the display device 100 and may be made of an insulating material. The substrate 110 may include a first substrate 110a, a second substrate 110b, and an interlayer insulating film 110c. The interlayer insulating film 110c may be placed between the first substrate 110a and the second substrate 110b. By constructing the substrate 110 in this way with a first substrate 110a, a second substrate 110b, and an interlayer insulating film 110c, moisture penetration can be prevented. For example, the first substrate 110a and the second substrate 110b may be polyimide (PI) substrates, and the interlayer insulating film 110c may consist of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx).

[0048] A light-shielding layer 125 can be placed on the substrate 110.

[0049] The first buffer layer 111 may be placed on the substrate 110, covering the light-shielding layer 125. Specifically, a multi-buffer layer 111a may be placed on the substrate 110, covering the light-shielding layer 125, and an active buffer layer 111b may be placed on the multi-buffer layer 111a.

[0050] The multi-buffer layer 111a can delay the diffusion of moisture or oxygen that has penetrated the substrate 110 and may contain at least one of silicon nitride (SiNx) and silicon oxide (SiOx).

[0051] The active buffer layer 111b protects the first active layer A1 and can block various types of defects flowing in from the substrate 110. For example, the active buffer layer 111b may include at least one of a-Si, silicon nitride (SiNx), and silicon oxide (SiOx).

[0052] The first thin-film transistor TR1 may be placed on the first buffer layer 111. The first thin-film transistor TR1 may include a first active layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. Here, depending on the design of the pixel circuit, the first source electrode S1 may become the first drain electrode, and the first drain electrode D1 may become the first source electrode.

[0053] The first active layer A1 may be placed on the first buffer layer 111 so as to overlap with the light-shielding layer 125. The first active layer A1 may include amorphous silicon or polycrystalline silicon. For example, the first active layer A1 may include low-temperature polysilicon (LTPS). For example, polysilicon materials have high mobility (100 cm²). 2Because it has low energy consumption (greater than / Vs) and excellent reliability, it can be applied to gate drivers and / or multiplexers (MUX) for driving thin-film transistors for display elements, and can be applied to the first active layer A1 of the driving thin-film transistor in a display device 100 according to one embodiment of this specification, but is not limited thereto. For example, depending on the characteristics of the display device 100, it can also be applied to the second active layer A2 of the switching thin-film transistor. Polysilicon can be formed by depositing amorphous silicon (a-Si) material on a first buffer layer 111 and performing a dehydrogenation process and a crystallization process, and the first active layer A1 can be formed by patterning the polysilicon. Here, the first active layer A1 may include a first channel region in which a channel is formed when the first thin-film transistor TR1 is driven, first source regions on both sides of the first channel region, and first drain regions. The first source region means the portion of the first active layer A1 connected to the first source electrode S1, and the first drain region means the portion of the first active layer A1 connected to the first drain electrode D1. For example, the first source region and the first drain region may be formed by ion doping (impurity doping) of the first active layer A1. The first source region and the first drain region may be generated by ion doping of the polysilicon material, while the first channel region may represent the portion of the polysilicon material that is not ion-doped.

[0054] A first gate insulating layer 112a may be disposed on the first active layer A1. The first gate insulating layer 112a may consist of a single layer or multiple layers thereof of silicon nitride (SiNx) or silicon oxide (SiOx). Contact holes may be formed in the first gate insulating layer 112a for connecting the first source electrode S1 and the first drain electrode D1 of the first thin-film transistor TR1 to the first source region and the first drain region of the first active layer A1 of the first thin-film transistor TR1, respectively.

[0055] The first gate electrode G1 of the first thin-film transistor TR1 and the first capacitor electrode C1 of the storage capacitor Cst may be placed on the first gate insulating layer 112a.

[0056] In this case, the first gate electrode G1 and the first capacitor electrode C1 may be formed as a single or multilayer of one of the following materials or an alloy thereof: molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd). The first gate electrode G1 may be formed on the first gate insulating layer 112a so as to overlap with the first channel region of the first active layer A1 of the first thin-film transistor TR1.

[0057] The first capacitor electrode C1 may be omitted based on the driving characteristics of the display device 100, the structure and type of the thin-film transistor, etc. The first gate electrode G1 and the first capacitor electrode C1 can be formed by the same process. Furthermore, the first gate electrode G1 and the first capacitor electrode C1 can be formed from the same material and on the same layer.

[0058] A first interlayer insulating layer 113a may be placed above the first gate insulating layer 112a, the first gate electrode G1, and the first capacitor electrode C1. The first interlayer insulating layer 113a may consist of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). Contact holes may be formed in the first interlayer insulating layer 113a to expose the first source region and the first drain region of the first active layer A1 of the first thin-film transistor TR1.

[0059] A second capacitor electrode C2 of the storage capacitor Cst may be placed on the first interlayer insulating layer 113a. The second capacitor electrode C2 may be formed as a single or multilayer structure made of one of the following materials or an alloy thereof: molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd). The second capacitor electrode C2 may be formed on the first interlayer insulating layer 113a so as to overlap with the first capacitor electrode C1. Alternatively, the second capacitor electrode C2 may be formed from the same material as the first capacitor electrode C1. The second capacitor electrode C2 may be omitted based on the driving characteristics of the display device 100, the structure and type of the thin-film transistor, etc.

[0060] A second buffer layer 114 may be disposed on the first interlayer insulating layer 113a and the second capacitor electrode C2. The second buffer layer 114 may consist of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). Contact holes may be formed in the second buffer layer 114 to expose the first source region and the first drain region of the first active layer A1 of the first thin-film transistor TR1. Contact holes may also be formed in the second buffer layer 114 to expose the second capacitor electrode C2 of the storage capacitor Cst.

[0061] The second buffer layer 114 can be formed in multiple layers, but is not limited to this configuration.

[0062] A second active layer A2 of a second thin-film transistor TR2 may be placed on the second buffer layer 114. Here, the second thin-film transistor TR2 may include a second active layer A2, a second gate insulating layer 112b, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. Here, depending on the design of the pixel circuit, the second source electrode S2 may become the drain electrode, and the second drain electrode D2 may become the source electrode.

[0063] Furthermore, the second active layer A2 may include a second channel region where a channel is formed when the second thin-film transistor TR2 is driven, a second source region on both sides of the second channel region, and a second drain region. The second source region may represent the portion of the second active layer A2 connected to the second source electrode S2, and the second drain region may represent the portion of the second active layer A2 connected to the second drain electrode D2.

[0064] The second active layer A2 may be made of an oxide semiconductor. Oxide semiconductor materials have a larger band gap compared to silicon materials, so electrons cannot cross the band gap in the off state, resulting in a low off-current. Therefore, thin-film transistors including an active layer made of an oxide semiconductor may be suitable for switching thin-film transistors that have a short on-time and maintain a long off-time, but are not limited to this. Depending on the characteristics of the display device 100, they may also be applied to driving thin-film transistors. Furthermore, because the off-current is small, the size of the auxiliary capacitance can be reduced, making them suitable for high-resolution display elements. For example, the second active layer A2 may be made of a metal oxide, and can consist of various metal oxides such as IGZO (indium-gallium-zinc-oxide). Here, we have assumed that the second active layer A2 of the second thin-film transistor TR2 is composed of IGZO from among various metal oxides, but we are not limited to this, and it may be formed of other metal oxides such as IZO (indium-zinc oxide), IGTO (indium-gallium-tin oxide), or IGO (indium-gallium oxide).

[0065] The second active layer A2 can be formed by depositing a metal oxide onto the second buffer layer 114, performing a heat treatment process for stabilization, and then patterning the metal oxide.

[0066] The second gate insulating layer 112b may be distributed across the entire substrate 110, including the second active layer A2. For example, the second gate insulating layer 112b may consist of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx).

[0067] A second gate electrode G2 may be placed on the second gate insulating layer 112b.

[0068] The second gate electrode G2 may be formed as a single or multilayer structure consisting of one of the following materials or an alloy thereof: molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd).

[0069] For example, a metallic material is formed on the second gate insulating layer 112b, a photoresist pattern is formed on the metallic material, and then the metallic material is wet-etched using the photoresist pattern as a mask to form the second gate electrode G2. The wet etching solution used to etch the metallic material may be one that selectively etches molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or their alloys, which constitute the metallic material, without etching the insulating material.

[0070] A second interlayer insulating layer 113b may be placed on the second gate insulating layer 112b and the second gate electrode G2. Contact holes may be formed in the second interlayer insulating layer 113b to expose the first active layer A1 of the first thin-film transistor TR1 and the second active layer A2 of the second thin-film transistor TR2. For example, contact holes may be formed in the second interlayer insulating layer 113b to expose the first source region and the first drain region of the first active layer A1 of the first thin-film transistor TR1. Contact holes may be formed in the second interlayer insulating layer 113b to expose the second source region and the second drain region of the second active layer A2 of the second thin-film transistor TR2.

[0071] The second interlayer insulating layer 113b may consist of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx).

[0072] On the second interlayer insulating layer 113b, a connecting electrode CE, the first source electrode S1 and first drain electrode D1 of the first thin-film transistor TR1, and the second source electrode S2 and second drain electrode D2 of the second thin-film transistor TR2 may be arranged.

[0073] The connecting electrode CE can be electrically connected to the second drain electrode D2 of the second thin-film transistor TR2. Furthermore, the connecting electrode CE can be electrically connected to the second capacitor electrode C2 of the storage capacitor Cst through contact holes formed in the second buffer layer 114 and the second interlayer insulating layer 113b. In other words, the connecting electrode CE can play a role in electrically connecting the second capacitor electrode C2 of the storage capacitor Cst and the second drain electrode D2 of the second thin-film transistor TR2.

[0074] Here, the first source electrode S1 and the first drain electrode D1 of the first thin-film transistor TR1 can be connected to the first active layer A1 of the first thin-film transistor TR1 through contact holes formed in the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, and the second interlayer insulating layer 113b.

[0075] The second source electrode S2 and second drain electrode D2 of the second thin-film transistor TR2 can be connected to the second active layer A2 through contact holes formed in the second interlayer insulating layer 113b.

[0076] The connecting electrode CE, the first source electrode S1 and first drain electrode D1 of the first thin-film transistor TR1, and the second source electrode S2 and second drain electrode D2 of the second thin-film transistor TR2 can be formed from the same material by the same process.

[0077] For example, the connecting electrode CE, the first source electrode S1 and first drain electrode D1 of the first thin-film transistor TR1, and the second source electrode S2 and second drain electrode D2 of the second thin-film transistor TR2 may be formed as a single or multilayer structure of one of the following materials: molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), or an alloy thereof. For example, the connecting electrode CE, the first source electrode S1 and first drain electrode D1 of the first thin-film transistor TR1, and the second source electrode S2 and second drain electrode D2 of the second thin-film transistor TR2 may, but are not limited to, a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti).

[0078] The connecting electrode CE may, but is not limited to, be formed as an integrated unit connected to the second drain electrode D2 of the second thin-film transistor TR2.

[0079] The first planarization layer 115a may be placed on top of the connecting electrode CE, the first source electrode S1 and first drain electrode D1 of the first thin-film transistor TR1, the second source electrode S2 and second drain electrode D2 of the second thin-film transistor TR2, and the second interlayer insulating layer 113b.

[0080] The first planarization layer 115a may be an organic layer for planarizing and protecting the upper surfaces of the first thin-film transistor TR1 and the second thin-film transistor TR2. For example, the first planarization layer 115a may be formed from an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0081] An auxiliary electrode 145 may be placed on the first planarization layer 115a. The auxiliary electrode 145 may be connected to the second drain electrode D2 of the second thin-film transistor TR2 through a contact hole in the first planarization layer 115a. The auxiliary electrode 145 can serve to electrically connect the second thin-film transistor TR2 and the anode 121. The auxiliary electrode 145 may be formed as a single or multilayer of one of the following materials or alloys: molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd). The auxiliary electrode 145 may be formed from the same material as the second source electrode S2 and second drain electrode D2 of the second thin-film transistor TR2.

[0082] A second planarization layer 115b may be placed on top of the auxiliary electrode 145 and the first planarization layer 115a. For example, the second planarization layer 115b may be formed from an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0083] A light-emitting element 120 may be placed on the second planarization layer 115b.

[0084] An anode 121 may be placed on the second planarization layer 115b. In this case, the anode 121 may be electrically connected to the auxiliary electrode 145 through a contact hole provided in the second planarization layer 115b. The anode 121 may be formed of a metallic material.

[0085] If the display device 100 is a top-emission type in which the light emitted by the light-emitting element 120 is emitted onto the top of the substrate 110 on which the light-emitting element 120 is arranged, the anode 121 may further include a transparent conductive layer and a reflective layer on the transparent conductive layer. The transparent conductive layer may be made of a transparent conductive oxide such as ITO or IZO, and the reflective layer may be made of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or alloys thereof.

[0086] Bank 116a may be arranged so as to cover the anode 121. The portion of bank 116a corresponding to the light-emitting region of the subpixel may be open. Part of the anode 121 may be exposed in the open portion of bank 116a (hereinafter referred to as the open region). In this case, bank 116a may be made of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or an organic insulating material such as benzocyclobutene resin, acrylic resin, or imide resin, but is not limited to these. A spacer 116b may be further arranged on bank 116a.

[0087] The light-emitting layer 122 may be positioned in and around the open region of bank 116a. This allows the light-emitting layer 122 to be positioned on the anode 121 exposed through the open region of bank 116a.

[0088] A cathode 123 may be placed on the light-emitting layer 122.

[0089] A light-emitting element 120 can be formed by an anode 121, a light-emitting layer 122, and a cathode 123. The light-emitting layer 122 can contain multiple organic films.

[0090] The sealing layer 117 may be located on the light-emitting element 120 described above.

[0091] The sealing layer 117 may have a single-layer structure or a multilayer structure. For example, the sealing layer 117 may include a first sealing layer 117a, a second sealing layer 117b, and a third sealing layer 117c.

[0092] In this case, the first sealing layer 117a and the third sealing layer 117c may be composed of inorganic films, and the second sealing layer 117b may be composed of an organic film. Among the first sealing layer 117a, the second sealing layer 117b, and the third sealing layer 117c, the second sealing layer 117b is the thickest and can play the role of a planarization layer.

[0093] The first sealing layer 117a is placed on the cathode 123 and may be positioned closest to the light-emitting element 120. The first sealing layer 117a may be formed from an inorganic insulating material that can be deposited at low temperatures. For example, the first sealing layer 117a may be composed of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Since the first sealing layer 117a is deposited in a low-temperature atmosphere, damage to the light-emitting layer 122, which contains organic material that is vulnerable to high-temperature atmospheres, can be prevented during the deposition process.

[0094] The second sealing layer 117b may be formed in a smaller area than the first sealing layer 117a. In this case, the second sealing layer 117b may be formed so as to expose both ends of the first sealing layer 117a. The second sealing layer 117b can serve as a buffer to alleviate stress between layers caused by warping of the flexible display device and to enhance the planarization performance.

[0095] For example, the second sealing layer 117b may be composed of an organic insulating material such as acrylic resin, epoxy resin, polyimide, polyethylene, or silicon oxycarbon (SiOC). For example, the second sealing layer 117b may be formed by an inkjet method, but is not limited thereto.

[0096] The third sealing layer 117c may be formed on top of the substrate 110 on which the second sealing layer 117b is formed, so as to cover the upper and side surfaces of the second sealing layer 117b and the first sealing layer 117a, respectively. In this case, the third sealing layer 117c can minimize or block the penetration of external moisture and oxygen into the first sealing layer 117a and the second sealing layer 117b. For example, the third sealing layer 117c may be made of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0097] A touch-sensing layer may be placed on the sealing layer 117.

[0098] For example, a touch buffer layer 118a may be placed on the third sealing layer 117c, and a touch electrode TE may be placed on the touch buffer layer 118a.

[0099] The touch electrode TE may include a touch sensor metal TS and a bridge metal BM located in different layers from each other. A touch interlayer insulating layer 118b may be placed between the touch sensor metal TS and the bridge metal BM.

[0100] The touch buffer layer 118a and the inter-touch insulating layer 118b may be arranged to eliminate any steps at the location where the touch electrode TE is placed and to ensure good electrical insulation.

[0101] On the other hand, although not shown in the diagram, a polarization layer may be placed on the touch-sensing layer.

[0102] The polarizing layer suppresses the reflection of external light on the display area DA of the substrate 110. When the display device 100 is used outdoors, external natural light may flow in and be reflected by the reflective layer contained in the anode 121 of the light-emitting element 120, or by the metal electrodes located below the light-emitting element 120. The image on the display device 100 may not be visible due to the light reflected in this way. The polarizing layer polarizes the light flowing in from the outside in a specific direction and prevents the reflected light from being emitted outside the display device 100.

[0103] Although not shown in the diagram, a cover glass may be bonded to the polarizing layer by an adhesive layer. The adhesive layer can serve to bond the various components of the display device 100 together and may be formed using, but is not limited to, optically transparent display adhesives such as pressure-sensitive adhesives, optical clear adhesives (OCR), or optical clear resins (OCR).

[0104] The cover glass protects the components of the display device 100 from external impacts and prevents damage such as scratches.

[0105] Figure 3 is a plan view showing an enlarged view of region A, which corresponds to the optical region in Figure 1.

[0106] Referring to Figure 3, the optical area OA has a through-hole TH in the center for the placement of an optical electronic device, where a camera module or sensor may be placed. The optical area OA can include the entire area where the circular or elliptical through-hole TH and the neighboring dam structure 300, connection prevention section 200, etc., are located. The through-hole TH can be removed with a laser in the panel completion step. The non-display area NDA may be located between the through-hole TH and the display area DA, and high-potential power supply wiring PL and gate wiring SL, etc., may be placed there. The connection prevention section 200 and the dam structure 300 may be placed around the through-hole TH. Referring to Figure 3, the connection prevention section 200 may consist of a first prevention section 210 and a second prevention section 220, and the dam structure 300 may consist of a first dam 301 and a second dam 302. The first prevention section 210, the first dam 301, the second prevention section 220 and the second dam 302 may be placed sequentially around the through-hole TH. Generally, the dam structure may aim to maintain the adhesive force between the upper and lower substrates constituting the display panel DP by preventing the second sealing layer 117b, which is part of the sealing layer 117, from sliding down to the end of the outer casing of the display panel DP. The dam structure 300 of the optical region OA may also be formed of multiple structures such as a first dam 301 and a second dam 302 to prevent the second sealing layer 117b of the sealing layer 117 for protecting the light-emitting element 120 from encroaching on or leaking into the optical region OA. The connection prevention section 200 may be formed to prevent the penetration of moisture or oxygen by disrupting the connection of the light-emitting layer 122. Although this specification proposes two dams, it is not limited thereto, and further dams can be arranged depending on the spatial arrangement. Referring to Figure 3, the first prevention section 210 is positioned near the through-hole TH, and thereafter the first dam 301, the second prevention section 220 and the second dam 302 can be positioned in order. The first prevention section 210 and the second prevention section 220 may be positioned to protect the light-emitting element 120 in the display area from moisture or oxygen that may flow in through the through-hole TH. The light-emitting layer 122 of the light-emitting element 120 may be deposited on the front surface of the display panel DP, but may also be uniformly deposited in the optical area OA. Due to the properties of the organic material, the light-emitting layer 122 is highly reactive and propagates easily to moisture and oxygen, and can transfer moisture and oxygen to the light-emitting element 120 in the display area DA.To prevent this, the first and second prevention parts 210 and 220 can be configured to partially interrupt the light-emitting layer 122. Two prevention parts are shown in this specification, but are not limited thereto.

[0107] Although the placement of the optical region OA eliminates the light-emitting elements 120 and pixel circuits in that region, the light-emitting elements 120 and pixel circuits positioned above, below, left, and right of the optical region OA must be electrically connected. For this reason, high-potential power supply wiring PL and gate wiring SL can be arranged in the non-display region NDA adjacent to the optical region OA so as to bypass the through-hole TH and connect them above, below, left, and right.

[0108] Figure 4 is a plan view showing an enlarged view of area B in Figure 3.

[0109] Referring to Figure 4, the first prevention section 210 is positioned near the through-hole TH, the first dam 301 may be positioned between the first prevention section 210 and the second prevention section 220, and the second dam 302 may be positioned to the right of the second prevention section 220. The first prevention section 210 includes the first structure 211, the second structure 212, the third structure 213, and the fourth structure 214, and the second prevention section 220 may include the fifth structure 221, the sixth structure 222, the seventh structure 223, and the eighth structure 224. Referring to Figures 3 and 4, it can be seen that the first prevention section 210, the first dam 301, the second prevention section 220, and the second dam 302 are arranged in a closed loop shape around the through-hole TH. The reason for arranging the first prevention section 210, the first dam 301, the second prevention section 220, and the second dam 302 in a closed loop shape is that if even one opening is made, moisture and oxygen can penetrate the display area DA from the outside, or conversely, the second sealing layer 117b can overflow from the inside into the optical area OA and even into the through-hole TH. Referring to Figure 4, the first prevention section 210 and the second prevention section 220 may each consist of four structures, but are not limited to this. For example, they may consist of three or fewer structures, or five or more structures, but are not limited to this.

[0110] Figure 5 is a cross-sectional view along the V-V' optical region in Figure 4.

[0111] A first prevention section 210 and a second prevention section 220 are arranged in a closed loop around the through-hole TH, a first dam 301 is positioned between the first prevention section 210 and the second prevention section 220, and a second dam 302 may be positioned in a closed loop on the other side of the second prevention section 220. Referring to Figure 5, the through-hole TH may be positioned close to the first prevention section 210.

[0112] The first prevention section 210 may include first to fourth structures 211 to 214, as described with reference to Figure 4. The first to fourth structures 211 to 214 may be formed in a two-tiered structure, upper and lower, to interrupt the light-emitting layer 122, which could become a moisture permeability path from the area where the through-hole TH is located, and an undercut structure may be formed on the side surface of the upper section. Specifically, the upper part of the first to fourth structures 211 to 214 may be arranged to have a trapezoidal cross-section with a positive taper, and the lower part may be arranged to have a rectangular cross-section with a reverse taper or a constant height close to vertical on the side surface, so that a difference in width occurs between the lower surface of the upper section and the upper surface of the lower section, which are the points where the upper and lower sections meet. Since the upper surface of the lower section may be formed to be narrower than the lower surface of the upper section, an undercut structure may be formed in which a part of the lower surface of the upper section is exposed. As a result, the light-emitting layer 122 deposited on the front surface of the display panel DP may be interrupted by the undercut structure on the side surface of the upper part of the first to fourth structures 211 to 214 described above.

[0113] The first to fourth structures 211, 212, 213, and 214 constituting the first prevention section 210 may consist of organic and inorganic materials. For example, the upper parts of each of the first to fourth structures 211, 212, 213, and 214 may, but are not limited to, the same material as the first flattening layer 115a and the second flattening layer 115b. Also, the lower parts of each of the first to fourth structures 211, 212, 213, and 214 may, but are not limited to, the same material as the second interlayer insulating layer 113b.

[0114] The second prevention section 220 may include fifth structures 221 to eighth structures 224. The fifth structures 221 to eighth structures 224 constituting the second prevention section 220 may be formed in a two-tiered structure with an upper and lower section, similar to the first structures 211 to fourth structures 214. The second sealing layer 117b placed on the second prevention section 220 makes it difficult for moisture or oxygen to penetrate the upper part, and an undercut structure can be formed on the upper side surface, similar to the first prevention section 210, to block the penetration paths mainly through the through-hole TH and the side where the first prevention section 210 is located. The arrangement of the first prevention section 210 and the second prevention section 220 makes it possible to prevent moisture or oxygen from penetrating the light-emitting element 120 of the display area DA in the optical area OA through the light-emitting layer 122.

[0115] The fifth to eighth structures 221, 222, 223, and 224 constituting the second prevention section 220 may also consist of organic and inorganic materials. For example, the upper parts of each of the fifth to eighth structures 221, 222, 223, and 224 may be made of the same material as the first flattening layer 115a and the second flattening layer 115b, but are not limited to this. The lower parts of each of the fifth to eighth structures 221, 222, 223, and 224 may be made of the same material as the second interlayer insulating layer 113b, but are not limited to this.

[0116] As shown in Figure 5, the first dam 301 and the second dam 302 can be formed by stacking the second flattening layer 115b, the bank 116a, and the spacer 116b, but are not limited thereto, and may further include the first flattening layer 115a or other layers.

[0117] Referring to Figure 3, the optical region OA may vary depending on the size of the camera applied to the product. Although the region is shown as an empty space, insulating films or wiring structures may be placed in part of it. However, since this is a dummy region that will not remain in the finished product when the through-hole TH is removed by laser, separate representation is omitted. The laser may be irradiated in a circular or elliptical shape along the shape of the optical region OA, and the entire upper region of the substrate, including the substrate 110, may be removed through laser irradiation. There may be a difference between the actual optical region OA and the laser irradiation region. For example, the laser irradiation region in the optical region OA may be a region approximately 100 μm deeper inside. Only when there is such a difference between the laser irradiation region and the optical region OA can the insulating layer of the optical region OA not be damaged during laser irradiation. The laser can be a picosecond laser or a femtosecond laser, but is not limited to these. Lasers utilize stimulated emission by amplifying the light generated when energy is applied to a specific material. They possess characteristics similar to radio waves, are monochromatic and directional, and are used in communications, medical, and industrial applications. Lasers allow for the formation of patterns in desired areas or the easy removal of specific areas. Lasers use energy to form or remove patterns; when laser energy is directed at a material, the thermal energy melts the material, forming a pattern. The longer the laser is applied, the greater the potential for thermal effects to occur, where heat is transferred to the surrounding areas of the patterned region. This thermal effect can cause heat to accumulate around the laser-irradiated area of ​​the material, potentially burning or deforming areas larger than the set pattern. Due to these characteristics of lasers, if the laser-irradiated area overlaps with or is adjacent to an insulating film, the laser's thermal energy can also deform the film. This deformation of the insulating film can cause cracks, which can propagate through the film, leading to delamination or the penetration of moisture and oxygen.For example, to prevent deformation or peeling of insulating films such as the multi-buffer layer 111a, active buffer layer 111b, first gate insulating layer 112a, first interlayer insulating layer 113a, second buffer layer 114, second gate insulating layer 112b, and second interlayer insulating layer 113b, the entire insulating film can be removed at a distance of approximately 100 μm from the laser irradiation position.

[0118] Cracks generated when the substrate 110 is cut by a laser pose a problem because they can be propagated through the inorganic insulating layer. While moisture or oxygen is characterized by being propagated by reacting with the light-emitting layer 122 of the light-emitting element 120, cracks can be propagated through the rigid, inflexible inorganic insulating layer. Alternatively, cracks may occur in through-holes TH formed by the laser due to interference during the assembly of a camera or sensor. Cracks generated at this time can also be propagated through the inorganic insulating layer. If cracks generated in through-holes TH are propagated through the inorganic insulating layer, line defects or GDS (growing dark spot) defects may occur.

[0119] Therefore, in the display device 100 according to one embodiment of this specification, by arranging the first trench T1 in a part of the plurality of insulating layers arranged in the optical region OA, a stepped structure can be formed in the plurality of insulating layers, thereby blocking the crack propagation path.

[0120] Figure 6a is a cross-sectional view showing an enlarged view of area C in Figure 5 according to one embodiment of this specification.

[0121] Referring to Figures 5 and 6a, according to one embodiment of this specification, a first trench T1 may be included, which is located in part of a plurality of insulating layers that overlap with at least one coupling prevention portion 200 in the optical region OA. For example, the plurality of insulating layers may be at least one of a first buffer layer 111, a first gate insulating layer 112a, a first interlayer insulating layer 113a, a second buffer layer 114, a second gate insulating layer 112b, and a second interlayer insulating layer 113b, which are located on the substrate 110, and the first trench T1 may be located in part of the insulating layers located at the top of the plurality of insulating layers.

[0122] Specifically, referring to both Figure 3 and Figure 6a, the optical region OA may include a first trench T1 in which at least a portion of the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b is etched, superimposed on a plurality of insulating layers.

[0123] The first trench T1 can create a stepped structure in multiple insulating layers, thereby preventing crack propagation even if a crack occurs in the through hole TH, because the inorganic insulating layer through which the crack propagates in the region where the first trench T1 is formed is removed.

[0124] Furthermore, according to one embodiment of this specification, the first trench T1 can be filled by placing at least one of the first planarization layer 115a or the second planarization layer 115b within the first trench T1.

[0125] According to one embodiment of this specification, a portion of multiple inorganic insulating layers through which cracks propagate is removed to form a first trench T1, and the first trench T1 is filled with an organic material. In this way, if a crack occurs in a through hole TH, the crack does not need to propagate further within the first trench T1.

[0126] Figures 5 and 6a show the first trench located in the optical region OA, but the first trench in the optical region OA according to one embodiment of this specification is not limited thereto.

[0127] Figure 6b is a cross-sectional view of a display device according to another embodiment of this specification. Figure 6c is a cross-sectional view of a display device according to yet another embodiment of this specification. Figure 6d is a cross-sectional view of a display device according to yet another embodiment of this specification. Figure 6e is a cross-sectional view of a display device according to yet another embodiment of this specification.

[0128] Other embodiments of the Specified Display Device 1000, as shown in Figure 6b, may further include a second trench T2 located in a portion of a plurality of insulating layers located in a dam structure 300, which is located in the optical region OA, along with a first trench T1 superimposed on at least one coupling prevention portion 200 located in the optical region OA.

[0129] Specifically, as shown in Figure 6b, the optical region OA may include a first trench T1 in which at least a portion of the first gate insulating layer 112a, first interlayer insulating layer 113a, second buffer layer 114, second gate insulating layer 112b, and second interlayer insulating layer 113b are etched, superimposed on at least one linkage prevention portion 200, and a second trench T2 in which at least a portion of the first gate insulating layer 112a, first interlayer insulating layer 113a, second buffer layer 114, second gate insulating layer 112b, and second interlayer insulating layer 113b are etched, superimposed on the dam structure 300.

[0130] Therefore, in the display device 1000 according to another embodiment of this specification, by arranging the first trench T1 and the second trench T2 in the optical region OA, even if a crack occurs when forming the through-hole TH in the optical region OA or when assembling the optical electronic device in the through-hole TH, the first trench T1 and the second trench T2 block the crack propagation path, thereby preventing defects due to crack propagation.

[0131] For example, after forming multiple insulating layers, the depth of the first trench T1 and the second trench T2, which are placed in a portion of the multiple insulating layers, can be adjusted using a masking process. In this case, the first trench T1 and the second trench T2 can be formed by the same masking process.

[0132] The depths of the first trench T1 and the second trench T2 can be adjusted as needed by changing the conditions of the masking process.

[0133] Figure 6c is a cross-sectional view of a display device according to another embodiment of this specification.

[0134] As shown in Figure 6c, in the display device 1100 according to another embodiment of this specification, the first trench T1 and the second trench T2 are superimposed on at least one coupling prevention portion 200 and dam structure 300, and can be arranged in at least a portion of the gate metal GM, first interlayer insulating layer 113a, second buffer layer 114, second gate insulating layer 112b and second interlayer insulating layer 113b, which are arranged in the same layer as the gate electrode G1 of the first thin-film transistor.

[0135] Figure 6d is a cross-sectional view of a display device according to yet another embodiment of this specification. Figure 6e is a cross-sectional view of a display device according to yet another embodiment of this specification.

[0136] As shown in Figure 6d, in the display device 1200 according to another embodiment of this specification, the first trench T1 and the second trench T2 are superimposed on at least one connection prevention portion 200 and dam structure 300, and can be arranged on at least a portion of the light-shielding layer 125, the first buffer layer 111, the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b.

[0137] Figure 6e is a cross-sectional view of a display device according to another embodiment of this specification.

[0138] As shown in Figure 6e, in the display device 1300 according to another embodiment of this specification, the first trench T1 and the second trench T2 are superimposed on at least one connection prevention portion 200 and dam structure 300, and can be arranged in at least a portion of the first buffer layer 111, the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b.

[0139] According to another embodiment of this specification, by arranging a first trench T1 and a second trench T2 in the optical region OA, even if a crack occurs during the formation of a through-hole TH in the optical region OA or during the assembly of an optical electronic device in the through-hole TH, the first trench T1 and the second trench T2 block the crack propagation path, thereby preventing defects caused by crack propagation.

[0140] Furthermore, according to another embodiment of this specification, the first trench T1 and the second trench T2 are arranged so as to overlap with at least one linkage prevention section 200 and a dam structure 300 in the optical region OA, thereby eliminating the need for a separate space for crack propagation prevention and minimizing the non-display area (NDA) adjacent to the optical region OA.

[0141] In the following, Figure 7 will be used together with the present invention for a more detailed explanation of the optical region OA of a display device according to another embodiment of this specification.

[0142] Figure 7a is a cross-sectional view of a display device according to yet another embodiment of this specification. Figure 7b is a cross-sectional view of a display device according to yet another embodiment of this specification. Figure 7c is a cross-sectional view of a display device according to yet another embodiment of this specification. Figure 7d is a cross-sectional view of a display device according to yet another embodiment of this specification. The cross-sectional views of Figures 7a to 7d are substantially identical to the cross-sectional views of Figures 6a to 6e, except for the first and second metal layers. Therefore, for the sake of convenience, redundant explanations excluding the first and second metal layers will be omitted.

[0143] In another embodiment of the present specification, the display device 1400 may further include a first metal layer 410 disposed along the surface of some of the insulating layers among a plurality of insulating layers in the first trench T1 and the second trench T2, respectively.

[0144] For example, the first metal layer 410 may be arranged so as to be in contact with the surfaces of multiple insulating layers in the first trench T1 and the second trench T2, respectively.

[0145] As shown in Figure 7a, a first metal layer 410 may be positioned inside the first trench T1 and the second trench T2, in contact with the surfaces of multiple insulating layers. For example, the first metal layer 410 may be made of the same material as the first source electrode S1 and the first drain electrode D1 of the first thin-film transistor TR1.

[0146] In another embodiment of the display device 1400 described herein, the step structure of multiple insulating layers formed by the first trench T1 and the second trench T2 blocks the propagation path of cracks, and the first metal layer 410, which is arranged inside the first trench T1 and the second trench T2 so as to be in contact with the surfaces of the multiple insulating layers, further blocks the propagation of cracks. Therefore, even if a crack occurs when a through-hole TH is formed in the optical region OA or when an optical electronic device is assembled in the through-hole TH, the first trench T1, the second trench T2 and the first metal layer 410 completely block the propagation path of the crack, thereby preventing defects caused by crack propagation.

[0147] Figure 7a shows the structure of the first metal layer 410 arranged along the surface of some of the insulating layers among the multiple insulating layers in the first trench T1 and the second trench T2 of the optical region OA, respectively, but the structure of the optical region OA according to one embodiment of this specification is not limited thereto.

[0148] Figure 7b is a cross-sectional view of a display device according to another embodiment of this specification.

[0149] In another embodiment of this specification, the display device 1500 may further include a second metal layer 520 disposed beneath the first trench T1 and the second trench T2 of the optical region OA, respectively.

[0150] For example, as shown in Figure 7b, the first metal layer 510 is in contact with the sides of some of the insulating layers among the multiple insulating layers in the first trench T1 and the second trench T2, respectively, and the first metal layer 510 and the second metal layer 520 may be in contact with each other. For example, the first metal layer 510 may be located in the same layer as the first source electrode S1 and the first drain electrode D1 and made of the same material, and the second metal layer 520 may be located in the same layer as the first gate electrode G1 and made of the same material.

[0151] In another embodiment of the display device 1500 described herein, the step structure of multiple insulating layers formed by the first trench T1 and the second trench T2 blocks the crack propagation path, and the first metal layer 510 and the second metal layer 520, respectively, are placed inside and below the first trench T1 and the second trench T2, respectively, further blocking the crack propagation path. Even if a crack occurs when forming the through-hole TH of the optical region OA or when assembling the through-hole TH with an optical electronic device, the crack propagation path is completely blocked by the first trench T1, the second trench T2, the first metal layer 510, and the second metal layer 520, preventing defects due to crack propagation.

[0152] According to other embodiments of this specification, the depths of the first trench T1 and the second trench T2, which are located in a portion of the plurality of insulating layers, can be adjusted, and in this case, the materials forming the first metal layer 510 and the second metal layer 520 can be different depending on the depths of the first trench T1 and the second trench T2.

[0153] Figure 7c is a cross-sectional view of a display device according to another embodiment of this specification. As shown in Figure 7c, in the display device 1600 according to another embodiment of this specification, the first metal layer 610 may be made of the same material as the first source electrode S1 and the first drain electrode D1, and the second metal layer 620 may be made of the same material as the light-shielding layer 125.

[0154] Figure 7d is a cross-sectional view of a display device according to another embodiment of this specification. As shown in Figure 7d, in the display device 1700 according to another embodiment of this specification, the second metal layer 720 may be arranged so as to be in contact with the surfaces of a plurality of insulating layers in the first trench T1 and the second trench T2, respectively, and the first metal layer 710 may be arranged so as to be in contact with the surface of the second metal layer 720 in the first trench T1 and the second trench T2, respectively. For example, the first metal layer 710 may be located in the same layer as the second source electrode S2 and the second drain electrode D2 and made of the same material, and the second metal layer 720 may be located in the same layer as the first source electrode S1 and the first drain electrode D1 and made of the same material.

[0155] According to another embodiment of this specification, by arranging the first trench T1 and the second trench T2 in the optical region OA, even if a crack occurs during the formation of the through-hole TH in the optical region OA or during the assembly of the optical electronic device in the through-hole TH, the first trench T1 and the second trench T2 block the crack propagation path, thereby preventing defects due to crack propagation. Furthermore, by arranging the first trench T1 and the second trench T2 to overlap with at least one connection prevention section 200 and dam structure 300 in the optical region OA, a separate space for crack propagation prevention is not required, thus minimizing the non-display area (NDA) adjacent to the optical region OA.

[0156] Furthermore, according to other embodiments of this specification, by arranging the first metal layers 410, 510, 610, and 710 within the first trench T1 and the second trench T2, and arranging the second metal layers 420, 520, 620, and 720 in contact with the first metal layers 410, 510, 610, and 710, crack propagation is further blocked. Even if a crack occurs during the formation of the through-hole TH in the optical region OA or during the assembly of the through-hole TH in the optical electronic device, the crack propagation path is completely blocked by the first trench T1, the second trench T2, the first metal layers 410, 510, 610, and 710, and the second metal layers 420, 520, 620, and 720, defects due to crack propagation can be prevented.

[0157] Embodiments of the present invention can also be described as follows.

[0158] According to an aspect of the present invention, the present invention includes a substrate including a display area, an optical area disposed within the display area and including a through-hole, and a non-display area surrounding the display area, a plurality of insulating layers disposed on the substrate, at least one dam disposed on the plurality of insulating layers, and at least one coupling prevention portion disposed on the plurality of insulating layers and positioned closer to the through-hole than at least one dam, wherein the first trench is disposed in a portion of the plurality of insulating layers that overlap with at least one coupling prevention portion in the optical area. According to other features of this specification, the plurality of insulating layers include at least one of a first buffer layer, a first gate insulating layer, a first interlayer insulating layer, a second buffer layer, a second gate insulating layer, and a second interlayer insulating layer disposed on the substrate, and the first trench may be disposed in a portion of the insulating layers that are positioned on the upper part of the plurality of insulating layers.

[0159] According to other features of this specification, a second trench may be further provided, which is located in part of a plurality of insulating layers superimposed on at least one dam in the optical region.

[0160] According to other features of this specification, a first metal layer may be further provided, which is positioned along the surface of some of the insulating layers among a plurality of insulating layers in each of the first and second trenches.

[0161] According to other features of this specification, the first metal layer may be arranged so as to be in contact with the surfaces of multiple insulating layers in the first trench and the second trench, respectively.

[0162] According to other features of this specification, the invention may further include a first thin-film transistor disposed on a substrate of a display area and comprising a first active layer, a first gate electrode, a first source electrode, and a first drain electrode; at least one insulating layer disposed on the first gate electrode; and a second thin-film transistor disposed on the insulating layer and comprising a second active layer, a second gate electrode, a second source electrode, and a second drain electrode.

[0163] According to other features of this specification, the first metal layer may be composed of the same material as the first source electrode and the first drain electrode.

[0164] According to other features of this specification, a second metal layer may be further provided, which is located beneath the first trench and the second trench, respectively.

[0165] According to other features of this specification, the first metal layer is in contact with the sides of some of the insulating layers among the plurality of insulating layers in the first trench and the second trench, respectively, and the first metal layer and the second metal layer may be in contact with each other.

[0166] According to other features of this specification, the first metal layer may be located in the same layer as the first source electrode and the first drain electrode and be made of the same material, and the second metal layer may be located in the same layer as the first gate electrode and be made of the same material.

[0167] According to other features of this specification, the device further includes a light-shielding layer disposed beneath the first active layer so as to overlap with the first gate electrode, wherein the first metal layer is made of the same material as the first source electrode and the first drain electrode, and the second metal layer is made of the same material as the light-shielding layer.

[0168] According to other features of this specification, the second metal layer may be arranged in contact with the surfaces of multiple insulating layers in the first trench and the second trench, respectively, and the first metal layer may be arranged in contact with the surface of the second metal layer in the first trench and the second trench, respectively.

[0169] According to other features of this specification, the first metal layer may be located in the same layer as the second source electrode and the second drain electrode and be made of the same material, and the second metal layer may be located in the same layer as the first source electrode and the first drain electrode and be made of the same material.

[0170] According to other features of this specification, the invention may further include optical electronic devices arranged in conjunction with the optical region.

[0171] Although embodiments of this specification have been described in more detail above with reference to the attached drawings, this specification is not necessarily limited to these embodiments and can be modified and implemented in various ways without deviating from the technical concept of this specification. Therefore, the embodiments disclosed herein are for illustrative purposes only, not to limit the technical concept of this specification, and the scope of the technical concept of this specification is not limited by such embodiments. Accordingly, the embodiments described above should be understood to be illustrative and non-limiting in all respects. All technical concepts within the scope equivalent to the claims of this specification should be construed as being included in the scope of rights of this specification.

Claims

1. A substrate including a display area, an optical area disposed within the display area and including a through-hole, and a non-display area surrounding the display area. Multiple insulating layers arranged on the substrate, At least one dam disposed on the plurality of insulating layers, and It includes at least one connection prevention portion disposed on the plurality of insulating layers and positioned closer to the through hole than at least one dam, A display device in which a first trench is disposed in a portion of the plurality of insulating layers that overlap with at least one coupling prevention portion in the optical region.

2. The plurality of insulating layers include at least one of the first buffer layer, first gate insulating layer, first interlayer insulating layer, second buffer layer, second gate insulating layer, and second interlayer insulating layer arranged on the substrate. The display device according to claim 1, wherein the first trench is located in some of the insulating layers that are located in the upper part of the plurality of insulating layers.

3. The display device according to claim 1, further comprising a second trench disposed in a portion of the plurality of insulating layers superimposed on the at least one dam in the optical region.

4. A first thin-film transistor, which is arranged on the substrate in the display area and includes a first active layer, a first electrode, a first source electrode, and a first drain electrode, At least one insulating layer disposed on the first gate electrode, A second thin-film transistor, disposed on at least one insulating layer, comprising a second active layer, a second gate electrode, a second source electrode, and a second drain electrode, A first planarization layer disposed on the first source electrode and the first drain electrode of the first thin-film transistor, and on the second source electrode and the second drain electrode of the second thin-film transistor, and The invention further includes a second flattening layer disposed on the first flattening layer, The display device according to claim 2, wherein at least one of the first planarization layer and the second planarization layer is disposed within the first trench to fill the first trench.

5. The display device according to claim 3, further comprising a first metal layer disposed along the surface of some of the insulating layers among the plurality of insulating layers in each of the first trench and the second trench.

6. The display device according to claim 5, wherein the first metal layer is arranged in contact with the surfaces of the plurality of insulating layers in the first trench and the second trench, respectively.

7. A first thin-film transistor, which is arranged on the substrate in the display area and includes a first active layer, a first electrode, a first source electrode, and a first drain electrode, At least one insulating layer disposed on the first gate electrode, and The display device according to claim 6, further comprising a second thin-film transistor disposed on at least one insulating layer, the second active layer, the second gate electrode, the second source electrode, and the second drain electrode.

8. The display device according to claim 7, wherein the first metal layer is made of the same material as the first source electrode and the first drain electrode.

9. The display device according to claim 7, further comprising a second metal layer disposed beneath the first trench and the second trench, respectively.

10. The first metal layer is in contact with the side surfaces of some of the insulating layers among the plurality of insulating layers in the first trench and the second trench, The display device according to claim 9, wherein the first metal layer and the second metal layer are in contact with each other.

11. The first metal layer is located in the same layer as the first source electrode and the first drain electrode, and is made of the same material. The display device according to claim 10, wherein the second metal layer is arranged in the same layer as the first gate electrode and is made of the same material.

12. The present invention further includes a light-shielding layer disposed below the first active layer so as to overlap with the first gate electrode, The first metal layer is made of the same material as the first source electrode and the first drain electrode. The display device according to claim 10, wherein the second metal layer is made of the same material as the light-shielding layer.

13. The second metal layer is arranged so as to be in contact with the surfaces of the plurality of insulating layers in the first trench and the second trench, respectively. The display device according to claim 10, wherein the first metal layer is arranged in contact with the surface of the second metal layer in the first trench and the second trench, respectively.

14. The first metal layer is located in the same layer as the second source electrode and the second drain electrode, and is made of the same material. The display device according to claim 13, wherein the second metal layer is arranged in the same layer as the first source electrode and the first drain electrode and is made of the same material.

15. The display device according to claim 1, further comprising an optical electronic device arranged in superimposed on the optical region.

16. The display device according to claim 15, wherein the through-hole is formed to correspond to the optical electronic device.

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