Multi-junction polarization-controlled vertical cavity surface-emitting laser and its fabrication method

Abstract

To provide a multi-junction polarization-controlled vertical cavity surface-emitting laser and a method for fabricating the same. [Solution] A vertical-cavity surface-emitting laser (VCSEL) is disclosed, comprising a semiconductor substrate, a lower distributed Bragg reflector (DBR), a semiconductor active region including at least one active sub-region, and an upper DBR, arranged from the bottom to the top of the VCSEL, and a method for fabricating or forming the VCSEL. A dielectric layer may be included between the lower DBR and the semiconductor active region including at least one active sub-region, or the semiconductor active region may include two active sub-regions without a dielectric layer between the lower DBR and the semiconductor active region. The VCSEL may further include a grating structure.

Description

Technical Field

[0001] The present disclosure relates to vertical-cavity surface-emitting lasers (VCSELs), and more particularly to methods for fabricating VCSELs.

Background Art

[0002] In connection with VCSELs, it is continuously desired to improve wafer bonding yield, stability, thermal conductivity to the substrate, and the efficiency of VCSELs for converting electrical input power, also known as "slope", into optical output power, and to control the emission polarization of VCSELs.

Summary of the Invention

Problems to be Solved by the Invention

[0003]

Means for Solving the Problems

[0004] Disclosed herein are VCSELs, such as IR VCSELs, by wafer bonding using an optional low-refractive-index material between a first and a second semiconductor wafer, where the second semiconductor wafer includes one or more active regions and the first semiconductor wafer includes a first distributed Bragg reflector (DBR), and methods of fabricating the same, where multi-junction and current confinement structures are formed either before or after fusing the two wafers.

[0005] Further, disclosed is VCSEL emission polarization control by forming a polarization control structure (1) on or within a layer of a second DBR or a semiconductor layer adjacent to the second DBR, or (2) on a layer of the first semiconductor wafer at or adjacent to the wafer bonding interface of the first and second semiconductor wafers. In one example, each polarization control structure can include a grating structure.

[0006] Wafer bonding: More specifically, the fabrication of a VCSEL by wafer fusion using an optional low refractive index dielectric layer (hereinafter sometimes referred to as the "dielectric layer") disposed between the first and second wafers, between a second semiconductor wafer containing a second stack of semiconductor layers containing one or more active regions and a first semiconductor wafer containing a first stack of semiconductor layers containing a first DBR. In this disclosure, each instance of the "dielectric layer" should be understood and interpreted as "optional," that is, "optional dielectric layer." In other words, each instance of the "dielectric layer" in this disclosure should be understood and interpreted as being preceded by the word "optional."

[0007] In this disclosure, the dielectric layer can satisfy the requirement of an optical thickness of λx / 4, i.e., the dielectric layer can have a thickness of λx / 4, where x is an odd number, e.g., 1, 3, 5, etc., and λ is the wavelength of an optical signal, e.g., IR light, produced by a VCSEL. The dielectric layer may be formed as a continuous layer on either the first or second semiconductor wafer, so that after wafer fusion of the first and second semiconductor wafers, the dielectric layer can be positioned between the first and second semiconductor wafers. Alternatively, the dielectric layer may be formed by depositing a portion of the dielectric layer on both the first and second semiconductor wafers, so that after wafer fusion at the interface of the portions of the dielectric layer deposited on both the first and second semiconductor wafers, the dielectric layer has a thickness of λx / 4, where x is an odd number and λ is the wavelength of an optical signal produced by a VCSEL.

[0008] Wafer fusion using a dielectric layer with a thickness of λx / 4 between first and second semiconductor wafers can solve the problem that the first DBR for a VCSEL requires a large number of semiconductor DBR layers. To achieve this objective, it is assumed that the same first DBR reflectivity can be achieved with fewer semiconductor DBR layer pairs compared to wafer fusion without a λx / 4 thickness dielectric layer between the first and second semiconductor wafers. By reducing the number of semiconductor DBR layer pairs, the warpage of the fabricated VCSEL can be reduced, wafer fusion yield and wafer fusion stability can be improved, and the thermal conductivity through the first and second DBRs and the substrate of the first semiconductor wafer can be improved.

[0009] Increased slope: The slope of a VCSEL formed by fusion bonding of first and second semiconductor wafers using a dielectric layer between them can be further improved, for example, by the second semiconductor wafer containing one or preferably more semiconductor active regions, which can be doubled. In one example, each semiconductor active region includes a pair of resonator regions separated from each other by a tunnel junction layer or a quantum well layer located on one side of the layer, thereby enabling the flow of current between the upper and lower electrical contacts of the VCSEL. In another example, each semiconductor active region includes a pair of resonator regions separated from each other by a quantum well layer or a tunnel junction layer located on one side of the layer, thereby enabling the flow of current between the upper and lower electrical contacts of the VCSEL.

[0010] In this disclosure, for the sake of brevity, the locations of the upper and lower electrical contacts of each disclosed VCSEL are not specifically described or shown in the figures. However, those skilled in the art will understand that each disclosed VCSEL includes upper and lower electrical contacts for applying an electrical bias to the VCSEL for its operation and will understand where such upper and lower electrical contacts should be located.

[0011] In this disclosure, current confinement can be improved by adding an additional (or topmost) resonator layer to the second semiconductor wafer above the highest semiconductor active region of the second semiconductor wafer before fusing with the first semiconductor wafer.

[0012] After the fusion of the first and second semiconductor wafers, the substrate of the second semiconductor wafer can be selectively removed. For example, it has been observed that the fusion yield is significantly improved by forming a current confinement structure before or after the fusion of the first and second semiconductor wafers, with or without a dielectric layer between them, by oxidation (to form oxide openings), ion implantation, or structuring and overgrowth, and by removing the substrate of the second semiconductor wafer. To achieve this objective, the surfaces of the first and second semiconductor wafers fused together, with or without a dielectric layer between them, are not exposed to fabrication steps that may introduce one or more surface contaminants, such as photoresist (necessary for ion implantation), and their morphology is not altered by structuring and overgrowth. Surface contaminants and non-planar or rough surface shapes severely limit wafer fusion yield and stability.

[0013] Light polarization control: Regardless of the presence or absence of a dielectric layer between the first and second semiconductor wafers, the first and second semiconductor wafers can be fused together, and after removing the substrate from the second semiconductor wafer, a second DBR of the VCSEL can be added in place of the removed substrate from the second semiconductor wafer. The second DBR can be fabricated from a low-absorption dielectric layer. In one example, the second DBR may include a grating structure or layer as a polarization control structure for controlling the optical polarization of the VCSEL. In one example, this grating structure or layer can be formed between a pair of layers of the second DBR. In another example, this grating structure can be formed on the top or bottom layer of the second DBR. In one example, each line of the grating structure or layer may have a grating height h (see Figure 5) between zero and a quarter wavelength.

[0014] In another example, polarization control may be performed, or alternatively, at the fusion interface of the first and second semiconductor wafers. In one example, a grating structure or layer as a polarization control structure for controlling the optical polarization of a VCSEL may be formed of the material forming the dielectric layer of the first semiconductor substrate. In one example, this grating structure can be formed on the dielectric layer of the first semiconductor substrate before fusion with the second semiconductor wafer. In another example, this grating structure can be formed on the top resonator layer of the second semiconductor substrate before fusion with the first semiconductor wafer. In one example, each line of the grating structure or layer may have a grating height h (see Figure 6) between zero and a quarter wavelength. In one example, this grating structure or layer at the fusion interface of the first and second semiconductor wafers may be formed before fusion of the first and second semiconductor wafers.

[0015] In this specification, (a) forming or preparing a first semiconductor wafer including a first semiconductor substrate and a lower distributed Bragg reflector (DBR) from bottom to top of a first semiconductor wafer; and (b) forming or preparing a second semiconductor wafer including a second semiconductor substrate, a semiconductor active region including at least one active sub-region, and an upper resonator layer on the opposite side of the second semiconductor substrate to at least one active sub-region, wherein each active sub-region comprises a pair of resonator layers separated by a tunnel junction layer, and a quantum well layer on the opposite side of the second semiconductor substrate to the pair of resonator layers, or a quantum well layer A method for fabricating a vertical cavity surface-emitting laser (VCSEL) is disclosed, comprising the steps of: (c) coupling a lower DBR and a semiconductor active region using a second semiconductor substrate located on the semiconductor active region opposite to the lower DBR, and then removing the second semiconductor substrate; (d) forming an upper DBR on the semiconductor active region opposite to the lower DBR after removal of the second semiconductor substrate; and (e) forming a current confinement structure in all or part of at least one active sub-region of the semiconductor active region.

[0016] In this method, step (b) may include a semiconductor active region comprising two active subregions, or step (c) may include coupling the lower DBR and the semiconductor active region using a dielectric layer between them.

[0017] Furthermore, a vertical-cavity surface-emitting laser (VCSEL) is disclosed, comprising a semiconductor substrate, a lower distributed Bragg reflector (DBR), a semiconductor active region including at least one active sub-region, and an upper DBR, extending from the lower to the upper part of the VCSEL.

[0018] The VCSEL may further include one of the following: a dielectric layer between the lower DBR and the semiconductor active region, or a semiconductor active region containing two active sub-regions.

Brief Description of the Drawings

[0019] [Figure 1A] Schematic cross-sectional views of exemplary first and second semiconductor wafers that can be fused together to form a first exemplary VCSEL according to the principles of the present disclosure.

[0020] [Figure 1B] Schematic cross-sectional views of different exemplary semiconductor active regions that can include the second semiconductor wafer shown in FIG. 1A. [Figure 1C] Schematic cross-sectional views of different exemplary semiconductor active regions that can include the second semiconductor wafer shown in FIG. 1A. [Figure 1D] Schematic cross-sectional views of different exemplary semiconductor active regions that can include the second semiconductor wafer shown in FIG. 1A. [Figure 1E] Schematic cross-sectional views of different exemplary semiconductor active regions that can include the second semiconductor wafer shown in FIG. 1A. [Figure 1F] Schematic cross-sectional views of different exemplary semiconductor active regions that can include the second semiconductor wafer shown in FIG. 1A. [Figure 1G] Schematic cross-sectional views of different exemplary semiconductor active regions that can include the second semiconductor wafer shown in FIG. 1A.

[0021] [Figure 2] Schematic cross-sectional views of the assembled first and second semiconductor wafers shown in FIG. 1A, including further fabrication steps for forming different versions of the first exemplary VCSEL according to the principles of the present disclosure. [Figure 3] Schematic cross-sectional views of the assembled first and second semiconductor wafers shown in FIG. 1A, including further fabrication steps for forming different versions of the first exemplary VCSEL according to the principles of the present disclosure. [Figure 4A]Schematic cross-sectional views of the assembled first and second semiconductor wafers shown in FIG. 1A, including further fabrication steps for forming different versions of a first exemplary VCSEL according to the principles of the present disclosure. [Figure 4B] Schematic cross-sectional views of the assembled first and second semiconductor wafers shown in FIG. 1A, including further fabrication steps for forming different versions of a first exemplary VCSEL according to the principles of the present disclosure. [Figure 4C] Schematic cross-sectional views of the assembled first and second semiconductor wafers shown in FIG. 1A, including further fabrication steps for forming different versions of a first exemplary VCSEL according to the principles of the present disclosure. [Figure 4D] Schematic cross-sectional views of the assembled first and second semiconductor wafers shown in FIG. 1A, including further fabrication steps for forming different versions of a first exemplary VCSEL according to the principles of the present disclosure. [Figure 5] Schematic cross-sectional views of the assembled first and second semiconductor wafers shown in FIG. 1A, including further fabrication steps for forming different versions of a first exemplary VCSEL according to the principles of the present disclosure.

[0022] [Figure 6] Schematic cross-sectional views of exemplary first and second semiconductor wafers that can be fused together to form a second exemplary VCSEL according to the principles of the present disclosure.

[0023] [Figure 7] Schematic cross-sectional views of the assembled first and second semiconductor wafers shown in FIG. 6, including further fabrication steps for forming a second exemplary VCSEL according to the principles of the present disclosure.

[0024] [Figure 8] A separate cross-sectional view of another exemplary dielectric layer that can be used in place of the dielectric layers shown in FIGS. 1-7 and that includes voids, cavities, or pockets that do not contain material within the body of the dielectric layer. [Modes for carrying out the invention]

[0025] Spatial or directional terms used herein, such as “left,” “right,” “inside,” “outside,” “up,” and “down,” are related to the disclosure as shown in the depicted figures. However, it should be understood that the disclosure may assume various alternative orientations, and therefore such terms should not be considered limiting. Furthermore, when used herein, all figures representing dimensions, physical properties, processing parameters, amounts of components, reaction conditions, etc., used herein and in the claims should be understood in all cases as being modified by the term “approximately” or “about.” Therefore, unless otherwise indicated, the figures described herein and in the claims may vary depending on the desired properties to be obtained by the disclosure.

[0026] At a minimum, each numerical value should be interpreted, at least in light of the number of significant figures reported and by applying ordinary rounding techniques, not as an attempt to limit the application of the principle of equivalents to the scope of the claims. Furthermore, all ranges disclosed herein should be understood to encompass the initial range value and the final range value and all subranges contained therein. For example, a defined range of "1 to 10" should be considered to include all subranges between the minimum value of 1 and the maximum value of 10 (and including the minimum and maximum values), i.e., all subranges starting with a minimum value of 1 or greater and ending with a maximum value of 10 or less, e.g., 1 to 3.3, 4.7 to 7.5, 5.5 to 10, etc. "a" or "an" refers to one or more.

[0027] As used herein, “coupled,” “coupling,” and similar terms refer to two or more elements being joined, connected, fixed, linked, communicating, or otherwise associated with one another (e.g., mechanically, electrically, fluidly, optically, or electromagnetically). In various examples, elements may be associated directly or indirectly. For example, element A may be directly associated with element B. In another example, element A may be indirectly associated with element B, for example, via another element C. It will be understood that not all relationships between the various disclosed elements are necessarily represented. Therefore, other couplings may exist besides those shown in the figures.

[0028] As used herein, the phrase “at least one of” means, when used with a list of items, that one or more different combinations of the listed items may be used, and that only one of each item in the list may be required. For example, “at least one of item A, item B, and item C” is not limited to and may include item A, or item A and item B. This example may further include item A, item B, and item C, or item B and item C. In other examples, “at least one of” could be, for example, two of item A, one of item B, and ten of item C; four of item B and seven of item C; and other suitable combinations.

[0029] Referring to Figure 1A, a non-limiting example of a method for fabricating a first exemplary vertical-cavity surface-emitting laser (VCSEL) according to the principles of the present disclosure may include step A, in which a first semiconductor wafer A including a first stack of semiconductor layers is prepared. In one example, the first stack of semiconductor layers may include a first semiconductor substrate 2 and a bottom distributed Bragg reflector (DBR) 4, from bottom to top.

[0030] In one example, the lower DBR4 can be formed of one or more pairs of alternating layers 4-1 and 4-2 of low refractive index material and high refractive index material, for example, AlAs and GaAs, respectively. However, this should not be interpreted as limiting, as the lower DBR4 may be formed of alternating layers of any suitable and / or desirable material currently known or to be developed in the future that enables the lower DBR4 to function or operate in a manner known in the art. In one example, the alternating layers 4-1 and 4-2 of the lower DBR4 may have refractive indices ≤ 3.0 (e.g., 2.95) and > 3.4 (e.g., 3.45), respectively. In one example, each layer 4-1 and 4-2 may have a thickness of λx / 4, where x is an odd number, e.g., 1, 3, 5, etc., and λ is the wavelength of the signal produced by the VCSEL.

[0031] Continuing to refer to Figure 1A, this method may further include step B, which can provide a second semiconductor wafer B containing a second stack of semiconductor layers. In one example, the second stack of semiconductor layers may include, from bottom to top, a second semiconductor substrate 8 and a semiconductor active region 10 which may include any one or combination of the structures oriented in Figures 1B to 1G.

[0032] In one example, the semiconductor active region 10 in Figure 1A may include the semiconductor active region 10 shown in Figure 1B, which includes one or more active sub-regions 10-1, 10-2, and an upper resonator layer 18. Each active sub-region 10-1, 10-2 may include a pair of resonator layers 12 separated by a tunnel junction layer 14, and a quantum well layer 16 on the opposite side of the pair of resonator layers 12 from the second semiconductor substrate 8. If the semiconductor active region 10 of the second semiconductor wafer B in Figure 1A includes the semiconductor active region 10 shown in Figure 1B, then the first active sub-region 10-2 and the second active sub-region 10-1 may include, in the order from the second semiconductor substrate 8 to the upper resonator layer 18, an active sub-region 10-2 including a resonator layer 12-2, a tunnel junction layer 14-2, another resonator layer 12-2, and a quantum well layer 16-2, and an active sub-region 10-1 including a resonator layer 12-1, a tunnel junction layer 14-1, another resonator layer 12-1, and a quantum well layer 16-1.

[0033] In another example, the semiconductor active region 10 in Figure 1A may include the semiconductor active region 10 shown in Figure 1C, which is similar in many respects to the structure shown in Figure 1B, except that the positions of the tunnel junction layer 14 and quantum well layer 16 in Figure 1B are reversed in Figure 1C. If the semiconductor active region 10 of the second semiconductor wafer B in Figure 1A includes the semiconductor active region 10 shown in Figure 1C, then the first active sub-region 10-2 and the second active sub-region 10-1 may include, in the order from the second semiconductor substrate 8 to the upper resonator layer 18, an active sub-region 10-2 including a resonator layer 12-2, a quantum well layer 16-2, another resonator layer 12-2, and a tunnel junction layer 14-2, and an active sub-region 10-1 including a resonator layer 12-1, a quantum well layer 16-1, another resonator layer 12-1, and a tunnel junction layer 14-1.

[0034] In another example, the semiconductor active region 10 of the second semiconductor wafer B in Figure 1A may include the semiconductor active region 10 shown in Figure 1D, similar to the semiconductor active region 10 shown in Figure 1B, which includes an additional portion of the current confinement structure 20 formed around the periphery from bottom to top in Figure 1D, and all of the active sub-regions 10-2 including the resonator layer 12-2, the tunnel junction layer 14-2, other resonator layers 12-2, and the quantum well layer 16-2, and a portion of the active sub-regions 10-1 including the resonator layer 12-1, the tunnel junction layer 14-1, and other resonator layers 12-1, but not the quantum well layer 16-1.

[0035] In another example, the semiconductor active region 10 of the second semiconductor wafer B in Figure 1A may include an additional portion of the current confinement structure 20 formed around the periphery from bottom to top in Figure 1E, and all of the active sub-regions 10-2 including the resonator layer 12-2, the quantum well layer 16-2, other resonator layers 12-2, and the tunnel junction layer 14-2, and all of the active sub-regions 10-1 including the resonator layer 12-1, the quantum well layer 16-1, other resonator layers 12-1, and the tunnel junction layer 14-1, as well as the upper resonator layer 18, similar to the semiconductor active region 10 shown in Figure 1C.

[0036] In another example, the semiconductor active region 10 of the second semiconductor wafer B in Figure 1A may include the semiconductor active region 10 shown in Figure 1F, similar to the semiconductor active region 10 shown in Figure 1D, but excluding the active sub-region 10-2 and the portion of the current confinement structure 20 surrounding the excluded active sub-region 10-2.

[0037] In another example, the semiconductor active region 10 of the second semiconductor wafer B in Figure 1A may include a semiconductor active region 10 similar to the semiconductor active region 10 shown in Figure 1E, but excluding the active sub-region 10-2 and the portion of the current confinement structure 20 surrounding the excluded active sub-region 10-2, as shown in Figure 1G.

[0038] In one example, if the semiconductor active region 10 in Figure 1A includes the structure shown in Figure 1B or Figure 1C, the current confinement structure 20 may be formed after the wafer fusion of the first and second semiconductor wafers A and B, as described below in relation to any one of Figures 4A to 4D. In other words, step B may include preparing a second semiconductor wafer B containing the semiconductor active region 10 shown in Figure 1B or Figure 1C, without the current confinement structure 20 that may be added later, after the wafer fusion of the first and second semiconductor wafers A and B.

[0039] In contrast, if the semiconductor active region 10 of the second semiconductor wafer B in Figure 1A includes the structure shown in any one of Figures 1D to 1G, the current confinement structure 20 can be formed before the wafer fusion of the first and second semiconductor wafers A and B described below. In other words, step B may include preparing the second semiconductor wafer B which includes the semiconductor active region 10 including the current confinement structure 20 shown in any one of Figures 1D to 1G.

[0040] Regardless of when the current confinement structure 20 is introduced, i.e., before or after wafer fusion, the purpose after wafer fusion is to prepare the structure shown in one of Figures 4A to 4D for further processing, as shown and explained in relation to Figure 5.

[0041] In one example, each exemplary current confinement structure 20 described herein may be formed by oxidation (to form oxide openings), ion implantation, or by etching and overgrowth of all or part of the sides of one or more active subregions 10-1 and 10-2.

[0042] For example, each resonator layer 12 may be formed of InP, each tunnel junction layer 14 may be formed of alternating sublayers of InAlGaAs p++ and InAlGaAs n-- (not specifically shown in the figure), and each quantum well layer 16 may be formed of alternating sublayers of InGaAsP with different InGa ratios (not specifically shown in the figure). However, this should not be construed as limiting, as layers 12, 14, and / or 16 may be formed of any suitable and / or desirable material currently known or to be developed in the future that enables layers 12, 14, and / or 16 to function or operate in a manner known in the art.

[0043] In one example, the upper resonator layer 18 may be formed of InP. However, this should not be construed as limiting, as the upper resonator layer 18 may be formed of any suitable and / or desirable material currently known or to be developed in the future that enables the upper resonator layer 18 to function or operate in a manner known in the art.

[0044] In one example, step A may include a first semiconductor wafer A, or a portion thereof, containing a dielectric layer 6 (shown as a dashed line in Figure 1A) on the side of the lower DBR 4 opposite to the first semiconductor substrate 2. Furthermore, or alternatively, in another example, step B may include a second semiconductor wafer B, or a portion thereof, containing a dielectric layer 6' (shown as a dashed line in Figure 1A) on the side of the semiconductor active region 10 opposite to the second semiconductor substrate 8.

[0045] Steps A and B may be completed in any desired order.

[0046] Referring to Figure 2, and continuing to refer to Figure 1, after steps A and B, the method may further include step C, in which the first and second semiconductor wafers A and B may be joined or bonded together, for example, by fusing a lower DBR 4 and a semiconductor active region 10, and a dielectric layer 6, or 6', or 6 and 6', placed between the lower DBR 4 and the semiconductor active region 10. In Figure 2, the dielectric layer 6, or 6', or 6 and 6', may be formed from a portion of the dielectric layer 6, the dielectric layer 6', or the dielectric layers 6 and 6' shown in Figure 1A, respectively.

[0047] For example, if in step A the first semiconductor wafer A includes the entire dielectric layer 6 located on the side of the lower DBR 4 opposite to the first semiconductor substrate 2 (as shown in Figure 1A), and in step B the second semiconductor wafer B does not include the portion of the dielectric layer 6' on the side of the semiconductor active region 10 opposite to the second semiconductor substrate 8, then step C may include joining or bonding the first and second semiconductor wafers A and B together, for example, by fusion at the interface between the dielectric layer 6 and the semiconductor active region 10. In the diagram shown in Figure 1A, the second semiconductor wafer B may be inverted and placed on top of the first semiconductor wafer A.

[0048] For the purposes of this disclosure only, it is assumed that the second semiconductor wafer B is inverted and placed on top of the first semiconductor wafer A. However, this should not be construed as a limitation, as it is assumed that the first semiconductor wafer A may also be inverted and placed on top of the first semiconductor wafer B. Accordingly, the various figures and orientations shown in the figures are strictly for the purposes of this disclosure and should not be construed as a limitation.

[0049] In another example, if in step B the second semiconductor wafer B includes the entire dielectric layer 6' placed on the semiconductor active region 10, and in step A the portion of the dielectric layer 6 is not placed on the lower DBR 4, then step C may include joining or bonding the first and second semiconductor wafers A and B together, for example, by fusion at the interface between the dielectric layer 6' and the lower DBR 4. In the diagram shown in Figure 1A, the second semiconductor wafer B may be inverted and placed on top of the first semiconductor wafer A.

[0050] In another example, if a first portion of dielectric layer 6 is placed on the lower DBR 4 in step A, and a second portion of dielectric layer 6' is placed on the semiconductor active region 10 in step B, step C may include joining or bonding the first and second semiconductor wafers A and B together by fusion at the interface of the first and second portions of dielectric layers 6 and 6' as shown in the diagram in Figure 1A, for example, and the second semiconductor wafer B may be inverted and placed on top of the first semiconductor wafer A.

[0051] In one example, each dielectric layer 6 and / or 6', or each portion thereof, can have a refractive index n ≤ 1.5, and as a result, dielectric layers 6 and / or 6' can be considered low refractive index dielectric layers. However, this should not be interpreted as a limitation, as alternatively, each dielectric layer 6 and / or 6' can have a refractive index n > 1.5. In one example, at least after step C, dielectric layer 6, or 6', or 6 and 6', can have a total thickness of λx, where x is an odd number, e.g., 1, 3, 5, etc., and λ is the wavelength of the optical signal produced by the VCSEL. However, this should not be interpreted as a limitation, as dielectric layers 6, or 6', or 6 and 6', can have any thickness that seems appropriate and / or desirable for a particular application.

[0052] In this disclosure, each dielectric layer 6, or 6', or 6+6' may consist of a single layer or a number of sublayers of the same suitable and / or preferred dielectric material, or a number of sublayers of different suitable and / or preferred dielectric materials, for example, but not limited to SiO2 and Ta2O5.

[0053] Referring to Figure 3 and continuing to refer to all previous figures, after step C, this method may further include step D, in which the second semiconductor substrate 8 can be removed.

[0054] Referring to Figure 4A and continuing to refer to all previous figures, after step D, the method may further include step E. In this step E, if the semiconductor active region 10 includes the structure shown in Figure 1B, the current confinement structure 20 may be formed on all or part of the sides (e.g., around) of one or more active sub-regions 10-1, 10-2 of the semiconductor active region 10 of the second semiconductor wafer B after the fusion of the first and second semiconductor wafers A and B. In one example, the current confinement structure 20 may be formed by oxidation (to form oxide openings), by ion implantation, or by etching and overgrowth of all or part of the sides of one or more active sub-regions 10-1, 10-2.

[0055] Alternatively, step E can be omitted if the semiconductor active region 10 includes the structure shown in Figure 1D, which includes the current confinement structure 20 formed in step B before the fusion of the first and second semiconductor wafers A and B.

[0056] Regardless of when the current confinement structure 20 shown in Figure 4A is formed on the semiconductor active region 10, i.e., before or after the fusion of the first and second semiconductor wafers A and B, the semiconductor active region 10 including the current confinement structure 20 will have the layer order and arrangement shown in Figure 1D, except that it is inverted in step C above by inverting the second semiconductor wafer B for the fusion of the second semiconductor wafer B to the first semiconductor wafer A.

[0057] Referring to Figure 4B and continuing to refer to all previous figures, alternatively, if the semiconductor active region 10 includes the structure shown in Figure 1C, the current confinement structure 20 may be formed in step E, after the fusion of the first and second semiconductor wafers A and B, on all or part of the sides (e.g., around) of one or more active sub-regions 10-1, 10-2 of the semiconductor active region 10 of the second semiconductor wafer B. In one example, the current confinement structure 20 may be formed by oxidation (to form oxide openings), by ion implantation, or by etching and overgrowth of all or part of the sides of one or more active sub-regions 10-1, 10-2.

[0058] Alternatively, step E can be omitted if the semiconductor active region 10 includes the structure shown in Figure 1E, which includes the current confinement structure 20 formed in step B before the fusion of the first and second semiconductor wafers A and B.

[0059] Regardless of when the current confinement structure 20 shown in Figure 4B is formed in the semiconductor active region 10, i.e., before or after the fusion of the first and second semiconductor wafers A and B, the semiconductor active region 10 including the current confinement structure 20 will have the same layer order and arrangement as shown in Figure 1E, except that it is inverted by inverting the second semiconductor wafer B for the fusion of the second semiconductor wafer B to the first semiconductor wafer A in step C described above.

[0060] Referring to Figure 4C and continuing to refer to all previous figures, step E can be omitted if the semiconductor active region 10 includes the structure shown in Figure 1F, which includes the current confinement structure 20 formed in step B before the fusion of the first and second semiconductor wafers A and B. Alternatively, if the semiconductor active region 10 shown in Figure 1F does not include the current confinement structure 20 before wafer fusion, the current confinement structure 20 may be added to the semiconductor active region 10 in step E after wafer fusion.

[0061] Regardless of when the current confinement structure 20 shown in Figure 4C is formed in the semiconductor active region 10, i.e., before or after the fusion of the first and second semiconductor wafers A and B, the semiconductor active region 10 including the current confinement structure 20 will have the layer order and arrangement shown in Figure 1F, except that it is inverted in step C above by inverting the second semiconductor wafer B for the fusion of the second semiconductor wafer B to the first semiconductor wafer A.

[0062] Referring to Figure 4D and continuing to refer to all previous figures, step E can be omitted if the semiconductor active region 10 includes the structure shown in Figure 1G, which includes the current confinement structure 20 formed in step B before the fusion of the first and second semiconductor wafers A and B. Alternatively, if the semiconductor active region 10 shown in Figure 1G does not include the current confinement structure 20 before wafer fusion, the current confinement structure 20 may be added to the semiconductor active region 10 in step E after wafer fusion.

[0063] Regardless of when the current confinement structure 20 shown in Figure 4D is formed in the semiconductor active region 10, i.e., before or after the fusion of the first and second semiconductor wafers A and B, the semiconductor active region 10 including the current confinement structure 20 will have the layer order and arrangement shown in Figure 1G, except that it is inverted in step C above by inverting the second semiconductor wafer B for the fusion of the second semiconductor wafer B to the first semiconductor wafer A.

[0064] Referring to Figure 5 and continuing to refer to all previous figures, after step E, or after step D if step E can be omitted as described above, the method may include step F, in which the upper DBR 22 may be formed on the side of the semiconductor active region 10 opposite to the lower DBR 4. In one example, the upper DBR 22 may be formed of alternating layers 22-1 and 22-2 of SiO2 and Ta2O5, respectively. However, this should not be construed as limiting, as the upper DBR 22 may be formed of alternating layers of any suitable and / or desirable material currently known or to be developed in the future that enables the upper DBR 22 to function or operate in a manner known in the art. In one example, the alternating layers 22-1 and 22-2 of the upper DBR 22 may be formed of materials having refractive indices <2.0 (e.g., 1.45) and >2.0 (e.g., 2.25), respectively. In one example, each layer 22-1 and 22-2 can have a thickness of λx / 4, where x is an odd number, e.g., 1, 3, 5, etc., and λ is the wavelength of the optical signal produced by the VCSEL.

[0065] In one example, the upper DBR22 may include a first plurality of semiconductor layers, and the lower DBR4 may include a second plurality of semiconductor layers. In one example, the number of the first plurality of semiconductor layers in the upper DBR22 and the number of the second plurality of semiconductor layers in the lower DBR4 may be the same or different.

[0066] In the example shown in Figure 5, the grating structure 24 (indicated by the solid arrow 24 in Figure 5) can be formed on the exposed upper surface of the upper DBR 22 opposite the semiconductor active region 10. In another example (indicated by the dashed arrow 24 in Figure 5), the grating structure 24 can be formed between any pair of layers 22-1, 22-2 of the body of the second DBR 22. In yet another example (indicated by the dashed-dotted arrow 24 in Figure 5), the grating structure 24 can be formed between the semiconductor active region 10 and the bottom layer of the second DBR 22. The grating structure 24 may be formed at any one or more of the locations indicated by the solid arrow 24, dashed arrow 24, and / or dashed-dotted arrow 24 in Figure 5.

[0067] In one example, the grating structure or layer 24 may be formed of the material forming layer 22-1 or layer 22-2 of the second DBR 22. In another example, the grating structure 24 may be formed of a material known in the art as another layer, either further or alternatively.

[0068] In one example, the grating structure 24 may have lines 26 of height h and a spacing k between opposing sides of adjacent lines 26, where the values ​​of height h and spacing k can be chosen with respect to the wavelength of the optical signal generated by the VCSEL, for example, IR light. In one example, each line 26 of the grating structure 24 may have a grating height h between zero and 1 / 4 wavelength, i.e., λ / 4.

[0069] Referring to Figures 6 and 7, and continuing to refer to all previous figures, a method for fabricating a second exemplary VCSEL according to the principles of the present disclosure can be in most similar to the method for fabricating the first exemplary VCSEL described above with reference to Figures 1 to 5, except that the grating structure 24 may be formed before step C.

[0070] For example, as shown in Figure 6, if in step A the first semiconductor wafer A includes the entire dielectric layer 6 and in step B the second semiconductor wafer B does not include the grating structure 24' and portion of the dielectric layer 6', then step A may further include the first semiconductor wafer A including the grating structure 24 formed on the side of the dielectric layer 6 opposite the lower DBR 4. In this example, step C may include joining or bonding the first and second semiconductor wafers A and B together, for example by fusion at the interface between the grating structure 24 and the semiconductor active region 10, as shown in Figure 7.

[0071] In another example, if in step B the second semiconductor wafer B includes the entire dielectric layer 6', and in step A the second semiconductor wafer A does not include the grating structure 24 and portion of the dielectric layer 6, then step B may further include the second semiconductor wafer B including the grating structure 24' formed between the dielectric layer 6' and the semiconductor active region 10. In this example, the dielectric layer 6' may follow the shape and / or contour of the lines 26' of the grating structure 24'. In this example, step C may include joining or bonding the first and second semiconductor wafers A and B together, for example by fusion at the interface between the dielectric layer 6' and the lower DBR 4, as shown in Figure 7.

[0072] In another example, step A includes a first semiconductor wafer A that includes a first portion of a dielectric layer 6 located on the lower DBR 4 and does not include a portion of the grating structure 24, and step B includes a second semiconductor wafer B that includes a second portion of a dielectric layer 6', then step B may further include a second semiconductor wafer B that includes a grating structure 24' formed between the second portion of the dielectric layer 6' and the semiconductor active region 10. In this example, step C may include joining or bonding the first and second semiconductor wafers A and B together, for example by fusion bonding at the interface of the first and second portions of the dielectric layers 6 and 6', as shown in Figure 7.

[0073] In another example, step A may include forming a grating structure 24 that is in direct contact with the lower DBR 4 on the opposite side of the first semiconductor substrate 2, and the dielectric layer 6 (or a portion thereof) may be formed on the grating structure 24 on the opposite side of the lower DBR 4, i.e., the positions of the grating structure 24 and the dielectric layer 6 shown in Figure 6 may be reversed. In this example, the dielectric layer 6 (or a portion thereof) may follow the shape and / or contour of the lines 26 of the grating structure 24. In this example, step C may include joining or bonding the first and second semiconductor wafers A and B together, for example, by fusion at the interface between the dielectric layer 6 and the semiconductor active region 10.

[0074] In the examples shown in Figures 6 and 7, the grating structure or layer 24 and / or 24' (or each portion thereof) can be formed from the material forming layer 22-1 or layer 22-2 of the second DBR 22 shown in Figure 7. Furthermore or alternatively, the grating structure or layer 24 and / or 24' (or each portion thereof) may be formed from one or more suitable and / or preferred materials known in the art.

[0075] In one example, the grating structures 24 and / or 24' shown in Figures 6 and 7 may have lines 26 and / or 26' of height h and a spacing k between opposing sides of adjacent lines 26, where the values ​​of height h and spacing k can be chosen with respect to the wavelength of the optical signal produced by the VCSEL, e.g., IR light. In one example, each line 26 and / or 26' may have a height h between zero and 1 / 4 wavelength, i.e., λ / 4.

[0076] Following step C, a method for fabricating a second exemplary VCSEL according to the principles of this disclosure may include steps D, E (if applicable), and F as described above for the first exemplary VCSEL shown and described in relation to Figures 1 to 5.

[0077] Referring to Figure 8, and continuing to refer to all previous figures, in Figures 1 to 7, the dielectric layers 6, or 6', or 6 and 6', can be solid bodies. However, according to the principles of the present disclosure shown in Figure 8, it is assumed that the bodies of the dielectric layers 6, or 6', or 6 and 6' shown in Figures 1 to 7 can contain any number of voids, cavities, or pockets 30 of the same or different dimensions, which do not contain material. In one example, one or more voids, cavities, or pockets 30-1 can extend from one or both surfaces of the body of the dielectric layer 6 to a first depth into the body of the dielectric layer 6, or 6', or 6 and 6'. Further or alternatively, in another example, one or more voids, cavities, or pockets 30-2 can extend from one or both surfaces of the body of the dielectric layer 6, or 6', or 6 and 6', to a second deeper depth into or through the body of the dielectric layer 6, or 6', or 6 and 6'. Furthermore or alternatively, in yet another example, one or more voids, cavities, or pockets 30-3 may be formed inside the body of dielectric layer 6, or 6', or 6 and 6', for example, from the side of the body of dielectric layer 6. Furthermore or alternatively, in yet another example, the body of dielectric layer 6, or 6', or 6 and 6' may contain any combination of two or more voids, cavities, or pockets 30-1, 30-2, and / or 30-3.

[0078] In one example, each void, cavity, or pocket 30 can be filled with air having a refractive index n=1, or with any other suitable and / or desirable gas or combination of gases having a refractive index smaller than (n≦2) than the refractive index of dielectric layer 6, or 6', or 6 and 6'. The advantage of this is the reduction in the overall refractive index of dielectric layer 6, or 6', or 6 and 6', as well as the corresponding increase in refractive index contrast between dielectric layer 6, or 6', or 6 and 6' and the lower DBR4 in the examples shown in Figures 5 and 7. This means that the same reflectivity of the lower DBR4 can be achieved with fewer DBR layer pairs 4-1 and 4-2. The advantage of a lower DBR4 with fewer DBR layer pairs 4-1 and 4-2 is that it can reduce the warpage of the first semiconductor wafer A and improve the yield of joining or bonding the first and second semiconductor wafers A and B together, for example by fusion bonding. Another advantage is the improved thermal conductivity from the lower DBR4 to the first semiconductor substrate 2.

[0079] In one example, the properties of each void, cavity, or pocket 30 may include a width or diameter r≪λ (i.e., the wavelength of the optical signal of, for example, IR light produced by the VCSEL). The height t of each void, cavity, or pocket 30 may be the same height as the dielectric layer 6, or 6', or 6 and 6', i.e., it may extend through the thickness of the dielectric layer 6. Each void, cavity, or pocket 30 may have any suitable and / or desirable shape, e.g., circular, rectangular, cylindrical, tubular, etc. Each void, cavity, or pocket 30 may be formed by etching the dielectric layer 6, or 6', or 6 and 6', or by porous deposition of the material forming the dielectric layer 6, or 6', or 6 and 6'. Finally, the properties of each void, cavity, or pocket 30 can include polarization control, i.e., since the width r ≪ λ of each void, cavity, or pocket 30 has little to no effect on the polarization of the optical signal produced by the VCSEL, and as a result, each void, cavity, or pocket 30 has little to no diffraction. The exemplary VCSELs according to the principles of this disclosure can be formed by conventional semiconductor processing techniques known in the art, which are not described herein for the sake of brevity.

[0080] Other non-limiting examples or aspects of this disclosure are described in the following illustrative and illustrative numbered clauses.

[0081] Clause 1: A method for fabricating a vertical-cavity surface-emitting laser (VCSEL) comprises the steps of (a) forming or preparing a first semiconductor wafer including a first semiconductor substrate and a lower distributed Bragg reflector (DBR) from bottom to top of a first semiconductor wafer, and (b) forming or preparing a second semiconductor wafer including a second semiconductor substrate, a semiconductor active region including at least one active sub-region, and an upper resonator layer on the side of the second semiconductor substrate opposite to at least one active sub-region, wherein each active sub-region comprises a pair of resonator layers separated by a tunnel junction layer, and on the side of the second semiconductor substrate opposite to one The method includes (c) a quantum well layer on the side of a pair of resonator layers, or a pair of resonator layers separated by a quantum well layer, and a tunnel junction layer on the side of the pair of resonator layers opposite the second semiconductor substrate; (d) a lower DBR and a semiconductor active region coupled using a second semiconductor substrate located on the side of the semiconductor active region opposite the lower DBR, and then removing the second semiconductor substrate; (d) a step of forming an upper DBR on the side of the semiconductor active region opposite the lower DBR after the removal of the second semiconductor substrate; and (e) a step of forming a current confinement structure in all or part of at least one active sub-region of the semiconductor active region.

[0082] Clause 2: The method according to Clause 1, wherein step (b) may include a semiconductor active region comprising two active sub-regions, or step (c) may include coupling the lower DBR and the semiconductor active region using a dielectric layer between them.

[0083] Clause 3: The method described in Clause 1 or 2 may further include, prior to step (c), forming a dielectric layer on the side of the lower DBR opposite to the first semiconductor substrate, on the side of the semiconductor active region opposite to the second semiconductor substrate, or both, so that as a result step (c) may include bonding the lower DBR and the semiconductor active region with the dielectric layer between them.

[0084] Clause 4: The dielectric layer may have a refractive index n ≤ 1.5, according to the method of any one of the claims 1 to 3.

[0085] Article 5: The method according to any one of the claims 1 to 4, wherein the upper DBR may include a first plurality of semiconductor layers, and the lower DBR may include a second plurality of semiconductor layers.

[0086] Clause 6: The method according to any one of the clauses 1 to 5, wherein the first plurality of semiconductor layers of the upper DBR and the second plurality of semiconductor layers of the lower DBR may be different.

[0087] Article 7: A method described in any one of the clauses 1 to 6 may further include the step of forming a grating structure on the side of the upper DBR opposite to at least one semiconductor active region, or between layers of the upper DBR, or between the semiconductor active region and the upper DBR, or between the lower DBR and the semiconductor active region.

[0088] Clause 8: The current confinement structure of step (e) may be formed before or after step (c), as described in any one of the claims 1 to 7.

[0089] Article 9: The dielectric layer may have a thickness of λx / 4, where x is an odd number and λ is the wavelength of the optical signal produced by the VCSEL, according to any one of the claims 1 to 8.

[0090] Clause 10: The method according to any one of the claims 1 to 9, wherein the dielectric layer may include one or more voids, cavities, or pockets.

[0091] Clause 11: A vertical-cavity surface-emitting laser (VCSEL) comprising, from lower to upper, a semiconductor substrate, a lower distributed Bragg reflector (DBR), a semiconductor active region including at least one active sub-region, and an upper DBR.

[0092] Article 12: The VCSEL as described in Clause 11, which may further include one of the following: a dielectric layer between the lower DBR and the semiconductor active region, or a semiconductor active region comprising two active sub-regions.

[0093] Article 13: The dielectric layer may have a refractive index n ≤ 1.5, as described in VCSEL of Clause 11 or 12.

[0094] Article 14: The VCSEL described in any one of clauses 11 to 13 may further include a current confinement structure located in at least a portion of the semiconductor active region.

[0095] Article 15: The current-confining structure can be formed by oxidation, ion implantation, or etching and overgrowth of at least a portion of the semiconductor active region, as described in any one of Clauses 11 to 14.

[0096] Article 16: The VCSEL described in any one of clauses 11 to 15 may further include a grating structure on the side of the upper DBR layer opposite the semiconductor active region, or between the layers of the upper DBR, or between the semiconductor active region and the upper DBR, or between the lower DBR and the semiconductor active region.

[0097] Article 17: A VCSEL according to any one of the clauses 11 to 16, wherein each semiconductor active region may include one or more active sub-regions comprising: (a) a quantum well layer and a pair of resonator layers separated by a tunnel junction layer on the quantum well layer side opposite the dielectric layer; or (b) a tunnel junction layer and a pair of resonator layers separated by a quantum well layer on the tunnel junction layer side opposite the dielectric layer.

[0098] Article 18: The VCSEL described in any one of clauses 11 to 17 may further include an upper resonator layer between at least one active sub-region and the dielectric layer.

[0099] Article 19: The VCSEL described in any one of clauses 11 to 18 may further include current confinement structures located in at least a portion of each active sub-region.

[0100] Article 20: The current confinement structure may be located in each resonator layer and each tunnel junction layer of each active sub-region, as described in any one of clauses 11 to 19 of the VCSEL.

[0101] Article 21: The current confinement structure may be located in the quantum well layer of at least one active sub-region, as described in any one of the VCSELs of Clauses 11 to 20.

[0102] Article 22: The dielectric layer may have a thickness of λx / 4, where x is an odd number and λ is the wavelength of the optical signal produced by the VCSEL, as described in any one of the clauses 11 to 21.

[0103] This disclosure has been described in detail for illustrative purposes based on what is considered to be the most practical and preferred embodiments at present, but it should be understood that such details are for that purpose only, and that this disclosure is not limited to the disclosed embodiments, but rather intended to encompass modifications and equivalent configurations within the spirit and scope of the appended claims. For example, it should be understood that, wherever possible, this disclosure is intended to allow one or more features of any embodiment to be combined with one or more features of any other embodiment. [Explanation of symbols]

[0104] 2. First semiconductor substrate 4 Lower DBR 4-1, 4-2 Alternating layers of lower DBR 6, 6' dielectric layer 8. Second semiconductor substrate 10 Semiconductor active region 10-1, 10-2 active subregions 12 resonator layer 12-1, 12-2 resonator layer 14 Tunnel junction layer 14-1, 14-2 Tunnel junction layer 16 Quantum well layer 16-1, 16-2 Quantum well layer 18 Upper cavity layer 20 Current confinement structure 22 Upper DBR, Second DBR 22-1, 22-2: Alternating layers of upper DBR. 24, 24' grating structure 26, 26' line 30-1, 30-2, 30-3 Void, empty space, or pocket

Claims

1. A method for fabricating a vertical-cavity surface-emitting laser (VCSEL), (a) The step of forming or preparing the first semiconductor wafer, including a first semiconductor substrate and a bottom distributed Bragg reflector (DBR), from the bottom to the top of the first semiconductor wafer, (b) A step of forming or preparing the second semiconductor wafer, comprising a second semiconductor substrate, a semiconductor active region including at least one active sub-region, and an upper resonator layer on the side of the second semiconductor substrate opposite to the at least one active sub-region, wherein each active sub-region is A pair of resonator layers separated by a tunnel junction layer, and a quantum well layer on the side of the pair of resonator layers opposite the second semiconductor substrate, or A pair of resonator layers separated by a quantum well layer, and a tunnel junction layer on the side of the pair of resonator layers opposite the second semiconductor substrate. Steps including, (c) The lower DBR and the semiconductor active region are bonded using the second semiconductor substrate positioned on the side of the semiconductor active region opposite to the lower DBR, and then the second semiconductor substrate is removed. (d) After removing the second semiconductor substrate, the step of forming an upper DBR on the semiconductor active region side opposite to the lower DBR, (e) The step of forming a current confinement structure in all or part of the at least one active sub-region of the semiconductor active region. Methods that include...

2. The method according to claim 1, wherein step (b) includes the semiconductor active region comprising two active sub-regions, or step (c) includes bonding the lower DBR and the semiconductor active region using a dielectric layer between them.

3. The method of claim 2, further comprising the step of forming the dielectric layer on the side of the lower DBR opposite to the first semiconductor substrate, on the side of the semiconductor active region opposite to the second semiconductor substrate, or both, prior to step (c), wherein step (c) comprises bonding the lower DBR and the semiconductor active region using the dielectric layer between them.

4. The method according to claim 2, wherein the dielectric layer has a refractive index n ≤ 1.

5.

5. The upper DBR includes a first plurality of semiconductor layers, The lower DBR includes a second plurality of semiconductor layers, The method according to claim 1.

6. The method according to claim 5, wherein the first plurality of semiconductor layers of the upper DBR and the second plurality of semiconductor layers of the lower DBR are different.

7. The grating structure, On the side of the upper DBR opposite to the at least one semiconductor active region, or Between the layers of the upper DBR, or Between the semiconductor active region and the upper DBR, or Between the lower DBR and the semiconductor active region The method according to claim 1, further comprising the step of forming.

8. The method according to claim 1, wherein the current confinement structure of step (e) is formed before or after step (c).

9. The method according to claim 2, wherein the dielectric layer has a thickness of λx / 4, where x is an odd number and λ is the wavelength of the optical signal generated by the VCSEL.

10. The method according to claim 2, wherein the dielectric layer includes one or more voids, cavities, or pockets.

11. A vertical-cavity surface-emitting laser (VCSEL), wherein the laser beam travels from the bottom to the top, Semiconductor substrate and Lower distributed Bragg reflector (DBR), A semiconductor active region including at least one active subregion, Upper DBR and This includes vertical cavity surface-emitting lasers (VCSELs).

12. The VCSEL according to claim 11, further comprising the following: a dielectric layer between the lower DBR and the semiconductor active region, or one of the semiconductor active regions including two active sub-regions.

13. The VCSEL according to claim 12, wherein the dielectric layer has a refractive index n ≤ 1.

5.

14. The VCSEL according to claim 11, further comprising a current confinement structure disposed in at least a portion of the semiconductor active region.

15. The VCSEL according to claim 14, wherein the current confinement structure is formed by oxidation, ion implantation, or etching and overgrowth of at least a portion of the semiconductor active region.

16. The grating structure, On the side of the upper DBR layer opposite to the semiconductor active region, or Between the layers of the upper DBR, or Between the semiconductor active region and the upper DBR, or Between the lower DBR and the semiconductor active region Furthermore, the VCSEL according to claim 12.

17. Each of the aforementioned semiconductor active regions is one of the following, namely: (a) A quantum well layer, and a pair of resonator layers separated by a tunnel junction layer on the quantum well layer side opposite the dielectric layer, or (b) A tunnel junction layer and a pair of resonator layers separated by a quantum well layer on the side of the tunnel junction layer opposite the dielectric layer. The VCSEL according to claim 11, comprising one or more active subregions including one of the following.

18. The VCSEL according to claim 12, further comprising an upper resonator layer between the at least one active sub-region and the dielectric layer.

19. The VCSEL according to claim 17, further comprising a current confinement structure disposed in at least a portion of each active sub-region.

20. The VCSEL according to claim 19, wherein the current confinement structure is arranged in each resonator layer and each tunnel junction layer of each active sub-region.

21. The VCSEL according to claim 20, wherein the current confinement structure is arranged in the quantum well layer of at least one active sub-region.

22. The VCSEL according to claim 12, wherein the dielectric layer has a thickness of λx / 4, where x is an odd number and λ is the wavelength of the optical signal generated by the VCSEL.

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