Scan test circuit

Abstract

This provides a scan test circuit that can reduce the time and cost associated with testing. [Solution] The scan test circuit of the present disclosure comprises a logic circuit and an analog circuit, the logic circuit having a selection circuit and a logic circuit block, each logic circuit block having first to fourth flip-flops (FFs) and first and second combinational circuits, the selection circuit is connected to the first and third FFs, the first and second FFs are connected, the third and fourth FFs are connected, the second FF is connected to the first combinational circuit, the first combinational circuit and the third combinational circuit are connected, the fourth FF is connected to the second combinational circuit, the second combinational circuit and the fourth combinational circuit are connected, the third combinational circuit is connected to the fourth FF, and the fourth combinational circuit is connected to the third FF.

Description

Technical Field

[0001] The present disclosure relates to a scan test circuit applied to a logic circuit that drives an analog circuit.

Background Art

[0002] Generally, in a semiconductor circuit, testing of a logic circuit connected to an analog circuit such as a vertical scan circuit is performed by testing on the analog circuit side or by using an observation flip-flop (hereinafter referred to as FF) at the connection part.

[0003] However, in order to perform testing on the analog circuit side, it is necessary to inspect using an image of the circuit or the like, so the time and cost associated with the testing increase. Also, it is possible to implement a scan test by mounting a scan test circuit on a part of the analog circuit. However, since the connection part cannot be inspected, test coverage for ensuring the quality of the semiconductor circuit cannot be obtained.

[0004] Also, in the method of inspecting using an observation FF, the scan chain for the observation FF extends. As a result, the shift operation time of the scan test becomes long, so the test time increases, and in addition, since the circuit area for the observation FF increases, its leakage power also increases.

[0005] In Patent Document 1, a technique for inspecting the connection part between an analog circuit and a logic circuit has been proposed. Also, in Patent Documents 2, 3, and 4, techniques for confirming an inspection part have been proposed.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Patent Document 3

[0007] However, even using the technology described in Patent Document 1 does not reduce the number of observation flip-flops used in the test. Furthermore, even when using the technologies described in Patent Documents 2 to 4, the degrees of freedom of the scan chain are small, and the number of repetitions of the scan test shift and capture operations cannot be reduced. Therefore, the time and cost associated with the test cannot be reduced.

[0008] The technology disclosed herein has been made in view of the above and aims to provide a scan test circuit that can reduce the time and cost associated with testing. [Means for solving the problem]

[0009] To achieve the above objective, the scan test circuit according to this disclosure is a scan test circuit comprising a logic circuit and an analog circuit, wherein the logic circuit comprises a selection circuit and a plurality of logic circuit blocks to which the selection signal of the selection circuit is input, each of the plurality of logic circuit blocks comprising a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, a first combinational circuit, and a second combinational circuit, and operates when the selection signal of the selection circuit is input, and the selection circuit The scan test circuit is characterized in that it is connected to the first flip-flop and the third flip-flop, the first flip-flop and the second flip-flop are connected, the third flip-flop and the fourth flip-flop are connected, the second flip-flop is connected to the first combinational circuit, the first combinational circuit is connected to the analog circuit by a plurality of signal lines, the plurality of signal lines connected to the first combinational circuit are connected to the third combinational circuit, the fourth flip-flop is connected to the second combinational circuit, the second combinational circuit is connected to the analog circuit by a plurality of signal lines, the plurality of signal lines connected to the second combinational circuit are connected to the fourth combinational circuit, the third combinational circuit is connected to the fourth flip-flop, and the fourth combinational circuit is connected to the third flip-flop. [Effects of the Invention]

[0010] According to this disclosure, by converting the signal back to an FF using a combinational circuit, faults occurring in the parts connected to the analog circuit can be detected by scan testing. Furthermore, there are no concerns about increased circuit area or increased scan shift counts due to the addition of observation FFs. In addition, the number of iterations of scan test shift and capture operations is reduced, resulting in a reduction in the time and cost associated with testing. [Brief explanation of the drawing]

[0011] [Figure 1] This figure shows a schematic configuration of the scan test circuit according to the first embodiment. [Figure 2] A schematic diagram showing a typical scan test circuit and its operating timing. [Figure 3] Circuit diagram showing an example of a scan test circuit configuration that does not employ the present invention. [Figure 4] Circuit diagram using an observation flip-flop in a scan test circuit that does not employ the present invention. [Figure 5]Circuit diagram showing an example configuration of a scan test circuit according to the first embodiment. [Figure 6] Circuit diagram showing an example configuration of a scan test circuit according to the second embodiment. [Figure 7] Circuit diagram showing an example configuration of a scan test circuit according to the third embodiment. [Figure 8] Circuit diagram showing an example configuration of a scan test circuit according to the fourth embodiment. [Figure 9] Schematic diagram showing equipment equipped with a semiconductor device according to the fifth embodiment. [Modes for carrying out the invention]

[0012] Embodiments of this disclosure will be described below with reference to the drawings. However, this disclosure is not limited to the embodiments described below, and may be modified as appropriate without departing from its essence. Furthermore, in the drawings described below, components having the same function will be denoted by the same reference numerals, and their descriptions may be omitted or simplified.

[0013] (First Embodiment) The semiconductor circuit according to the first embodiment will be described below. Figure 1 is a schematic diagram showing the general configuration of a semiconductor circuit 11, which is a scan test circuit according to the first embodiment. In Figure 1, the semiconductor circuit shows a logic circuit 101 with a large number of output signals and an analog circuit 102 that receives these output signals. In such a circuit configuration, constructing a test method for the combinational circuit and output section of the logic circuit 101, as well as the analog circuit, is necessary to solve the above-mentioned problems.

[0014] Figures 2A and 2B show a schematic circuit diagram and its operating timing when a typical scan test is inserted. As shown in Figure 2A, when the scan shift enable signal (SCAN_SHIFTEN) is high, a clock signal is input from the clock CLK, and data is transferred from the scan data in signal (SCAN_DATAIN). Also, when the scan shift enable signal (SCAN_SHIFTEN) is low, data is input from the combinational circuit.

[0015] Also, FIG. 2B is a waveform diagram showing an outline of the operation timing in the circuit shown in FIG. 2A. As shown in FIG. 2B, during the capture operation (time t1), data is transferred from the combinational circuits 2004, 2005, and 2006, and data x is transferred to FF2001, data y is transferred to FF2002, and data z is transferred to FF2003, respectively. Then, at times t2 and t3, the data transferred by inputting the clock CLK is output, and it becomes possible to inspect the output values of the combinational circuits.

[0016] Next, the configuration of the logic circuit related to this embodiment will be described while referring to the figures. In the following description, descriptions of the signals of the clock, scan data in, and scan shift enable are omitted.

[0017] First, FIG. 3 shows the logic circuit configuration when this embodiment is not applied. As shown in FIG. 3, in the logic circuit 101, a selection circuit section 103, block circuits 300, 310... 3n0 (n is an integer of 2 or more; the same applies hereinafter) that operate when selected, and an input signal control circuit 104 of the combinational circuit are provided.

[0018] The input signal control circuit 104 is connected to the combinational circuits 3004, 3005, 3103, 3105... 3n04, 3n05. The input signal control circuit 104 controls the signals input to the combinational circuits 3004, 3005, 3103, 3105... 3n04, 3n05. Also, in the block circuit 300, at least FF3000, 3001, 3002, 3003 and combinational circuits 3004, 3005 are provided. Similarly, in the block circuit 310, at least FF3100, 3101, 3102, 3103 and combinational circuits 3104, 3105 are provided. Similarly, in the block circuit 3n0, at least FF3n00, 3n01, 3n02, 3n03 and combinational circuits 3n04, 3n05 are provided.

[0019] The selection circuit section 103 is connected to FF3000, 3002, 3100, 3102...3n00, 3n02. In addition, FF3000, 3002, 3100, 3102...3n00, 3n02 are connected to FF3001, 3003, 3101, 3103...3n01, 3n03, respectively.

[0020] Furthermore, FF3001 is connected to combination circuit 3004, and FF3003 is connected to combination circuit 3005. Similarly, FF3101 is connected to combination circuit 3104, and FF3103 is connected to combination circuit 3105. Likewise, FF3n01 is connected to combination circuit 3n04, and FF3n03 is connected to combination circuit 3n05.

[0021] In the block circuit shown in Figure 3, even if a scan test circuit is implemented and a scan test can be performed, it is not possible to test the combinational circuits 3004, 3005, 3104, 3105...3n04, 3n05 and the signals output from these combinational circuits.

[0022] Figure 4 shows an example of a circuit configuration using an observation flip-flop when this embodiment is not applied. As shown in Figure 4, the logic circuit 101 is provided with a selection circuit section 103 and an input signal control circuit 104 for combinational circuits 400, 410...4n0 that operate when selected by the selection circuit section 103. The input signal control circuit 104 is connected to combinational circuits 4004, 4007, 4104, 4107...4n04, 4n07.

[0023] The selection circuit section 103 is connected to FF4000, 4002 of block circuit 400, FF4100, 4102 of block circuit 410, ... FF4n00, 4n02 of block circuit 4n0. It is being done.

[0024] Furthermore, the block circuit 400 is provided with at least FF4000, 4001, 4002, 4003 and combinational circuits 4004, 4007, and OR gates 4005, 4008 and observation FF4006, 4009 for scan testing. FF4000 and FF4001 are connected, and FF4002 and FF4003 are connected. Also, FF4001 and combinational circuit 4004 are connected, and FF4003 and combinational circuit 4007 are connected.

[0025] The output of combinational circuit 4004 is combined with OR gate 4005 and then output to observation FF 4006. Similarly, the output of combinational circuit 4007 is combined with OR gate 4008 and then output to observation FF 4009.

[0026] In Figure 4, block circuits 410 and 4n0 have a circuit configuration similar to that of block circuit 400.

[0027] In the circuit shown in Figure 4, if a scan test circuit is implemented and a scan test is performed, it is possible to test the output signals of the combination circuits 4004, 4007, 4104, 4107...4n04, 4n07 and their combination circuits.

[0028] However, in the circuit configuration shown in Figure 4, the number of observation flip-flops (FFs) increases by adding observation FFs 4006, 4009, 4106, 4109...4n06, 4n09. As a result, the scan chain (scanbus (a bus in which FFs are connected serially)) becomes longer due to the increased number of observation FFs, and the test time also increases, leading to an increase in leakage power.

[0029] Next, Figure 5 shows an example of a schematic configuration of a logic circuit when this embodiment is applied. In the following description, components similar to those in the logic circuit 101 described above are denoted by the same reference numerals, and detailed explanations are omitted.

[0030] As shown in Figure 5, the logic circuit 1101 includes a selection circuit section 103 and an input signal control circuit 104 for combinational circuits and block circuits 500, 510...5n0 that operate when selected by the selection circuit section 103. The block circuits 500, 510...5n0 are multiple logic circuit blocks to which the selection signal of the selection circuit is input. Block circuits 500 and 510 are the first and second logic circuit blocks, which are adjacent to each other among the multiple logic circuit blocks.

[0031] Furthermore, the input signal control circuit 104 is connected to combination circuits 5004, 5008, 5104, 5108...5n04, 5n08. The selection circuit section 103 is connected to FF5000, 5002 of block circuit 500, FF5100, 5102 of block circuit 510...FF5n00, 5n02 of block circuit 5n0.

[0032] Furthermore, block circuit 500 includes FF5000, 5001, 5002, and 5003, combinational circuits 5004 and 5008, and combinational circuits 5005 and 5009 which are logical OR for scan testing. Block circuit 500 also includes logical AND 5006, 5010, and logical OR 5007 and 5011. Here, FF5000, 5001, 5002, and 5003 are the first to fourth flip-flops, combinational circuit 5004 is the first combinational circuit, and combinational circuit 5008 is the second combinational circuit.

[0033] Furthermore, combination circuits 5004 and 5008 connect to analog circuit 102 via multiple signal lines. They are connected. The semiconductor circuit 11 may be, for example, a vertical scanning circuit in a photoelectric converter that scans multiple pixels arranged in multiple rows and multiple columns row by row. In this case, the analog circuit 102 may be the signal output section (e.g., a buffer circuit) of the vertical scanning circuit. Another example of the semiconductor circuit 11 is a horizontal scanning circuit in the same photoelectric converter that scans multiple column circuits, each corresponding to a pixel in multiple columns, row by column. In this case, the analog circuit 102 may be the signal output section of the horizontal scanning circuit.

[0034] The multiple pixels of the photoelectric converter illustrated here are equipped with a photoelectric conversion unit that generates a signal charge based on incident light, and output a signal having a signal level based on that signal charge to a signal line. As this photoelectric conversion unit, a photodiode that stores signal charge over a certain period of time, an avalanche photodiode that generates avalanche multiplication in response to the incidence of photons, or a photoelectric conversion film formed including an organic film or an inorganic film can be used. Furthermore, the vertical scanning circuit and horizontal scanning circuit illustrated here can be configured as a decoder. In this configuration, the selection circuit unit 103 shown in Figure 5 can be an address decoder. In that case, the analog circuit 102 receives signals generated by combinational circuits 5n04 and 5n08, which receive the outputs of the selection circuit unit 103 (which is an address decoder) and the input signal control circuit 104, respectively. Based on these input signals, the analog circuit 102 outputs a control signal to the outside of the analog circuit 102.

[0035] If the semiconductor circuit 11 is a vertical scanning circuit, this control signal is output as a signal to control each of the multiple pixels. Examples of pixel control signals include a signal to control the transfer of charge from the photoelectric conversion unit to another charge holding unit, a signal to control the reset operation of the charge holding unit, and a signal to control the signal output from the pixel. Furthermore, if the semiconductor circuit 11 is a horizontal scanning circuit, the control signal is output as a signal to control each of the multiple column circuits. Examples of column circuit control signals include a signal to control the readout of the signal generated by the column circuit from the column circuit.

[0036] Multiple signal lines connected to combinational circuit 5004 are connected to combinational circuit 5005, and multiple signal lines connected to combinational circuit 5008 are connected to combinational circuit 5009. Here, combinational circuit 5005 is the third combinational circuit, and combinational circuit 5008 is the fourth combinational circuit.

[0037] The combinational circuits 5005 and 5009 do not necessarily have to be logical OR circuits; they can also be exclusive OR circuits, etc. The output of FF5000 is input to one side of the two-input logical OR circuit 5007, and its output goes into FF5001. Similarly, the output of FF5002 is input to one side of the two-input logical OR circuit 5011, and its output goes into FF5003.

[0038] One side of the two-input logical AND gate 5006 and 5010 inputs receives a signal for scan test mode. FF5001 is connected to combinational circuit 5004, and FF5003 is connected to combinational circuit 5008.

[0039] The signal output from combinational circuit 5004 is combined by combinational circuit 5005 and then input to two-input logical AND 5010. The output from two-input logical AND 5010 is then input to two-input logical OR 5011.

[0040] Similarly, the signal output from combinational circuit 5008 is combined by combinational circuit 5009 and then input to two-input logical AND 5006. The output from two-input logical AND 5006 is then input to two-input logical OR 5007.

[0041] Thus, the output from FF5001 enters FF5003 via a combinational circuit. Furthermore, the output from FF5003 is input to FF5001 via a combinational circuit. Therefore, because the output FF and the input FF are different, data changes are more likely to occur. As a result, the analysis efficiency of the scan test in logic circuit 1101 is improved, and it is expected that the test time will be shortened.

[0042] Furthermore, according to this embodiment, the logic circuit 1101 does not require the provision of additional observation flip-flops as in the logic circuit 101 described above. Therefore, the number of scan shifts is reduced, the test time is shortened, and there is no concern about an increase in area and leakage power due to the observation flip-flops. In this embodiment, the two-input logical AND and two-input logical OR may be other combinational circuits or composite gate circuits.

[0043] (Second Embodiment) Next, a semiconductor circuit according to the second embodiment will be described. In the following description, components similar to those in the first embodiment will be denoted by the same reference numerals, and detailed explanations will be omitted.

[0044] Figure 6 shows an example of a schematic configuration of a logic circuit when this embodiment is applied. The difference between the logic circuit 2101 according to this embodiment and the logic circuit 1101 according to the first embodiment shown in Figure 5 is that the output portion of the combinational circuit is connected across block circuits. According to the logic circuit 2101 of this embodiment, data is passed between block circuits, which improves the analysis efficiency in scan tests.

[0045] In this embodiment, the logic circuit 2101 includes a selection circuit unit 103 and a combinational input signal control circuit 104 which includes block circuits 600, 610...6m0, 6n0 that operate when selected by the selection circuit unit 103. Here, the relationship between m and n is m = n-1.

[0046] The input signal control circuit 104 is connected to combination circuits 6004, 6008, 6104, 6108...6m04, 6m08, 6n04, 6n08. The selection circuit section 103 is connected to FF6000, 6002 of block circuit 600, FF6100, 6102 of block circuit 610...FF6m00, 6m02 of block circuit 6m0, and FF6n00, 6n02 of block circuit 6n0.

[0047] Furthermore, block circuit 600 includes FF6000, 6001, 6002, 6003, combinational circuits 6004, 6008, and combinational circuits 6005, 6009 which are logical OR for scan testing. Block circuit 6000 also includes logical AND 6006, 6010, and logical OR 6007, 6011. Note that combinational circuits 6005 and 6009 may use exclusive OR or other operations instead of logical OR.

[0048] The output from FF6000 is input to the 2-input OR gate 6007, and the output from the 2-input OR gate 6007 is input to FF6001. Similarly, the output from FF6002 is input to the 2-input OR gate 6011, and the output from the 2-input OR gate 6011 is input to FF6003. In addition, signals for scan test mode are input to the 2-input AND gates 6006 and 6010. Furthermore, FF6001 is connected to combinational circuit 6004, and FF6003 is connected to combinational circuit 6008. The above configuration is the same as the logic circuit 1101 of the first embodiment shown in Figure 5.

[0049] In this embodiment, the signal output from combinational circuit 6004 is combined by combinational circuit 6005 and then input to a two-input logical AND 6110 of another block circuit. The output from the two-input logical AND 6110 is then input to a two-input logical OR 6111. Similarly, the signal output from combinational circuit 6008 is combined by combinational circuit 6009. After that, it is input to the 2-input logical AND 6106 of another block circuit. Then, the output from the 2-input logical AND 6106 is input to the 2-input logical OR 6107.

[0050] Thus, in this embodiment, the output from FF6001 is input to FF6103 via a combinational circuit, and the output from FF6003 is input to FF6101 via a combinational circuit.

[0051] Therefore, the difference between the output flip-flop (FF) and the input FF makes data changes more likely. As a result, the analysis efficiency of the scan test in logic circuit 2101 is improved, and a reduction in test time can be expected.

[0052] Furthermore, according to this embodiment, the logic circuit 2101 does not require the provision of additional observation flip-flops as in the logic circuit 101 described above. Therefore, the number of scan shifts is reduced, the test time is shortened, and there is no concern about an increase in area and leakage power due to the observation flip-flops. In this embodiment, the two-input logical AND and two-input logical OR may be other combinational circuits or composite gate circuits.

[0053] (Third embodiment) Next, a semiconductor circuit according to the third embodiment will be described. In the following description, components similar to those in the first and second embodiments will be denoted by the same reference numerals, and detailed descriptions will be omitted.

[0054] Figure 7 shows an example of a schematic configuration of a logic circuit when this embodiment is applied. As shown in Figure 7, the logic circuit 3101 is provided with a selection circuit section 103 and an input signal control circuit 104 for combinational circuits, which are block circuits 700, 710...7n0 that operate when selected by the selection circuit section 103.

[0055] Furthermore, an FF105 is provided to switch the block circuit multiplexer (hereinafter referred to as Mux) according to a pattern for scan testing. The FF105 employs a circuit configuration that maintains the same value when a clock is input, and the FF105 always outputs 0 when SCANTEST_MODE is 0.

[0056] The selection circuit section 103 is connected to FF7000, 7002 of block circuit 700, FF7100, 7102 of block circuit 710, ... FF7n00, 7n02 of block circuit 7n0. Block circuit 700 also includes FF7000, 7001, 7002, 7003, combinational circuits 7004, 7007, and combinational circuits 7005, 7008 and Mux7006, 7009, which are logical ORs for scan testing. Here, Mux7006 is a first multiplexer that receives a signal output from the fourth combinational circuit and inputs its output to the second flip-flop. Mux7009 is a second multiplexer that receives a signal output from the third combinational circuit and inputs its output to the fourth flip-flop.

[0057] In this embodiment, combinational circuits 7005 and 7008 may employ exclusive OR or the like instead of logical OR. The output from FF7000 is input to the side of Mux7006 where the selection signal is 0, and the output from Mux7006 is input to FF7001. Similarly, the output from FF7002 is input to the side of Mux7009 where the selection signal is 0, and its output is input to FF7003.

[0058] Furthermore, the output from FF105 is input to Mux7006 and 7009 as a selection signal for Mux7006 and 7009. FF7001 is connected to combinational circuit 7004. FF7003 is connected to combinational circuit 7007. The signal output from combinational circuit 7004 is combined by combinational circuit 7005 and then input to the side of Mux7009 where the selection signal is 1. Similarly, the signal output from combinational circuit 7007 is combined by combinational circuit 7008 and then input to the side of Mux7006 where the selection signal is 1.

[0059] In this embodiment, the output from FF7001 is input to FF7003 via a combinational circuit, and the output from FF7003 is input to FF7001 via a combinational circuit.

[0060] Therefore, the difference between the output flip-flop and the input flip-flop makes data changes more likely. As a result, the analysis efficiency of the scan test in logic circuit 3101 is improved, and a reduction in test time can be expected.

[0061] Furthermore, according to this embodiment, the logic circuit 3101 does not require the provision of additional observation flip-flops as in the logic circuit 101 described above. Therefore, the number of scan shifts is reduced, the test time is shortened, and there is no concern about an increase in area and leakage power due to the observation flip-flops. In this embodiment, the two-input logical AND and two-input logical OR may be other combinational circuits or composite gate circuits.

[0062] (Fourth Embodiment) Next, a semiconductor circuit according to the fourth embodiment will be described. In the following description, components similar to those in the first to third embodiments will be denoted by the same reference numerals, and detailed descriptions will be omitted.

[0063] Figure 8 shows an example of a schematic configuration of a logic circuit when this embodiment is applied. As shown in Figure 8, the logic circuit 4101 includes a selection circuit section 103, block circuits 800, 810...8m0, 8n0 that operate when selected by the selection circuit section 103, and an input signal control circuit 104 for the combinational circuit. The relationship between m and n is m = n-1.

[0064] Additionally, an FF105 is provided to switch the Mux of the block circuit according to a pattern for scan testing. The FF105 employs a circuit configuration that maintains the same value when a clock is input, and the FF105 always outputs 0 when SCANTEST_MODE is 0.

[0065] The selection circuit section 103 is connected to FF8000 and 8002 of block circuit 800, FF8100 and 8102 of block circuit 810, ... FF8m00 and 8m02 of block circuit 8m0, and FF8n00 and 8n02 of block circuit 8n0.

[0066] Furthermore, the block circuit 800 includes FF8000, 8001, 8002, and 8003, combinational circuits 8004 and 8007, and combinational circuits 8005, 8008 and Mux8006 and 8009, which are logical OR circuits for scan testing.

[0067] In this embodiment, combinational circuits 8005 and 8008 may employ exclusive OR or other operations instead of logical OR. The output from FF8000 is input to the side of Mux8006 where the selection signal is 0, and the output from Mux8006 is input to FF8001. Similarly, the output from FF8002 is input to the side of Mux8009 where the selection signal is 0, and the output from Mux8009 is input to FF8003. In addition, the output from FF105 is input to Mux8006 and 8009 as the selection signal for Mux8006 and 8009. Furthermore, FF8001 is connected to combinational circuit 8004, and FF8003 is connected to combinational circuit 8007. The above configuration is the same as the logic circuit 3101 of the third embodiment shown in Figure 7.

[0068] In the logic circuit 4101 according to this embodiment, the signal output from combinational circuit 8004 is combined by combinational circuit 8005 and then input to the side of the next block circuit where the selection signal of Mux8109 is 1. Similarly, the signal output from combinational circuit 8007 is combined by combinational circuit 8008 and then input to the side of the next block circuit where the selection signal of Mux8106 is 1.

[0069] In this embodiment, the output from FF8001 is input to FF8103 via a combinational circuit, and the output from FF8003 is input to FF8101 via a combinational circuit. Similarly, the output from FF8101 is input to FF8003 via a combinational circuit, and the output from FF8103 is input to FF8001 via a combinational circuit.

[0070] Mux8106 is the first multiplexer, receiving a signal output from the fourth combinational circuit of the first logic circuit block, and its output is fed into the second flip-flop of the second logic circuit block. Mux8109 is the second multiplexer, receiving a signal output from the third combinational circuit of the first logic circuit block, and its output is fed into the fourth flip-flop of the second logic circuit block. Mux8009 is the third multiplexer, receiving a signal output from the third combinational circuit of the second logic circuit block, and its output is fed into the fourth flip-flop of the first logic circuit block. Mux8006 is the fourth multiplexer, receiving a signal output from the fourth combinational circuit of the second logic circuit block, and its output is fed into the second flip-flop of the first logic circuit block.

[0071] Therefore, the difference between the output flip-flop (FF) and the input FF makes data changes more likely. As a result, the analysis efficiency of the scan test in logic circuit 4101 is improved, and a reduction in test time can be expected.

[0072] Furthermore, according to this embodiment, the logic circuit 4101 does not require the provision of additional observation flip-flops as in the logic circuit 101 described above. Therefore, the number of scan shifts is reduced, the test time is shortened, and there is no concern about an increase in area and leakage power due to the observation flip-flops. In this embodiment, the two-input logical AND and two-input logical OR may be other combinational circuits or composite gate circuits.

[0073] (Fifth embodiment) Next, a semiconductor device according to the fifth embodiment will be described. Any of the semiconductor circuits of the first to fourth embodiments can be applied to the semiconductor device of the fifth embodiment. Figure 9 is a schematic diagram illustrating a device 9191 equipped with the semiconductor device 930 of this embodiment. The device 9191 equipped with the semiconductor device 930 will be described in detail. As described above, the semiconductor device 930 may include a semiconductor device 910 having a semiconductor layer 10, as well as a package 920 that houses the semiconductor device 910. The package 920 may include a substrate to which the semiconductor device 910 is fixed, and a lid such as glass facing the semiconductor device 910. The package 920 may further include bonding members such as bonding wires or bumps that connect terminals provided on the substrate and terminals provided on the semiconductor device 910.

[0074] The device 9191 may include at least one of the following: an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The component 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, shutter, or mirror. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0075] The processing unit 960 is a signal processing unit that processes signals output from the semiconductor device 930. The processing unit 960 is a semiconductor device such as a CPU or ASIC that constitutes an AFE (analog front end) or DFE (digital front end). The display device 970 is an EL display device or liquid crystal display device that displays information (images) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or semiconductor device that stores the information (images) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or a hard disk drive.

[0076] The mechanical device 990 has movable parts or propulsion parts such as motors and engines. The device 9191 displays signals output from the semiconductor device 930 on the display device 970 or transmits them to the outside using a communication device (not shown) provided in the device 9191. For this purpose, it is preferable that the device 9191 further includes a storage device 980 and a processing device 960, separate from the memory circuits and arithmetic circuits of the semiconductor device 930. The mechanical device 990 may be controlled based on signals output from the semiconductor device 930.

[0077] Furthermore, the device 9191 is suitable for electronic devices such as information terminals with shooting capabilities (e.g., smartphones and wearable devices) and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). In a camera, the mechanical device 990 can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in a camera can move the semiconductor device 930 for vibration damping.

[0078] Furthermore, the device 9191 may be a transport device such as a vehicle, ship, or aircraft. The mechanical device 990 in the transport device may be used as a mobile device. The device 9191 as a transport device is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) through its imaging function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing to operate the mechanical device 990 as a mobile device based on information obtained from the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring instrument such as a distance sensor, an analytical instrument such as an electron microscope, office equipment such as a copier, or industrial equipment such as a robot.

[0079] According to the fifth embodiment described above, good pixel characteristics can be obtained. Therefore, the value of the semiconductor device 930 can be increased. Increasing the value here means at least one of the following: addition of functions, improvement of performance, improvement of characteristics, improvement of reliability, improvement of manufacturing yield, reduction of environmental impact, cost reduction, miniaturization, and weight reduction.

[0080] Therefore, by using the semiconductor device 930 according to the fifth embodiment in the device 9191, the value of the device can also be improved. For example, by mounting the semiconductor device 930 on a transport device, excellent performance can be obtained when taking external images of the transport device or measuring the external environment. Therefore, when manufacturing and selling transport devices, deciding to mount the semiconductor device 930 according to the fifth embodiment on the transport device is advantageous in improving the performance of the transport device itself. In particular, the semiconductor device 930 is suitable for transport devices that use information obtained from the semiconductor device 930 to assist in the operation of the transport device and / or to perform automatic operation.

[0081] The embodiments described above can be modified as appropriate without departing from the technical concept. Yes. Furthermore, the disclosures in this specification include not only what is written herein, but also all matters that can be understood from this specification and the drawings attached herein. In addition, the disclosures in this specification include the complement of the concepts written herein. That is, if this specification states, for example, that "A is greater than B", then even if the statement that "A is not greater than B" is omitted, this specification can be said to disclose that "A is not greater than B". This is because, when it states that "A is greater than B", it is assumed that the case where "A is not greater than B" is being considered.

[0082] This embodiment includes the following configuration. (Composition 1) A scan test circuit comprising logic circuits and analog circuits, The logic circuit comprises a selection circuit and a plurality of logic circuit blocks to which the selection signal of the selection circuit is input. Each of the plurality of logic circuit blocks comprises a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, a first combinational circuit, and a second combinational circuit, and operates when a selection signal is input to the selection circuit. The selection circuit is connected to the first flip-flop and the third flip-flop, The first flip-flop and the second flip-flop are connected, The third flip-flop and the fourth flip-flop are connected, The second flip-flop is connected to the first combinational circuit, The first combination circuit is connected to the analog circuit by a plurality of signal lines, The plurality of signal lines connected to the first combination circuit are connected to the third combination circuit. The fourth flip-flop is connected to the second combinational circuit, The second combination circuit is connected to the analog circuit by multiple signal lines, The plurality of signal lines connected to the second combination circuit are connected to the fourth combination circuit. The third combinational circuit is connected to the fourth flip-flop, The fourth combinational circuit is connected to the third flip-flop. A scan test circuit characterized by the following features. (Configuration 2) In the first and second logic circuit blocks, which are adjacent to each other among the plurality of logic circuit blocks, The third combinational circuit of the first logic circuit block is connected to the fourth flip-flop of the second logic circuit block. The fourth combinational circuit of the first logic circuit block is connected to the second flip-flop of the second logic circuit block. The scan test circuit according to configuration 1, characterized by the above. (Composition 3) In the first and second logic circuit blocks, which are adjacent to each other among the plurality of logic circuit blocks, The third combinational circuit of the second logic circuit block is connected to the fourth flip-flop of the first logic circuit block. The fourth combinational circuit of the second logic circuit block is connected to the second flip-flop of the first logic circuit block. The scan test circuit according to configuration 1, characterized by the above. (Composition 4) The signal output from the fourth combination circuit is input to the first multiplexer. The output of the first multiplexer is input to the second flip-flop, and the first multiplexer, A second multiplexer to which the signal output from the third combination circuit is input, and the output of the second multiplexer is input to the fourth flip-flop, A flip-flop for switching between the first multiplexer and the second multiplexer, The scan test circuit according to configuration 1, further comprising the above. (Composition 5) A first multiplexer to which the signal output from the fourth combinational circuit of the first logic circuit block is input, wherein the output of the first multiplexer is input to the second flip-flop of the second logic circuit block, A second multiplexer to which a signal output from the third combinational circuit of the first logic circuit block is input, wherein the output of the second multiplexer is input to the fourth flip-flop of the second logic circuit block, A flip-flop for switching between the first multiplexer and the second multiplexer, The scan test circuit according to configuration 2 or 3, further comprising: (Composition 6) A third multiplexer to which a signal output from the third combinational circuit of the second logic circuit block is input, wherein the output of the third multiplexer is input to the fourth flip-flop of the first logic circuit block, A fourth multiplexer to which the signal output from the fourth combinational circuit of the second logic circuit block is input, wherein the output of the fourth multiplexer is input to the second flip-flop of the first logic circuit block, It further possesses, The flip-flop switches between the third multiplexer and the fourth multiplexer. The scan test circuit according to configuration 5, characterized by the following features. (Composition 7) A photoelectric converter comprising a plurality of pixels arranged across multiple rows and columns, and a vertical scanning circuit that scans the plurality of pixels row by row, wherein the vertical scanning circuit has a scan test circuit as described in any of configurations 1 to 5. (Composition 8) A photoelectric converter comprising a plurality of pixels arranged across multiple rows and multiple columns, a plurality of column circuits arranged corresponding to the plurality of columns, and a horizontal scanning circuit that scans the plurality of column circuits in column units, wherein the horizontal scanning circuit has a scan test circuit as described in any of configurations 1 to 5. (Composition 9) A device comprising a semiconductor device having a scan test circuit as described in any of configurations 1 to 6, Optical device corresponding to the aforementioned semiconductor device, Control device for controlling the aforementioned semiconductor device, A signal processing device that processes the signal output from the semiconductor device, A display device that displays information obtained by the aforementioned semiconductor device, A memory device for storing information obtained by the aforementioned semiconductor device, and The apparatus is characterized by further comprising at least one of the following: a mechanical device that operates based on information obtained from the semiconductor device. [Explanation of Symbols]

[0083] 11 Scan test circuit, 1101 Logic circuit, 102 Analog circuit, 5n00, 5n01, 5n02, 5n03 FF, 5n04, 5n05, 5n08, 5n09 Combination circuit

Claims

1. A scan test circuit comprising logic circuits and analog circuits, The logic circuit comprises a selection circuit and a plurality of logic circuit blocks to which the selection signal of the selection circuit is input. Each of the plurality of logic circuit blocks comprises a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, a first combinational circuit, and a second combinational circuit, and operates when a selection signal is input to the selection circuit. The selection circuit is connected to the first flip-flop and the third flip-flop, The first flip-flop and the second flip-flop are connected, The third flip-flop and the fourth flip-flop are connected, The second flip-flop is connected to the first combinational circuit, The first combination circuit is connected to the analog circuit by a plurality of signal lines, The plurality of signal lines connected to the first combination circuit are connected to the third combination circuit. The fourth flip-flop is connected to the second combinational circuit, The second combination circuit is connected to the analog circuit by a plurality of signal lines. The plurality of signal lines connected to the second combination circuit are connected to the fourth combination circuit. The third combinational circuit is connected to the fourth flip-flop, The above fourth combinational circuit is connected to the above third flip-flop. A scan test circuit characterized by the following features.

2. In the first and second logic circuit blocks, which are adjacent to each other among the plurality of logic circuit blocks, The third combinational circuit of the first logic circuit block is connected to the fourth flip-flop of the second logic circuit block. The fourth combinational circuit of the first logic circuit block is connected to the second flip-flop of the second logic circuit block. The scan test circuit according to feature 1.

3. In the first and second logic circuit blocks, which are adjacent to each other among the plurality of logic circuit blocks, The third combinational circuit of the second logic circuit block is connected to the fourth flip-flop of the first logic circuit block. The fourth combinational circuit of the second logic circuit block is connected to the second flip-flop of the first logic circuit block. The scan test circuit according to feature 1.

4. A first multiplexer receives the signal output from the fourth combinational circuit and its output is input to the second flip-flop, A second multiplexer receives the signal output from the third combinational circuit and its output is input to the fourth flip-flop, A flip-flop for switching between the first multiplexer and the second multiplexer, The scan test circuit according to claim 1, further comprising the above.

5. The signal output from the fourth combinational circuit of the first logic circuit block is input. A first multiplexer wherein the output of the first multiplexer is input to the second flip-flop of the second logic circuit block, A second multiplexer to which a signal output from the third combinational circuit of the first logic circuit block is input, wherein the output of the second multiplexer is input to the fourth flip-flop of the second logic circuit block, A flip-flop for switching between the first multiplexer and the second multiplexer, The scan test circuit according to claim 2 or 3, further comprising the above.

6. A third multiplexer to which a signal output from the third combinational circuit of the second logic circuit block is input, wherein the output of the third multiplexer is input to the fourth flip-flop of the first logic circuit block, A fourth multiplexer to which the signal output from the fourth combinational circuit of the second logic circuit block is input, wherein the output of the fourth multiplexer is input to the second flip-flop of the first logic circuit block, It further possesses, The flip-flop switches between the third multiplexer and the fourth multiplexer. The scan test circuit according to claim 5.

7. A photoelectric converter comprising a plurality of pixels arranged across multiple rows and multiple columns, and a vertical scanning circuit that scans the plurality of pixels row by row, wherein the vertical scanning circuit has the scan test circuit described in claim 1.

8. A photoelectric converter comprising a plurality of pixels arranged across multiple rows and multiple columns, a plurality of column circuits arranged corresponding to the plurality of columns, and a horizontal scanning circuit that scans the plurality of column circuits in column units, wherein the horizontal scanning circuit has the scan test circuit described in claim 1.

9. A device comprising a semiconductor device having a scan test circuit as described in claim 1, Optical device corresponding to the aforementioned semiconductor device, Control device for controlling the aforementioned semiconductor device, A signal processing device that processes the signal output from the semiconductor device, A display device that displays information obtained by the aforementioned semiconductor device, A memory device for storing information obtained by the aforementioned semiconductor device, and The apparatus is characterized by further comprising at least one of the following: a mechanical device that operates based on information obtained from the semiconductor device.

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