Chemical mechanical planarization method and apparatus in semiconductor manufacturing processes

Abstract

This invention provides a chemical mechanical planarization method and apparatus for semiconductor manufacturing processes to achieve planarization. [Solution] According to one embodiment of the present invention, the technical gist of the present invention is a chemical mechanical planarization method in a semiconductor manufacturing process, which involves applying an electric field to the wafer surface using electrophoretic phenomena during a CMP (Chemical Mechanical Planarization) process to control the distribution of charged particles in a slurry, and a chemical mechanical planarization apparatus for a semiconductor manufacturing process, which includes CMP equipment for performing a CMP process to planarize the wafer surface, and an electric field application control unit for applying an electric field to the wafer surface during the CMP process.

Description

[Technical Field]

[0001] The present invention relates to a chemical mechanical planarization method and apparatus in a semiconductor manufacturing process, and more particularly to a chemical mechanical planarization method and apparatus in a semiconductor manufacturing process that uses electrophoretic phenomena to control wafer surface planarization and etching rate.

[0002] The following national research and development projects supported this invention:

[0003] Project-specific number: 1711183984 Project number 2023M3H3A1059080 Ministry / Agency: Science and Technology Information and Communications Agency Project Management (Specialized) Institution: Korea Research Foundation Research project name: Source Technology Development Project Research Project Title: Construction of a Quantum Device Manufacturing Infrastructure Based on General-Purpose Equipment Project implementing organization: Korea Nanotechnology Institute Research period: August 7, 2020 - December 31, 2025 [Background technology]

[0004] Semiconductor chips used in quantum technology require extremely high levels of accuracy and reliability. In particular, in fields such as quantum computing or quantum communications, the surface flatness of the semiconductor chip significantly impacts signal transmission speed and energy loss.

[0005] Here, the chemical mechanical planarization (CMP) process is an essential step in semiconductor chip manufacturing, playing a role in removing non-uniform surfaces between layers in multilayer semiconductor devices and making them flat.

[0006] In particular, unlike general semiconductor devices, quantum devices have fine patterns and structures, so a higher level of CMP (Chemical Manufacturing Process) is required to minimize surface non-uniformity. Also, if the surface of the metal wiring layer used in quantum devices is not uniform, the current flow will become unstable during signal transmission.

[0007] The CMP process required for quantum technology chips is centered on reducing problems such as dishing and erosion. Disshing is a phenomenon in which the metal wiring layer is polished too much, causing indentations, while erosion is a phenomenon in which the dielectric material other than the target material is unintentionally eroded, reducing surface uniformity.

[0008] Figure 1(a) is a schematic diagram showing the profile of a semiconductor device before the conventional CMP process, Figure 1(b) is a schematic diagram showing the surface after the ideal CMP process, and Figure 1(c) is a schematic diagram showing the dishing and corrosion phenomena that occur during the CMP process.

[0009] Such dishing and corrosion phenomena can interfere with the fine structure and signal transmission accuracy of quantum devices. Furthermore, unlike conventional semiconductor devices, the CMP process in quantum technology requires more precise planarization, making control of the initial topography and the chemical composition of the polishing solution (Slurry) extremely important.

[0010] Thus, in semiconductor devices for quantum technology, extremely precise planarization is required, and dishing due to excessive polishing of the metal layer during the CMP process can be a major problem. If dishing occurs, the thickness of the metal wiring becomes uneven, distorting the signal transmission path and potentially leading to a decrease in the performance of the quantum device.

[0011] In addition, erosion where the insulating layer that is not the target substance is excessively etched damages the surface uniformity and destabilizes the electrical characteristics of the quantum device. This may increase the energy loss during signal transmission and inhibit the accuracy of high-performance quantum computing systems.

[0012] Also, if the initial topography is not uniform, the surface uniformity may not be sufficiently ensured even after the CMP process. In particular, the fine structure of quantum technology elements is sensitive to such non-uniformity.

[0013] In addition, problems of oxidation or contamination may occur during the wafer transfer process of the CMP process, which may affect the electrical characteristics particularly important in quantum devices and may lead to a decrease in process quality.

[0014] Therefore, in the semiconductor manufacturing process, it can be said that improving the CMP process to maintain low dishing and low erosion, and solving the problems of oxidation or contamination between processes are important problems to be solved.

Summary of the Invention

Problems to be Solved by the Invention

[0015] An object of the present invention is to provide a chemical mechanical planarization method and apparatus in a semiconductor manufacturing process for improving the CMP process in the semiconductor manufacturing process to minimize problems of dishing and erosion, and achieving planarization by applying an electric field to the wafer surface using the electrophoresis phenomenon to control the distribution of charged particles in the slurry.

[0016] Another object is to provide a chemical mechanical planarization method and apparatus in a semiconductor manufacturing process for solving the problems of oxidation and contamination that may occur during the process where the CMP process and the plating process are continuously performed.

Means for Solving the Problems

[0017] According to an embodiment of the present invention, there is provided a chemical mechanical planarization method in a semiconductor manufacturing process, which uses electrophoresis phenomenon during a CMP (Chemical Mechanical Planarization) process to apply an electric field to the wafer surface to control the distribution of charged particles in the slurry. The technical essence is a chemical mechanical planarization method in a semiconductor manufacturing process.

[0018] Further, the present invention provides a chemical mechanical planarization apparatus for a semiconductor manufacturing process, which includes a CMP equipment for performing a CMP process to planarize the wafer surface and an electric field application control unit for applying an electric field to the wafer surface during the CMP process. Another technical essence is a chemical mechanical planarization apparatus in a semiconductor manufacturing process.

[0019] Preferably, the electric field is applied perpendicular to the wafer surface, and the distribution of ions in the slurry is changed by the potential difference between the metal and the insulator to adjust the local etching rate of the metal surface.

[0020] Further, by applying the electric field, ions having negative or positive charges in the slurry can be concentrated on the metal surface to reduce the etching rate of the metal.

[0021] After the CMP process, a plating process is performed. After the CMP process and the plating process, the uniformity of the wafer surface is measured. If it is below the standard, additional plating processes and CMP processes can be repeatedly performed. The plating process can include at least one of an electrolytic plating process or an electroless plating process.

[0022] Also, when the height difference (h0 - h1) of the wafer surface is measured to be below the standard after the plating process and the CMP process, if the α coefficient (w up / w original , the ratio of the surface widths before and after plating) is 0.99 or less, the plating process can be stopped and the CMP process can be performed.

[0023] Furthermore, by applying a voltage to the wafer surface to prevent current from flowing and creating an electric field, the movement of charged particles in the slurry can be adjusted, thereby controlling the etching rate of the wafer surface.

[0024] Furthermore, by applying an electric current to the wafer surface via a conductive substrate to form a potential difference and create an electric field, the etching rate of the wafer surface can be adjusted.

[0025] Furthermore, negatively charged ions in the slurry can be concentrated on the metal surface by electrophoresis, thereby reducing the rate of metal etching.

[0026] Furthermore, in the semiconductor process, the chemical mechanical planarization method can be carried out in an inert gas atmosphere during the CMP process.

[0027] Furthermore, the process includes a standby phase in which no electric field is applied, and the electric field application phase and the standby phase can be repeated periodically.

[0028] Furthermore, the distribution of the electric field can be controlled to have symmetrical non-uniformity with respect to the center of the wafer surface.

[0029] Furthermore, the etching rate can be adjusted by applying a differential electric field to regions with high and low metal area density.

[0030] Furthermore, an electroless plating process can be additionally performed on a specific area of ​​the wafer surface.

[0031] Furthermore, after the electroless plating process, mechanical polishing can be performed on the wafer surface.

[0032] Furthermore, quantum superconductor materials used in semiconductor devices for quantum technology can be one or more of the following: Nb, Sn, Al, Zn, Ta, Nb-Ti, Nb3Sn, V3Si, V3Ga, Nb3Ge, MgB2, YBCO, BSCCO, Iron Pnictides, LBCO, Iron Chalcogenides, TBCCO, Hg-1223, and Iron-Based Superconductors. [Effects of the Invention]

[0033] According to embodiments of the present invention, the etching rate on the wafer surface can be locally adjusted by applying an electric field or electric current to control the distribution of charged particles in the slurry. Therefore, excessive dishing and erosion can be minimized in the CMP process, and uniform surface planarization can be achieved.

[0034] Furthermore, by controlling the charged particles (cations and anions) present in the slurry with an electric field or electric current, they can be concentrated on specific parts of the wafer surface. Therefore, the etching rate of metals and insulators can be adjusted, and only the desired areas can be selectively planarized.

[0035] Furthermore, oxidation of the wafer surface can be prevented by carrying out the process in an inert gas atmosphere or by introducing an insulator. This prevents oxidation of the metal wiring layer and subsequent deterioration of its electrical properties, thereby improving process quality.

[0036] Furthermore, by adjusting the application period, which involves periodically applying and controlling an electric field, unnecessary etching during the CMP process can be prevented, and materials can be efficiently removed. In addition, if the uniformity of the wafer surface is measured to be below a certain standard, the number of repetitions of the CMP and plating processes can be reduced, thereby increasing productivity.

[0037] Furthermore, the electric field in a specific region can be locally concentrated by using a conductive plate containing an insulator or by a current application method. Therefore, complex patterns and height differences in specific regions can be effectively reduced and flattened.

[0038] Furthermore, by controlling the symmetry and intensity of the electric field distribution, it is possible to apply differential electric fields to regions with high and low metal area density. Therefore, it is possible to adjust the local etching rate while maintaining uniformity across the entire wafer surface.

[0039] Thus, according to one embodiment of the present invention, high-quality quantum devices can be manufactured by improving the CMP process to minimize the problems of dishing and erosion, and by improving the flatness of the wafer surface.

[0040] Furthermore, it is possible to solve the problems of oxidation and contamination that may occur during the continuous CMP and plating processes, and improve productivity through an automated transfer system between processes and precise process control.

[0041] Therefore, since high-quality quantum elements can be manufactured, superior performance can be provided in high-precision application fields such as quantum computers and quantum communication. [Brief explanation of the drawing]

[0042] [Figure 1] (a) is a schematic diagram showing the profile of a semiconductor device before the conventional CMP process. (b) is a schematic diagram showing the surface after the ideal CMP process. (c) is a schematic diagram showing the phenomena of dishing and corrosion that occur during the CMP process. [Figure 2] This is a schematic diagram illustrating the principle of electrophoresis according to one embodiment of the present invention. [Figure 3] This is a block diagram of a chemical mechanical planarization method in a semiconductor manufacturing process according to one embodiment of the present invention. [Figure 4] Figure 3 is a schematic diagram of the process according to the embodiment. [Figure 5] This is a block diagram of a chemical mechanical planarization method in a semiconductor manufacturing process according to another embodiment of the present invention. [Figure 6] Figure 5 is a schematic diagram of the process according to the embodiment. [Figure 7] This is a block diagram of a chemical mechanical planarization method in a semiconductor manufacturing process according to another embodiment of the present invention. [Figure 8] This is a schematic diagram showing the profile of a semiconductor device according to one embodiment of the present invention. [Figure 9] A schematic diagram of the main parts of a chemical mechanical planarization apparatus in a semiconductor manufacturing process according to one embodiment of the present invention. [Figure 10] This is a schematic diagram showing various embodiments of applying an electric field to a wafer in a chemical mechanical planarization apparatus used in a semiconductor manufacturing process according to one embodiment of the present invention. [Modes for carrying out the invention]

[0043] The present invention relates to a chemical mechanical planarization method and apparatus in a semiconductor manufacturing process, which improves the CMP process to minimize the problems of dishing and erosion, achieve high planarization, and further solve the problems of oxidation and contamination that may occur during the continuous operation of the CMP process and the plating process.

[0044] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. Figure 2 is a schematic diagram illustrating the principle of electrophoresis according to one embodiment of the present invention, Figure 3 is a block diagram of a chemical mechanical planarization method in a semiconductor manufacturing process according to one embodiment of the present invention, Figure 4 is a schematic diagram of the process according to the embodiment of Figure 3, Figure 5 is a block diagram of a chemical mechanical planarization method in a semiconductor manufacturing process according to another embodiment of the present invention, Figure 6 is a schematic diagram of the process according to the embodiment of Figure 5, Figure 7 is a block diagram of a chemical mechanical planarization method in a semiconductor manufacturing process according to another embodiment of the present invention, Figure 8 is a schematic diagram showing the profile of a semiconductor element according to one embodiment of the present invention, Figure 9 is a schematic diagram of the main part of a chemical mechanical planarization apparatus in a semiconductor manufacturing process according to one embodiment of the present invention, and Figure 10 is a diagram showing a chemical mechanical planarization apparatus in a semiconductor manufacturing process according to one embodiment of the present invention, and is a schematic diagram showing various embodiments of applying an electric field to a wafer.

[0045] As shown in Figures 2 to 7, the chemical mechanical planarization method in a semiconductor manufacturing process according to an embodiment of the present invention involves applying an electric field to the wafer surface using the electrophoretic phenomenon during the CMP (Chemical Mechanical Planarization) process to control the distribution of charged particles in the slurry.

[0046] Furthermore, as shown in Figures 2 to 7, the chemical mechanical planarization apparatus in the semiconductor manufacturing process according to an embodiment of the present invention includes a CMP equipment for performing a CMP process to planarize the wafer surface, and an electric field application control unit for applying an electric field to the wafer surface during the CMP process.

[0047] Therefore, the present invention can minimize dishing and corrosion phenomena in the CMP process and achieve uniform planarization of the wafer surface. Furthermore, oxidation and contamination that may occur during the process can be prevented by repeating the electric field application and waiting phases, the electrolytic / electroless plating process, and the supply of an inert gas. Thus, high-quality manufacturing of quantum devices is possible, and excellent performance can be provided in application fields such as quantum computers and quantum communications, including high-speed signal transmission and reduced energy loss.

[0048] According to an embodiment of the present invention, the distribution of charged particles in the slurry can be controlled by applying an electric field to the wafer surface using electrophoresis during the CMP (Chemical Mechanical Planarization) process. This involves adjusting the distribution of charged particles in the slurry by applying an electric field to the wafer surface and controlling the etching rate. In other words, by applying an electric field to the wafer surface, the high level of planarization required for quantum devices can be achieved.

[0049] Chemical Mechanical Planarization (CMP) is used in semiconductor manufacturing processes to flatten multilayer wafers. It involves polishing the wafer surface with a polishing pad and slurry (an abrasive containing fine particles). Here, charged particles (cations, anions, etc.) in the slurry move in response to an electric field; this phenomenon is called electrophoresis. By applying an electric field to the wafer surface, the charged particles in the slurry move, allowing for increased or decreased polishing speed in specific areas. This phenomenon allows for adjustment of the etching rate in specific areas of the wafer, resulting in a uniform surface.

[0050] For example, if there is a large height difference between the area where the metal layer needs to be planarized and the insulating layer, an electric field can be applied to induce concentrated etching of the metal layer. This minimizes problems that commonly occur in CMP processes, such as dishing and erosion.

[0051] Figure 2 is a schematic diagram illustrating the principle of electrophoresis according to one embodiment of the present invention, showing the process of adjusting the distribution of charged particles in a slurry by applying an electric field during the chemical mechanical planarization (CMP) process in semiconductor manufacturing. In other words, it describes a method of controlling the etching rate of the wafer surface using the electrophoretic phenomenon in order to effectively perform planarization in the CMP process.

[0052] As shown in the figure, an electric field is formed on the wafer surface, and this electric field induces the movement of charged particles in the slurry. To generate the electric field, a voltage is applied between the wafer surface and the structure located beneath it. The potential difference is approximately 1V, and the electric field acting on the wafer surface is calculated to be approximately 10,000 V / m. This electric field plays a role in inducing the movement of charged particles in the slurry. That is, the strength of the electric field is 10,000 V / m, and this value was calculated based on a potential difference with a height difference of 100 μm on the wafer surface. The electric field strength is 10,000 V / m, and the distance is 10 -4 Since the thickness is m (100 μm), the potential difference is calculated to be 1 V.

[0053] The slurry contains particles with both positive (+) and negative (-) charges. In the diagram, positively charged particles (+) are shown in red and negatively charged particles (-) are shown in blue. Due to the influence of the electric field, positively charged particles move towards the (-) electrode, and negatively charged particles move towards the (+) electrode. This movement of particles changes the distribution of charged particles in the slurry, thereby adjusting the etching rate at specific locations.

[0054] The diagram also shows that the electric field is applied vertically. A vertical electric field is generated between the wafer surface and the electrode below it, and this electric field plays a crucial role in controlling the local etching rate of the wafer surface. The potential difference provides the energy necessary for the etching and polishing processes of the wafer surface, and as the potential difference increases or decreases, the movement of charged particles becomes faster or slower.

[0055] In this way, positively and negatively charged particles in the slurry are distributed to the wafer surface by the electric field, thereby controlling the etching rate. As positively charged particles move towards the (-) electrode and negatively charged particles move towards the (+) electrode, the concentration and distribution of charged particles in the slurry begin to affect the wafer surface.

[0056] A localized potential difference is formed on the wafer surface by an electric field, thereby controlling the etching rate in each region. This is used as a method to adjust the degree of etching and planarization in specific areas of the wafer surface, and by controlling the local etching rate, problems such as dishing and erosion can be solved.

[0057] Furthermore, if the overall distribution is uniform or formed to have a specific pattern, the etching rate of the wafer surface is also adjusted accordingly. Thus, non-uniformity of the wafer surface can be reduced and the degree of planarization can be optimized.

[0058] Furthermore, according to one embodiment of the present invention, the electric field is applied perpendicularly to the wafer surface, and the potential difference between the metal and the insulator changes the ion distribution in the slurry, thereby adjusting the local etching rate of the metal surface.

[0059] An electric field applied perpendicular to the wafer surface generates a potential difference between the metal and the insulator. This potential difference induces the movement of charged particles in the slurry, thereby regulating the polishing speed on the surface. The potential difference between the metal layer and the insulating layer guides specific ions to specific regions, thereby increasing or decreasing the polishing speed in those areas. Thus, the surface height can be precisely controlled.

[0060] For example, if polishing of the metal surface is more necessary than polishing of the insulator, the potential difference is increased to concentrate the charged particles in the slurry on the metal surface. This increases the etching rate of the metal surface and decreases the etching rate of the insulator, thereby enabling more effective planarization.

[0061] Furthermore, according to embodiments of the present invention, the rate of metal etching is reduced by concentrating positively or negatively charged ions in the slurry on the metal surface through the application of an electric field.

[0062] In the CMP process, the concentration of negatively or positively charged ions in the slurry significantly affects the surface etching rate. By applying an electric field, specific ions can be concentrated on the metal surface of the wafer, thereby adjusting the etching rate of the metal layer. This effectively prevents surface dishing and reduces excessive etching.

[0063] For example, when polishing a copper (Cu) metal layer, if positively charged ions are concentrated in the slurry, chemical reactions on the metal surface are suppressed, resulting in a lower etching rate. Therefore, it is possible to control the etching process so that the metal layer is not excessively etched.

[0064] Furthermore, according to an embodiment of the present invention, a plating process is performed after the CMP process, and then the uniformity of the wafer surface is measured. If it falls below a standard, additional plating and CMP processes are repeated.

[0065] If surface planarization cannot be sufficiently achieved in the CMP process due to problems such as dishing or corrosion, the height difference on the wafer surface is compensated for by the plating process, and the final flatness of the wafer surface is improved by repeating the CMP process.

[0066] This has the effect of improving the signal transmission efficiency and electrical characteristics of semiconductor devices. For example, if the metal wiring layer is unevenly etched after the CMP process, the wafer surface is realigned by additional plating and then uniformly polished again by CMP.

[0067] Furthermore, according to embodiments of the present invention, the plating process includes at least one of electrolytic plating or electroless plating.

[0068] Electrolytic plating is a process that uses electric current to deposit metal ions onto the wafer surface, offering the advantage of rapidly depositing a thick metal layer. On the other hand, electroless plating is a process that uses chemical reactions to reduce metal ions and deposit them onto the surface without electric current, enabling uniform plating. By selecting the appropriate method from these two, plating can be performed depending on the planar state of the wafer surface.

[0069] For example, electrolytic plating is used when the thickness of a metal wiring layer needs to be increased rapidly, while electroless plating is used when a uniform plating layer is required.

[0070] Furthermore, according to the embodiment of the present invention, if the height difference (h0-h1) of the wafer surface is measured to be below a standard after the CMP process and the plating process, the alpha coefficient (w up / w original When the value is 0.99 or less, the plating process is stopped and the CMP process is carried out.

[0071] The alpha coefficient represents the ratio of the surface width before and after plating. When this ratio is 0.99 or less, it indicates that surface planarization is complete and no further plating is required. At this point, the plating process is stopped and the process is switched to the CMP (Chemical Polishing) process to improve process efficiency. This minimizes surface dishing and corrosion, and optimizes the flatness of the wafer surface during repeated processes.

[0072] Furthermore, according to an embodiment of the present invention, an electric field is formed by applying a voltage to prevent current from flowing, thereby regulating the movement of charged particles in the slurry.

[0073] By applying a voltage instead of electric current to create an electric field, the movement of charged particles within the slurry is controlled. This method avoids direct current effects on the surface, thus preventing electrical damage during the etching process. Furthermore, the etching rate can be adjusted for specific regions (see Figures 10(a), 10(b), and 10(C)).

[0074] Furthermore, according to embodiments of the present invention, an electric potential is formed by applying a current to the wafer surface via a conductive substrate, thereby creating an electric field. By directly applying a current to the wafer surface using a conductive substrate, a surface potential can be formed and an electric field can be created. This is effective for locally adjusting the etching rate in a specific region by adjusting the electric field (see Figure 10(d)).

[0075] Furthermore, according to embodiments of the present invention, negatively charged ions in the slurry can concentrate on the metal surface by electrophoresis, thereby reducing the rate of metal etching.

[0076] In the CMP process, the type and distribution of charged particles in the slurry significantly affect the surface etching rate. By applying an electric field to control the concentration of negatively charged ions in the slurry on the metal surface, excessive etching of the metal layer is prevented. This method is effective in preventing excessive polishing of the metal layer and minimizing the dishing phenomenon. Therefore, it is possible to prevent unnecessary etching while maintaining a uniform metal layer.

[0077] For example, by applying an electric field to an exposed metal surface, negatively charged ions in the slurry can be concentrated, thereby suppressing chemical reactions on the metal surface and reducing the etching rate.

[0078] Furthermore, according to one embodiment of the present invention, the CMP process is carried out in an inert gas atmosphere to prevent oxidation of the wafer surface. Negative effects such as oxidation of the wafer surface can occur. To prevent this, the process is carried out in an inert gas atmosphere (e.g., argon, helium, nitrogen), which blocks contact with oxygen and prevents oxidation and contamination of the metal layer. Thus, the planar state of the wafer surface is maintained and the electrical properties of the surface are stabilized. For example, if argon gas is used in the CMP process of a copper (Cu) plated layer, oxide formation during the process is suppressed, and higher quality planarization is possible.

[0079] Furthermore, according to one embodiment of the present invention, the process includes a waiting stage in which no electric field is applied, and the electric field application stage and the waiting stage are repeated periodically. Repeating the electric field application stage and the waiting stage periodically is more effective in achieving uniform surface planarization than continuously applying an electric field to the wafer surface during the CMP process. While no electric field is applied, the particles in the slurry can move freely and adjust their overall distribution. In this way, periodic application of the electric field enables uniform polishing across the entire surface, rather than concentrating in specific areas.

[0080] For example, by applying an electric field for a certain period of time to concentrate charged particles in a specific region of the surface, and then moving to a waiting phase to allow the particle distribution to naturally rearrange again, the planarization process can be carried out more uniformly.

[0081] Furthermore, the electric field distribution is controlled to have symmetrical heterogeneity with respect to the center of the wafer surface. The symmetrical heterogeneity of the electric field distribution significantly affects the efficiency of the CMP process depending on the surface characteristics. By adjusting the electric field distribution symmetrically with respect to the center of the wafer surface, uniform etching can be achieved across the entire surface. Therefore, localized over-etching and insufficient etching can be prevented.

[0082] For example, the influence of the electric field can be efficiently adjusted by distributing the electric field strength differently using a specific pattern on the wafer surface.

[0083] Furthermore, according to one embodiment of the present invention, the etching rate is adjusted by applying the electric field differentially to regions with high and low metal area density. In the CMP process, the etching rate differs depending on the metal area density, and in order to control this, a differential electric field is applied to regions with high and low metal area density. Regions with high metal area density have a low etching rate, and conversely, regions with low area density have a high etching rate, so the electric field distribution is controlled to enable uniform flattening.

[0084] For example, by applying an electric field to a region with a high metal area density to concentrate charged particles in the slurry, the etching rate in that area is increased, while in a region with a low metal area density, the electric field is weakened to reduce the etching rate and form a uniform surface.

[0085] Furthermore, according to one embodiment of the present invention, an electroless plating process is further performed on a specific area of ​​the wafer surface. If non-uniformity remains after the CMP process, the electroless plating process is performed on that area to adjust the surface height difference. Since electroless plating can deposit metal ions onto the surface by chemical reaction without the need for electric current, metal can be added uniformly only to specific areas.

[0086] For example, a metal layer can be deposited by electroless plating only in specific areas where the metal layer is not flat, and then a CMP process can be performed to form a uniform surface overall.

[0087] Furthermore, according to one embodiment of the present invention, mechanical polishing is performed on the wafer surface after the electroless plating process. After adjusting the height of a specific area by electroless plating, the plating layer is flattened by mechanical polishing. Electroless plating is effective in eliminating localized non-uniformity, but the final flattening of the surface after plating is more accurately achieved by mechanical polishing. That is, after depositing metal only on a specific area of ​​the wafer surface by electroless plating, the area is polished to match the height of the surrounding area.

[0088] Furthermore, the quantum superconducting material used in the quantum technology semiconductor device according to the embodiment of the present invention can be composed of a variety of metals and superconducting materials.

[0089] Specifically, one or more of the following can be used: Nb, Sn, Al, Zn, Ta, Nb-Ti, Nb3Sn, V3Si, V3Ga, Nb3Ge, MgB2, YBCO, BSCCO, Iron Pnictides, LBCO, Iron Chalcogenides, TBCCO, Hg-1223, and Iron-Based Superconductors.

[0090] Semiconductor devices used in quantum computing, quantum communication, and other applications require extremely high electrical properties and safety. For this purpose, superconducting materials such as Nb (niobium), Sn (tin), and Al (aluminum) are used. Such materials possess low resistance and fast signal transmission characteristics. Special care is required when handling these materials in the CMP (Chemical Manufacturing Process), and uniform and precise planarization can optimize the performance of the device.

[0091] For example, Nb3Sn is a material with high conductivity and superconductivity, and can be used for wiring quantum devices. Here, the efficiency of the device is increased when the surface of the material is planarized by a CMP process and a uniform thickness is maintained. Quantum technology devices, by their very nature, use superconducting materials that have high conductivity and safety. Various metal, alloy, and compound superconductors are mentioned in the claims of this invention, each of which can be selected depending on the properties of the quantum device. Such materials exhibit superconductivity at very low temperatures and are essential for the fast and accurate transmission of information in quantum computing and quantum communication.

[0092] For example, YBCO (Yttrium Barium Copper Oxide) is a superconductor with a high critical temperature, making it suitable for signal transmission in quantum devices. When planarizing the surface of this material by the CMP process, the selection of the slurry and the applied electric field conditions are crucial.

[0093] The chemical mechanical planarization apparatus in a semiconductor manufacturing process according to an embodiment of the present invention is an apparatus for performing chemical mechanical planarization and includes a CMP equipment for performing the CMP process and an electric field application control unit for applying an electric field to the wafer surface.

[0094] According to embodiments of the present invention, the distribution of charged particles is adjusted by applying an electric field during the CMP process, thereby controlling the etching rate of the wafer surface. By concentrating the electric field on a specific region of the wafer surface using the electric field application control unit, the uniformity of etching is enhanced, and dishing and corrosion are minimized. Unlike general CMP equipment, this device provides even greater precision in wafer surface planarization by adding a control unit that can apply an electric field.

[0095] For example, by applying an electric field to the surface of a wafer having a specific pattern, charged particles of the slurry can be concentrated in the metal region, thereby adjusting the local etching rate.

[0096] Furthermore, the electric field application control unit according to the embodiment of the present invention applies an electric field perpendicular to the wafer surface to form a potential difference between the metal and the insulator. This controls the ion distribution in the slurry.

[0097] By applying a vertical electric field during the CMP process, the distribution of charged particles in the slurry can be controlled, thereby adjusting the etching rate on the wafer surface. In particular, since the etching rate changes depending on the potential difference between the metal and the insulator, surface uniformity can be improved by appropriately adjusting this.

[0098] For example, by applying an electric field perpendicular to the wafer surface, the insulating surface is insufficiently etched, while the metal surface is etched more, thereby enabling uniform planarization.

[0099] According to embodiments of the present invention, by applying an electric field, ions having negative or positive charges are concentrated on the wafer surface, thereby reducing the rate of metal etching. By concentrating ions having negative or positive charges on the metal surface within the slurry, etching due to chemical reactions is suppressed. Therefore, excessive etching of the metal surface is prevented, and stable etching can be maintained. This method is effective in suppressing the dishing phenomenon of metal wiring in the CMP process.

[0100] For example, by applying an electric field, positively charged ions in the slurry are concentrated on the metal surface to suppress metal etching and form uniform metal wiring.

[0101] Furthermore, according to embodiments of the present invention, a measurement unit is included that performs a plating process on the wafer surface after the CMP process, measures the uniformity of the wafer surface after the CMP and plating processes, and performs additional plating and CMP processes if it is below a standard. The uniformity of the wafer surface is improved by performing the CMP and plating processes alternately. After the process, the uniformity of the surface is measured to determine if additional processes are necessary, and if necessary, the desired surface flatness can be achieved by performing additional plating and CMP at different levels. This process is particularly important for quantum devices that require a high degree of planarization.

[0102] For example, after the CMP process, a measuring device is used to measure the height difference of the surface. If it is below the standard, the height is corrected by an additional plating process before the final CMP process is carried out.

[0103] Furthermore, according to embodiments of the present invention, the plating process includes at least one of either electroplating equipment or electroless plating equipment. Electroplating uses electric current to deposit metal ions onto the wafer surface, while electroless plating deposits metal through a chemical reaction. The plating can be carried out by selecting and using the most suitable method from both, or by combining both processes. This makes the metal thickness on the wafer surface uniform and improves its flatness.

[0104] For example, electroplating is applied to electrically conductive parts, while electroless plating is applied to complex structures or non-conductive parts to create a uniform surface.

[0105] Furthermore, the electric field application control unit according to the embodiment of the present invention applies a voltage to the wafer surface to form an electric field, preventing current from flowing. This controls the etching rate by adjusting the movement of charged particles in the slurry.

[0106] An electric field is created by applying a voltage that prevents current from flowing, thereby regulating the movement of charged particles in the slurry. This method effectively controls surface etching while minimizing contamination and damage caused by current. For example, a voltage can be applied to the wafer surface to prevent charged particles in the slurry from concentrating in specific locations, thereby maintaining a uniform etching rate.

[0107] Furthermore, the FMS electric field application control unit according to one embodiment of the present invention plays a role in adjusting the etching rate of the wafer surface by applying a current to the wafer surface via a conductive substrate to form a potential and locally creating an electric field.

[0108] By directly applying an electric current to the wafer surface via a conductive substrate, a potential difference is formed, creating a localized electric field. Such a localized electric field can control the movement of ions in the slurry, thereby adjusting the etching rate. This allows for the suppression or promotion of etching in specific areas, enabling uniform planarization of the wafer surface during the CMP process. By generating a localized potential difference, the etching rate can be precisely controlled according to various surface patterns.

[0109] For example, if an electric current is applied to a metal surface in a specific area to form a local electric field, ions in the slurry will concentrate in that area, causing the local etching rate to increase or decrease.

[0110] Furthermore, the electric field application control unit according to the embodiment of the present invention controls negatively charged ions in the slurry to concentrate on the metal surface by electrophoresis. By using electrophoresis to control the concentration of negatively charged ions in the slurry on the metal surface, the etching rate of the metal surface can be reduced or adjusted. Electrophoresis is a phenomenon in which charged particles move due to an electric field, and this is utilized to concentrate ions in the slurry at specific locations. As a result, excessive etching of the metal surface can be prevented, enabling uniform polishing.

[0111] For example, applying an electric field during the CMP process causes negatively charged ions in the slurry to move to the metal surface, reducing the etching rate of that surface and thus reducing the dishing phenomenon.

[0112] Furthermore, to prevent oxidation of the wafer surface during the CMP process, it includes an inert gas supply unit that allows the CMP process to be carried out in an inert gas atmosphere.

[0113] To prevent oxidation of the wafer surface during the CMP (Chemical Polishing) process, a device for supplying an inert gas is necessary. The inert gas can be composed of low-reactivity elements such as He, Ar, and N2. Performing the process in such an atmosphere prevents surface oxidation and contamination. In particular, such oxidation prevention techniques are essential for maintaining surface quality in processes requiring high precision, such as those used in semiconductor devices for quantum technology.

[0114] For example, oxidation prevention gas is injected into the CMP equipment via an inert gas supply unit to minimize oxidation of the wafer surface during the process.

[0115] Furthermore, according to embodiments of the present invention, the inert gas comprises at least one of He, Ar, Ne, Kr, and N2. The inert gas used in the CMP process is used to prevent oxidation of the wafer surface and to provide a clean environment. By maintaining the atmosphere inside the equipment using at least one of He, Ar, Ne, Kr, and N2, oxidation or contamination of the metal layer during the CMP process is prevented. When selecting and using such inert gases, an appropriate atmosphere can be created depending on the properties of each gas and the wafer material.

[0116] For example, to prevent oxidation of metal surfaces, N2 gas is used to maintain an N2 atmosphere inside CMP equipment.

[0117] Furthermore, according to embodiments of the present invention, the electric field application control unit controls the distribution of the electric field to have symmetrical non-uniformity with respect to the center of the wafer surface. When an electric field is applied to the wafer surface, its distribution is adjusted to be symmetrically non-uniform with respect to the center of the wafer surface. Such a symmetrical electric field distribution helps to achieve uniform etching during the wafer planarization process and reduces defects that may occur due to non-uniform etching. Such a non-uniform electric field distribution is used to avoid etching that is concentrated only in specific areas while maintaining a uniform electric field distribution. For example, different electric fields are applied to the edges and the center of the wafer surface to more precisely etch a specific pattern of metal wiring.

[0118] Furthermore, according to embodiments of the present invention, the electric field application control unit adjusts the etching rate by applying differential electric fields to areas with high and low metal area density on the wafer surface. The etching rate is adjusted by applying different electric fields depending on the area density of the metal formed on the wafer surface. By applying different electric fields to areas with high and low metal area density, uniformity of etching can be maintained, and excessive polishing of specific areas can be prevented. Therefore, the entire surface can be uniformly flattened, and the uniformity of the wiring thickness can be improved. For example, a low electric field can be applied to areas with high metal area density, and a high electric field can be applied to areas with low metal area density to achieve overall uniform etching.

[0119] Furthermore, according to an embodiment of the present invention, the electric field application control unit adjusts the etching rate of the wafer surface by periodically repeating an electric field application stage and a standby stage where no electric field is applied. That is, instead of continuously applying an electric field, the etching rate is adjusted by periodically repeating the electric field application stage and the standby stage. Therefore, the etching rate of a specific area on the wafer surface can be finely adjusted, and excessive etching and contamination can be prevented. Since the movement of charged particles stops or slows down in the standby stage, the etching speed and uniformity in the electric field application stage can be effectively adjusted.

[0120] For example, by applying an electric field for a specific period and then allowing a certain waiting period to pass, it is possible to maintain a uniform etching rate across the entire surface.

[0121] Furthermore, according to an embodiment of the present invention, the electric field application control unit controls the strength and direction of the electric field to change over time, thereby adjusting the etching rate of a specific area on the wafer surface. The etching rate of the wafer surface is controlled by a function that allows the strength and direction of the electric field to be adjusted over time. This method periodically adjusts the magnitude and direction of the electric field to prevent uneven etching from occurring on the wafer surface. When concentrated etching is required in a specific area, the strength of the electric field can be increased or its direction can be concentrated on a specific part, and conversely, when it is desired to reduce the etching rate, the electric field can be weakened. Therefore, it is possible to respond sensitively to local shape changes on the wafer surface and realize the desired flattening. For example, when it is necessary to etch the edges of the wafer surface more, the etching effect can be concentrated on that part by increasing the strength and adjusting the direction of the electric field.

[0122] Furthermore, according to embodiments of the present invention, the electric field application control unit plays a role in finely adjusting the distribution of the electric field and the direction of the current in order to locally adjust the etching rate of the wafer surface. The distribution of the electric field is locally adjusted to finely adjust the etching rate for a specific region of the wafer. In addition, by finely adjusting the direction of the current, the movement of charged particles in the slurry can be precisely controlled. Such control enables fine planarization, such as increasing or decreasing the etching rate in a specific region, and supports uniform etching of the wafer surface. For example, if the wafer pattern is complex, the direction and intensity of the current are finely adjusted to perform etching according to the complex pattern.

[0123] Furthermore, quantum superconductor materials used in semiconductor devices for quantum technology may consist of one or more of the following materials: Nb, Sn, Al, Zn, Ta, Nb-Ti, Nb3Sn, V3Si, V3Ga, Nb3Ge, MgB2, YBCO, BSCCO, Iron Pnictides, LBCO, Iron Chalcogenides, TBCCO, Hg-1223, and Iron-Based Superconductors.

[0124] Superconductors required for semiconductor devices in quantum technology need properties that enable high electrical conductivity, low resistance, and fast signal transmission. The proposed materials possess these properties, enabling the efficient operation of quantum devices. In particular, the use of such superconductors in quantum computing and communications plays a crucial role in minimizing energy loss, accelerating signal transmission, and improving device performance. For example, Nb3Sn has a high critical current, and high-temperature superconductors like YBCO are suitable for wiring in quantum computers that require high-speed operation.

[0125] Furthermore, according to one embodiment of the present invention, a protective film can be formed on the wafer surface after the plating process and the CMP process in order to prevent oxidation remaining on the wafer surface after the CMP process. After the CMP process is completed, a protective film is formed to prevent the metal wiring on the wafer surface from reacting with oxygen in the air and oxidizing. The protective film generally consists of an antioxidant substance and blocks the metal layer from coming into contact with moisture and oxygen in the air. Therefore, the electrical properties and surface condition of the metal wiring on the wafer surface can be stably maintained. For example, a protective film such as SiO2 or Si3N4 is deposited on the metal surface to prevent oxidation.

[0126] Furthermore, according to one embodiment of the present invention, the electric field application control unit can finely adjust the distribution of the electric field and the direction of the current in order to locally adjust the etching rate of the wafer surface. By precisely adjusting the distribution of the electric field and the direction of the current, the etching rate of a specific region can be finely adjusted. Therefore, uniform flattening of the wafer surface can be maintained, and selective etching can be induced only in the necessary areas. For example, even when the specific pattern structure or pad size of the wafer varies, the strength and direction of the electric field can be adjusted so that etching can be performed in accordance with each part. In addition, when fine polishing is required in a specific part of the wafer, the direction of the current can be concentrated in that part, and the strength of the electric field can be adjusted to precisely control the etching rate.

[0127] Furthermore, according to one embodiment of the present invention, the electric field application control unit controls the intensity and direction of the electric field to change over time, thereby adjusting the etching rate of a specific region on the wafer surface. This method adjusts the etching rate by controlling the intensity and direction of the electric field, which change over time. This is useful when trying to change or adjust the etching rate of a specific part of the wafer surface. By changing the electric field over time, the speed and form of etching change, and this can be used to concentrate on adjusting the etching of a specific part. For example, if you want to increase the etching rate of the central part of the wafer, you can concentrate the electric field on that part at regular time intervals.

[0128] Furthermore, according to one embodiment of the present invention, the electric field application control unit can adjust the etching rate of the wafer surface by periodically repeating the steps of applying an electric field and a standby step of not applying an electric field. Periodically repeating the electric field application step and the standby step is a method that can precisely adjust the etching rate of the wafer surface.

[0129] When an electric field is continuously applied, excessive etching may occur in specific areas. Therefore, the etching rate on the wafer surface is adjusted by controlling the application-and-wait cycle. This method has the advantage of controlling localized height differences on the surface and preventing damage from excessive etching or polishing.

[0130] For example, to prevent excessive etching of the wafer surface during the CMP process, the surface etching rate is adjusted by repeatedly switching off the electric field, entering a standby phase, and then reapplying it.

[0131] The following describes in detail other embodiments of the present invention.

[0132] The chemical mechanical planarization method in a semiconductor manufacturing process according to an embodiment of the present invention includes the steps of: measuring the initial topography of the wafer surface to measure the non-uniformity of the wafer surface; performing a plating process if the height difference (h0-h1) of the wafer surface is below a certain standard; performing a CMP process to planarize the wafer surface; and after the plating process and the CMP process, remeasuring the uniformity of the wafer surface to confirm whether additional plating and additional CMP processes are necessary, and repeating the CMP process and the plating process at least once.

[0133] During the CMP process, an electric field is applied to the wafer surface using electrophoresis to control the distribution of charged particles in the slurry. That is, the electrophoresis process can be performed once or more times in each process, or in each process as needed, such as in the initial process, intermediate process, or reprocess.

[0134] Figures 3, 5, and 7 show a process in which an electric field is applied one or more times during each CMP process to utilize electrophoresis. Figure 3 shows a process in which an electric field (current) is applied one or more times during the CMP process. Figure 5 shows a process in which an additional plating process is performed after an electric field (current) is applied one or more times during the CMP process. Figure 7 shows a process in which an additional plating process is performed after an additional CMP process is performed after an additional electric field (current) is applied one or more times during the CMP process.

[0135] Each step can be performed one or more times as needed, and depending on the wafer surface condition, the electric field application step can be performed during the CMP steps, i.e., one or more of the initial CMP step, intermediate CMP step, and re-CMP step.

[0136] An apparatus for performing chemical mechanical planarization in a semiconductor manufacturing process according to an embodiment of the present invention is an apparatus for performing chemical mechanical planarization in a semiconductor manufacturing process, comprising: a CMP equipment 200 formed on one side of an element formation equipment 100 and performing a CMP process to planarize the wafer surface; a plating equipment 300 formed on one side of the CMP equipment 200 and performing a plating process to plate the wafer surface; a measuring unit 600 that measures the initial topography of the wafer surface provided by the element formation equipment 100 and senses non-uniformity; a control unit 700 that senses the height difference (h0-h1) of the wafer surface measured by the measuring unit 600 and controls the CMP equipment 200 and the plating equipment 300; and a transfer system for transferring wafers in each of the element formation equipment 100, the CMP equipment 200 and the plating equipment 300.

[0137] In a chemical mechanical planarization apparatus used in such a semiconductor manufacturing process, according to one embodiment of the present invention, the role of an electric field application control unit can be added to the configuration of the control unit. That is, according to one embodiment of the present invention, the apparatus may include CMP equipment, a control unit including the function of an electric field application control unit, plating equipment, a measuring unit, and a transfer system.

[0138] As described above, the electric field application control unit applies an electric field to the wafer surface during the CMP process to adjust the distribution of charged particles in the slurry and control the etching rate. It also optimizes the flatness of the surface by adjusting the intensity, direction, and application and standby periods of the electric field.

[0139] The present invention relates to a method and apparatus for repeatedly performing plating and CMP processes in a semiconductor manufacturing process, measuring the non-uniformity of the wafer surface, and performing additional plating and CMP processes if necessary.

[0140] Furthermore, the CMP process of the present invention involves measuring the initial topology of the wafer, and if the height difference on the wafer surface is below a certain standard, performing a plating process, followed by flattening the surface with the CMP process. After that, uniformity is evaluated by re-measurement, and the process is repeated as necessary.

[0141] Furthermore, the present invention provides an apparatus for carrying out a process in an inert gas atmosphere to prevent oxidation during wafer transfer.

[0142] One embodiment of the present invention provides a chemical mechanical planarization method in a semiconductor manufacturing process, which first measures the non-uniformity of the wafer surface by measuring the initial topography of the wafer surface.

[0143] A wafer according to one embodiment of the present invention includes one or more semiconductor elements. The semiconductor elements are formed on a substrate by a semiconductor process, a dielectric layer 10 is formed, a barrier layer 20 is formed on top of the dielectric layer, and a wiring metal layer (Cu) is formed on top of the barrier layer. Then, in order to form the metal wiring 40, the upper part of the wiring metal layer and the barrier layer 20 are planarized by a chemical mechanical planarization (CMP) process to complete the metal wiring 40.

[0144] If necessary, the wafer of the present invention may also include a wafer in which such semiconductor elements and metal wiring 40 are stacked in multiple layers. Here, the CMP process plays a role in removing non-uniform surfaces between layers in the multilayer semiconductor element to make it flat.

[0145] In silicon semiconductor processes, materials such as Ta, TaN, TiN, Ti, W, WN, Ru, Co, CoSi2, Ni, and NiSi can be used as the barrier layer 20.

[0146] According to one embodiment of the present invention, the semiconductor device is for quantum technology, and the material forming the main effective layer is made of a quantum superconductor.

[0147] According to one embodiment of the present invention, the quantum superconducting material used in the semiconductor device for quantum technology is Nb, Sn, Al, Zn, Ta, Nb-Ti, Nb3Sn, V3Si, V3Ga, Nb3Ge, MgB2, YBCO(YBa2Cu3O 7-x ), BSCCO(Bi2Sr2Ca2Cu3O10 ) Iron Pnictides (e.g., Ba 1-x K x Fe2As2), LBCO (La 2-x Ba x CuO4), Iron Chalcogenides (e.g., FeSe), TBCCOTl2Ba2Ca2Cu3O 10 ), Hg - 1223 (HgBa2Ca2Cu3O 8+x ), or a material obtained by mixing any one or two or more of Iron - Based Superconductors (LaFeAsO, BaFe2As2, SmFeAsORb3C60).

[0148] Measure the initial topography of the surface of such a wafer to measure the non - uniformity of the wafer surface. That is, by precisely measuring the height difference, roughness, etc. of the wafer surface, non - uniform portions can be identified, and this is implemented by the measuring unit 600 according to an embodiment of the present invention.

[0149] The measuring unit 600 for measuring the topography of the wafer surface can measure the topography by measuring the change in reflectivity or distance of the wafer surface using a laser or light. Also, by sensing the change in capacitance between the wafer surface and the sensor, the height difference and pattern change of the surface can be measured, and in particular, the change in the thickness of the plating layer can be precisely measured.

[0150] Here, the wafer surface is in a state where the barrier layer 20 is formed on the dielectric layer 10 and the metal wiring layer 30 is formed by a plating process, and the height of the metal wiring layer 30 can be formed in various ways corresponding to the pattern and form of the semiconductor element.

[0151] On the other hand, prior to measuring the non - uniformity of the wafer surface, a preliminary CMP process can also be performed. Thus, subsequent plating processes or CMP processes can be carried out more smoothly.

[0152] If the initial state of the wafer surface is too uneven, or if the planarization process cannot be completed using only the CMP process of the present invention, or if there are large height differences in the wafer, uneven pressure may be applied during the polishing process, making uniform planarization impossible. In this case, by removing some of the initial unevenness with a preliminary CMP process, more precise planarization becomes possible in the subsequent CMP process of the present invention.

[0153] In one embodiment of the present invention, the vertical cross-section is formed in a square pattern shape, and the metal wiring layer 30 is also formed to have different heights according to the square pattern. The initial topography measurement of the present invention senses the surface of the metal wiring layer 30 with such different heights.

[0154] Figure 8 is an illustrative diagram showing variables related to the initial topography after the initial plating process is completed. It illustrates a state in which a barrier layer 20 is formed on top of the dielectric layer (SiO2) 10, and a metal wiring layer 30 is formed on top of that by the plating process.

[0155] As shown in Figure 8, by performing the plating process, the lower width (w) of the wafer surface is reduced. original - The width of the barrier layer pattern before plating is compared to the upper width of the wafer surface (w up - The width of the plating pattern after plating can be made smaller. Upon completion of the plating process, a change in topology can be achieved, as shown in Figure 6(b).

[0156] The alpha coefficient is w up / w original This shows the upper width (w) of the wafer surface. up -Width of the plating pattern after plating) and width of the bottom of the wafer surface (w original - Indicates the ratio of the width of the barrier layer pattern before plating.

[0157] In the surface topology, the height-related variables are h0, h1, h2, and h3, each representing the height of a different layer or region. For example, h0 represents the maximum height of the plating pattern when the initial plating process is completed at a predetermined baseline, h1 represents the minimum height of the plating pattern formed by the initial plating process, h2 represents the height up to the barrier layer 20, and h3 represents the height up to the exposed metal wiring 40 after the barrier layer 20 is removed.

[0158] Then, once the initial topography measurement is complete, if the height difference (h0-h1) on the wafer surface is below a certain standard, that is, if the initial plating process is complete, the preliminary CMP process is performed to ensure that the difference between the maximum height h0 of the plating pattern and the minimum height h1 of the plating pattern formed by the initial plating process is below a certain standard, and a re-plating process is then carried out.

[0159] In other words, if the height difference of the pattern is large, a preliminary CMP process is performed to flatten the pattern first. Then, when the height difference of the pattern falls below a certain standard, a re-plating process is performed to minimize the occurrence of dishing and corrosion. In one embodiment of the present invention, the re-plating process is performed when the height difference is below a certain standard, which is 10 μm or less. If the height difference is greater than 10 μm, the plated metal layer may be formed unevenly.

[0160] In one embodiment of the present invention, the plating process may include at least one of electrolytic plating and electroless plating. That is, based on the initial topography, only electrolytic plating may be performed, only electroless plating may be performed, or both electrolytic plating and electroless plating may be performed, or each may be repeated multiple times.

[0161] When the metal wiring layer 30 is removed during the CMP process, excessive removal of part of the metal wiring layer 30 from the wafer surface (dishing and corrosion) can occur, resulting in thickness non-uniformity. To solve this problem, a plating process is necessary, which reconstructs the metal layer on the wafer surface to maintain surface uniformity. In response to this need, the present invention attempts to solve surface non-uniformity by performing a plating process during the CMP process and introducing electrolytic plating and electroless plating processes to selectively deposit metal onto the wafer surface.

[0162] Generally, electroplating uses electric current to deposit metal ions onto the wafer surface, offering the advantages of uniform deposition of a metal layer (metal wiring layer) and high-speed plating. In one embodiment of the present invention, when there is a large difference in the height of the wafer surface, electroplating can fill in the lower points on the surface and uniformly deposit a metal layer. In the case of electroplating, if the metal wiring layer 30 remains, the plating is mainly formed on top of it.

[0163] Furthermore, electroless plating is a method of depositing metal onto the wafer surface through a chemical reaction without using electric current. In this method, metal ions are reduced on the wafer surface to form a metal layer, and plating can be performed on structures that are not electrically conductive or have complex structures. A uniform plating thickness can be obtained, and selective plating can be performed on specific areas.

[0164] In one embodiment of the present invention, the plating material can be any one or more of the following metal materials with excellent electrical conductivity: Cu, Al, Au, Ag, Ni, Cr, Zn, Sn, etc.

[0165] Furthermore, depending on the shape or structure of the element, the plating process can be selectively applied to specific areas of the wafer surface by initial topography. That is, if the non-uniformity of the wafer surface is taken into consideration, or if there is a higher likelihood of dishing and corrosion occurring in a particular area, the plating process can be performed only in that area. In this case, electroless plating can be appropriately used. When electrolytic plating is performed, other areas can be masked, and plating can be performed only on the exposed areas.

[0166] Furthermore, the electroless plating process can be performed in specific areas of the wafer surface before and / or after the CMP process, in areas where the height of the wafer surface is less than or equal to a certain value h3.

[0167] In other words, during the CMP process, some areas of the wafer surface may not have their non-uniformity removed, or areas may be polished more than expected. To solve this, electroless plating is used to deposit metal onto specific areas that require plating, and then this is planarized.

[0168] The wafer surface height h3 before and / or after the CMP process indicates the height to the exposed metal wiring 40 after the barrier layer 20 has been removed, and electroless plating deposits metal onto the lower parts of the wafer surface, selectively depositing metal onto areas with unevenness, complex structures, or areas without electrical conductivity.

[0169] Furthermore, an additional electroless plating process can be performed due to non-uniformity of the wafer surface. That is, if non-uniformity remains on the wafer surface after the CMP process, an additional electroless plating process can be performed to compensate for it. This method aims to make the wafer surface more uniform by selectively applying electroless plating when complete planarization is not achieved even after the CMP process, the re-plating process, and the CMP process. Electroless plating deposits metal onto the lower parts of the wafer surface, selectively depositing metal onto areas with non-uniformity, complex structures, and regions without electrical conductivity.

[0170] This process involves re-measuring the surface after the CMP (Chemical Polishing) process, and if the non-uniformity of the wafer surface exceeds a certain standard, additional electroless plating is performed. Since this process does not require current, it can be effectively carried out even in areas with complex structures or non-conductive regions. Subsequently, the CMP process can be repeated to finally planarize the surface. Therefore, non-uniformity of the wafer surface can be minimized, and the performance of the quantum device can be maximized.

[0171] Furthermore, according to one embodiment of the present invention, the non-uniformity of the wafer surface can be detected during the plating process, and the plating thickness can be automatically adjusted.

[0172] If the plating process in semiconductor device manufacturing is not carried out correctly, non-uniformity will remain on the wafer surface, affecting signal transmission and device performance. Therefore, the wafer surface condition is monitored in real time during plating, and the plating thickness is precisely adjusted only in areas where adjustment is necessary, preventing unnecessary plating and optimizing wafer surface planarization.

[0173] Such non-uniformity is detected by measuring the height difference on the wafer surface using the aforementioned measuring unit (equipped with an optical sensor or laser scanning device) 600, and the control unit 700 transmits this data to the plating equipment 300 and other devices to cause a change in the plating process conditions.

[0174] As one method for automatically adjusting the plating thickness, the electroplating process during the plating stage can involve performing a pulse-reverse current process during a pulse-forward current process, or repeatedly performing the pulse-forward current process and the pulse-reverse current process.

[0175] Electroplating uses electric current to rapidly deposit metal ions onto the wafer surface, which is advantageous for forming a metal layer of uniform thickness. The positive current process maintains a constant current to deposit metal ions onto the wafer surface. Here, the thickness of the plating can be precisely adjusted by controlling the current intensity and duration. When using only this process, the uniformity of the plating layer may be reduced due to uneven metal ion concentration or localized differences in current density on the wafer surface.

[0176] To this end, in one embodiment of the present invention, a current is passed in the opposite direction to the positive current to temporarily remove some of the metal from the wafer surface. This process removes defects in the metal layer and improves the uniformity of the plating layer.

[0177] In other words, localized non-uniformity may occur on the wafer surface during the plating process. By using a reverse current to temporarily remove the metal, the non-uniform areas on the surface can be flattened.

[0178] In one embodiment of the present invention, by alternately performing a positive current process and a reverse current process, the positive current process is advantageous for rapid and uniform deposition of metal, but if localized non-uniformity occurs, a reverse current is provided to temporarily remove the metal layer and eliminate the non-uniformity. In this case, the metal layer can be deposited more precisely, surface defects can be reduced, and a high-quality metal layer can be formed.

[0179] In other words, when using only a positive current process on wafers with complex patterns, excessive metal deposition can occur in certain areas. Introducing a reverse current process solves this problem and enables uniform plating.

[0180] Furthermore, as the plating process progresses, the lower width (w) of the wafer surface changes. original - The width of the barrier layer pattern before plating is compared to the upper width of the wafer surface (w up- The width of the plating pattern after plating can be made smaller. Upon completion of the plating process, a change in topology can be achieved, as shown in Figure 8(b).

[0181] α coefficient (w up / w original , upper width (w up -Width of the plating pattern after plating) and width of the bottom of the wafer surface (w original If the ratio of the α coefficient (width of the barrier layer pattern before plating) is 0.99 or less, the re-plating can be stopped and the CMP process can be carried out. The closer the α coefficient is to 1, the better the plated layer maintains the shape of the original pattern. If it is 0.99 or less, it indicates that the plating has reached an appropriate level, and therefore the plating process can be interrupted and the CMP process can be carried out.

[0182] In other words, as shown in Figure 8, plating is performed on the top of the pattern, and the width of the pattern before and after plating is compared. If the α coefficient is 0.99 or less, the re-plating can be stopped and the CMP process can be carried out. If the α coefficient is greater than 0.99, and the re-plating is not stopped, there is a high possibility that the plating layer will become too thick or form unevenly.

[0183] Thus, the alpha coefficient acts as an important criterion for controlling the plating and CMP processes. When the alpha coefficient reaches 0.99, it indicates that the plating process is complete. By stopping the plating process and proceeding with the CMP process based on this value, the overall efficiency and quality of the process are ensured.

[0184] Furthermore, by measuring the α coefficient in real time, if the α coefficient falls below 0.99 during the plating process, the plating process can be automatically stopped and switched to the CMP process. Thus, process automation can be achieved, and unnecessary plating processes can be prevented. In one embodiment of the present invention, such functions can be controlled by the control unit 700. That is, by utilizing the α coefficient, the end point of the plating process and the start point of the CMP process can be clearly set to maximize process efficiency.

[0185] After the re-plating process is complete, a CMP (Chemical Polishing) process is performed to planarize the wafer surface. In the CMP process, as used in the semiconductor device manufacturing process, chemical reactions and mechanical polishing are applied simultaneously to uniformly planarize the surface of the semiconductor device, allowing subsequent processes to be carried out stably. In particular, the CMP process plays a role in removing non-uniform interlayer surfaces in multilayer semiconductor devices and forming a flat surface.

[0186] Generally, a wafer is fixed on a polishing pad, and the surface is polished together with a slurry to remove surface irregularities. The slurry triggers a chemical reaction that selectively removes specific substances from the wafer surface, while the abrasive mechanically polishes the wafer surface.

[0187] In one embodiment of the present invention, the slurry is used to remove layers such as oxides, metals, and insulating films, so abrasive particles such as silica (SiO2) and alumina (Al2O3) can be used, or an alkaline slurry can be used when removing an oxide film. An appropriate slurry is selected and the CMP process is carried out. The insulating film on the wafer surface is removed and planarized, or after forming a metal wiring layer 30, the wiring layer is planarized to facilitate subsequent processes, or each layer in a multilayer semiconductor device is planarized to reduce alignment errors.

[0188] After the plating and CMP processes, the uniformity of the wafer surface is remeasured to determine if additional plating and CMP processes are necessary. If additional plating or CMP processes are required, the CMP and plating processes are repeated one or more times. After each process, the surface condition is checked, and the process is repeated as needed.

[0189] The re-measurement of the uniformity of the wafer surface is performed using a measurement unit 600 that employs an optical sensor or the like, in the same manner as during the initial topography measurement.

[0190] In other words, after the CMP process is completed, if necessary, the surface uniformity is remeasured to determine if an additional plating or CMP process is required. If necessary, an additional plating process and an additional CMP process are carried out to finally complete the surface planarization. Re-plating and additional plating processes can prevent the possibility of dishing and corrosion.

[0191] The CMP and plating processes according to this embodiment of the present invention can be carried out in an inert gas atmosphere to prevent oxidation of the wafer surface. The inert gas can be a mixture of one or more of He, Ar, Ne, Kr, and N2.

[0192] Oxidation can occur on the wafer surface during CMP (Chemical Polishing) or plating processes. If oxidation occurs during the formation of the metal wiring layer 30, the electrical conductivity of the metal will decrease, potentially causing problems with signal transmission. In particular, this can be fatal to the performance of quantum semiconductor devices.

[0193] In one embodiment of the present invention, an inert gas is supplied by the inert gas supply unit 500 during the CMP process and the plating process to block contact with oxygen and prevent oxidation of the metal layer.

[0194] In one embodiment of the present invention, the internal pressure of the CMP equipment 200 and the plating equipment 300 can be set to approximately 5 to 200 mbar higher than atmospheric pressure. This prevents external air and contaminants from flowing into the equipment, and also prevents oxidation of the wafer surface by increasing the concentration of the inert gas, thereby maintaining a clean surface.

[0195] According to one embodiment of the present invention, the control unit 700 controls the pressure via a pressure sensor and a check valve, monitors it in real time to maintain a state 5 to 200 mbar higher than atmospheric pressure, and works in conjunction with the inert gas supply unit 500 to maintain a constant pressure and atmosphere inside the equipment. That is, the internal pressure of the CMP equipment 200 and the plating equipment 300 is maintained constant while continuously supplying inert gas.

[0196] Furthermore, the CMP process may include a cleaning step to remove residual impurities from the wafer surface after the CMP process. After the CMP process is completed, residual impurities (polishing residue and chemical by-products) may remain on the wafer surface, which are washed with ultrapure water or a chemical cleaning agent and then dried.

[0197] Furthermore, if additional plating and CMP steps are not required after the aforementioned plating and CMP steps, an additional protective film can be formed to protect the wafer surface.

[0198] If additional plating or CMP processes are not required, a mechanical polishing process may be added to remove unwanted residues and rough areas. According to one embodiment of the present invention, mechanical polishing methods such as buffing or lapping are used.

[0199] Furthermore, in one embodiment of the present invention, oxides (SiO2) or nitrides (Si3N4) can be used to protect the wafer surface and prevent the plated metal layer from corroding due to oxygen, moisture, etc. in the air.

[0200] Figure 3 shows a chemical mechanical planarization method in a semiconductor manufacturing process according to one embodiment of the present invention, in which one or more steps of electric field application are performed during the CMP process; Figure 5 shows an additional plating step performed after electric field application during the CMP process; and Figure 7 shows an additional plating step performed after electric field application during the CMP process, followed by an additional CMP process. Cleaning and drying steps are performed between each step.

[0201] Figure 4 is a schematic diagram of the process according to the embodiment in Figure 3. Figure 4(a) shows a wafer (device) in which a barrier layer 20 is formed on a dielectric layer 10 and a metal wiring layer 30 is formed on top of it by an initial plating process. Figure 4(b) shows a wafer in which a portion of the metal wiring layer 30 has been polished by a CMP process. Figure 4(c) shows that the initial topography of the wafer surface is measured, and the non-uniformity of the wafer surface is measured. It is determined that the height difference of the wafer surface is below a certain standard, and a re-plating process is carried out. Figures 4(d) and 4(e) show that the re-plating process is stopped by the alpha coefficient and the CMP process is carried out. After the plating process and the CMP process, the uniformity of the wafer surface is measured again, and since no additional plating or CMP process is necessary, the CMP process is completed. In the embodiment in Figure 4, an electric field can be applied during each CMP process for electrophoretic phenomena.

[0202] Figure 5 shows a chemical mechanical planarization method in a semiconductor manufacturing process according to one embodiment of the present invention, in which an electric field (current) is applied one or more times during the CMP process, followed by an electroplating process. In addition, wafer surface planarization can be achieved by performing another CMP process, an additional electroless plating process, and another CMP process. Cleaning and drying processes are performed between each process.

[0203] Figure 6 is a schematic diagram of the process according to the embodiment of Figure 5. Figure 6(a) shows a wafer (device) in which a barrier layer 20 is formed on a dielectric layer 10 and a metal wiring layer 30 is formed on top of it by an initial plating process. Figure 6(b) shows a wafer in which a portion of the metal wiring layer 30 has been polished by a CMP process. Figure 6(c) shows the initial topography of the wafer surface being measured, the non-uniformity of the wafer surface being measured, and if the height difference of the wafer surface is judged to be below a certain standard, a re-plating process is carried out. Figure 6(d) shows the re-plating process being stopped by the α coefficient and the CMP process being carried out. After the plating process and CMP process, the uniformity of the wafer surface is remeasured, and if additional plating and CMP processes are necessary, electroless plating is additionally carried out as shown in Figure 6(e). Subsequently, surface planarization is achieved by carrying out a CMP process as shown in Figure 6(f). After that, if the uniformity of the wafer surface is remeasured and additional plating and CMP processes are necessary, electroless plating can also be additionally carried out. In the embodiment of Figure 6, an electric field can be applied during each CMP process for electrophoretic phenomena.

[0204] This allows for minimizing dishing and corrosion problems and achieving a high degree of wafer surface planarization by applying an electric field during the CMP process or by introducing a plating process.

[0205] Figure 7 shows a process in which an electric field (current) is applied one or more times during the CMP process, followed by an additional plating process and then another CMP process. Cleaning and drying processes can be performed between each process.

[0206] The following describes a chemical mechanical planarization apparatus in a semiconductor manufacturing process according to one embodiment of the present invention. Parts that overlap with the above description will be omitted.

[0207] In Figure 9, a chemical mechanical planarization apparatus in a semiconductor manufacturing process according to one embodiment of the present invention is an apparatus for performing chemical mechanical planarization, and includes a CMP equipment 200 for performing the CMP process and an electric field application control unit 720 for applying an electric field to the wafer surface.

[0208] According to one embodiment of the present invention, an apparatus for performing chemical mechanical planarization in a semiconductor manufacturing process includes: a CMP equipment 200 formed on one side of an element formation equipment 100 and performing a CMP process to planarize the wafer surface; a plating equipment 300 formed on one side of the CMP equipment 200 and performing a plating process to plate the wafer surface; a measuring unit 600 that measures the initial topography of the wafer surface provided by the element formation equipment 100 and senses non-uniformity; a control unit 700 that senses the height difference (h0-h1) of the wafer surface measured by the measuring unit 600 and controls the CMP equipment 200 and the plating equipment 300; and a transfer system for transferring wafers in each of the element formation equipment 100, the CMP equipment 200 and the plating equipment 300.

[0209] According to an embodiment of the present invention, the distribution of charged particles is adjusted by applying an electric field during the CMP process, thereby controlling the etching rate of the wafer surface. The electric field application control unit 720 concentrates the electric field on a specific area of ​​the wafer surface to improve the uniformity of etching and minimize dishing and corrosion. Unlike general CMP equipment, this apparatus provides greater precision in wafer surface planarization by adding a control unit 700 that includes an electric field application control unit 720 capable of applying an electric field.

[0210] The wafers manufactured in the element formation equipment 100 are transferred to the CMP equipment 200 and the plating equipment 300 to carry out each process. The element formation equipment 100 according to one embodiment of the present invention carries out the process in a vacuum state and may be PVD or an e-Bean Evaporator, etc.

[0211] The CMP equipment 200 is formed on one side of the element formation equipment 100 and is used to planarize the wafer surface. It physically polishes the wafer surface using a polishing pad and slurry, and forms a uniform surface through a chemical reaction.

[0212] The plating equipment 300 deposits a metal wiring layer 30 onto the wafer surface after the CMP process, and may include one or more of either electroplating equipment 300 or electroless plating equipment 300.

[0213] The measuring unit 600 measures the topography of the wafer surface and can be used to measure the height difference of the wafer surface to confirm the flatness after the CMP process or to measure the thickness of the metal wiring layer 30 before and after plating. In other words, it can be used to measure the initial topography or to remeasure after the CMP process, and thus it is possible to determine whether an additional CMP process is necessary.

[0214] The control unit 700 controls the CMP equipment 200 and the plating equipment 300, and can automatically adjust the process based on the data measured by the measuring unit 600. The control unit 700 determines whether or not to perform the CMP process and the plating process based on the height difference (h0-h1) of the wafer surface. That is, the control unit 700 controls whether to perform the plating process when the height difference of the wafer surface is below a certain standard, or to perform an additional CMP process if necessary. Furthermore, it can automatically control the operation of the CMP equipment 200 and the plating equipment 300 based on data measured in real time.

[0215] The transfer system (e.g., a robotic arm) is for smoothly transferring wafers between the element formation equipment 100, the CMP equipment 200, and the plating equipment 300, and it moves the wafers in a vacuum to prevent contamination and oxidation that may occur during the process.

[0216] In other words, the wafer is safely transported under vacuum, the transitions between the device formation, CMP, and plating processes are smoothed, and the wafer surface is prevented from oxidizing between processes.

[0217] The present invention, in one embodiment, is a chemical mechanical planarization apparatus for a semiconductor manufacturing process that provides a wafer in a vacuum state from an element formation apparatus 100, and includes a CMP apparatus 200, a plating apparatus 300, a measuring unit 600, a control unit 700, and a transfer system. The apparatus measures the initial topography of the wafer to identify non-uniformity, performs a CMP process to remove the non-uniformity of the wafer, plates a metal onto the wafer surface after the CMP process, measures whether the surface has become flat after plating, and the control unit 700 confirms whether an additional CMP or plating process is necessary. The transfer system safely transfers the wafer without contamination between all processes.

[0218] On the other hand, the CMP equipment 200 for the CMP process and the plating equipment 300 for the plating process may include one or more partitions 400 between the element forming equipment 100, the CMP equipment 200, and the plating equipment 300 to maintain a vacuum state for the element forming equipment 100 and to maintain an inert gas atmosphere for the CMP equipment 200 and the plating equipment 300.

[0219] A partition wall 400 is installed between the element formation equipment, the CMP equipment 200, and the plating equipment 300 to maintain the process atmosphere while the wafer moves between each process, thereby protecting the wafer from potential vacuum disruption, oxidation, and contamination that may occur when the wafer moves between the equipment.

[0220] According to one embodiment of the present invention, the partition wall 400 opens while the wafer is being transported and closes while each process is being carried out. For example, the partition wall 400 is formed to open when a sensor detects that the wafer has arrived in the transport area and close when the transport is complete, and can be made of a chemically stable metal or a highly durable synthetic material. For example, it can be made of tempered glass or stainless steel. Alternatively, a vacuum-equipped load lock can perform this role.

[0221] In one embodiment of the present invention, during the CMP process, an electric field is applied to the wafer surface by an electric field application control unit 720 to induce the movement of charged particles in the slurry and adjust the local etching rate of the metal surface. By periodically repeating the electric field application stage and the waiting stage, excessive etching is prevented and uniform planarization is achieved. After the CMP process, the uniformity of the wafer surface is evaluated, and if it is below a standard, plating and additional CMP processes are performed to ensure uniformity. Electrolytic plating and electroless plating are selectively performed to maintain a uniform etching rate on the wafer surface. An inert gas is supplied to prevent oxidation of the wafer surface during the CMP or plating process.

[0222] Figure 10 is a schematic diagram showing various embodiments of a chemical mechanical planarization apparatus in a semiconductor manufacturing process according to one embodiment of the present invention, illustrating various electric field application methods for planarizing the wafer surface using slurry and an electric field in the semiconductor CMP process.

[0223] The chemical mechanical planarization apparatus shown in Figure 10(a) includes a conductive substrate (conductor plate), a wafer (substrate), an insulator, a slurry, a platen (polishing pad), a voltage source (electric field application control unit), and a control unit. The conductor plate is located on top of the wafer and forms an electric field through the wafer and the insulator. An electric field is applied by creating a potential difference between the conductor plate and the platen via the voltage source, and this electric field induces the movement of charged particles present in the slurry. In this method, the distribution and movement of charged particles in the slurry can be controlled by applying an electric field perpendicular to the wafer surface. Therefore, the etching rate of the wafer surface can be uniformly adjusted, and the desired planarization can be achieved. In addition, the effects of impurities such as oxidation can be minimized by supplying an inert gas.

[0224] By providing an inert gas supply unit, oxidation of the wafer during the CMP process is prevented using an inert gas (e.g., argon, helium), and the behavior of charged particles in the slurry is stabilized when an electric field is applied, enabling uniform etching.

[0225] The chemical mechanical planarization apparatus shown in Figure 10(b) includes a conductive plate, a wafer (substrate), an insulator, a slurry, a platen, a voltage source (electric field application control unit), and a control unit. A voltage is applied through the conductive plate to generate an electric field on the wafer surface. Here, the electric field is designed to uniformly distribute charged particles within the slurry. The distribution of charged particles within the slurry is controlled uniformly to planarize the wafer surface. Therefore, minute height differences on the wafer surface can be minimized, and precise planarization can be achieved.

[0226] The chemical mechanical planarization apparatus shown in Figure 10(c) includes a conductive plate (including a portion of an insulator), a wafer (substrate), a slurry, a platen, a voltage source (electric field application control unit), and a control unit. A portion of the conductive plate is made of an insulator, and thus the electric field is controlled to concentrate only in a specific region. By forming a portion of the conductive plate with an insulator, the concentration of the electric field is adjusted. As a result, the etching rate of the wafer surface can be adjusted more precisely, and localized planarization can be achieved by concentrating the electric field in a specific region.

[0227] The chemical mechanical planarization apparatus shown in Figure 10(d) includes a conductive plate, a wafer (substrate), an insulator, a slurry, a platen, a current source (electric field application control unit), and a control unit. By directly applying current to the wafer via the conductive plate, the charged particles in the slurry are adjusted. The current source creates a potential by flowing current, controlling the movement of ions in the slurry. Planarization is performed by applying a current, not a voltage. Therefore, electric field formation in specific regions is possible locally, and the etching rate of the wafer surface can be finely adjusted. Thus, planarization can be performed more accurately.

[0228] This method controls the distribution of charged particles in the slurry by applying an electric field or current to the wafer surface, thereby adjusting the etching rate of the wafer surface and performing planarization. Each method is applicable depending on the process conditions and can provide effects such as uniform surface planarization, oxidation prevention, and precise adjustment of the etching rate.

[0229] As described above, the various methods from (a) to (d) achieve wafer surface planarization by applying an electric field and adjust the etching rate by controlling the ion distribution and the movement of charged particles in the slurry during the process. Therefore, it is possible to ensure high wafer planarization, oxidation prevention, and uniform process conditions in the semiconductor manufacturing process.

[0230] Thus, the electric field application control unit according to the embodiment of the present invention plays the role of applying an electric field to the wafer surface during the CMP process, thereby adjusting the movement and distribution of charged particles in the slurry and controlling the etching rate of the wafer surface.

[0231] As described above, the electric field application control unit controls the distribution of charged particles in the slurry by applying an electric field to the wafer surface to form a potential difference between the metal and the insulator. Such an electric field affects the surface etching rate, and by adjusting this, a uniform planarization process can be achieved.

[0232] Furthermore, the electric field application control unit finely adjusts the strength and direction of the electric field to control the local etching rate of the wafer surface. For example, surface planarization can be induced by applying a stronger electric field to a specific area to increase or decrease the etching rate in that area.

[0233] Furthermore, by creating an electric potential at specific locations on the wafer surface and changing the local distribution of charged particles in the slurry, the etching rate can be controlled locally. Therefore, the etching rate can be uniformly adjusted in regions with different metal pattern densities.

[0234] Furthermore, the electric field application control unit precisely adjusts the etching rate by periodically repeating the steps of applying and waiting for the electric field to be applied. This prevents localized non-uniformity from occurring during the planarization process.

[0235] Furthermore, when applying an electric field, the electric field is precisely controlled by adjusting the voltage to prevent current from flowing across the wafer surface, or by applying a localized current through a conductive substrate to create a potential. This adjustment controls the movement and reaction of ions within the slurry, optimizing the etching rate.

[0236] Furthermore, the electric field application control unit ensures uniformity of the electric field across the entire wafer surface and can selectively apply the electric field to areas with high and low metal area density. This function compensates for regional etching non-uniformity and improves the final planarization level.

[0237] Thus, the electric field application control unit is used to utilize the electrophoretic phenomenon during the overall CMP process. By precisely adjusting the electric field strength, direction, and application time, it plays a crucial role in achieving uniform surface planarization and the optimal etching rate.

[0238] As described above, according to the embodiments of the present invention, the etching rate of the wafer surface can be locally adjusted by applying an electric field or electric current to control the distribution of charged particles in the slurry. Therefore, excessive dishing and erosion can be minimized in the CMP process, and uniform surface planarization can be achieved.

[0239] Furthermore, by controlling the charged particles (cations and anions) present in the slurry with an electric field or electric current, they can be concentrated on specific parts of the wafer surface. Therefore, the etching rate of metals and insulators can be adjusted, allowing for selective planarization of only the desired areas.

[0240] Furthermore, oxidation of the wafer surface can be prevented by carrying out the process in an inert gas atmosphere or by introducing an insulator. This prevents oxidation of the metal wiring layer and subsequent deterioration of its electrical properties, thereby improving process quality.

[0241] Furthermore, by adjusting the application period, which controls the periodic application of an electric field, unnecessary etching during the CMP process can be prevented, enabling efficient material removal. In addition, if the uniformity of the wafer surface is measured to be below the standard, the number of repetitions of the CMP and plating processes can be reduced, thereby increasing productivity.

[0242] Furthermore, the electric field in a specific region can be locally concentrated by using a conductive plate containing an insulator or by a current application method. Therefore, complex patterns and height differences in specific regions can be effectively flattened.

[0243] Furthermore, by controlling the symmetry and intensity of the electric field distribution, it is possible to apply differential electric fields to regions with high and low metal area density. Therefore, it is possible to adjust the local etching rate while maintaining uniformity across the entire wafer surface.

[0244] Thus, according to one embodiment of the present invention, high-quality quantum devices can be manufactured by improving the CMP process to minimize the problems of dishing and erosion, and by improving the flatness of the wafer surface.

[0245] Furthermore, it is possible to solve oxidation and contamination problems that may occur during the continuous execution of the CMP and plating processes, and improve productivity through an automated transfer system between processes and precise process control.

[0246] Therefore, since high-quality quantum elements can be manufactured, superior performance can be provided in high-precision application fields such as quantum computers and quantum communication. [Explanation of Symbols]

[0247] 10 Dielectric layer 20 Barrier layer 30 Metal wiring layer 40 Metal wiring 100 element formation equipment Equipped with 200 CMPs 300 Plated 400 Bulkhead 500 Inert gas supply unit 600 Measuring part 700 Control Unit 720 Electric field application control unit

Claims

1. A chemical mechanical planarization method in the semiconductor manufacturing process, A chemical mechanical planarization method in semiconductor manufacturing, which uses electrophoresis during the CMP (Chemical Mechanical Planarization) process to apply an electric field to the wafer surface and control the distribution of charged particles in the slurry.

2. The method for chemical mechanical planarization in a semiconductor manufacturing process according to claim 1, wherein the electric field is applied perpendicularly to the wafer surface to change the distribution of ions in the slurry by the potential difference between the metal and the insulator, thereby adjusting the local etching rate of the metal surface.

3. The chemical mechanical planarization method in a semiconductor manufacturing process according to claim 2, wherein the application of the electric field concentrates negatively charged or positively charged ions in the slurry onto the metal surface to reduce the etching rate of the metal.

4. A chemical mechanical planarization method in a semiconductor manufacturing process according to claim 2, wherein a plating process is performed after the CMP process, and after the CMP process and the plating process, the uniformity of the wafer surface is measured, and if it is below a standard, an additional plating process and a CMP process are repeated.

5. The chemical mechanical planarization method for semiconductors according to claim 4, wherein the plating step includes at least one of an electrolytic plating step or an electroless plating step.

6. After the plating process and the CMP process, if the height difference (h0-h1) on the wafer surface is measured to be below the standard, the alpha coefficient (w ｕｐ / w ｏｒｉｇｉｎａｌ A chemical mechanical planarization method in a semiconductor process according to claim 4, wherein if the ratio of the surface width before and after plating is 0.99 or less, the plating process is stopped and the CMP process is carried out.

7. A chemical mechanical planarization method in a semiconductor process according to claim 1, comprising applying a voltage to the wafer surface to form an electric field so that no current flows, thereby adjusting the etching rate of the wafer surface by regulating the movement of charged particles in the slurry.

8. A chemical mechanical planarization method in a semiconductor process according to claim 1, wherein the etching rate of the wafer surface is adjusted by applying an electric current to the wafer surface via a conductive substrate to form a potential difference and create an electric field.

9. A method for chemical mechanical planarization in a semiconductor process according to claim 1, wherein negatively charged ions in the slurry concentrate on the metal surface by electrophoresis, thereby reducing the rate of metal etching.

10. The chemical mechanical planarization method in the semiconductor manufacturing process is the chemical mechanical planarization method in the semiconductor process according to claim 1, wherein the CMP process is carried out in an inert gas atmosphere.

11. A method for chemical mechanical planarization in a semiconductor manufacturing process according to claim 1, comprising a standby stage in which no electric field is applied, and further comprising periodically repeating the electric field application stage and the standby stage.

12. A method for chemical mechanical planarization in a semiconductor manufacturing process according to claim 1, wherein the distribution of the electric field is controlled to have symmetrical heterogeneity with respect to the center of the wafer surface.

13. A chemical mechanical planarization method in a semiconductor manufacturing process according to claim 1, comprising applying a differential electric field to regions with high and low metal area density to adjust the etching rate.

14. A method for chemical mechanical planarization in a semiconductor process according to claim 1, further comprising performing an electroless plating process on a specific region of the wafer surface.

15. A chemical mechanical planarization method in a semiconductor process according to claim 14, wherein mechanical polishing is performed on the wafer surface after the electroless plating process.

16. Quantum superconductors used in semiconductor devices for quantum technology include Nb, Sn, Al, Zn, Ta, Nb-Ti, and Nb ３ Sn, V ３ Si, V ３ Ga, Nb ３ Ge, MgB ２ A chemical mechanical planarization method in a semiconductor manufacturing process according to claim 1, wherein the material is a mixture of one or more of the following: YBCO, BSCCO, Iron Pnictides, LBCO, Iron Chalcogenides, TBCCO, Hg-1223, and Iron-Based Superconductors.

17. An apparatus for performing chemical mechanical planarization in the semiconductor manufacturing process, A chemical mechanical planarization apparatus for a semiconductor manufacturing process, comprising a CMP equipment for performing a CMP process to planarize the wafer surface, and an electric field application control unit for applying an electric field to the wafer surface during the CMP process.

18. The electric field application control unit controls the distribution of ions in the slurry by applying an electric field perpendicular to the wafer surface to form a potential difference between the metal and the insulator, as described in claim 17.

19. The chemical mechanical planarization apparatus for a semiconductor manufacturing process according to claim 18, wherein the application of the electric field concentrates ions having a negative or positive charge on the wafer surface to reduce the rate of metal etching.

20. A chemical mechanical planarization apparatus for a semiconductor manufacturing process according to claim 17, comprising a measuring unit that performs a plating process on the wafer surface after a CMP process, measures the uniformity of the wafer surface after the CMP process and the plating process, and performs an additional plating process and a CMP process if it is below a standard.

21. The chemical mechanical planarization apparatus for a semiconductor manufacturing process according to claim 20, comprising at least one of electroplating equipment or electroless plating equipment for the aforementioned plating process.

22. The electric field application control unit applies a voltage to the wafer surface to form an electric field, thereby adjusting the etching rate by adjusting the movement of charged particles in the slurry, as described in claim 17.

23. The electric field application control unit adjusts the etching rate of the wafer surface by applying a current to the wafer surface via a conductive substrate to form a potential and locally creating an electric field, as described in claim 17.

24. The electric field application control unit controls negatively charged ions in the slurry to concentrate on the metal surface by electrophoresis, as described in claim 17, for use in a chemical mechanical planarization apparatus for a semiconductor manufacturing process.

25. A chemical mechanical planarization apparatus for a semiconductor manufacturing process according to claim 17, comprising an inert gas supply unit for performing the CMP process in an inert gas atmosphere in order to prevent oxidation of the wafer surface during the CMP process.

26. The inert gas is He, Ar, Ne, Kr, and N ２ A chemical mechanical planarization apparatus for a semiconductor manufacturing process according to claim 25, comprising at least one of the following.

27. The electric field application control unit controls the distribution of the electric field to have symmetrical non-uniformity with respect to the center of the wafer surface, as described in claim 17, a chemical mechanical planarization apparatus for a semiconductor manufacturing process.

28. The electric field application control unit adjusts the etching rate by applying a differential electric field to regions of high and low metal area density on the wafer surface, as described in claim 17, for a chemical mechanical planarization apparatus in a semiconductor manufacturing process.

29. The chemical mechanical planarization apparatus for a semiconductor manufacturing process according to claim 17, wherein the electric field application control unit periodically repeats a step of applying an electric field and a standby step of not applying an electric field to adjust the etching rate of the wafer surface.

30. The chemical mechanical planarization apparatus for a semiconductor manufacturing process according to claim 17, wherein the electric field application control unit controls the intensity and direction of the electric field to change over time, thereby adjusting the etching rate of a specific region on the wafer surface.

31. The electric field application control unit adjusts the distribution of the electric field and the direction of the current in order to locally adjust the etching rate of the wafer surface, as described in claim 17, a chemical mechanical planarization apparatus for a semiconductor manufacturing process.

32. The quantum superconducting materials used in semiconductor devices for quantum technology are Nb, Sn, Al, Zn, Ta, Nb-Ti, Nb ３ Sn, V ３ Si, V ３ Ga, Nb ３ Ge, MgB ２ , YBCO, BSCC0, iron pnictides, LBCO, iron chalcogenides, TBCC0, Hg-1223, and a substance obtained by mixing any one or more of iron-based superconductors, the chemical mechanical planarization apparatus in the semiconductor manufacturing process according to claim 17.

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