Analog-to-digital conversion circuit and analog-to-digital conversion method

Abstract

This invention provides an analog-to-digital conversion circuit that can shorten the conversion time. [Solution] An analog-to-digital conversion circuit is provided, comprising a window comparator connected to an analog input circuit, a comparator connected to the analog input circuit and a digital-to-analog conversion circuit, and a successive analog-to-digital conversion circuit connected to the window comparator. The successive analog-to-digital conversion circuit detects the detection range of the window comparator and uses the window comparator to convert the upper m (m is a natural number) bits.

Description

Technical Field

[0001] The present disclosure relates to an analog-to-digital conversion circuit and an analog-to-digital conversion method.

Background Art

[0002] Analog-to-digital conversion circuits have been developed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, a successive conversion type analog-to-digital conversion circuit has a problem that the conversion takes time. Therefore, an object of the present disclosure is to provide an analog-to-digital conversion circuit or the like that can shorten the conversion time.

[0005] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0006] According to one embodiment, an analog-to-digital conversion circuit includes a window comparator connected to an analog input circuit, and a comparator connected to the analog input circuit and a digital-to-analog conversion circuit, and includes a successive conversion type analog-to-digital conversion circuit connected to the window comparator.

Effects of the Invention

[0007] According to the above embodiment, an analog-to-digital conversion circuit and the like that can shorten the conversion time are provided. [Brief explanation of the drawing]

[0008] [Figure 1] This is a diagram showing the configuration of a related successive analog-to-digital conversion circuit. [Figure 2] This is a circuit diagram of an analog-to-digital conversion circuit using related window comparators. [Figure 3] This is a block diagram showing the configuration of a related window comparator and a successive analog-to-digital conversion circuit. [Figure 4] This is a block diagram showing the configuration of the first analog-to-digital conversion circuit of this disclosure. [Figure 5] This is an illustrative diagram of priority interrupt processing using the second analog-to-digital conversion circuit of this disclosure. [Modes for carrying out the invention]

[0009] For clarity of explanation, the following descriptions and diagrams have been omitted and simplified as appropriate. Furthermore, each element shown in the diagrams as a functional block performing various processes can, for example, be composed of a CPU (Central Processing Unit), memory, and other circuits in hardware terms, and implemented in software terms by a program loaded into memory. Therefore, these functional blocks can be implemented by hardware, software running on the hardware, or a combination thereof. Note that identical elements are denoted by the same reference numeral in each diagram, and redundant explanations have been omitted where necessary.

[0010] Furthermore, the aforementioned programs can be stored and supplied to a computer using various types of non-transitory computer-readable media. Non-transitory computer-readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (e.g., flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (e.g., magneto-optical disks), CD-ROMs (Read Only Memory), CD-Rs, CD-R / Ws, and semiconductor memory (e.g., mask ROMs, PROMs (Programmable ROMs), EPROMs (Erasable PROMs), flash ROMs, and RAMs (Random Access Memory)). Programs may also be supplied to a computer using various types of transient computer-readable media. Examples of transient computer-readable media include electrical signals, optical signals, and electromagnetic waves. Transitory computer-readable media can be supplied to a computer via wired communication channels such as electric wires and optical fibers, or via wireless communication channels.

[0011] (Explanation of related successive analog-to-digital conversion circuits) Figure 1 is a block diagram showing the configuration of a related successive analog-to-digital conversion circuit. Figure 2 is a circuit diagram of an analog-to-digital conversion circuit using a related window comparator. Figure 3 is a block diagram showing the configuration of a related window comparator and a successive analog-to-digital conversion circuit. The related successive analog-to-digital conversion circuit will be explained with reference to Figures 1 to 3.

[0012] As shown in FIG. 1, the successive conversion type analog-to-digital conversion circuit 10 includes a comparator 11 connected to a DAC (Digital Analog Converter) 12 that generates an analog input and a Ref (Reference) potential. In the comparator, as shown in comparison 13 of the analog input and the Ref potential, the potential of the analog input and the Ref potential are compared.

[0013] As shown in the lower diagram of FIG. 1, first, the analog input potential and the 1 / 2Ref potential are compared. Since the analog input potential is greater than the 1 / 2Ref potential, the MSB (Most Significant Bit) is set to 1. Next, the 3 / 4 potential is generated by the DAC 12, and the analog input potential 1 and the 3 / 4Ref potential are compared. Since the analog input potential is less than the 3 / 4Ref potential, the next bit is set to 0.

[0014] Thus, while dividing the Ref potential by 1 / 2 and adding, it is compared with the analog potential. If it exceeds, the bit is set to 1, and if it does not exceed, the bit is set to 0 to make the Ref potential approach the analog potential. When all n bits are executed, the analog input potential is converted into an n-bit digital potential.

[0015] The successive conversion type analog-to-digital conversion circuit requires n cycles and takes time for conversion.

[0016] Therefore, as shown in FIG. 2, there is a window comparator (WC) that shortens the conversion time. The window comparator converts an analog potential between Vref1 and Vref2 into a digital potential.

[0017] If the analog potential is between Vref1 and Vref2, it can be easily converted from analog to digital, but there is a problem of poor accuracy.

[0018] Therefore, as shown in FIG. 3, there is a circuit that performs analog-to-digital conversion by combining a window comparator and a successive conversion type analog-to-digital conversion circuit.

[0019] The analog-digital conversion circuit 30 includes a plurality of window comparators 31 connected to an analog input circuit, and a comparator 32 connected to the analog input circuit and the DAC 33. The analog-digital conversion circuit 30 converts the upper bits with the window comparator 31 and the lower bits with the comparator 32.

[0020] As shown in the lower diagram of FIG. 3, when an analog input potential is input, the window comparator 31 determines the upper bits on the MSB side (1). Then, the comparator 32 that inherits the upper bits from the window comparator 31 starts comparison from the set potential. And the comparator 32 performs analog-digital conversion only for the lower bits.

[0021] In this case, there is no need to convert from the REF potential [Max] / 2. Also, although the operation cycles of the input terminal side sample hold (S&H) circuit, R2R circuit, etc. are necessary (1), the conversion time can be shortened. However, a large number of window comparators need to be operated in parallel, resulting in increased power consumption. Also, there are issues in ensuring the accuracy of the window comparators.

[0022] (Description of the analog-digital conversion circuit of the present disclosure) FIG. 4 is a block diagram showing the configuration of the first analog-digital conversion circuit of the present disclosure. The analog-digital conversion circuit of the present disclosure will be described while referring to FIG. 4.

[0023] As shown in FIG. 4, the first analog-digital conversion circuit 400 includes one window comparator 403 connected to an external analog input circuit 402, and a sample hold circuit or R2R circuit 404 connected to the analog input circuit 402. The sample hold circuit is also called a sample & hold circuit (S&H circuit).

[0024] The window comparator 403 is connected to the successive analog-to-digital conversion circuit 401. The window comparator 403 outputs the higher bits. The sample-and-hold circuit, or R2R circuit 404, is connected to the comparator 405.

[0025] The successive analog-to-digital conversion circuit 401 includes a comparator 405 and a DAC 406 for generating a reference potential. The comparator 405 receives an analog input by connecting one end to a sample-and-hold circuit or an R2R circuit 404, and a reference potential input by connecting the other end to the DAC 406. The comparator 405 compares the analog input with the reference potential. The comparator 405 outputs the lower bits.

[0026] As shown in the lower part of Figure 4, the window comparator 403 includes the analog input potential between its upper and lower reference potentials. Therefore, the window comparator 403 can determine the upper bits on the MSB side. The comparator 405 inherits the upper bits from the setting of the window comparator 403 and starts the comparison from the set potential.

[0027] The conversion start cycle begins when the analog-to-digital conversion circuit detects the detection range of the window comparator 403 and uses the window comparator 403 to convert the upper m (m is a natural number) bits. In other words, the inheritable upper bits are determined from the setting range of the window comparator 403. The position of pointer 407 is specified as the conversion start cycle. Pointer 407 can also utilize the cycle counter in an existing analog-to-digital conversion sequencer. If the total number of bits is n, the lower nm bits are converted using the comparator (6). The nm bits can be set arbitrarily.

[0028] By providing a single window comparator 403 outside the successive analog-to-digital conversion circuit 401, it is not necessary to use multiple window comparators. Furthermore, the operation cycle of the window comparator can be hidden by the operation cycle of the input terminal side sample-and-hold circuit or R2R circuit, thus shortening the conversion time (1). In addition, it is not necessary to convert from the REF potential [Max] / 2 (2).

[0029] Furthermore, as shown in the lower left diagram of Figure 4, when multiple system processes are branched, the window comparator 403 can detect this, allowing some system processes to be executed while the window comparator 403 is processing. For example, module A can be loaded before the analog-to-digital conversion is complete. Alternatively, another branch may be triggered when comparator 405 completes the analog-to-digital conversion. For example, a branch may be triggered based on the result of the analog-to-digital conversion. In this way, the overall branching process can be advanced based on the detection result of the window comparator 403, and time can be reduced by preloading data for the expected next processing section.

[0030] (Description of the analog-to-digital conversion circuit according to Embodiment 2) Figure 5 is an illustrative diagram of priority interrupt processing using the second analog-to-digital conversion circuit of this disclosure. The second analog-to-digital conversion circuit will be described with reference to Figure 5.

[0031] As shown in Figure 5, the second analog-to-digital conversion circuit 500 comprises a plurality of analog input circuits 501, a sample-and-hold circuit 502 connected to one of the plurality of analog input circuits 501, an analog switching circuit 503 connected to the sample-and-hold circuit 502, and a successive analog-to-digital conversion circuit 401. The plurality of analog input circuits 501 are connected to a window comparator 403.

[0032] Consider the case where, while analog-to-digital conversion 504 of analog input 1 is being performed, a request for analog-to-digital conversion 505 of analog input 1', which has a higher priority, is received. Since the sample-and-hold circuit is placed between one of the multiple analog input circuits 501 and the analog switching circuit 503, the input potential can be held. Therefore, for example, after performing m-bit analog-to-digital conversion 504 with the window comparator 403, analog-to-digital conversion 505 can be performed, and then nm-bit analog-to-digital conversion 504 can be performed again with the successive-type analog-to-digital conversion circuit 401.

[0033] In other words, the analog-to-digital converter 504 is capable of priority interrupt processing. Depending on the holding characteristics of each input potential, it may also accept interrupts with even higher priority. By restarting the analog-to-digital conversion of analog input potential 1 after the conversion of analog potential 1' is complete, the potential holding period by the sample-and-hold circuit is shortened, and an improvement in accuracy can be expected. Track and hold may be used instead of the sample-and-hold circuit. In this disclosure, an example is shown in which the sample-and-hold circuit is connected to one of multiple analog input circuits, but the sample-and-hold circuit may be connected to each of the multiple analog input circuits.

[0034] Thus, when the input potential can be held using a sample-and-hold circuit, it is possible to execute a priority interrupt during the analog-to-digital conversion of multiple inputs, and then resume the analog-to-digital conversion after the priority processing is complete.

[0035] This disclosure is applicable to methods as appropriate. For example, this disclosure provides an analog-to-digital conversion method for an analog-to-digital conversion circuit comprising a window comparator connected to an analog input circuit, a comparator connected to the analog input circuit and a digital-to-analog conversion circuit, and a successive analog-to-digital conversion circuit connected to the window comparator. The analog-to-digital conversion method detects the detection range of the window comparator and uses the window comparator to convert the upper m (m is a natural number) bits.

[0036] The present invention has been described in detail above based on embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible without departing from the spirit of the invention. [Explanation of Symbols]

[0037] 400 First analog-to-digital conversion circuit, 401 Successive analog-to-digital conversion circuit, 402 Analog input circuit, 403 Window comparator, 404 Sample-and-hold circuit, or R2R circuit, 405 Comparator, 406 DAC, 407 Pointer, 500 Second analog-to-digital conversion circuit, 501 Multiple analog input circuits, 502 Sample-and-hold circuit, 503 Analog switching circuit, 504 Analog-to-digital conversion, 505 Analog-to-digital conversion

Claims

1. A window comparator connected to the analog input circuit, The analog input circuit and the digital-to-analog conversion circuit are connected to a comparator, and the window comparator is connected to a successive analog-to-digital conversion circuit, An analog-to-digital conversion circuit equipped with this feature.

2. The analog-to-digital conversion circuit according to claim 1, wherein the successive analog-to-digital conversion circuit detects the detection range of the window comparator and converts the upper m (where m is a natural number) bits using the window comparator.

3. Let the total number of bits be n (where n is a natural number). The analog-to-digital conversion circuit according to claim 2, wherein the comparator is used to convert n-m bits.

4. The analog-to-digital conversion circuit according to claim 3, wherein the n-m bits can be arbitrarily changed.

5. Multiple analog input circuits, The system comprises a sample-and-hold circuit positioned between a plurality of analog input circuits and a successive analog-to-digital conversion circuit, The analog-to-digital conversion circuit according to claim 3, wherein priority interrupt processing is performed among a plurality of analog input circuits based on the analog-to-digital conversion by the window comparator or the analog-to-digital conversion by the comparator.

6. The system processing has multiple branches, The analog-to-digital conversion circuit according to claim 2, which performs some system processing after branching, triggered by the analog-to-digital conversion by the window comparator or the analog-to-digital conversion by the comparator.

7. A window comparator connected to the analog input circuit, An analog-to-digital conversion method for an analog-to-digital conversion circuit comprising an analog input circuit and a comparator connected to the digital-to-analog conversion circuit, and a successive analog-to-digital conversion circuit connected to the window comparator, wherein An analog-to-digital conversion method that detects the detection range of the aforementioned window comparator and converts the upper m (where m is a natural number) bits using the aforementioned window comparator.

8. Let the total number of bits be n (where n is a natural number). The analog-to-digital conversion method according to claim 7, wherein n-m bits are converted using the aforementioned comparator.

9. The analog-to-digital conversion method according to claim 8, wherein the n-m bits can be arbitrarily changed.

10. The aforementioned analog-to-digital conversion circuit Multiple analog input circuits, The system comprises a sample-and-hold circuit positioned between a plurality of analog input circuits and a successive analog-to-digital conversion circuit, The analog-to-digital conversion method according to claim 8, wherein priority interrupt processing is performed among a plurality of analog input circuits based on the analog-to-digital conversion by the window comparator or the analog-to-digital conversion by the comparator.

11. The aforementioned analog-to-digital conversion circuit The system processing has multiple branches, The analog-to-digital conversion method according to claim 7, wherein some system processing after branching is performed while the analog-to-digital conversion by the window comparator is being carried out.

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