Multilayer ceramic electronic components and circuit boards

Abstract

This invention provides multilayer ceramic electronic components with low equivalent series inductance (ESL) and improved mountability on circuit boards. [Solution] In the multilayer ceramic capacitor 100, the base body 10 has a laminate 20 in which ceramic layers 21 and internal electrodes 22a and 22b mainly composed of metal are alternately stacked. The base body has a plurality of via conductors 23a and 23b arranged to penetrate the ceramic layers in the stacking direction, with one end extended to the surface of the laminate and electrically connected to the internal electrodes. Terminal electrodes 40a and 40b electrically connected to the via conductors are arranged on the surface from which the ends of the via conductors are extended. The surface from which the ends of the via conductors are extended and the terminal electrodes are arranged is surrounded by a peripheral edge 111 and has a raised structure composed of a raised portion 112 that rises relative to the peripheral edge, and a portion of each terminal electrode is located on the slope of the raised portion.

Description

[Technical Field]

[0001] This invention relates to multilayer ceramic electronic components and circuit boards. [Background technology]

[0002] In recent years, with the increasing sophistication of electronic devices such as smartphones, the semiconductors used have also become more high-performance. Because high-performance semiconductors are more susceptible to noise, multilayer ceramic capacitors (MLCCs) are used as decoupling capacitors to eliminate this noise.

[0003] In multilayer ceramic capacitors for decoupling capacitors, it is known that in order to reduce the equivalent series inductance (ESL), multiple conductors (via conductors) are provided for each polarity to electrically connect the external electrode placed on the main surface with multiple internal electrodes, and that they are arranged so that the magnetic fields generated by the flowing current cancel each other out (Patent Document 1).

[0004] Furthermore, in recent years, with the miniaturization of multilayer ceramic capacitors, efforts have been made to accurately mount small multilayer ceramic capacitors onto circuit boards. For example, as a method of controlling the flow of solder when mounting multilayer ceramic capacitors onto a circuit board, it is known that the end face, which is the surface from which the internal electrodes are drawn out and connected to the external electrodes, is tapered in shape, widening from the main surface facing the circuit board to the top surface facing the main surface (Patent Document 2). [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2001-148324 [Patent Document 2] Japanese Patent Publication No. 2021-120977 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] In the multilayer ceramic capacitor disclosed in Patent Document 1, which has multiple via conductors for each polarity, the ESL decreases as the distance between via conductors of different polarities decreases. Therefore, from the viewpoint of reducing ESL, it is preferable to reduce the distance between via conductors of different polarities and also reduce the distance between external electrodes electrically connected to them. However, the smaller the distance between external electrodes of different polarities, the higher the possibility that the external electrodes will connect to each other due to wetting and spreading solder when mounted on a circuit board. For this reason, there was a limit to reducing ESL by narrowing the spacing between via conductors and external electrodes.

[0007] In the multilayer ceramic capacitor with tapered end faces disclosed in Patent Document 2, the current path cannot be brought closer than the distance between opposing end faces, so the effect of reducing ESL was limited.

[0008] The present invention was made to solve the above problems and aims to provide a multilayer ceramic electronic component with low ESL and improved mountability on a circuit board, and a circuit board on which the electronic component is mounted. [Means for solving the problem]

[0009] The inventors of the present invention conducted various studies to solve the aforementioned problems and found that the above objective can be achieved by providing a multilayer ceramic electronic component in which the ends of via conductors are drawn out and at least one of the main surfaces on which terminal electrodes are arranged has a raised structure composed of a peripheral portion and a raised portion surrounded by the peripheral portion and rising relative to the peripheral portion, and by configuring each of the terminal electrodes so that at least a part of them is located on the slope of the raised portion, thus completing the present invention.

[0010] In other words, the first aspect of the present invention for solving the above problems is a laminate in which ceramic layers and internal electrodes mainly composed of metal are alternately stacked, a protective part covering the surface of the laminate, and a rectangular parallelepiped body having a plurality of via conductors arranged to penetrate the ceramic layers in the stacking direction of the laminate, with at least one end drawn out to the surface of the protective part and electrically connected to the internal electrodes, and a plurality of terminal electrodes, which are electrically connected to at least one of the plurality of via conductors, and which are arranged on the surface from which the ends of the via conductors are drawn out, among the surfaces forming the surface of the body, wherein at least one of the two main surfaces of the body, which consists of the surface from which the ends of the via conductors are drawn out and the surface opposite to the surface, has a raised structure consisting of a peripheral portion and a raised portion surrounded by the peripheral portion and rising relative to the peripheral portion, and at least a part of each of the terminal electrodes arranged on the main surface having the raised structure is located on the slope of the raised portion.

[0011] Furthermore, a second aspect of the present invention for solving the aforementioned problems is a circuit board on which the multilayer ceramic electronic component relating to the first aspect is mounted. [Effects of the Invention]

[0012] According to the present invention, it is possible to provide a multilayer ceramic electronic component with low ESL and improved mountability on a circuit board, and a circuit board on which the electronic component is mounted. [Brief explanation of the drawing]

[0013] [Figure 1] This is a schematic diagram (perspective view) showing the structure of a multilayer ceramic capacitor according to the first embodiment of the present invention. [Figure 2] This is a cross-sectional view of AA in Figure 1. [Figure 3] This is a schematic diagram illustrating the procedure for determining whether the main surface of the base body has a raised structure, and the procedure for determining whether at least a portion of the terminal electrodes placed on the main surface are located on the slope of the raised portion. [Figure 4a] This is a schematic diagram illustrating the procedure for determining whether the end of a via conductor extended from the main surface of the base body is located on the slope of a raised portion. [Figure 4b] This is a schematic diagram illustrating how to handle cases where the end of a via conductor drawn out to the main surface of a base body does not reach the main surface of the base body when determining whether the end of the via conductor being determined is located on the slope of a raised portion. [Figure 5] This is a schematic diagram illustrating the procedure for determining the maximum height of a raised structure relative to its periphery. [Figure 6] This is a schematic diagram illustrating the procedure for determining the distance from the outer edge of the main surface to the boundary between the periphery and the raised portion in a raised structure, and the procedure for determining the inclination angle of the periphery in a main surface having a raised structure. [Figure 7] This is a cross-sectional view showing the structure of a multilayer ceramic capacitor in which one of the main surfaces has a raised structure and the other has a flat shape. [Figure 8a] This is a schematic diagram (perspective view) showing the position of a cross-section parallel to the stacking direction of the laminate, passing through the diagonal of the main surface on which the raised portion is formed, in a multilayer ceramic capacitor according to the first embodiment of the present invention. [Figure 8b] This is a schematic diagram showing a case in a multilayer ceramic capacitor according to the first embodiment of the present invention, where the raised portion of the main surface has two peaks in a cross section perpendicular to the stacking direction of the laminate that passes through the diagonal of the main surface, i.e., in the BB cross section in Figure 8a. [Figure 9] This is a schematic diagram illustrating the procedure for determining whether a raised portion of the main surface has two peaks in a cross-section parallel to the stacking direction of the laminate that passes through the diagonal of the main surface, as well as the procedure for determining the distance between each peak and the protrusion height of each peak from the lowest point between each peak. [Figure 10a] This is a schematic diagram (plan view from the T-axis direction) showing an example of the size of the terminal electrodes in a multilayer ceramic capacitor according to the first embodiment of the present invention. [Figure 10b] This is a schematic diagram (plan view from the T-axis direction) showing another example of the size of the terminal electrodes in a multilayer ceramic capacitor according to the first embodiment of the present invention. [Figure 11] This is a schematic diagram illustrating the procedure for determining whether a terminal electrode has a recess in the lamination direction of the laminate at a position covering the end of a via conductor, and the procedure for determining the depth of said recess. [Modes for carrying out the invention]

[0014] The structure and effects of the present invention will be explained below, along with the technical concepts, with reference to the drawings. However, the mechanism of action is based on assumptions, and its accuracy does not limit the present invention.

[0015] [Multilayer ceramic capacitors] <First Embodiment> Figures 1 and 2 show an embodiment of a multilayer ceramic capacitor according to a first aspect of the present invention, as the first embodiment. The multilayer ceramic capacitor 100 according to the first embodiment has a rectangular parallelepiped shape and has one pair of faces that are perpendicular to three mutually orthogonal axes, namely the L-axis (length direction), the W-axis (width direction), and the T-axis (height direction). The rectangular parallelepiped is not limited to a mathematically defined rectangular parallelepiped, but any shape that is recognized as a rectangular parallelepiped when the overall shape is observed is acceptable. For this reason, shapes with slightly rounded edges or corners, slightly curved edges, and surfaces with small curvature also fall under the category of a rectangular parallelepiped in this disclosure. Naturally, shapes whose main surface has the raised structure described above also fall under the category of a rectangular parallelepiped in this disclosure. The dimensions of the ceramic capacitor 100 in the length (L) direction, width (W) direction, and height (T) direction can each take on any independent value.

[0016] Examples of dimensions for a multilayer ceramic capacitor 100 include a length of 200 μm or more and 2000 μm or less in the L direction, a length of 100 μm or more and 2000 μm or less in the W direction, and a length of 30 μm or more and 220 μm or less in the T direction, with a W / L ratio of 0.3 or more and 1.0 or less. Preferably, the dimensions are such that the length of the L direction is 400 μm or more and 1200 μm or less, the length of the W direction is 400 μm or more and 1200 μm or less, and the length of the T direction is 40 μm or more and 150 μm or less, with a W / L ratio of 0.4 or more and 1.0 or less. A T-direction dimension of 100 μm or less is more preferable because it allows for a narrower gap between the circuit board and the motherboard on which it is mounted, even when mounted on the back side of the circuit board (the side opposite to the side on which the semiconductor is mounted).

[0017] The multilayer ceramic capacitor 100 according to the first embodiment comprises a base body 10 having a laminate 20 in which ceramic layers 21 and internal electrodes 22 mainly composed of metal are alternately stacked in the T direction, and a protective part 30 covering the surface of the laminate 20, as schematically shown in the cross-sectional view in Figure 2. The internal electrodes 22 include internal electrodes 22a of one polarity that are electrically connected to each other, and internal electrodes 22b of a different polarity that are electrically connected to each other. Here, the cross-section shown in Figure 2 (cross-section AA in Figure 1) is a plane parallel to the T direction that passes through the line segment connecting the ends drawn out to the main surface 11 of the via conductors 23a and 23b, which will be described later.

[0018] A protective portion 30 is positioned on the surface of the base body 10, covering the surface of the laminated body 20. The protective portion 30 includes a cover portion 31 positioned on a plane perpendicular to the T direction, and margin portions 32 positioned on a plane perpendicular to the W direction and a plane perpendicular to the L direction, respectively.

[0019] The base body 10 is arranged to penetrate the ceramic layer 21 in the stacking direction of the laminate 20, with at least one end extended to the surface of the protective portion 30 (cover portion 31), and has a plurality of via conductors 23 electrically connected to the internal electrode 22. The via conductors 23 include via conductors 23a electrically connected to the internal electrode 22a and via conductors 23b electrically connected to the internal electrode 22b. Although the multilayer ceramic capacitor 100 shown in Figures 1 and 2 has four via conductors 23, the number of via conductors in the multilayer ceramic capacitor according to the first aspect of the present invention is not limited to this.

[0020] The multilayer ceramic capacitor 100 according to the first embodiment includes a plurality of terminal electrodes 40 arranged on at least one of the surfaces forming the surface of the base body 10, on the surface from which the ends of the via conductors 23 (23a, 23b) are drawn. The terminal electrodes 40 include a terminal electrode 40a electrically connected to the via conductor 23a and a terminal electrode 40b electrically connected to the via conductor 23b. Hereinafter in this disclosure, a pair of surfaces of the base body 10, consisting of the surface from which the ends of the via conductors 23 (23a, 23b) are drawn and the surface opposite to that surface, will be referred to as the main surface 11. Of the main surface 11, the surface opposite to the surface from which the ends of the via conductors 23 (23a, 23b) are drawn may or may not have the ends of the via conductors 23 (23a, 23b) drawn. Although the multilayer ceramic capacitor 100 shown in Figures 1 and 2 has four terminal electrodes 40, the number of terminal electrodes in the multilayer ceramic capacitor according to the first aspect of the present invention is not limited to this. Furthermore, while the multilayer ceramic capacitor 100 has terminal electrodes 40 (40a, 40b) arranged on only one main surface 11, the multilayer ceramic capacitor according to the first side of the present invention may have terminal electrodes 40 (40a, 40b) arranged on both main surfaces 11, or the terminal electrodes 40 (40a, 40b) may extend to the end surface or side surface that intersects with both main surfaces 11.

[0021] In the multilayer ceramic capacitor 100 according to the first embodiment, at least one of the pair of main surfaces 11 of the base body 10, from which the ends of the via conductors 23 (23a, 23b) are drawn out and the terminal electrodes 40 (40a, 40b) are arranged, has a raised structure composed of a peripheral portion 111 and a raised portion 112 that is surrounded by the peripheral portion 111 and rises above the peripheral portion 111. At least a portion of each of the terminal electrodes 40 (40a, 40b) arranged on the main surface 11 having the raised structure is located on the slope of the raised portion 112. Because at least one of the main surfaces 11 has a raised structure, and at least a portion of the terminal electrodes 40 (40a, 40b) arranged on the main surface 11 is located on the slope of the raised portion 112, the occurrence of defects where the terminal electrodes are connected to each other by solder can be suppressed when mounting on a circuit board. This is presumed to be because the flow of molten solder from the raised portion 112 to the peripheral portion 111 is promoted, thereby suppressing the flow of molten solder to the other terminal electrodes. Furthermore, in the multilayer ceramic capacitor 100 according to the first embodiment, the molten solder generated during circuit board mounting can be held between the circuit board and the peripheral portion 111, thereby effectively suppressing contact between the wet and spreading solder and other adjacent electronic components or pads.

[0022] The thickness of the base body 10, obtained by subtracting the thickness of the terminal electrodes 40 (40a, 40b) from the T-direction dimension of the multilayer ceramic capacitor 100 described above, is, for example, 20 μm or more and 200 μm or less, and preferably 30 μm or more and 180 μm or less.

[0023] The following describes in detail the various components that make up the multilayer ceramic capacitor 100 according to the first embodiment.

[0024] (Ceramic layer) The ceramic layer 21 is formed of ceramic. The composition of the ceramic is not particularly limited as long as it forms a dense ceramic layer 21 by co-firing with the internal electrodes 22, which will be described later, and can be appropriately selected according to the characteristics required for the multilayer ceramic capacitor. Examples of ceramic compositions include those mainly composed of barium titanate (BaTiO3), those mainly composed of strontium titanate (SrTiO3), and those having a perovskite-type structure. 1-x-y Ca x Sr y Ti 1-z Zr z Examples include ceramics with O3 as the main component. The ceramic may also contain additive elements along with the main component. Examples of additive elements include Mo, Nb, Ta, W, Mg, Mn, V, Cr, and rare earth elements (Y, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, and Yb), as well as at least one selected from Co, Ni, Li, B, Na, K, and Si. The additive elements may be included as individual elements or in the form of compounds such as oxides, nitrides, and carbides. Furthermore, the additive elements may exist in a solid solution state in the main component, and may form a different phase with the elements constituting the main component or other additive elements.

[0025] (Internal electrode) The internal electrodes 22 (22a, 22b) are mainly composed of metal. The type of metal is not particularly limited, and nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), and gold (Au), as well as alloys thereof, can be used. Of these, nickel (Ni) is preferred as the main component element because its high heat resistance allows for a higher firing temperature when firing it together with the ceramic layer 21, enabling the formation of a dense ceramic layer 21, and it is also relatively inexpensive. Here, "main component element" in this specification means the element that has the highest content expressed as atomic percentage (atomic %).

[0026] The internal electrodes 22 (22a, 22b) may contain, in addition to metal, ceramic particles having a similar composition to the ceramics that make up the ceramic layer 21, or glass components.

[0027] (Protection Department) The protective part 30 has the function of protecting the ceramic layer 21 and the internal electrodes 22. The material of the protective part 30 is not limited as long as it has high electrical insulation properties and low permeability to degradation factors such as moisture. In terms of ensuring uniform shrinkage during firing when manufacturing the multilayer ceramic capacitor 100 and relieving internal stress within the multilayer ceramic capacitor 100, it is preferable that the main component of the protective part 30 be the same as the ceramic forming the ceramic layer 21.

[0028] (via conductor) The via conductors 23 (23a, 23b), like the internal electrodes 22 (22a, 22b), are mainly composed of metal. Suitable metals include those used for the internal electrodes 22 (22a, 22b) as described above. The metal composition of the via conductors may differ from that of the internal electrodes 22 (22a, 22b), but it is preferable to use the same metal composition. By using the same metal composition for the via conductors 23 (23a, 23b) and the internal electrodes 22 (22a, 22b), the magnitude of shrinkage caused by firing during the manufacturing of the multilayer ceramic capacitor 100 is uniform, suppressing deformation. Furthermore, the resistivity of the conductive paths of the multilayer ceramic capacitor 100 becomes uniform, suppressing localized heat generation during use.

[0029] The diameter of the via conductors (23a, 23b) is not particularly limited, but from the standpoint of reducing electrical resistance and suppressing heat generation during circuit operation while ensuring the capacitance of the multilayer ceramic capacitor 100, it is preferable to have a diameter of 5 μm to 100 μm, and more preferably 10 μm to 50 μm.

[0030] (Main surface of the base body) Of the pair of main surfaces 11 of the base body 10, at least one of the surfaces from which the ends of the via conductors 23 (23a, 23b) are drawn out and on which the terminal electrodes 40 (40a, 40b) are arranged has, as described above, a raised structure composed of a peripheral portion 111 and a raised portion 112 that is surrounded by the peripheral portion 111 and rises with respect to the peripheral portion 111. And all of the terminal electrodes 40 (40a, 40b) arranged on the main surface 11 having the raised structure have at least a part thereof located on the slope of the raised portion 112.

[0031] Here, the determination as to whether or not the main surface 11 of the base body 10 has a raised structure and the determination as to whether or not at least a part of the terminal electrodes 40 (40a, 40b) arranged on the main surface 11 is located on the slope of the raised portion 112 are each performed by the following procedure. First, the multilayer ceramic capacitor 100 is cut or polished along a plane parallel to the lamination direction of the laminate 20 to form an observation surface on which a plurality of terminal electrodes 40 (40a, 40b) and internal electrodes 22 (22a, 22b) are observed. The observation surface may be formed by performing rough polishing, mirror polishing, and milling on the resin-embedded multilayer ceramic capacitor 100 in this order. The observation surface may be formed by resin-embedding the multilayer ceramic capacitor 100 after cutting so that the cut surface is exposed, and then performing mirror polishing and milling on the cut surface in this order. The observation surface may be formed by performing focused ion beam (FIB) processing on the multilayer ceramic capacitor 100. Next, the observation surface is observed with an optical microscope or a scanning electron microscope (SEM), and an image is obtained in which at least a part of the entire main surface 11 to be determined, the terminal electrodes 40 (40a, 40b) arranged on the main surface 11, and the internal electrodes 22 (22a, 22b) enter the same visual field as shown in FIG. 3. Next, in the obtained image, points p1 and p2 that are the two ends of the main surface 11 to be determined, and a straight line m passing through each of these points b are drawn. Next, in the image, at each end of the boundary line between each of the terminal electrodes 40a and 40b arranged on the main surface 11 and the protection portion 30 (cover portion 31), a point t b1 , a point t t1 , a point t b2 and a point t t2 are each drawn, and the point t b1 and the point tt1 A straight line m passing through the two points. s1 , and point t b2 and point t t2 A straight line m passing through the two points. s2 Construct each of these. Here, point t b1 The point drawn on the peripheral end of the boundary line between one terminal electrode 40a and the cover portion 31 is point t t1 The terms t represent points drawn at the central end of the boundary line between the terminal electrode 40a and the cover portion 31, respectively. b2 The point drawn on the peripheral end of the boundary line between the other terminal electrode 40b and the cover portion 31 is point t t2 These represent points drawn at the central end of the boundary line between the terminal electrode 40b and the cover portion 31. Note that Figure 3 shows a configuration in which one end of the terminal electrode 40 (40a, 40b) extends to the end of the main surface 11, i.e., point t b1 t coincides with point p1, b2 This shows the case where point t coincides with point p2, but point t b1 and point p1, and t b2 It goes without saying that point p2 and point m may be in different positions. Also, although Figure 3 shows the case where the polarity of the terminal electrodes 40 placed on the main surface 11 to be judged is different, the polarity of the terminal electrodes 40 may be the same. And the line m s1 and a straight line and a straight line m s2 In all cases, when viewed from the periphery towards the center, the line m b The presence of elevation angles θ1 and θ2 relative to the main surface 11 determines that the main surface 11 being judged has a raised structure, and that at least a portion of the terminal electrodes 40 (40a, 40b) arranged on the main surface 11 is located on the slope of the raised portion 112.

[0032] The aforementioned elevation angles θ1 and θ2 are preferably set to 3° to 45°, and more preferably to 5° to 20°, respectively, in order to significantly suppress soldering between terminal electrodes when mounting on a circuit board.

[0033] Preferably, the ends of the via conductors 23 (23a, 23b) that are drawn out onto the main surface 11 on which the raised portion 112 is formed are located on the slope of the raised portion 112. By having the ends of the via conductors 23 (23a, 23b) located on the slope, when the multilayer ceramic capacitor 100 is mounted on the circuit board, the ends of the via conductors 23 (23a, 23b) are positioned directly above the pads of the circuit board, thus shortening the current path and reducing ESL.

[0034] Here, the determination of whether the ends of the via conductors 23 (23a, 23b) drawn out to the main surface 11 of the base body 10 are located on the slope of the raised portion 112 is performed by the following procedure. First, the multilayer ceramic capacitor 100 is cut or ground along a plane parallel to the stacking direction of the laminate 20 to form an observation surface on which the multiple terminal electrodes 40 (40a, 40b) and the via conductors 23 (23a, 23b) connected thereto, as well as the internal electrodes 22 (22a, 22b), can be observed. The observation surface may also be formed by rough polishing, mirror polishing, and milling in that order on the resin-embedded multilayer ceramic capacitor 100. Alternatively, the observation surface may be formed by cutting the multilayer ceramic capacitor 100, then embedding it in resin so that the cut surface is exposed, and then mirror polishing and milling in that order on the cut surface. Alternatively, the observation surface may be formed by performing focused ion beam (FIB) processing on the multilayer ceramic capacitor 100. Next, the observation surface is observed with an optical microscope or a scanning electron microscope (SEM) to obtain an image in which the entire main surface 11 on which the raised portion is formed, the terminal electrodes 40 (40a, 40b) placed on the main surface 11, the via conductors 23 (23a, 23b) connected to the terminal electrodes 40 (40a, 40b), and at least a portion of the internal electrodes 22 (22a, 22b) connected to the via conductors 23 (23a, 23b) are all within the same field of view. Next, using the same procedure as described above for determining whether the main surface 11 has a raised structure and whether at least a portion of the terminal electrodes 40 (40a, 40b) placed on the main surface 11 are located on the slope of the raised portion 112, points p1, p2, and t are added to the acquired image. b1 , point t t1 , point t b2 and point t t2 , and also the straight line m b , straight line m s1 , and straight line ms2 Each of these is then drawn. Next, in the image, as shown in Figure 4a, point v is placed on the peripheral side of the boundary between the via conductor 23a to be judged and the main surface 11 from which the via conductor 23a is drawn. b1 Draw a diagram, and place a point v on the central side of the aforementioned boundary. t1 The diagram is drawn. Note that in Figure 4a, in order to improve the visibility of the drawn points and lines, only the outline of the terminal electrode 40a is shown with a dotted line. Next, in the image, the aforementioned point v b1 and point v t1 A straight line m passing through the two points. e1 Construct the line m. e1 is a straight line m b θ is the angle it makes with respect to e1 However, in a straight line m s1 is a straight line m b The angle with respect to becomes greater than or equal to θ1, that is, θ e1 Since ≥θ1, it is determined that the end of the via conductor 23a being evaluated is located on the slope of the raised portion.

[0035] Furthermore, point v mentioned above b1 and point v t1 When drawing the diagram, if the end of the via conductor 23a to be judged has a portion that does not reach the main surface 11, as shown in Figure 4b, the line segment obtained by linearly approximating the boundary line between the via conductor 23a and the protective part 30 (cover part 31) is extended to the main surface 11 to form a straight line m v Draw the line m v The intersection point of the main surface 11 (point v in the figure) t1 The boundary between the via conductor 23a located on the main surface 11 and the main surface 11 is defined as the boundary between the via conductor 23a located on the main surface 11 and the main surface 11.

[0036] The height of the raised structure is not particularly limited, but it is preferable that the maximum height of the raised portion 112 relative to the peripheral portion 111 be 5 μm or more, in that soldering between terminal electrodes is significantly suppressed when mounting on a circuit board. From this point of view, it is more preferable that the maximum height be 10 μm or more, and even more preferable that it be 15 μm or more. On the other hand, it is preferable that the maximum height be 40 μm or less in order to suppress the height dimension of the multilayer ceramic capacitor 100. From this point of view, it is more preferable that the maximum height be 35 μm or less, and even more preferable that it be 30 μm or less. From the above, it is preferable that the maximum height be 5 μm or more and 40 μm or less, more preferable that it be 10 μm or more and 35 μm or less, and even more preferable that it be 15 μm or more and 30 μm or less.

[0037] The boundary position between the peripheral portion 111 and the raised portion 112 on the main surface 11 having a raised structure is not particularly limited, but it is preferable that the boundary exists in a region where the distance from the outer edge of the main surface 11 is 0.0005 mm or more and 0.0030 mm or less. When the distance of the boundary from the outer edge is 0.0005 mm or more, the effect of holding the molten solder between the peripheral portion 111 and the circuit board is enhanced when mounting the multilayer ceramic capacitor 100 to the circuit board, and contact with other adjacent electronic components or pads can be effectively suppressed. On the other hand, when the distance of the boundary from the outer edge is 0.0030 mm or less, the area of ​​the raised portion 112, which is the part that is placed on the circuit board when mounting the multilayer ceramic capacitor 100 to the circuit board, becomes larger, and the posture of the multilayer ceramic capacitor 100 is stabilized, improving workability and mounting yield.

[0038] In the main surface 11 having a raised structure, the inclination of the peripheral portion 111 is preferably such that it is not downward toward the raised portion 112, and more preferably upward toward the raised portion 112. This makes it easier for the molten solder to flow toward the peripheral portion 111 when the multilayer ceramic capacitor 100 is mounted on the circuit board.

[0039] Here, the determination of the maximum height of the raised portion 112 relative to the peripheral portion 111 in the raised structure is performed by the following procedure. First, similar to the procedure described above for determining whether the main surface 11 of the base body 10 has a raised structure and whether at least a portion of the terminal electrodes 40 (40a, 40b) placed on the main surface 11 are located on the slope of the raised portion 112, a microscopic image of the observation surface is obtained, and points p1, p2 and line m are drawn in the image. b Next, in the image above, as shown in Figure 5, the line m b Among the lines that are parallel to and intersect the main surface 11 that is the subject of evaluation, line m b The straight line m that is the maximum distance from u Construct the line m. b and m u The distance to the periphery 111 is measured, and the value obtained by dividing the obtained distance by the observation magnification of the image is the maximum height h of the raised portion 112 relative to the peripheral portion 111. max Let's assume that.

[0040] Furthermore, the determination of the distance from the outer edge of the main surface 11 to the boundary between the peripheral portion 111 and the raised portion 112 in the raised structure, and the determination of the inclination angle of the peripheral portion 111 on the main surface 11 having the raised structure, are performed in the following procedure, following the procedure for determining the maximum height described above. First, as shown in the image above in an enlarged view in Figure 6, a straight line m b from h max A point c1 is drawn on the main surface 11 at a distance equivalent to / 10. Next, the shape of the main surface 11 observed between point p1 and point c1 is linearly approximated to determine a line segment, and a straight line m is drawn by extending both ends of the line segment. p1 The above is drawn in the image. Next, the distance between point p1 and point c1 is measured. The above operations are also performed on the other end side of the main surface 11 (point p2 side), and the distance between point c2 and line m p2 A diagram (not shown) is drawn, and the distance between point p2 and point c2 is measured. Then, the average of the distance between p1-c1 and the distance between p2-c2 is calculated, and the value obtained by dividing the result by the observation magnification of the image is taken as the distance from the outer edge of the main surface 11 to the boundary between the peripheral portion 111 and the raised portion 112. Also, the straight line m b and a straight line m p1 The angle φ1 formed by the and the straight line m b and a straight line mp2 The angles φ2 (not shown) formed by and are measured, and the average value is taken as the inclination angle of the peripheral portion 111 on the main surface 11 having a raised structure.

[0041] The pair of main surfaces 11 on the base body 10 may both have a raised structure, but as shown in Figure 7, it is preferable that only one has the raised structure and the other is flat, as this facilitates handling when mounting on a circuit board. This is because, when mounting the multilayer ceramic capacitor 100 on a circuit board, the main surface 11 opposite to the surface facing the circuit board is usually handled by adsorption using the suction pad of the mounter, and it is presumed that if the adsorbed main surface 11 is flat, variations in the adsorption force will be less likely to occur.

[0042] As shown in Figures 8a and 8b, the raised portion 112 has two peaks in a cross-section parallel to the stacking direction of the laminate 20, passing through the diagonal of the main surface 11 on which it is formed, and the distance d between each peak p However, the length of the diagonal d d For comparison, 0.2d d ≤d p ≤0.8d d It is preferable that the above conditions are met. Having such a shape for the raised portion 112 results in multiple contact points when the main surface 11 is placed on a flat surface, thus stabilizing the orientation of the multilayer ceramic capacitor 100 and facilitating handling during circuit board mounting. Furthermore, when using adhesive to increase bonding strength during circuit board mounting of the multilayer ceramic capacitor 100, the adhesive fills the recesses formed between the peaks, increasing the amount of adhesive and the bonding area, thus improving bonding strength.

[0043] The protrusion height of each peak is more preferably 0.1 μm or more and 25 μm or less from the lowest point between each peak. When the protrusion height is 0.1 μm or more from the lowest point, the ease of handling and adhesive strength mentioned above are significantly improved. From this point of view, the protrusion height is even more preferably 1 μm or more from the lowest point, and particularly preferably 3 μm or more from the lowest point. On the other hand, when the protrusion height is 25 μm or less from the lowest point, when adhesive is used during circuit board mounting, the ability of the adhesive to fill the region between the peaks can be ensured. From this point of view, the protrusion height is even more preferably 20 μm or less from the lowest point, and particularly preferably 10 μm or less from the lowest point. From the above, the protrusion height is even more preferably 1 μm or more and 20 μm or less from the lowest point, and particularly preferably 3 μm or more and 10 μm or less from the lowest point.

[0044] Here, it is determined whether the raised portion 112 of the main surface 11 has two peaks in a cross section parallel to the stacking direction of the laminate 20 passing through the diagonal of the main surface 11, and the distance d between each peak. p The determination of the height of each peak and the height of the protrusion of each peak from the lowest point between each peak is performed by the following procedure. First, the terminal electrodes 40 (40a, 40b) formed on the main surface 11 of the multilayer ceramic capacitor 100 are removed to expose the ends of the via conductors 23 (23a, 23b) on the main surface 11. Methods for removing the terminal electrodes 40 include polishing with a precision hand grinder or acid dissolution. Next, the height distribution along the diagonal of the main surface 11 where the ends of the via conductors 23 (23a, 23b) are exposed is measured using a laser microscope. Next, in the obtained measurement results, as shown in Figure 9, a height distribution with a shape similar to the graph of a quartic function having a local minimum between two local maximums is confirmed near the center of the diagonal, and it is determined that the raised portion 112 of the measured main surface 11 has two peaks in a cross section parallel to the stacking direction of the laminate 20 passing through the diagonal of the main surface 11. Next, based on the obtained measurement results, the diagonal distance between the maximum values ​​is determined, and this distance is d pFurthermore, based on the obtained measurement results, the difference between each of the maximum and minimum values ​​is determined, and the obtained value is defined as the projection height of each peak from the lowest point between each peak.

[0045] The length d of the diagonal of the main surface 11 described above is also included. d This is determined by observing the main surface 11 under a microscope, measuring the distance between the vertices that form the ends of the diagonals in the obtained image, and dividing it by the magnification of the microscope.

[0046] (terminal electrode) The material of the terminal electrodes 40 (40a, 40b) is not limited as long as it is conductive. Examples of materials include metals such as nickel (Ni), copper (Cu), tin (Sn), palladium (Pd), platinum (Pt), silver (Ag), and gold (Au), alloys in which any of these are the main component elements, and conductive resins.

[0047] The terminal electrodes 40 (40a, 40b) may have a base conductor 41 that contacts the base body 10 and a plated conductor 42 formed on the surface of the base conductor 41. Terminal electrodes 40 (40a, 40b) with such a structure can improve adhesion to the base body 10 with the base conductor 41, while improving solder wettability when mounted on a circuit board with the plated conductor 42.

[0048] Ni is an example of a material for the base conductor 41. The thickness of the base conductor 41 can be 0.1 μm or more and 10 μm or less, and preferably 0.5 μm or more and 5 μm or less.

[0049] The plated conductor 42 may be formed as a single layer or as multiple layers. When the plated conductor 42 is made up of multiple layers, the number of layers is preferably two to four. Examples of the material and structure of the plated conductor 42 include those made of Cu, Ni, and Sn in that order. The thickness of the plated conductor 42 can be 1 μm to 20 μm, and preferably 3 μm to 10 μm.

[0050] The shape of the terminal electrodes 40 (40a, 40b), as viewed from a direction perpendicular to the main surface 11, is not particularly limited as long as it covers the ends of the via conductors 23 (23a, 23b) drawn out onto the main surface 11, and may be circular, elliptical, or polygonal. The polygon is not limited to mathematically defined polygons, but may be any shape that is recognized as a polygon when the overall shape is observed. For this reason, shapes with slightly rounded vertices and slightly curved edges also fall under the category of polygons in this disclosure. Furthermore, the size of the terminal electrodes 40 (40a, 40b) as viewed from a direction perpendicular to the main surface 11 is not particularly limited as long as it covers the ends of the via conductors 23 (23a, 23b) drawn out onto the main surface 11. It may be slightly larger than the ends of the via conductors 23 (23a, 23b) drawn out onto the main surface 11, as shown in Figure 10a, or it may cover most of the main surface, as shown in Figure 10b.

[0051] The area of ​​the terminal electrodes 40 (40a, 40b), that is, the area of ​​the terminal electrodes 40 (40a, 40b) observed when the multilayer ceramic capacitor 100 is viewed from a direction perpendicular to the main surface 11, is not particularly limited. It should be large enough to facilitate mounting on a circuit board, and small enough so that electrodes with different polarities do not short-circuit. Preferably, the ratio of the total area of ​​the terminal electrodes 40 to the area of ​​the mounting surface 11 is 0.2 or more and 0.9 or less, and more preferably, the ratio is 0.3 or more and 0.8 or less.

[0052] Preferably, the terminal electrodes 40 (40a, 40b) have recesses that are recessed in the stacking direction of the laminate 20, at positions that cover the ends of the via conductors 23 (23a, 23b). Having these recesses on the surface of the terminal electrodes 40 (40a, 40b) allows solder balls to fit into the recesses and fix their position when mounting the multilayer ceramic capacitor 100 onto a circuit board, thereby facilitating the mounting process.

[0053] The depth of the recess is not particularly limited, but it is more preferably 0.1 μm or more, even more preferably 1 μm or more, and particularly preferably 2 μm or more, in that the positioning effect of the solder ball is significant. On the other hand, in that the thickness of the terminal electrode is reduced and the height dimension of the multilayer ceramic capacitor 100 is reduced, it is more preferably 30 μm or less, even more preferably 10 μm or less, and particularly preferably 6 μm or less. From the above, the depth of the recess is more preferably 0.1 μm or more and 30 μm or less, even more preferably 1 μm or more and 10 μm or less, and particularly preferably 2 μm or more and 6 μm or less.

[0054] Here, the determination of whether the terminal electrodes 40 (40a, 40b) have a recess in the stacking direction of the laminate 20 at a position where they cover the ends of the via conductors 23 (23a, 23b), and the determination of the depth of the recess, are carried out by the following procedure. First, the multilayer ceramic capacitor 100 is ground along a plane parallel to the stacking direction of the laminate 20 up to the vicinity of the center of gravity of the via conductors 23 (23a, 23b) drawn out to the main surface 11, exposing the cross-sections of the via conductors 23 (23a, 23b) and the cross-sections of the terminal electrodes 40 (40a, 40b) electrically connected to the via conductors 23 (23a, 23b). The grinding may be performed mechanically on the multilayer ceramic capacitor 100 embedded in the resin, or by focused ion beam (FIB) processing. Next, the ground surface where the via conductors 23 (23a, 23b) are exposed is observed with an optical microscope or a scanning electron microscope (SEM) to obtain an image in which the surface of the terminal electrode 40 (40a, 40b) to be judged, the boundary between the via conductors 23 (23a, 23b) connected to the terminal electrode 40 (40a, 40b) and the protective part 30 (cover part 31 and margin part 32), and the boundary between the via conductors 23 (23a, 23b) and the ceramic layer 21 are all within the same field of view, as shown in Figure 11. Next, in the acquired image, two line segments are drawn that define the boundary between the via conductors 23 (23a, 23b) and the cover part 31, and the boundary between the via conductors 23 (23a, 23b) and the ceramic layer 21 or margin part 32, and both ends of these segments are extended to form straight lines m vo and straight line m vi Let's assume that the line mvo extends the two ends of a line segment that defines the boundary between via conductors 23 (23a, 23b) and the cover portion 31 located outside thereof (opposite to the laminate 20), and the boundary between via conductors 23 (23a, 23b) and the margin portion 32 or the ceramic layer 21 located outside thereof, which is a straight line m vi extends the two ends of a line segment that defines the boundary between via conductors 23 (23a, 23b) and the cover portion 31 located inside thereof (on the side of the laminate 20), and the boundary between via conductors 23 (23a, 23b) and the ceramic layer 21 located inside thereof. When drawing each of the above straight lines, if each of the boundaries forms a curve or a broken line, the curve or the broken line is linearly approximated, the line segment that defines each boundary is drawn, and then the two ends of the line segment are extended. Next, in the image, the straight line m vo and the straight line m vi the points where they intersect the surface of the terminal electrodes 40 (40a, 40b) are respectively taken as t o and t i and are drawn, and a straight line m o passing through point t i and point t t is drawn. Then, if the surface of the terminal electrodes 40 (40a, 40b) located between the straight line m vo and the straight line m vi exists continuously on the side of the laminate 20 from the straight line m o t i over 20% of the length of the line segment t t , it is determined that the terminal electrodes 40 (40a, 40b) to be judged have a depression that is recessed in the stacking direction of the laminate 20 at a position covering the ends of the via conductors 23 (23a, 23b). Also, among the distances between each point on the surface of the terminal electrodes 40 (40a, 40b) located between the straight line m vo and the straight line m vi and the straight line m t (line segment t o t i ), the maximum value divided by the observation magnification of the image is taken as the depth of the depression.

[0055] As described above, in the multilayer ceramic capacitor according to the first aspect of the present invention, the number of terminal electrodes is not limited, but it is preferable to have four or more terminal electrodes in order to suppress the amount of heat generated during high-frequency driving. This is because having four or more terminal electrodes increases the number of current paths that flow during driving, suppressing the amount of current flowing through each path and thus suppressing resistive heating.

[0056] In multilayer ceramic capacitors with four or more terminal electrodes, it is preferable that each terminal electrode has a different polarity from the nearest terminal electrode in the main surface, as this reduces the ESL during operation. This is because the direction of the current flowing through the via conductors electrically connected to each terminal electrode is opposite for the nearest via conductors, causing the magnetic fields generated by the currents to cancel each other out. The aforementioned ESL reduction effect is particularly noticeable when the multilayer ceramic capacitor has two sets of faces parallel to the stacking direction of the laminate, where the distance between one set of faces, i.e., the dimension in the L direction, is Lμm, and the distance between the other set of faces, i.e., the dimension in the W direction, is Wμm (where L≧W), and the value of W / L, which is the ratio of W to L, is between 0.8 and 1, i.e., the main surface 11 has a shape close to a square.

[0057] [Manufacturing method for multilayer ceramic electronic components] A multilayer ceramic capacitor according to the first aspect of the present invention can be manufactured by the procedure described below.

[0058] ((A) Preparation of ceramic powder) First, prepare the ceramic powder. Commercially available ceramic powder can be used as appropriate. If you are making your own ceramic powder, mix the various raw material powders containing the constituent elements in a predetermined ratio and pre-fire them (calcination). When mixing the various raw material powders in a predetermined ratio, you may further add the aforementioned additive elements and sintering aids, or you may further add these additives to the powder after calcination.

[0059] ((B) Preparation of raw sheets) Next, the aforementioned ceramic powder is mixed with a binder and a dispersion medium to prepare a slurry, and the slurry is formed into a sheet to obtain a raw sheet.

[0060] The binder used should be one that can maintain the shape of the raw sheet and volatilize without leaving any carbon residue after the binder removal process prior to firing. Examples of usable binders include polyvinyl alcohol-based, polyvinyl butyral-based, cellulose-based, urethane-based, and vinyl acetate-based binders. The amount of binder used is not particularly limited, but since it will be removed in a later process, it is preferable to use as little as possible within the range where the desired moldability and shape retention can be achieved, in order to reduce raw material costs.

[0061] As the dispersion medium, one should be used that does not cause aggregation of the ceramic powder and binder, and can be easily removed by volatilization or other means after the raw sheet molding process described later. Examples of usable dispersion media include water and alcohol-based solvents.

[0062] Components that adjust the properties of the slurry, such as dispersants, plasticizers, and thickeners, may be added to the slurry.

[0063] The method for mixing the above-mentioned mixed powder with a binder and dispersion medium is not particularly limited, as long as it ensures that each component is uniformly mixed while preventing the introduction of impurities. One example is ball mill mixing.

[0064] Conventional methods such as the doctor blade method and the die-coating method can be used to form the prepared slurry into a sheet and obtain a raw sheet.

[0065] ((C) Formation of via holes) Next, via holes are formed at predetermined positions on the obtained raw sheet. Via holes are holes that penetrate the raw sheet in the thickness direction, and are filled with via conductor forming paste, becoming part of the via conductor after lamination and firing. Examples of methods for forming via holes include punching, drilling, and laser processing.

[0066] ((D) Formation of internal electrode pattern and via conductor pattern) Next, an internal electrode pattern containing metal is formed on the raw sheet, and via conductor formation paste is filled into via holes formed in the raw sheet to form via conductor patterns. The internal electrode pattern and via conductor pattern may be formed individually or simultaneously. The internal electrode pattern can be formed by printing or coating the internal electrode paste in a predetermined pattern, or by forming a metallic film in a predetermined pattern by vapor deposition or sputtering. The via conductor pattern can be formed by filling the via holes with via conductor formation paste by printing or injection. When forming the internal electrode pattern or via conductor pattern by printing, a printing method using a screen mask or a metal mask can be employed. The internal electrode pattern and via conductor pattern formed on the same raw sheet are formed with sufficient spacing to ensure electrical insulation.

[0067] When a paste is used to form an internal electrode pattern or via conductor pattern, the paste is obtained by mixing metal particles and a vehicle in a three-roll mill. In addition to the components mentioned above, the paste may also contain glass frit or ceramic powder.

[0068] The type and amount of binder and solvent contained in the vehicle used are not limited and should be selected appropriately considering the viscosity of the internal electrode paste, ease of handling, and compatibility with the raw sheet.

[0069] ((E) Preparation of biolaids) Next, a predetermined number of raw sheets on which internal electrode patterns and via conductor patterns are formed are stacked, and the raw sheets are pressed together to obtain a raw laminate. The stacking and pressing can be carried out by conventional methods, such as pressing the stacked raw sheets in the stacking direction while heating them, and using a binder to heat-press them together. During pressing, by placing an elastic sheet on at least one side of the raw sheets in the stacking direction, a raised structure can be formed on the main surface in contact with the elastic sheet. This is because the action of the elastic sheet increases the homogeneity of the stress distribution in the plane perpendicular to the pressing direction, so that the overall thickness of the raw laminate reflects the difference in height (thickness) between the presence and absence of internal electrode patterns in each raw sheet, and the thickness in the stacking direction where the internal electrode pattern is formed becomes thicker than where the pattern is not formed. In addition, if the internal electrode pattern is formed by printing, the outer edge of the internal electrode pattern, which is pulled upward when the mask used for printing separates from the raw sheet, will be raised compared to its center, resulting in a raised portion having two peaks. Since the raised structure is formed on the main surface that the elastic sheet was in contact with during the fabrication of the raw laminate, if the raised structure is to be formed on only one main surface, the elastic sheet only needs to be placed on one side in the lamination direction of the raw sheet. If the raised structure is to be formed on both main surfaces, the elastic sheet should be placed on both sides in the lamination direction of the raw sheet.

[0070] During lamination and crimping, a raw sheet that will form the cover portion when a multilayer ceramic capacitor is formed may be added to the end of the raw sheet in the lamination direction. In this case, the added raw sheet may have the same composition as the raw sheet on which the internal electrode pattern is printed, or a different composition. From the viewpoint of matching the shrinkage rate during firing, it is preferable that the composition of the added raw sheet is the same as or similar to the raw sheet on which the internal electrode precursor is arranged. For the added raw sheet that is placed on the main surface side from which the via conductors are drawn, via holes are formed in the procedure of (C) described above, and then via conductor patterns are formed in the procedure of (D) described above. At that time, terminal electrode patterns may be formed on the raw sheet placed in the outermost layer. In this case, the procedure of (H) described later can be omitted. Furthermore, when adding a raw sheet for forming the cover portion, by making one or more raw sheets placed in the outermost layer have only via holes and no via conductor patterns, the ends of the via conductors drawn to the main surface can be recessed relative to the main surface, and the surface of the terminal electrode covering the ends can be made recessed.

[0071] When a raised structure is formed on the main surface of a raw laminate by pressing through an elastic sheet, the compressive stress applied to the periphery increases, resulting in a higher density at the periphery. Therefore, multilayer ceramic capacitors with a raised structure on the main surface, obtained by firing the raw laminate, have a dense periphery, which has the advantage of effectively suppressing the intrusion of degradation factors such as moisture.

[0072] ((G) singulation) Next, the raw laminate is divided into individual pieces to form the shape of each multilayer ceramic capacitor. Conventional methods such as dicing saws and laser cutting machines can be used for this division.

[0073] (Formation of (H) terminal electrode pattern) Next, terminal electrode patterns are formed on the surface of the separated raw laminate where the via conductor patterns are exposed, creating pre-firing chips. The terminal electrode patterns can be formed by printing or coating a terminal electrode paste, or by forming a metallic film by vapor deposition or sputtering. When using a terminal electrode paste to form the terminal electrode patterns, the same components as those used for the internal electrode paste described above can be used, and the proportions of each component should be determined so that a uniform pattern of a predetermined thickness is obtained.

[0074] ((I) Removal of the binder) Next, the resulting unfired chips are heated to remove the binder by volatilization. The heating conditions should be set appropriately considering the binder's volatilization temperature and content. One example is to hold the chips in a nitrogen (N2) atmosphere at a temperature of 200°C to 500°C for 5 to 20 hours.

[0075] ((J) Firing of chips before firing) Next, the unfired chips, from which the binder has been removed, are heated to a predetermined temperature for firing. When setting the firing conditions, it is preferable to consider the sinterability of the ceramic powder, as well as the heat resistance and oxidation resistance of the metals contained in the internal electrode pattern, via conductor pattern, and terminal electrode pattern, respectively. An example of firing conditions is to hold the chips at a temperature of 1100°C to 1400°C for 10 minutes to 2 hours in a reducing atmosphere of nitrogen (N2), hydrogen (H2), and water vapor (H2O). After firing, a re-oxidation treatment may be performed by holding the chips at 600°C to 1000°C in a nitrogen (N2) gas atmosphere or a low-oxygen atmosphere.

[0076] The sintered body obtained in this way may be used as is as a multilayer ceramic capacitor, or a conductive layer may be formed on the surface of the terminal electrode pattern by plating before it is used as a multilayer ceramic capacitor.

[0077] A multilayer ceramic capacitor according to the first aspect of the present invention can also be manufactured by omitting (C) via hole formation in the above procedure, and performing (F) below after (E) fabrication of the raw laminate. In this case, (D) formation of the internal electrode pattern and via conductor pattern becomes (D') formation of the internal electrode pattern. In addition, in the above procedure, (G) framing and (H) formation of the terminal electrode pattern may be swapped.

[0078] (Formation of via conductor pattern (F)) (E) Holes are formed in the raw laminate obtained by the fabrication of the raw laminate, and conductive paste is filled into the holes to form a via conductor pattern. Conventional methods such as drilling or lasers can be used to form the holes. Among these, the use of a laser is preferred because it can form a smooth processed surface. Conventional methods such as injection using a syringe or printing using a metal mask or form mask can be used to fill the holes with conductive paste. Among these, printing using a metal mask is preferred because it is excellent in filling small diameter holes. The components of the conductive paste can be the same as those of the internal electrode paste described above, and the amount of each component should be determined considering the ability to fill the holes.

[0079] [Circuit board] The circuit board according to the second aspect of the present invention is equipped with a multilayer ceramic capacitor according to the first aspect. Because this circuit board is equipped with a multilayer ceramic capacitor that can suppress solder wetting and spreading during mounting, other adjacent electronic components and pads can be placed in close proximity, enabling miniaturization and high integration. [Examples]

[0080] The present invention will be described in more detail below with reference to examples, but the present invention is not limited to these examples.

[0081] [Example 1] (Preparation of raw sheets) As the ceramic powder, calcined barium titanate (BaTiO3) powder was prepared. A polyvinyl butyral-based binder and an alcohol-based solvent were added to this powder and mixed using a wet ball mill. The resulting mixture slurry was formed using a doctor blade to obtain a raw sheet with a thickness of 1 μm.

[0082] (Fabrication of multilayer ceramic capacitors) After forming via holes in the obtained green sheet using a laser processing machine, an internal electrode paste containing nickel powder as a metal powder was screen-printed onto the green sheet to form an internal electrode pattern. Next, by printing using a metal mask, a via conductor forming paste containing nickel powder as a metal powder was filled into the via holes of the green sheet to form a via conductor pattern. Fifty green sheets on which the internal electrode pattern and the via conductor pattern were formed were stacked, and five green sheets on which neither the internal electrode pattern nor the via conductor pattern was formed were stacked on the lower surface thereof, and four green sheets on which only the via conductor pattern was formed were stacked on the upper surface thereof. Then, one green sheet on which the via conductor pattern and the terminal electrode pattern were formed was placed on the topmost surface to obtain a green sheet laminate. After placing rubber sheets on the upper and lower surfaces of the obtained green sheet laminate, thermocompression bonding was performed to obtain a green laminate. This green laminate was separated into individual pieces to obtain pre-firing chips. These pre-firing chips were heated to 300 °C in a nitrogen atmosphere for debinding treatment, and then heated to 1200 °C in a so-called reducing-steam atmosphere in which steam was introduced into a reducing gas containing hydrogen in nitrogen, held for 2 hours for firing, and cooled to near room temperature to obtain a sintered body. On the nickel layer formed by sintering the terminal electrode forming paste present on the surface of the obtained sintered body, layers of copper, nickel, and tin were formed in this order by plating to obtain a multilayer ceramic capacitor according to Example 1. The obtained multilayer ceramic capacitor had a rectangular parallelepiped shape with an L-direction dimension of 700 μm, a W-direction dimension of 600 μm, and a T-direction dimension of 100 μm, and had four terminal electrodes on the main surface. Also, it was confirmed that the obtained multilayer ceramic capacitor had a raised structure on both main surfaces of the body and that at least a part of each of the terminal electrodes was located on the slope of the raised portion by the above-described procedure. Further, by the above-described procedure, each raised portion of the multilayer ceramic capacitor had two peaks in a cross section parallel to the stacking direction of the laminate passing through the diagonal line of each main surface, and the distance d p between the peaks was the length m of the diagonal line of each main surface d , and it was confirmed that d p = 0.3m d .

[0083] [Comparative Example 1] A multilayer ceramic capacitor according to Comparative Example 1 was obtained using the same method as in Example 1, except that rubber sheets were not placed on the upper and lower surfaces of the raw sheet laminate during thermocompression bonding. The obtained multilayer ceramic capacitor was confirmed to have no raised structure on the main surface of the base body by the procedure described above.

[0084] (PCB mounting test) Multilayer ceramic capacitors according to Example 1 and Comparative Example 1 were subjected to substrate mounting tests. First, multilayer ceramic capacitors were placed on a conductor pattern on a glass epoxy substrate (FR4) using solder paste, and the test circuit board was prepared by heating it in a reflow oven under a nitrogen atmosphere to a temperature range of 250°C to 270°C. Next, the resistance between terminals with different polarities on the test circuit board was measured using an IR checker, and those with a resistance of less than 1 MΩ were judged to be unsatisfactory. 200 multilayer ceramic capacitors each according to Example 1 and Comparative Example 1 were tested, and the number of unsatisfactory capacitors was counted. The results are shown in Table 1.

[0085] [Table 1]

[0086] From the above results, it can be said that the multilayer ceramic capacitor according to the present invention, in which at least one main surface of the base body has a raised structure and at least a portion of the terminal electrodes arranged on the main surface are located on the slope of the raised portion, suppresses soldering between terminal electrodes when mounted on a circuit board.

[0087] [Example 2] A multilayer ceramic capacitor according to Example 2 was obtained in the same manner as in Example 1, except that the rubber sheet was placed only on the side from which the via conductor pattern of the raw sheet laminate was drawn during thermocompression bonding. The obtained multilayer ceramic capacitor was confirmed by the procedure described above to have a raised structure on the main surface from which the via conductors were drawn in the base body, and at least a portion of each terminal electrode is located on the slope of the raised portion, while the main surface from which the via conductors were not drawn in the base body does not have a raised structure. Furthermore, the multilayer ceramic capacitor was confirmed by the procedure described above to have two peaks in the raised portion in a cross section parallel to the lamination direction of the laminate passing through the diagonal of the main surface, with a distance d between the peaks. p However, the length of the diagonal of the main surface is m d In contrast, d p = 0.3m d It was confirmed that this is the case.

[0088] (Handling test using mounting equipment) A handling test using a mounting machine was performed on the multilayer ceramic capacitors according to Example 1 and Example 2. Each multilayer ceramic capacitor was placed on a flat surface with the terminal electrodes facing downwards, and its upper surface was suctioned by the mounting machine and moved to a predetermined position on the circuit board. Among the tested multilayer ceramic capacitors, those that detached from the mounting machine's suction pad when the pad rose, and those that fell from the suction pad during movement, were deemed unsatisfactory. The test was performed on 1000 multilayer ceramic capacitors each from Example 1 and Example 2, and the number of unsatisfactory capacitors was counted. The results are shown in Table 2.

[0089] [Table 2]

[0090] Based on the above results, it can be said that among the multilayer ceramic capacitors according to the present invention, those having a raised structure on only one main surface of the base body are easier to handle when mounted on a circuit board compared to those having raised structures on both main surfaces.

[0091] This specification also discloses the following technologies:

[0092] (Note 1) A laminate in which ceramic layers and internal electrodes mainly composed of metal are alternately stacked. A protective part that covers the surface of the laminate, and A plurality of via conductors are arranged in the stacking direction of the laminate, penetrating the ceramic layer, with at least one end extended to the surface of the protective portion, and electrically connected to the internal electrode. A rectangular parallelepiped body having, and A plurality of terminal electrodes are arranged on at least one of the surfaces forming the surface of the substrate, on the surface from which the end of the via conductor is drawn, and are electrically connected to at least one of the plurality of via conductors. Equipped with, In the aforementioned body, of the pair of main surfaces formed by the surface from which the end of the via conductor is drawn and the surface opposite to said surface, at least one of the surfaces from which the end of the via conductor is drawn and on which the terminal electrode is arranged is: Periphery and, Surrounded by the peripheral edge, and having a raised portion that rises relative to the peripheral edge It has a raised structure composed of, Each terminal electrode arranged on the main surface having the raised structure is positioned such that at least a portion of it is located on the slope of the raised portion. Multilayer ceramic electronic components.

[0093] (Note 2) The multilayer ceramic electronic component as described in (Note 1), wherein the end of the via conductor drawn out to the main surface is located on the slope of the raised portion.

[0094] (Note 3) A multilayer ceramic electronic component according to (Appendix 1) or (Appendix 2), wherein only one of the pair of main surfaces has the raised structure.

[0095] (Note 4) The raised portion has two peaks in a cross-section parallel to the stacking direction of the laminate, passing through the diagonal of the main surface, and the distance d between each peak is p However, the length of the diagonal is m d In contrast, 0.2m d ≤d p ≤0.8m d A multilayer ceramic electronic component that satisfies any of the conditions described in (Appendix 1) to (Appendix 3).

[0096] (Note 5) The multilayer ceramic capacitor as described in (Appendix 4), wherein the protrusion height of the two peaks is 0.1 μm or more and 25 μm or less from the lowest point between the peaks.

[0097] (Note 6) A multilayer ceramic electronic component according to any one of (Appendix 1) to (Appendix 5), wherein the maximum height of the raised portion relative to the peripheral portion is 5 μm or more and 40 μm or less.

[0098] (Note 7) The multilayer ceramic electronic component according to any of (Appendix 1) to (Appendix 6), wherein the boundary between the peripheral portion and the raised portion is located in a region at a distance of 0.0005 mm or more and 0.0030 mm or less from the outer edge of the main surface.

[0099] (Note 8) The multilayer ceramic electronic component according to any one of (Appendix 1) to (Appendix 7), wherein the terminal electrode has a recess that is recessed in the stacking direction of the laminate at a position that covers the end of the via conductor.

[0100] (Note 9) The multilayer ceramic electronic component as described in (Note 8), wherein the depth of the recess is 0.1 μm or more and 30 μm or less.

[0101] (Note 10) A multilayer ceramic electronic component according to any one of (Appendix 1) to (Appendix 9), wherein the number of terminal electrodes disposed on at least one of the pair of main surfaces is four or more.

[0102] (Note 11) The multilayer ceramic electronic component as described in (Appendix 10), wherein each terminal electrode has a different polarity from the other terminal electrodes that are in contact with the nearest terminal electrode in the main surface.

[0103] (Note 12) A circuit board on which a multilayer ceramic electronic component described in any of (Appendix 1) to (Appendix 11) is mounted. [Industrial applicability]

[0104] According to the present invention, it is possible to provide a multilayer ceramic electronic component with low ESL and improved mountability on a circuit board, and a circuit board on which the electronic component is mounted. Such multilayer ceramic capacitors and circuit components are useful in that they contribute to reducing the failure rate and miniaturizing electronic devices equipped with high-performance semiconductors. [Explanation of Symbols]

[0105] 100, 200 Multilayer Ceramic Capacitors 10 Base Body 11 Main surface 111 Peripheral area 112 Ridge 20 Laminate 21 Ceramic layer 22(22a, 22b) Internal electrode 23 (23a, 23b) via conductor 30 Protection Department 31 Cover section 32 Margin section 40(40a, 40b) terminal electrode 41 Underlayment conductor 42 Plated conductor

Claims

1. A laminate in which ceramic layers and internal electrodes mainly composed of metal are alternately stacked. A protective part that covers the surface of the laminate, and A plurality of via conductors are arranged in the stacking direction of the laminate, penetrating the ceramic layer, with at least one end extended to the surface of the protective portion, and electrically connected to the internal electrode. A rectangular parallelepiped body having, and A plurality of terminal electrodes are arranged on at least one of the surfaces forming the surface of the substrate, on the surface from which the end of the via conductor is drawn, and are electrically connected to at least one of the plurality of via conductors. Equipped with, In the aforementioned body, of the pair of main surfaces formed by the surface from which the end of the via conductor is drawn and the surface opposite to said surface, at least one of the surfaces from which the end of the via conductor is drawn and on which the terminal electrode is arranged is: Periphery and, Surrounded by the peripheral edge, and having a raised portion that rises relative to the peripheral edge It has a raised structure composed of, Each terminal electrode arranged on the main surface having the raised structure is positioned such that at least a portion of it is located on the slope of the raised portion. Multilayer ceramic electronic components.

2. The multilayer ceramic electronic component according to claim 1, wherein the end of the via conductor drawn out to the main surface is located on the slope of the raised portion.

3. The multilayer ceramic electronic component according to claim 1, wherein only one of the pair of main surfaces has the raised structure.

4. The raised portion has two peaks in a cross-section parallel to the stacking direction of the laminate, passing through the diagonal of the main surface, and the distance d between each peak is ｐ However, the length of the diagonal is m ｄ In contrast, 0.2m ｄ ≦d ｐ ≦0.8m ｄ A multilayer ceramic electronic component according to claim 1, satisfying the requirements.

5. The multilayer ceramic capacitor according to claim 4, wherein the protrusion height of the two peaks is 0.1 μm or more and 25 μm or less from the lowest point between each peak.

6. The multilayer ceramic electronic component according to claim 1, wherein the maximum height of the raised portion relative to the peripheral portion is 5 μm or more and 40 μm or less.

7. The multilayer ceramic electronic component according to claim 1, wherein the boundary between the peripheral portion and the raised portion is located in a region at a distance of 0.0005 mm or more and 0.0030 mm or less from the outer edge of the main surface.

8. The multilayer ceramic electronic component according to claim 1, wherein the terminal electrode has a recess that is recessed in the stacking direction of the laminate at a position that covers the end of the via conductor.

9. The multilayer ceramic electronic component according to claim 8, wherein the depth of the recess is 0.1 μm or more and 30 μm or less.

10. The multilayer ceramic electronic component according to claim 1, wherein the number of terminal electrodes arranged on at least one of the pair of main surfaces is four or more.

11. The multilayer ceramic electronic component according to claim 10, wherein each of the terminal electrodes has a different polarity from other terminal electrodes that are in contact with the nearest terminal electrode in the main surface.

12. A circuit board on which a multilayer ceramic electronic component according to any one of claims 1 to 12 is mounted.

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