Manufacturing method of wiring boards

Abstract

Improved quality of wiring boards. [Solution] The manufacturing method of the wiring board of the embodiment includes forming a first wiring (wiring pattern 1B) and a second wiring (conductor pattern 1C) located at a different position from the first wiring on a seed layer of a first insulating layer 21; covering the surface of the first wiring with a mask M1; removing the seed layer from the first insulating layer 21 while the surface of the first wiring is covered with the mask M1; and roughening the surface of the second wiring while the surface of the first wiring is covered with the mask M1, thereby making the surface roughness of the second wiring greater than that of the first wiring.

Description

Technical Field

[0001] The technology disclosed in the present application relates to a method for manufacturing a wiring board.

Background Art

[0002] Patent Document 1 discloses a method for manufacturing a wiring board, which includes forming a first conductor layer having a conductor pad and a wiring pattern, roughening the exposed surface of the first conductor layer, providing a coating film on part or all of the exposed surface of the first conductor layer, forming an insulating layer covering the first conductor layer and the coating film, forming a second conductor layer on the insulating layer, and forming a connection conductor penetrating the insulating layer to connect the conductor pad and the second conductor layer. In roughening the exposed surface of the first conductor layer, it is described that the exposed surface of the wiring pattern is not roughened while the exposed surface of the conductor pad is roughened.

[0003] It is also described in the method for manufacturing a wiring board described in Patent Document 1 that the coating film is provided on the exposed surface of the wiring pattern and not on the exposed surface of the conductor pad. Further, it is described in the method for manufacturing a wiring board described in Patent Document 1 that roughening the exposed surface of the first conductor layer includes providing a resist film covering the wiring pattern.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] It is required to realize, in fewer steps, forming a plurality of wirings on an insulating layer and making the surfaces of these wirings have different surface roughnesses. For example, in order to prevent a part of the wiring from being roughened, providing a coating film or a resist film covering the non - roughened part will result in steps for providing these films. [Means for solving the problem]

[0006] The method for manufacturing a wiring board according to the present disclosure includes forming a first wiring and a second wiring located at a different position from the first wiring on a seed layer on a first insulating layer; covering the surface of the first wiring with a mask; removing the seed layer from the first insulating layer while the surface of the first wiring is covered with the mask; and roughening the surface of the second wiring while the surface of the first wiring is covered with the mask, thereby making the surface roughness of the second wiring greater than that of the first wiring.

[0007] According to embodiments of this disclosure, it is possible to form multiple wirings on an insulating layer and give the surfaces of these wirings different surface roughness in fewer steps. [Brief explanation of the drawing]

[0008] [Figure 1] This is a cross-sectional view showing an example of a wiring board manufactured by the wiring board manufacturing method of the first embodiment of the present disclosure. [Figure 2] This is a plan view showing an example of the conductor pattern of the first conductor layer in the first embodiment of the present disclosure. [Figure 3] This is an enlarged view of part III in Figure 1. [Figure 4A] This is a cross-sectional view showing an example of the manufacturing process for a wiring board according to the first embodiment of the present disclosure. [Figure 4B] This is a cross-sectional view showing an example of the manufacturing process for a wiring board according to the first embodiment of the present disclosure. [Figure 4C] This is a cross-sectional view showing an example of the manufacturing process for a wiring board according to the first embodiment of the present disclosure. [Figure 4D] This is a cross-sectional view showing an example of the manufacturing process for a wiring board according to the first embodiment of the present disclosure. [Figure 4E] This is a cross-sectional view showing an example of the manufacturing process for a wiring board according to the first embodiment of the present disclosure. [Figure 4F] This is a cross-sectional view showing an example of the manufacturing process for a wiring board according to the first embodiment of the present disclosure. [Figure 4G] This is a cross-sectional view showing an example of the manufacturing process for a wiring board according to the first embodiment of the present disclosure. [Figure 4H] This is a cross-sectional view showing an example of the manufacturing process for a wiring board according to the first embodiment of the present disclosure. [Figure 4I] This is a cross-sectional view showing an example of the manufacturing process for a wiring board according to the first embodiment of the present disclosure. [Modes for carrying out the invention]

[0009] Hereinafter, an example of an embodiment of this disclosure will be described in detail with reference to the drawings.

[0010] Figure 1 is a cross-sectional view showing an example of a wiring board 100 manufactured by the wiring board manufacturing method of the first embodiment of this disclosure, and Figure 2 is a plan view showing the wiring board 100. Figure 1 is also a cross-sectional view of line II in Figure 2. The orientation of the wiring board 100 in each drawing does not restrict the actual usage state of the wiring board 100.

[0011] As shown in Figure 1, the wiring board 100 includes a core board 3. Of the two main surfaces of the core board 3, the upper surface in Figure 1 is the first surface 3A, and the lower surface is the second surface 3B.

[0012] The core substrate 3 comprises an insulating layer 32 and a conductive layer 31. The conductive layer 31 is formed on both sides of the insulating layer 32. Hereinafter, in the thickness direction of the wiring board 100, the side furthest from the insulating layer 32 will be referred to as the "upper side," "upper," or "top," and the side closer to the insulating layer 32 will be referred to as the "lower side," "downward," or "bottom." Furthermore, in each layer provided on both sides of the insulating layer 32, the side facing away from the insulating layer 32 will be referred to as the "upper surface," and the side facing the insulating layer 32 will be referred to as the "lower surface."

[0013] The wiring board 100 further comprises a first insulating layer 21, a first conductor layer 11, a second insulating layer 22, and a second conductor layer 12. The first insulating layer 21, the first conductor layer 11, the second insulating layer 22, and the second conductor layer 12 are laminated on the first surface 3A of the core substrate 3 in order from the first surface 3A side.

[0014] The first insulating layer 21 covers the first surface 3A of the core substrate 3. The first conductor layer 11 is formed on the first insulating layer 21 in a predetermined pattern by a conductor. The second insulating layer 22 covers the first conductor layer 11. The second insulating layer 22 further covers a portion of the first insulating layer 21 that is not covered by the first conductor layer 11. The second conductor layer 12 is formed on the second insulating layer 22 in a predetermined pattern by a conductor.

[0015] The wiring substrate 100 further includes two insulating layers 23 and two conductor layers 13. The two insulating layers 23 and the two conductor layers 13 are laminated on the second surface 3B of the core substrate 3. The two insulating layers 23 and the two conductor layers 13 are laminated alternately from the second surface 3B side.

[0016] The insulating layer 32 of the core substrate 3 includes a connection conductor 33. The connection conductor 33 connects the conductor layers 31 on both surfaces of the core substrate 3. The connection conductor 33 is a so-called through-hole conductor.

[0017] The first insulating layer 21 includes a connection conductor 4P. The second insulating layer 22 includes a connection conductor 4Q. The two insulating layers 23 include a connection conductor 4R.

[0018] The connection conductor 4P included in the first insulating layer 21 connects the conductor layer 31 and the first conductor layer 11. The connection conductor 4Q included in the second insulating layer 22 connects the first conductor layer 11 and the second conductor layer 12. The connection conductors 4R included in each of the two insulating layers 23 connect the conductor layer 31 and the conductor layer 13 or connect the conductor layers 13 to each other. The connection conductors 4P, 4Q, and 4R are so-called via conductors formed within each insulating layer (the first insulating layer 21, the second insulating layer 22, and the insulating layer 23).

[0019] The first insulating layer 21, the second insulating layer 22, the insulating layer 23, and the insulating layer 32 are formed of an arbitrary insulating resin. Examples of the insulating resin include an epoxy resin, a bismaleimide triazine resin (BT resin), or a phenolic resin.

[0020] In the example shown in Figure 1, the insulating layer 32 includes a core material 32A. The core material 32A is formed of, for example, glass fibers and aramid fibers. The core material 32A also serves as a reinforcing material that reinforces the insulating layer 32. Although not shown in Figure 1, each insulating layer other than the insulating layer 32 (first insulating layer 21, second insulating layer 22, and insulating layer 23) may also include a core material made of glass fibers or the like. The first insulating layer 21, second insulating layer 22, insulating layer 23, and insulating layer 32 may also include an inorganic filler formed of fine particles such as silica (SiO2), alumina, or mullite.

[0021] The first conductor layer 11, the second conductor layer 12, the conductor layer 13, the conductor layer 31, the connecting conductors 4P, 4Q, 4R, and the connecting conductor 33 are formed using any metal, such as copper or nickel.

[0022] The conductor layer 31 includes a metal foil 31A, a metal film 31B, and a plating film 31C. In the example shown in Figure 1, the connecting conductor 33 is integrally formed with the conductor layer 31. The first conductor layer 11, the second conductor layer 12, the conductor layer 13, and the connecting conductors 4P, 4Q, and 4R each include a metal film 10B and a plating film 10C, respectively. The connecting conductors 4P, 4Q, and 4R are integrally formed with the first conductor layer 11, the second conductor layer 12, or the conductor layer 13, respectively. The plating film 31C and the plating film 10C are, for example, electroplated films. The metal film 31B and the metal film 10B are, for example, electroless plating films or sputtering films. The metal film 31B and the metal film 10B each function as power supply layers when the plating films 31C and 10C are formed by electroplating.

[0023] The surface layer of the first side 3A of the core substrate 3 is provided with a second insulating layer 22 and a second conductive layer 12. Solder resist 6 is formed on the second insulating layer 22 and the second conductive layer 12. The surface layer of the second side 3B of the core substrate 3 is provided with an insulating layer 23 and a conductive layer 13. Solder resist 6 is also formed on the insulating layer 23 and the conductive layer 13.

[0024] The solder resist 6 is provided with an opening 6A. The opening 6A exposes a portion of the second conductor layer 12 or the conductor layer 13. The solder resist 6 is formed of, for example, a photosensitive epoxy resin or polyimide resin.

[0025] The first conductor layer 11, the second conductor layer 12, the conductor layer 13, and the conductor layer 31 each contain a predetermined conductor pattern. The first conductor layer 11 includes a conductor pad 1A, a wiring pattern 1B, and a conductor pattern 1C. The wiring pattern 1B is an example of the first wiring of the disclosed technology. The conductor pattern 1C is an example of the second wiring of the disclosed technology.

[0026] The conductor pad 1A is in contact with the connecting conductor 4Q that penetrates the second insulating layer 22. That is, the connecting conductor 4Q is formed on top of the conductor pad 1A. The conductor pad 1A is a so-called receiving pad for the connecting conductor 4Q that penetrates the second insulating layer 22. Therefore, a portion of the surface of the conductor pad 1A on the second insulating layer 22 side is covered by the connecting conductor 4Q that penetrates the second insulating layer 22. In other words, a portion of the surface of the conductor pad 1A on the second insulating layer 22 side faces the bottom surface of the connecting conductor 4Q that penetrates the second insulating layer 22. In the example shown in Figure 1, the connecting conductor 4P that penetrates the first insulating layer 21 and the connecting conductor 4Q that penetrates the second insulating layer 22 are formed to overlap, forming a so-called stacked via conductor. The conductor pad 1A is provided as a so-called via pad for the connecting conductor 4P (via conductor) that penetrates the first insulating layer 21.

[0027] The wiring pattern 1B has a coating film 5 on all sides except the side facing the first insulating layer 21. The outside of the coating film 5 is covered by the second insulating layer 22. The wiring pattern 1B functions as a conductive path used for transmitting any electrical signal. The wiring pattern 1B may, for example, connect a predetermined source and destination of an electrical signal, either alone or in conjunction with other conductor patterns. The wiring pattern 1B may also be a transmission path for high-frequency signals, such as those exceeding several GHz.

[0028] Figure 1 shows two wiring patterns 1B. These two wiring patterns 1B connect two conductor pads 1D within the first conductor layer 11, as shown in Figure 2. The portions 1A2 and 1D2 enclosed by dashed lines in the conductor pads 1A and 1D shown in Figure 2 are the portions covered by the connecting conductor 4Q (see Figure 1) that penetrates the second insulating layer 22. Portion 1A2 is also the surface of conductor pad 1A that is covered by the connecting conductor 4Q.

[0029] In the examples shown in Figures 1 and 2, the first conductor layer 11 further includes a conductor pattern 1C. The conductor pattern 1C extends over a portion of the area on the first insulating layer 21 where the conductor pads 1A and wiring patterns 1B are not formed. The conductor pattern 1C may be a so-called solid plane. The conductor pattern 1C is a wiring pattern that functions as a conductive path used for power supply. The conductor pattern 1C may be used, for example, as a ground plane or power plane to which the ground potential or the potential of a specific power source is applied.

[0030] Figure 3 shows an enlarged view of part III of Figure 1. As shown in Figure 3, a coating film 5 is formed on the surface of the first conductor layer 11. That is, the wiring board 100 has a coating film 5 between the first conductor layer 11 and the second insulating layer 22. Note that "the surface of the first conductor layer 11" refers to the region of the surface of the first conductor layer 11 that faces the second insulating layer 22.

[0031] The coating film 5 improves the adhesion between the first conductor layer 11 and the second insulating layer 22. The coating film 5 is formed from a material that can bond with both an organic material such as a resin constituting the second insulating layer 22 and an inorganic material such as a metal constituting the first conductor layer 11. The coating film 5 is formed from a material that includes both reactive groups that can chemically bond with organic materials and reactive groups that can chemically bond with inorganic materials. In the disclosed art, the coating film 5 is particularly formed from an azole compound. Examples of azole compounds include silane coupling agents containing azole silane compounds such as triazole compounds. The material of the coating film 5 is not limited to silane coupling agents, as long as it can increase the adhesion strength between the first conductor layer 11 and the second insulating layer 22 compared to the case where the second insulating layer 22 is directly formed on the first conductor layer 11. The coating film 5 allows the first conductor layer 11 and the second insulating layer 22 to adhere with greater strength compared to the case where the second insulating layer 22 is directly formed on the first conductor layer 11.

[0032] As shown in Figure 3, in this embodiment, the surface 1B1 of the first conductor layer 11 facing the second insulating layer 22 in the wiring pattern 1B is covered with a coating film 5. That is, the adhesion between the wiring pattern 1B and the second insulating layer 22 is improved compared to when there is no coating film 5. Therefore, it is considered that lifting or peeling of the second insulating layer 22 from the wiring pattern 1B is less likely to occur.

[0033] In the example shown in Figure 3, the surface 1B1 of the wiring pattern 1B is covered with the coating film 5. In contrast, the surface 1A1 of the conductor pad 1A and the surface 1C1 of the conductor pattern 1C are not covered with the coating film 5. The surface 1A1 of the conductor pad 1A and the second insulating layer 22 are in direct contact without the coating film 5. The surface 1C1 of the conductor pattern 1C and the second insulating layer 22 are in direct contact without the coating film 5.

[0034] In this embodiment, the surface 1B1 of the wiring pattern 1B is not roughened. In contrast, the surface 1A1 of the conductor pad 1A and the surface 1C1 of the conductor pattern 1C are roughened, for example, by micro-etching, as will be described later. Therefore, as shown in Figure 3, the conductor pad 1A and the conductor pattern 1C of the first conductor layer 11 have irregularities formed on the surface that is in contact with the first insulating layer 21. In the first conductor layer 11, the difference in height of the irregularities on the surface 1A1 of the conductor pad 1A and the surface 1C1 of the conductor pattern 1C is greater than the difference in height of the irregularities on the surface 1B1 of the wiring pattern 1B. Hereinafter, the surface roughness of the surface 1A1 of the conductor pad 1A and the surface 1C1 of the conductor pattern 1C will be referred to as the "second surface roughness," and the surface roughness of the surface 1B1 of the wiring pattern 1B will be referred to as the "first surface roughness."

[0035] These surface roughnesses can be quantified, for example, as surface roughness defined in ISO 25178. For example, arithmetic mean roughness (Ra) can be used as a parameter to indicate surface roughness.

[0036] In the wiring board 100 of this embodiment, the surface roughness (second surface roughness) of the surface 1A1 of the conductor pad 1A and the surface 1C1 of the conductor pattern 1C is higher than the surface roughness (first surface roughness) of the surface 1B1 of the wiring pattern 1B. A sufficient anchoring effect is obtained both between the conductor pad 1A and the second insulating layer 22 and between the conductor pattern 1C and the second insulating layer 22. It is considered that interfacial delamination between the conductor pad 1A and the second insulating layer 22, and interfacial delamination between the conductor pattern 1C and the second insulating layer 22, is unlikely to occur. Specifically, unintended intrusion of liquid into the interface between the conductor pad 1A and the conductor pattern 1C and the second insulating layer 22 is prevented by the irregularities of the surface 1A1 of the conductor pad 1A and the surface 1C1 of the conductor pattern 1C, which have relatively high second surface roughness. As a result, delamination between the conductor pad 1A and the conductor pattern 1C and the second insulating layer 22 that could be caused by such liquid intrusion may be suppressed.

[0037] More specifically, in the manufacturing process of the wiring board 100, the inner wall of the through-hole 4A (see Figure 4A) provided in the second insulating layer 22 for the formation of the connecting conductor 4Q may be exposed to various processing solutions and plating solutions. These liquids may then penetrate from the inner wall of the through-hole 4A to the interface between the conductor pad 1A and the second insulating layer 22, causing delamination between the conductor pad 1A and the second insulating layer 22. Furthermore, if these liquids penetrate to the interface between the conductor pattern 1C and the second insulating layer 22, they may cause delamination between the conductor pattern 1C and the second insulating layer 22. However, in this embodiment, the unintended penetration of liquids that could cause such delamination is prevented by the irregularities of the surface 1A1 of the conductor pad 1A and the surface 1C1 of the conductor pattern 1C, which have relatively high surface roughness (second surface roughness).

[0038] On the other hand, the surface 1B1 of the wiring pattern 1B is not roughened. The surface roughness (first surface roughness) of the surface 1B1 of the wiring pattern 1B is lower than the surface roughness (second surface roughness) of the surface 1A1 of the conductor pad 1A and the surface 1C1 of the conductor pattern 1C. For example, the arithmetic mean roughness (Ra) of the surface 1B1 of the wiring pattern 1B is between 0.05 μm and 0.15 μm. For example, in wiring patterns with a roughened surface, the effective impedance increases due to the skin effect during high-frequency signal transmission, which can degrade transmission characteristics, i.e., insertion loss can increase. Also, in fine wiring patterns, for example, with a wiring width of 10 μm or less and a wiring spacing of 10 μm or less, if the surface is highly roughened, the desired shape may not be obtained after roughening relative to the design wiring width and thickness. However, in this embodiment, the surface 1B1 of the wiring pattern 1B is not roughened. The surface 1B1 of the wiring pattern 1B has a lower surface roughness compared to the case where it is roughened. Therefore, it is considered that problems such as a decrease in high-frequency transmission characteristics, i.e., insertion loss, caused by the high surface roughness of the surface 1B1 of the wiring pattern 1B, are less likely to occur. For example, if the arithmetic mean roughness (Ra) of the surface 1B1 of the wiring pattern 1B is 0.15 μm or less, it is considered that problems such as a decrease in high-frequency transmission characteristics are less likely to occur compared to the case where the arithmetic mean roughness (Ra) is greater than 0.15 μm. Also, for example, if the arithmetic mean roughness (Ra) of the surface 1B1 of the wiring pattern 1B is 0.05 μm or more, it is considered that there is no need to excessively polish the surface 1B1 of the wiring pattern 1B compared to the case where the arithmetic mean roughness (Ra) is less than 0.05 μm.

[0039] The surface 1B1 of the wiring pattern 1B is covered with a coating film 5 that improves the adhesion between the wiring pattern 1B and the second insulating layer 22. In this way, because the surface 1B1 of the wiring pattern 1B is covered with the coating film 5, it is considered that delamination between the wiring pattern 1B and the second insulating layer 22 is less likely to occur.

[0040] Thus, in the wiring board 100, good transmission characteristics and sufficient adhesion with the second insulating layer 22 are obtained in the wiring pattern 1B. Moreover, delamination between the conductor pad 1A and the second insulating layer 22 is suppressed. Quality degradation of the wiring board 100 due to delamination and the like is suppressed. Quality degradation due to delamination between the conductor pattern 1C and the second insulating layer 22 is also suppressed.

[0041] In order to improve the high-frequency transmission characteristics of the wiring pattern 1B and prevent liquid from entering the interface between the conductor pad 1A and the conductor pattern 1C and the second insulating layer 22, it is preferable that the difference between the surface roughness (second surface roughness) of the surface 1A1 of the conductor pad 1A and the surface 1C1 of the conductor pattern 1C and the surface roughness (first surface roughness) of the surface 1B1 of the wiring pattern 1B be large. For example, the surface roughness (second surface roughness) of the surface 1A1 of the conductor pad 1A and the surface 1C1 of the conductor pattern 1C is 100% or more higher than the surface roughness (first surface roughness) of the surface 1B1 of the wiring pattern 1B. In that case, it is considered that good transmission characteristics for high-frequency signals on the order of several GHz can be obtained in the wiring pattern 1B while maintaining the effect of reliably preventing liquid from entering the interface between the conductor pad 1A and the conductor pattern 1C and the second insulating layer 22.

[0042] The second surface roughness may be 200% or more and 1200% or less of the first surface roughness. In this case, the roughening process of the surface 1A1 of the conductor pad 1A does not require excessive time, and damage to the first insulating layer 21 and other components during the roughening process is considered to be minimal.

[0043] The arithmetic mean roughness (Ra) of the surface 1A1 of the conductor pad 1A and the surface 1C1 of the conductor pattern 1C is, for example, 0.3 μm or more and 0.6 μm or less. Also, the arithmetic mean roughness (Ra) of the surface 1B1 of the wiring pattern 1B is, for example, 0.05 μm or more and 0.15 μm or less. In other words, the arithmetic mean roughness (Ra) of the surface 1A1 of the conductor pad 1A and the surface 1C1 of the conductor pattern 1C is between 2 and 12 times the arithmetic mean roughness (Ra) of the surface 1B1 of the wiring pattern 1B.

[0044] In the example shown in Figure 3, the coating film 5 is not interposed between the surface 1A1 of the conductor pad 1A and the connecting conductor 4Q. That is, the conductor pad 1A and the connecting conductor 4Q are in direct contact. For example, without the use of an organic material such as a silane coupling agent, the metal constituting the conductor pad 1A and the metal constituting the connecting conductor 4Q are in contact at the interface between the conductor pad 1A and the connecting conductor 4Q. Therefore, it is considered that a mechanically strong and electrically low-resistance joint is obtained at the interface between the conductor pad 1A and the connecting conductor 4Q.

[0045] Figure 1 is a cross-sectional view taken along line II in Figure 2. Figure 1 is also a cross-sectional view taken in a direction perpendicular to the extension direction of wiring pattern 1B. In this cross-section, the wiring width of conductor pattern 1C is wider than that of wiring pattern 1B. In the cross-section shown in Figure 1, multiple wiring patterns 1B and multiple conductor patterns 1C are visible, but the minimum wiring width of conductor pattern 1C is greater than the maximum wiring width of wiring pattern 1B that appears in this cross-section. Since conductor pattern 1C has a wider wiring width than wiring pattern 1B, the electrical resistance of conductor pattern 1C over a certain length in the direction normal to this cross-section is smaller than that of wiring pattern 1B over the same length. When conductor pattern 1C is used for power supply, the power loss is also small due to the low electrical resistance.

[0046] Next, the method for manufacturing a wiring board of the technology of this disclosure will be explained using the wiring board 100 of the first embodiment shown in Figure 1 as an example, with reference to Figures 4A to 4I.

[0047] As shown in Figure 4A, a starting substrate (e.g., a double-sided copper-clad laminate) is prepared, which includes an insulating layer that will become the insulating layer 32 of the core substrate 3, and metal foils 31A laminated on both surfaces of the insulating layer. The conductor layer 31 and connecting conductors 33 of the core substrate 3 are formed on this starting substrate. For example, through holes are formed at the formation locations of the connecting conductors 33 by drilling or irradiation with carbon dioxide laser light. A metal film 31B is formed inside the through holes and on the metal foils 31A by electroless plating or sputtering. Then, a plating film 31C is formed by electroplating using the metal film 31B as a power supply layer. As a result, a three-layer conductor layer 31 and a two-layer connecting conductor 33 are formed. Subsequently, a core substrate 3 having a predetermined conductor pattern is obtained by patterning the conductor layer 31 using a subtractive method.

[0048] As shown in Figure 4A, the first insulating layer 21 and the insulating layer 23 are formed on the first surface 3A and the second surface 3B of the core substrate 3, respectively. In the formation of the first insulating layer 21 and the insulating layer 23, for example, a film-like epoxy resin is laminated on the core substrate 3 and then heated and pressurized. As a result, the first insulating layer 21 and the insulating layer 23 are formed. The first insulating layer 21 and the insulating layer 23 are not limited to a film-like epoxy resin, but can be formed from any resin such as BT resin or phenolic resin.

[0049] Through holes 4A for forming connecting conductors 4P and 4R are formed in the first insulating layer 21 and the insulating layer 23, for example by irradiation with carbon dioxide laser light.

[0050] The residue generated during the formation of the through-hole 4A is removed by wet desmear treatment using an alkaline permanganate solution, or by dry desmear treatment using a gas such as plasma.

[0051] In the manufacturing method of the wiring board of this embodiment, a first conductor layer 11 including a conductor pad 1A, a wiring pattern 1B, and a conductor pattern 1C is formed on the first surface 3A side of the core substrate 3. The first conductor layer 11 including the wiring pattern 1B and the conductor pattern 1C is formed such that the wiring width of the conductor pattern 1C is wider than the wiring width of the wiring pattern 1B. A conductor layer 13 is formed on the second surface 3B side of the core substrate 3.

[0052] Connecting conductors 4P and 4R are formed in the first insulating layer 21 and insulating layer 23, respectively. The first conductor layer 11, the conductor layer 13, and the connecting conductors 4P and 4R are formed, for example, using a semi-additive method. That is, a metal film 10B is formed inside the through hole 4A and on the surfaces of the first insulating layer 21 and insulating layer 23, for example, by electroless plating or sputtering. The metal film 10B acts as a seed layer when electrolytic plating is performed in the manufacturing method of the wiring board.

[0053] On the first surface 3A, a resist (not shown) having openings corresponding to the conductor pad 1A, wiring pattern 1B, and conductor pattern 1C is provided on the metal film 10B. On the second surface 3B, a plating resist (not shown) having openings corresponding to the conductor pattern included in the conductor layer 13 is provided. Then, by electroplating using the metal film 10B as a power supply layer, a plating film 10C is formed within the openings of the plating resist. As a result, the first conductor layer 11 and the conductor layer 13, each consisting of the metal film 10B and the plating film 10C, are formed. A connecting conductor 4P, consisting of the metal film 10B and the plating film 10C, is formed in the through hole 4A.

[0054] Here, the upper surface of the plating film 10C may be flattened by polishing. The polishing method is not particularly limited, but one example is CMP (Chemical Mechanical Polishing).

[0055] The arithmetic mean roughness (Ra) of the upper surface of the plating film 10C is, for example, between 0.03 μm and 0.1 μm.

[0056] Subsequently, the plating resist is removed using an alkaline stripping agent, such as sodium hydroxide.

[0057] Next, as shown in Figures 4B and 4C, a resist film R1 is formed on the portion of the first conductive layer 11 that will become the conductive pad 1A and conductive pattern 1C. The resist film R1 is composed of, for example, a dry film resist. The resist film R1 is an example of a second mask of the disclosed technology.

[0058] The resist film R1 is not formed on the portion of the first conductor layer 11 that will become the wiring pattern 1B. A mask M1 is formed on the resist film R1 and on the portion of the first conductor layer 11 that is not covered by the resist film R1, i.e., the portion that will become the wiring pattern 1B. The mask M1 is formed by adsorbing a rust inhibitor, such as an azole compound, onto the portion of the first conductor layer 11 that will become the wiring pattern 1B. The portion of the first conductor layer 11 that will become the wiring pattern 1B is covered by the mask M1.

[0059] Next, as shown in Figure 4D, the resist film R1 is removed. The resist film R1 is removed using an alkaline stripping agent, such as sodium hydroxide. At this time, the portion of the mask M1 that is formed on top of the resist film R1 is also removed along with the resist film R1. The portions of the first conductor layer 11 that will become the conductor pads 1A and conductor patterns 1C are exposed and not covered by the mask M1. The portions of the first conductor layer 11 that will become the wiring patterns 1B remain covered by the mask M1.

[0060] Next, as shown in Figure 4E, the first conductor layer 11 is etched. Etching removes the metal film 10B (seed layer) from the portion of the first conductor layer 11 that is exposed and not covered by the mask M1. In addition, the portion of the first conductor layer 11 that is exposed and not covered by the mask M1, in other words, the portion that becomes the conductor pad 1A and the conductor pattern 1C, is roughened by etching. That is, the mask M1, which acts as a member to prevent the removal of a portion of the metal film 10B, also acts as a member to prevent the roughening of a portion of the first conductor layer 11, i.e., it also acts as a mask during etching. The surface 1A1 of the conductor pad 1A and the surface 1C1 of the conductor pattern 1C are roughened to have, for example, an arithmetic mean roughness (Ra) of 0.3 μm or more and 0.6 μm or less. For etching, for example, quick etching using an acidic solvent can be applied.

[0061] Of the first conductor layer 11, the portion covered by the mask M1, i.e., the portion that becomes the wiring pattern 1B, is not roughened by etching. The mask M1 is a coating film 5 (see Figures 1, 4F, and 4G) that covers the surface 1B1 of the wiring pattern 1B. The coating film 5 is provided on the entire exposed surface of the wiring pattern 1B. The coating film 5 improves the adhesion between the wiring pattern 1B and the second insulating layer 22 (see Figure 4H) that is formed in a later process.

[0062] Next, as shown in Figure 4F, a second insulating layer 22 is formed on the first surface 3A of the core substrate 3, covering the first conductor layer 11. On the second surface 3B of the core substrate 3, an additional insulating layer 23 is formed.

[0063] As shown in Figure 4G, the second insulating layer 22 also covers the coating film 5. The second insulating layer 22 and the insulating layer 23 are formed, like the first insulating layer 21, for example, by lamination of film-like epoxy resin, and by heating and pressurizing. Furthermore, the second insulating layer 22 and the insulating layer 23 are not limited to film-like epoxy resin, but can be formed from any resin such as BT resin or phenolic resin.

[0064] Through-holes 4A are formed in the second insulating layer 22 for forming the connecting conductor 4Q (see Figure 4H) in a later process, for example by irradiation with carbon dioxide laser light. The through-holes 4A are formed in the region of the second insulating layer 22 above the conductor pad 1A. A portion 1A2 of the surface of the conductor pad 1A is exposed by the through-holes 4A. In addition, through-holes are also formed in the insulating layer 23 for forming the connecting conductor 4R (see Figure 4H) in the insulating layer 23 in a later process.

[0065] The through-hole 4A is formed at a position corresponding to the upper surface of the conductor pad 1A. On the upper surface of the conductor pad 1A, the surface on which the through-hole 4A is formed may be smoother and have a lower surface roughness than the surface on which the through-hole 4A is not formed. For example, the arithmetic mean roughness (Ra) of the surface on which the through-hole 4A is formed may be 0.1 μm or more and 0.3 μm or less.

[0066] After the formation of the through-hole 4A, a desmear treatment is preferably performed to remove the resin residue (smear) generated by the formation of the through-hole 4A. For example, the smear inside the through-hole 4A is removed by exposing the inner wall of the through-hole 4A to a treatment solution such as an alkaline permanganate solution.

[0067] The penetration of the processing liquid for this desmear treatment into the interface between the conductor pad 1A and the conductor pattern 1C and the second insulating layer 22 is prevented by the roughened surface 1A1 of the conductor pad 1A and the roughened surface 1C1 of the conductor pattern 1C. This is thought to prevent the dissolution of the coating film 5 on surface 1A1 by the processing liquid and the resulting defects such as interface delamination.

[0068] Next, as shown in Figures 4H and 4I, a second conductor layer 12 is formed on the second insulating layer 22, and a connecting conductor 4Q is formed that penetrates the second insulating layer 22. The connecting conductor 4Q connects the conductor pad 1A and the second conductor layer 12. On the second surface 3B side of the core substrate 3, a conductor layer 13 and a connecting conductor 4R are further formed.

[0069] The second conductor layer 12 is formed, for example, by a method similar to the method for forming the first conductor layer 11 described above, such as a semi-additive method. The upper surface of the second conductor layer 12 may be polished. The connecting conductor 4Q that penetrates the second insulating layer 22 is formed, for example, by a method similar to the method for forming the connecting conductor 4P that penetrates the first insulating layer 21 described above, such as a semi-additive method. The conductor layer 13 and connecting conductor 4R further formed on the second surface 3B side of the core substrate 3 are formed, for example, by a semi-additive method.

[0070] The second conductor layer 12 and the connecting conductor 4Q are formed, for example, in the same manner as the first conductor layer 11 and the connecting conductor 4P described above. For example, the second conductor layer 12 and the connecting conductor 4Q, as well as the conductor layer 13 and the connecting conductor 4R further formed on the second surface 3B side of the core substrate 3, are formed by a semi-additive method.

[0071] In the example shown in Figure 4H, a solder resist 6 is formed. The solder resist 6 is provided with an opening 6A that exposes a portion of the second conductive layer 12 or conductive layer 13. The solder resist 6 and the opening 6A are formed by forming a resin layer containing, for example, a photosensitive epoxy resin or polyimide resin, and then exposure and development using a mask having an appropriate opening pattern.

[0072] In the formation of the connecting conductor 4Q to the second insulating layer 22 by the semi-additive method, as shown in Figure 4I, a metal film 10B is formed in the through hole 4A, for example by electroless plating, and then a plating film 10C is formed by electrolytic plating. In the manufacturing method of the wiring board of this embodiment, penetration of the plating solution into the interface between the conductor pad 1A and the second insulating layer 22 during the formation of the metal film 10B is prevented by the roughened surface 1A1 of the conductor pad 1A. This prevents problems such as interface peeling caused by the plating solution.

[0073] By going through the above steps, the wiring board 100 shown in Figure 1 is completed. A surface protective film (not shown) may be formed on the surface of a portion of the second conductor layer 12 or conductor layer 13 exposed in the opening 6A of the solder resist 6 by electroless plating, solder leveling, or spray coating.

[0074] In the method for manufacturing a wiring board of the technology disclosed herein, in the example shown in Figure 4D, the portion of the first conductor layer 11 that will become the wiring pattern 1B is covered by the mask M1, while the portions that will become the conductor pad 1A and the conductor pattern 1C are exposed and not covered by the mask M1. Alternatively, the portions that will become the wiring pattern 1B and the conductor pad 1A may be covered by the mask M1, while the portion that will become the conductor pattern 1C is exposed and not covered by the mask M1. In this case, the etching shown in Figure 4E will not roughen the surface 1B1 of the wiring pattern 1B, but will roughen the surface 1C1 of the conductor pattern 1C. That is, a wiring board is obtained in which the surface 1B1 of the wiring pattern 1B has a first surface roughness, and the surface 1C1 of the conductor pattern 1C has a second surface roughness.

[0075] In the manufacturing method of the wiring board of this embodiment, the surface 1B1 of the wiring pattern 1B is not roughened, while the surface 1C1 of the conductor pattern 1C is roughened. Because the surface 1C1 of the conductor pattern 1C is roughened, the penetration of various liquids into the boundary between the conductor pattern 1C and the second insulating layer 22 is suppressed by the irregularities of the surface 1C1 of the conductor pattern 1C. Therefore, delamination at the interface between the conductor pattern 1C and the second insulating layer 22 may be suppressed.

[0076] On the other hand, a coating film 5 is formed on the surface 1B1 of the wiring pattern 1B, which can have good high-frequency transmission characteristics without roughening, to improve the adhesion between the first conductor layer 11 and the second insulating layer 22. Therefore, in the wiring pattern 1B, for example, good high-frequency transmission characteristics and sufficient adhesion between the first conductor layer 11 and the second insulating layer 22 can be obtained.

[0077] As described above, the manufacturing method of the wiring board of this embodiment ensures the desired characteristics of the wiring pattern 1B and the adhesion between the wiring pattern 1B and the second insulating layer 22, and can also suppress quality deterioration of the wiring board due to peeling between the conductor pattern 1C and the second insulating layer 22.

[0078] In the manufacturing method of the wiring board of this embodiment, as shown in Figure 4E, the mask M1, which is a member that covers the metal film 10B to prevent its removal during etching, also serves as a member that covers the first conductor layer 11 to prevent its roughening. Therefore, the step of providing a member to cover the first conductor layer 11 to prevent its roughening is unnecessary. Compared to the case where a film is provided to cover the first conductor layer 11 to prevent its roughening, it is possible to achieve different surface roughness on the surfaces of multiple wirings (conductor pads 1A and conductor patterns 1C) on the insulating layer with fewer steps.

[0079] The wiring boards of the embodiments are not limited to those having the structures illustrated in each drawing, or the structures, shapes, and materials illustrated herein. The wiring boards of the embodiments may have any laminated structure. For example, the wiring boards of the embodiments may be coreless boards that do not include a core board. The wiring boards of the embodiments may include any number of conductor layers and insulating layers. The first conductor layer 11 may be located at any level on the laminated structure of the wiring board. The first conductor layer 11 does not have to include a plating film 10C made of an electroplating film, and may include only a metal film 10B made of an electroless plating film, for example. Furthermore, some or all of the multiple conductor layers included in the wiring board may include conductor pads 1A, wiring patterns 1B, and conductor patterns 1C, such as those included in the first conductor layer 11. Furthermore, the conductor pad 1A does not have to be a via pad for a connecting conductor that penetrates the insulating layer below the first conductor layer 11 (the first insulating layer 21 in the wiring board 100).

[0080] The method for manufacturing the wiring board of the embodiment is not limited to the method described with reference to the drawings. For example, the first conductor layer 11 and the second conductor layer 12 may be formed by a fully additive method. Also, the first insulating layer 21 and the second insulating layer 22 may be formed using any form of resin, not limited to a film-like resin. Furthermore, connecting conductors may not be formed in insulating layers other than the second insulating layer 22. In addition to the steps described above, any additional steps may be added to the method for manufacturing the wiring board of the embodiment, and some of the steps described above may be omitted.

[0081] In the manufacturing method of the wiring board of this embodiment, for example, the coating film 5 may be removed after the step shown in Figure 4E. Even with the wiring board obtained in this way, the surface 1B1 of the wiring pattern 1B has a first surface roughness, and the surface 1C1 of the conductor pattern 1C has a second surface roughness.

[0082] Examples of laser light used to remove the coating film 5 include carbon dioxide laser light and YAG laser light, but the laser light used to remove the coating film 5 is not limited to these. Furthermore, the method for removing the coating film 5 on the conductor pad 1A is not limited to laser light irradiation; for example, the coating film 5 may be removed by plasma treatment.

[0083] Next, a solder resist 6 (see Figure 1) is formed to cover the exposed portions of the second insulating layer 22 and the second conductor layer 12. The solder resist 6 is provided with an opening 6A that exposes a portion of the second conductor layer 12 or the conductor layer 13. The solder resist 6 and the opening 6A are formed by forming a resin layer containing, for example, a photosensitive epoxy resin or polyimide resin, and then exposure and development using a mask having an appropriate opening pattern.

[0084] In the formation of the connecting conductor 4Q to the second insulating layer 22 by the semi-additive method, a metal film 10B is formed in the through hole 4A, for example by electroless plating, and then a plating film 10C is formed by electrolytic plating. In the manufacturing method of the wiring board of this embodiment, the penetration of the plating solution into the interface between the conductor pad 1A and the second insulating layer 22 during the formation of the metal film 10B is prevented by the roughened surface 1A1 of the conductor pad 1A.

[0085] By going through the above steps, the wiring board 100 shown in Figure 1 is completed. A surface protective film (not shown) may be formed on the surface of a portion of the second conductor layer 12 or conductor layer 13 exposed in the opening 6A of the solder resist 6 by electroless plating, solder leveling, or spray coating. [Explanation of Symbols]

[0086] 1A Conductor Pad Surface of 1A1 conductor pad 1B Wiring Pattern (Example of First Wiring) 1B1 Wiring pattern surface 1C Conductor Pattern (Example of Second Wiring) Surface of the 1C1 conductor pattern 3 Core boards 3A Core board, first side 3B Core board, second side 4P, 4Q, 4R connecting conductors 4A through hole 5 Coating film 6 Solder Resist 11 First Conductor Layer 12 Second Conductor Layer 21 First insulating layer 22 Second insulating layer 23 Insulating layer 31 Conductor layer 32 Insulating layer 33 Connecting conductors 100 Wiring boards

Claims

1. A first wiring and a second wiring located at a different position from the first wiring are formed on the seed layer on the first insulating layer. Covering the surface of the first wiring with a mask, The seed layer is removed from the first insulating layer while the surface of the first wiring is covered with the mask, By roughening the surface of the second wiring while covering the surface of the first wiring with the mask, the surface roughness of the second wiring is made greater than the surface roughness of the first wiring. A method for manufacturing a wiring board that includes [the specified component].

2. A method for manufacturing a wiring board according to claim 1, The first wiring and the second wiring are formed such that the wiring width of the second wiring is wider than the wiring width of the first wiring.

3. A method for manufacturing a wiring board according to claim 1, This includes covering the surface of the first wiring with a mask by adsorbing a rust inhibitor onto the surface of the first wiring.

4. A method for manufacturing a wiring board according to claim 3, Furthermore, the method includes forming a second insulating layer that covers the second wiring and the first wiring covered by the mask.

5. A method for manufacturing a wiring board according to claim 1, Covering the surface of the first wiring with a mask is, The surface of the second wiring is covered with the second mask, The first wiring and the second mask are covered with the mask, Removing the second mask from the second wiring, Includes.

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