Semiconductor packages

Abstract

The present invention provides a semiconductor package that enables vertical interconnection of semiconductor chips and prevents distortion of semiconductor chips during molding. [Solution] The present invention relates to a semiconductor package 100 comprising: a first substrate 121 disposed on a redistribution layer 110 and having a first cavity H1; a first semiconductor chip 151 having a first connection pad P1; a first encapsulant 131 disposed between the redistribution layer 110 and the first substrate 121; a second substrate 122 disposed on the first substrate 121 and having a second cavity H2; a second semiconductor chip 152 with at least a portion disposed in the second cavity H2; a second encapsulant 132 disposed between the first and second substrates; a first connection via V1 penetrating the first encapsulant 131 and connecting the first connection pad P1 to the redistribution layer 110; and a second connection via V2 penetrating the first substrate 121 and the first and second encapsulants and connecting the second connection pad P2 to the redistribution layer 110.

Description

Technical Field

[0001] The present disclosure relates to semiconductor packages, such as stacked memory packages.

Background Art

[0002] For enhancing the AI (Artificial Intelligence) performance of mobile products, etc., high-performance stacked memory packages are in demand, and various vertical interconnection technologies, such as technologies using metal wires, etc., have been developed for the electrical connection of such stacked memory packages. However, there are limitations in forming tall and long thin metal wires, and there is a possibility that the metal wires may be damaged during molding after the formation of the metal wires.

Summary of the Invention

Problems to be Solved by the Invention

[0003] One of the various objects of the present disclosure is to provide a semiconductor package capable of vertically interconnecting stably stacked semiconductor chips.

[0004] Another one of the various objects of the present disclosure is to provide a semiconductor package capable of preventing semiconductor chips from being distorted during molding of the semiconductor chips.

Means for Solving the Problems

[0005] One of the various solutions provided through the present disclosure is to repeatedly perform a process of forming a cavity in a substrate, embedding semiconductor chips in the cavity, and then forming connection vias connected to the semiconductor chips to realize a package in which a plurality of semiconductor chips are stacked.

[0006] For example, one semiconductor package includes a redistribution layer, a first substrate disposed on the redistribution layer and having a first cavity, a first semiconductor chip having a first connection pad which is at least partially disposed in the first cavity and is oriented toward the redistribution layer, a first encapsulant disposed between the redistribution layer and the first substrate, covering at least a portion of the first semiconductor chip and filling at least a portion of the first cavity, a second substrate disposed on the first substrate and having a second cavity, and a third encapsulant which is at least partially disposed in the second cavity. The present invention may include a second semiconductor chip having a second connection pad positioned toward a substrate, a second encapsulant positioned between a first substrate and a second substrate, covering at least a portion of the second semiconductor chip and filling at least a portion of the second cavity, a first connection via penetrating the first encapsulant, directly connected to the first connection pad, and connecting the first connection pad to a redistribution layer, and a second connection via penetrating the first substrate, the first encapsulant, and the second encapsulant, directly connected to the second connection pad, and connecting the second connection pad to a redistribution layer.

[0007] For example, a semiconductor package according to one example may include a redistribution layer, a plurality of encapsulants and a plurality of substrates arranged alternately on the redistribution layer, a plurality of memory dies, each at least partially located in a cavity penetrating each of the plurality of substrates and at least partially covered by each of the plurality of encapsulants, and a plurality of connection vias, each penetrating one or more of the plurality of encapsulants and the plurality of substrates, solderless connected to each of the plurality of memory dies, and each of the plurality of memory dies connected to the redistribution layer. [Effects of the Invention]

[0008] One of the various effects of this disclosure is the ability to provide a semiconductor package that enables the vertical interconnection of stably stacked semiconductor chips.

[0009] Another of the various effects of this disclosure is that it can provide a semiconductor package that can prevent semiconductor chips from becoming distorted during the molding process. [Brief explanation of the drawing]

[0010] [Figure 1] This is a block diagram illustrating an example of an electronic equipment system. [Figure 2] This is a perspective view showing a schematic example of an electronic device. [Figure 3] This is a schematic cross-sectional view showing an example of a semiconductor package. [Figure 4] Figure 3 is a schematic process diagram illustrating an example of semiconductor package manufacturing. [Figure 5] This is a schematic cross-sectional view showing another example of a semiconductor package. [Modes for carrying out the invention]

[0011] The present disclosure will be described below with reference to the attached drawings. The shapes and sizes of elements in the drawings may be enlarged and / or reduced (or highlighted and / or simplified) for clearer explanation.

[0012] Figure 1 is a block diagram illustrating an example of an electronic equipment system.

[0013] Referring to the drawing, the electronic device 1000 houses the main board 1010. The main board 1010 is physically and / or electrically connected to chip-related components 1020, network-related components 1030, and other components 1040, etc. These, in combination with other electronic components described later, form various signal lines 1090.

[0014] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM (Dynamic Random Access Memory)), non-volatile memory (e.g., ROM (Read Only Memory)), and flash memory; application processor chips such as central processors (e.g., CPU (Central Processing Unit)), graphics processors (e.g., GPU (Graphics Processing Unit)), digital signal processors, cryptographic processors, microprocessors, and microcontrollers); and logic chips such as analog-to-digital converters and ASICs (Application Specific Integrated Circuits). Furthermore, these chip-related components 1020 can be combined with each other. The chip-related components 1020 may also be in the form of a package containing the aforementioned chips or electronic components.

[0015] Network-related components 1030 include Wi-Fi (registered trademark) (IEEE 802.11 family, etc.), WiMAX (registered trademark) (IEEE 802.16 family, etc.), IEEE 802.20, LTE (registered trademark) (long term evolution), Ev-DO (Evolution Data Only), HSPA+ (High Speed ​​Packet Access Plus), HSDPA+ (High Speed ​​Downlink Packet Access Plus), HSUPA+ (High Speed ​​Uplink Packet Access Plus), EDGE (Enhanced Data GSM Environment), GSM (Global System for Mobile communications), GPS (Global Positioning System), GPRS (General Packet Radio Service), CDMA (Code Division Multiple Access), TDMA (Time Division Multiple Access), DECT (Digital Enhanced Cordless Telecommunications), Bluetooth (registered trademark), and 3G (3rd Generation Mobile Communication). This includes, but is not limited to, any other wireless and wired protocols designated as System (third-generation mobile communication system), 4G (4th Generation Mobile Communication System), 5G (5th Generation Mobile Communication System), and later. It may also include any of many other wireless or wired standards or protocols. Furthermore, the network-related component 1030 may be combined with the chip-related component 1020.

[0016] Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCCs (Low Temperature Co-Firing Ceramics), EMI (Electro Magnetic Interference) filters, and MLCCs (Multi-Layer Ceramic Condensers). However, they are not limited to these, and may also include passive elements in the form of chip components used for various other applications. Furthermore, other components 1040 can be combined with chip-related components 1020 and / or network-related components 1030.

[0017] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the main board 1010, or not connected. Examples of other electronic components include a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. However, it is not limited to these, and may also include audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage devices (e.g., hard disk drives), CDs (Compact Disks), DVDs (Digital Versatile Discs), and other electronic components used for various purposes depending on the type of electronic device 1000.

[0018] The electronic device 1000 may be, for example, a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smartwatch, an automotive device, etc. However, it is not limited thereto, and any other electronic device that processes data, such as a server, may also be used.

[0019] FIG. 2 is a perspective view schematically showing an example of an electronic device.

[0020] Referring to the drawings, the electronic device may be, for example, a smartphone 1100. Inside the smartphone 1100, a motherboard 1110 is housed, and various components 1120 are physically and / or electrically connected to such a motherboard 1110. Also, components such as a camera module 1130 and / or a speaker 1140 may be physically and / or electrically connected to the motherboard 1110, or other components that may or may not be connected may be housed inside. Some of the components 1120 may be the chip-related components described above, for example, a semiconductor package 1121, but are not limited thereto.

[0021] FIG. 3 is a cross-sectional view schematically showing an example of a semiconductor package.

[0022] Referring to the drawing, the semiconductor package 100 consists of a redistribution layer 110, a plurality of encapsulating materials 131, 132, 133, 134 arranged alternately on the redistribution layer 110, and a plurality of substrates 121, 122, 123, 124, with at least a portion of each of the cavities H1, H2, H3, H4 penetrating each of the substrates 121, 122, 123, 124 being located within each of the plurality of semiconductor chips, each at least a portion of which is covered by the plurality of encapsulating materials 131, 132, 133, 134. It may include multiple connection vias V1, V2, V3, V4 that penetrate one or more of the chips 151, 152, 153, 154, as well as one or more of the multiple encapsulants 131, 132, 133, 134 and multiple substrates 121, 122, 123, 124, and are solderless connected to each of the multiple semiconductor chips 151, 152, 153, 154, and each of the multiple semiconductor chips 151, 152, 153, 154, and connect each of the multiple semiconductor chips 151, 152, 153, 154 to the redistribution layer 110.

[0023] More specifically, the semiconductor package 100 comprises a redistribution layer 110, a first substrate 121 disposed on the redistribution layer 110 and having a first cavity H1, a first semiconductor chip 151 having a first connection pad P1 disposed at least in part in the first cavity H1 and facing the redistribution layer 110, a first encapsulating material 131 disposed between the redistribution layer 110 and the first substrate 121, covering at least part of the first semiconductor chip 151 and filling at least part of the first cavity H1, a second substrate 122 disposed on the first substrate 121 and having a second cavity H2, and a first substrate disposed at least in part in the second cavity H2 The present invention may include a second semiconductor chip 152 having a second connection pad P2 positioned toward the board 121, a second encapsulant 132 positioned between the first substrate 121 and the second substrate 122, covering at least a portion of the second semiconductor chip 152 and filling at least a portion of the second cavity H2, a first connection via V1 that penetrates the first encapsulant 131 and is directly connected to the first connection pad P1, and connects the first connection pad P1 to the redistribution layer 110, and a second connection via V2 that penetrates the first substrate 121 and the first and second encapsulants 131 and 132 and is directly connected to the second connection pad P2, and connects the second connection pad P2 to the redistribution layer 110.

[0024] Further, the semiconductor package 100 is disposed on the second substrate 122, and includes a third substrate 123 having a third cavity H3, a third semiconductor chip 153 at least partially disposed in the third cavity H3 and having a third connection pad P3 disposed toward the second substrate 122, a third encapsulant 133 disposed between the second substrate 122 and the third substrate 123, covering at least a part of the third semiconductor chip 153 and filling at least a part of the third cavity H3, a third connection via V3 passing through the first substrate 121, the second substrate 122, and the third encapsulant 133 and directly connected to the third connection pad P3 to connect the third connection pad P3 to the redistribution layer 110, a fourth substrate 124 disposed on the third substrate 123 and having a fourth cavity H4, a fourth semiconductor chip 154 at least partially disposed in the fourth cavity H4 and having a fourth connection pad P4 disposed toward the third substrate 123, a fourth encapsulant 134 disposed between the third substrate 123 and the fourth substrate 124, covering at least a part of the fourth semiconductor chip 154 and filling at least a part of the fourth cavity H4, a fourth connection via V4 passing through the first substrate 121, the second substrate 122, the third substrate 123, and the fourth encapsulant 134 and directly connected to the fourth connection pad P4 to connect the fourth connection pad P4 to the redistribution layer 110, and a plurality of electrical connection metals 180 respectively disposed on the opposite side of the redistribution layer 110 from the side where the first substrate 121 is disposed and respectively connected to the redistribution layer 110.

[0025] In this way, the semiconductor package 100 has cavities H1, H2, H3, and H4 formed on each substrate 121, 122, 123, and 124, semiconductor chips 151, 152, 153, and 154 placed in each cavity H1, H2, H3, and H4, each semiconductor chip 151, 152, 153, and 154 covered with encapsulating material 131, 132, 133, and 134, and each semiconductor chip 151, 152, 153, and 154 can be connected to the redistribution layer 110 using connecting vias V1, V2, V3, and V4 that penetrate one or more of the substrates 121, 122, 123, and 124 and the encapsulating material 131, 132, 133, and 134, respectively. For example, vertical interconnection of semiconductor chips 151, 152, 153, and 154, which are stably stacked via connecting vias V1, V2, V3, and V4, may be possible without thin metal posts or metal wires. Also, since each substrate 121, 122, 123, and 124, on which cavities H1, H2, H3, and H4 are formed, surrounds each semiconductor chip 151, 152, 153, and 154, it is possible to prevent misalignment of each semiconductor chip 151, 152, 153, and 154 when covering each semiconductor chip 151, 152, 153, and 154 with encapsulating material 131, 132, 133, and 134. Furthermore, since interconnection occurs via connecting vias V1, V2, V3, and V4, solder bumps may not be necessary. For example, the vertical interconnection structure may be a solderless structure.

[0026] On the other hand, the first semiconductor chip 151, the second semiconductor chip 152, the third semiconductor chip 153, and the fourth semiconductor chip 154 ​​may each be memory dies. For example, the semiconductor package 100 may be a stack memory package. For example, each memory die may include wide I / O memory, and therefore, bandwidth can be significantly improved by processing data in parallel using more input / output (I / O) pins, and power consumption can be reduced. It can also play an important role in improving performance in small devices such as SoCs (System on Chip) for mobile devices. For example, it can be used to increase memory bandwidth in mobile environments that require high performance and low power in a confined space, and it can have a 3D stack structure.

[0027] On the other hand, the first substrate 121, the second substrate 122, the third substrate 123, and the fourth substrate 124 may each be ordinary organic substrates, and may include, for example, CCL (Copper Clad Laminate) or Unclad CCL. Therefore, process warpage can be effectively controlled. In addition, the first connection via V1, the second connection via V2, the third connection via V3, and the fourth connection via V4 can be formed more easily. Furthermore, when covering each semiconductor chip 151, 152, 153, and 154 with the encapsulating material 131, 132, 133, and 134, misalignment of each semiconductor chip 151, 152, 153, and 154 can be prevented.

[0028] On the other hand, the first cavity H1, the second cavity H2, the third cavity H3, and the fourth cavity H4 may each be through-cavities. For example, the first cavity H1, the second cavity H2, the third cavity H3, and the fourth cavity H4 can each penetrate between two opposing surfaces of the first substrate 121, the second substrate 122, the third substrate 123, and the fourth substrate 124, for example, between the top and bottom surfaces. Therefore, the first semiconductor chip 151, the second semiconductor chip 152, the third semiconductor chip 153, and the fourth semiconductor chip 154 ​​can be more easily placed in the first cavity H1, the second cavity H2, the third cavity H3, and the fourth cavity H4, and the difficulty of the embedding process may be reduced.

[0029] On the other hand, the surface of the first substrate 121 that contacts the second encapsulant 132 may be substantially coplanar with the surface of the first semiconductor chip 151 that contacts the second encapsulant 132. Similarly, the surface of the second substrate 122 that contacts the third encapsulant 133 may be substantially coplanar with the surface of the second semiconductor chip 152 that contacts the third encapsulant 133. Furthermore, the surface of the third substrate 123 that contacts the fourth encapsulant 134 may be substantially coplanar with the surface of the third semiconductor chip 153 that contacts the fourth encapsulant 134. In addition, the surface of the fourth substrate 124 opposite to the surface facing the third substrate 123 may be substantially coplanar with the surface opposite to the surface facing the fourth semiconductor chip 154 ​​and the third semiconductor chip 153. For example, in a carrier-based stacking process as described later, a flat base surface can be provided at each stage, making the stacking process easier. Furthermore, distortion of semiconductor chips 151, 152, 153, and 154 during the embedding process can be prevented more effectively.

[0030] On the other hand, the first connection via V1 and the second connection via V2 may be tapered such that the width of the end connected to the redistribution layer 110 in cross-section is wider than the width of the end connected to the first connection pad P1 and the second connection pad P2. For example, the first connection via V1 and the second connection via V2 can be formed by processing via holes from the side where the redistribution layer 110 is located to each connection pad P1 and P2, and then filling the via holes with plating. Therefore, a separate solder bump may not be necessary. For example, the vertical interconnection structure may be a solderless structure.

[0031] On the other hand, the third connection via V3 may include a third-first connection via V3-1 that penetrates the second substrate 122, the second encapsulant 132, and the third encapsulant 133 and is directly connected to the third connection pad P3, and a third-second connection via V3-2 that penetrates the first substrate 121 and the first encapsulant 131 and connects the third-first connection via V3-1 to the redistribution layer 110. Furthermore, the fourth connection via V4 may include a fourth-first connection via V4-1 that penetrates the third substrate 123 and the third and fourth encapsulants 133 and 134 and is directly connected to the fourth connection pad P4, a fourth-second connection via V4-2 that penetrates the second substrate 122 and the second encapsulant 132 and is connected to the fourth-first connection via V4-1, and a fourth-third connection via V4-3 that penetrates the first substrate 121 and the first encapsulant 131 and connects the fourth-second connection via V4-2 to the redistribution layer 110. For example, the third connection via V3 and the fourth connection via V4 may each be in a landless, vertically connected stacked via structure. Therefore, via connections may be possible more stably and with a finer pitch.

[0032] On the other hand, in cross-section, the width of the end of the 3-1 connecting via V3-1 connected to the 3-2 connecting via V3-2 may be wider than the width of the end of the 3-2 connecting via V3-2 connected to the 3-1 connecting via V3-1. Also, in cross-section, the width of the end of the 4-1 connecting via V4-1 connected to the 4-2 connecting via V4-2 may be wider than the width of the end of the 4-2 connecting via V4-2 connected to the 4-1 connecting via V4-1, and the width of the end of the 4-2 connecting via V4-2 connected to the 4-3 connecting via V4-3 may be wider than the width of the end of the 4-3 connecting via V4-3 connected to the 4-2 connecting via V4-2. For example, the third-first connection via V3-1 and the third-second connection via V3-2, and the fourth-first connection via V4-1, the fourth-second connection via V4-2, and the fourth-third connection via V4-3 may be formed by machining via holes from the side where the redistribution layer 110 is located to the opposite side, and then filling the via holes with plating, or they may be formed separately during the stacking process. Therefore, separate solder bumps may not be necessary. For example, the vertical interconnection structure may be a solderless structure. Also, therefore, via connections may be possible more stably and with a finer pitch.

[0033] The components of the semiconductor package 100 will be described in more detail below with reference to the drawings.

[0034] The redistribution layer 110 can serve as a redistribution layer for multiple semiconductor chips 151, 152, 153, and 154. For example, it can serve as a redistribution layer for fan-out. In this view, the redistribution layer 110 may include multiple insulating layers, multiple conductive pattern layers disposed within each of the multiple insulating layers, and multiple conductive via layers disposed within each of the multiple insulating layers and connected to one or more of the multiple conductive pattern layers. One of the multiple conductive pattern layers may include a conductive pattern connected to multiple connection vias V1, V2, V3, and V4. Another of the multiple conductive pattern layers may include a conductive pattern connected to multiple electrically connecting metals 180. The multiple conductive via layers can provide electrical connection paths within the redistribution layer 110.

[0035] Each of the multiple insulating layers may contain an organic insulating material. Here, the organic insulating material may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material containing an inorganic filler and / or organic filler together with the resin. For example, the organic insulating material here may be a non-photosensitive insulating material such as ABF (Ajinomoto Build up Film) (registered trademark), but is not limited to these, and other polymer materials may also be used. The organic insulating material may also contain a photosensitive insulating material such as PID (Photo Imageable Dielectric). The multiple insulating layers may contain substantially the same organic insulating material and may integrate with each other after curing, making the boundaries indistinct.

[0036] Each of the multiple conductive pattern layers may contain a metal. The metals may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Each of the multiple conductive pattern layers can perform various functions depending on the design. For example, they may include signal patterns, power patterns, ground patterns, etc. These patterns may each have various forms such as lines, planes, pads, and lands. Each of the multiple conductive pattern layers may include a sputtered layer and / or an electroless plating layer as a seed layer, and an electroplating layer as a plating layer formed on the seed layer. The number of multiple conductive pattern layers is not particularly limited and can be formed as needed.

[0037] Each of the conductive via layers may contain a metal. The metals may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Each of the conductive via layers may contain filled vias that fill via holes, or conformal vias that are positioned along the walls of via holes. Each of the conductive via layers can perform various functions depending on the design. For example, they may include ground vias, power vias, signal vias, etc. Each of the conductive via layers may contain a sputtered layer and / or an electroless plating layer as a seed layer, and an electroplating layer as a plating layer formed on the seed layer. The number of conductive via layers is not particularly limited and can be formed as needed.

[0038] The multiple substrates 121, 122, 123, and 124 can each contain an organic insulating material or an inorganic insulating material. Here, the organic insulating material can include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material containing an inorganic filler, an organic filler, and / or glass fibers together with the resin. For example, the organic insulating material here can include, but is not limited to, insulating materials such as PPG (Prepreg) and CCL (Copper Clad Laminate). The inorganic insulating material can include, but is not limited to, ceramics and glass. The multiple cavities H1, H2, H3, and H4 can each penetrate at least a portion of the multiple substrates 121, 122, 123, and 124, and are preferably through-cavities as described above, but are not limited to these.

[0039] The multiple encapsulants 131, 132, 133, and 134 may include an organic insulating material. Here, the organic insulating material may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material containing an inorganic filler and / or organic filler together with the resin. For example, the organic insulating material here may include, but is not limited to, ABF, EMC (Epoxy Molding Compound), etc., and other polymer materials may also be used. The multiple encapsulants 131, 132, 133, and 134 may contain substantially the same organic insulating material and may integrate with each other after curing, making the boundaries indistinct.

[0040] The multiple semiconductor chips 151, 152, 153, and 154 may each include an integrated circuit (IC) die in which hundreds to millions or more elements are integrated within a single chip. In this case, the integrated circuit may be a memory die such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, or an HBM (High Bandwidth Memory), and preferably may include a wide I / O memory as described above, but is not limited to these.

[0041] Each of the connection pads P1, P2, P3, and P4 may contain a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Each of the connection pads P1, P2, P3, and P4 may be positioned protruding from the active surface of each of the semiconductor chips 151, 152, 153, and 154, but may also be positioned embedded relative to the active surface of each of the semiconductor chips 151, 152, 153, and 154. If necessary, each of the connection pads P1, P2, P3, and P4 may contain a conductive bump, which may be a conventional metal bump other than a solder bump. For example, the metal bump may be formed on an aluminum pad and may include, but is not limited to, a seed layer containing sputtered titanium / copper or chemical copper and a plating layer containing electroplated copper. Multiple connection pads P1, P2, P3, and P4 may each be present in multiple quantities.

[0042] Multiple connection vias V1, V2, V3, and V4 can each contain a metal. These metals may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Each of the multiple connection vias V1, V2, V3, and V4 may contain filled vias that fill via holes, or conformal vias positioned along the walls of via holes. Each of the multiple connection vias V1, V2, V3, and V4 can perform various functions depending on the design. For example, they may include ground vias, power vias, signal vias, etc. Each of the multiple connection vias V1, V2, V3, and V4 may contain a sputtered layer and / or an electroless plating layer as a seed layer, and an electroplating layer as a plating layer formed on the seed layer. Each of the multiple connection vias V1, V2, V3, and V4 can be formed in multiple quantities. On the other hand, the shapes of the multiple connecting vias V1, V2, V3, and V4 do not necessarily have to be tapered; they may be cylindrical with approximately vertical sides as needed.

[0043] The multiple electrical coupling metals 180 may each be formed from a low-melting-point metal, such as a tin (Sn)-aluminum (Al)-copper (Cu) solder, but this is merely an example and the material is not particularly limited to these. The multiple electrical coupling metals 180 may each be balls, pins, etc. The multiple electrical coupling metals 180 may each be formed from multiple layers or a single layer. When formed from multiple layers, it may include copper columns and solder, and when formed from a single layer, it may include tin-silver solder, but is not limited to these. The multiple electrical coupling metals 180 may be used to mount the semiconductor package 100 onto other substrates or other packages. The number of multiple electrical coupling metals 180 is not particularly limited and can be formed as needed.

[0044] Figure 4 is a schematic process diagram illustrating an example of the manufacturing process for the semiconductor package shown in Figure 3.

[0045] Referring to the drawing, first, the fourth substrate 124, which has a fourth cavity H4 formed on it, is attached to the carrier 190, and then the fourth semiconductor chip 154 ​​is placed in the fourth cavity H4. After that, the fourth substrate 124 and the fourth semiconductor chip 154 ​​can be covered with the fourth encapsulant 134.

[0046] Next, the third substrate 123, on which the third cavity H3 is formed, is attached to the fourth encapsulating material 134. After placing the third semiconductor chip 153 in the third cavity H3, the third substrate 123 and the third semiconductor chip 153 can be covered with the third encapsulating material 133.

[0047] Next, via holes can be processed using a laser drill or mechanical drill to penetrate the third substrate 123, the third encapsulant 133, and the fourth encapsulant 134 up to the fourth connection pad P4 of the fourth semiconductor chip 154, and then filled with plating to form the fourth-first connection via V4-1.

[0048] Next, the second substrate 122, on which the second cavity H2 is formed, is attached to the third encapsulating material 133. After placing the second semiconductor chip 152 in the second cavity H2, the second substrate 122 and the second semiconductor chip 152 can be covered with the second encapsulating material 132.

[0049] Next, via holes can be processed using a laser drill or mechanical drill to penetrate the second substrate 122, the second encapsulant 132, and the third encapsulant 133 up to the third connection pad P3 of the third semiconductor chip 153, and then filled with plating to form the third-first connection via V3-1. Furthermore, via holes can be processed using a laser drill or mechanical drill to penetrate the second substrate 122, the second encapsulant 132, and the third encapsulant 133 up to the fourth-first connection via V4-1, and then filled with plating to form the fourth-second connection via V4-2.

[0050] Next, the first substrate 121, on which the first cavity H1 is formed, is attached to the second encapsulating material 132. After placing the first semiconductor chip 151 in the first cavity H1, the first substrate 121 and the first semiconductor chip 151 can be covered with the first encapsulating material 131.

[0051] Next, a via hole can be created through the first encapsulating material 131 to the first connection pad P1 of the first semiconductor chip 151 using a laser drill or mechanical drill, and then filled with plating to form the first connection via V1. Furthermore, a via hole can be created through the first substrate 121, the first encapsulating material 131, and the second encapsulating material 132 to the second connection pad P2 of the second semiconductor chip 152 using a laser drill or mechanical drill, and then filled with plating to form the second connection via V2. Finally, a via hole can be created through the first substrate 121, the first encapsulating material 131, and the second encapsulating material 132 to the third-first connection via V3-1 using a laser drill or mechanical drill, and then filled with plating to form the third-second connection via V3-2. Alternatively, via holes can be formed by using a laser drill or mechanical drill to penetrate the first substrate 121, the first encapsulant 131, and the second encapsulant 132 up to the 4-2nd connecting via V4-2, and then filling them with plating to form the 4-3rd connecting via V3-3. The 3-1st connecting via V3-1 and the 3-2nd connecting via V3-2 may be connected vertically to form the 3rd connecting via V3. The 4-1st connecting via V4-1, the 4-2nd connecting via V4-2, and the 4-3rd connecting via V4-3 may be connected vertically to form the 4th connecting via V4.

[0052] Next, a redistribution layer 110 can be formed on the first encapsulant 131. The redistribution layer 110 can be formed, for example, by sequentially forming a conductive pattern layer, an insulating layer, and a conductive via layer using a build-up process. The build-up process may include forming an insulating layer via coating or lamination, forming via holes via photolithography or laser processing, and forming a conductive pattern layer and a conductive via layer via a plating process using a resist.

[0053] Next, the semiconductor package manufactured from the carrier 190 can be separated, and multiple electrically coupled metals can be formed on the redistribution layer 110 as needed.

[0054] Other details may be substantially the same as those described for semiconductor package 100.

[0055] Figure 5 is a schematic cross-sectional view showing another example of a semiconductor package.

[0056] Referring to the drawings, the semiconductor package 500 may have a package-on-package structure. For example, it may have a structure in which the above-described semiconductor package 100 is stacked on a chip package 200. For example, the redistribution layer 110 of the above-described semiconductor package 100 may be placed on the chip package 200 and connected to the chip package 200 via a plurality of electrically connecting metals 180. The chip package 200 may include a semiconductor chip 250, and the semiconductor chip 250 may include an SoC. For example, the semiconductor package 500 may be a stacked structure of a chip package 200 including an SoC and a semiconductor package 100 including 3D stacked Wide I / O memory.

[0057] The components of the semiconductor package 500 will be described in more detail below with reference to the drawings.

[0058] The chip package 200 may include a front redistribution layer 210 and a backside redistribution layer 220, a semiconductor chip 250 mounted on the front redistribution layer 210, bumps 230 connecting the front redistribution layer 210 and the backside redistribution layer 220, molding material 240 positioned between the front redistribution layer 210 and the backside redistribution layer 220 to mold the semiconductor chip 250 and the bumps 230, and a plurality of electrically connecting metals 280 positioned on the opposite side of the front redistribution layer 210 from the side on which the semiconductor chip 250 is mounted. However, the structure of the chip package 200 is not limited to these, and various forms of package structures including a semiconductor chip 250 may be applied as the chip package 200.

[0059] The front redistribution layer 210 and the backside redistribution layer 220 may each include multiple insulating layers, multiple conductive pattern layers, and multiple conductive via layers. The specific details of the multiple insulating layers, multiple conductive pattern layers, and multiple conductive via layers may be substantially the same as those described for the redistribution layer 110 of the semiconductor package 100.

[0060] The bump 230 can include various forms of conductive bumps. For example, solder bumps, ordinary metal bumps without solder bumps, or hybrid bumps in which metal is placed within the solder may be used.

[0061] The molding material 240 may include an organic insulating material. Here, the organic insulating material may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material containing an inorganic filler and / or organic filler together with the resin. For example, the organic insulating material here may include ABF, EMC, etc., but is not limited to these, and other polymer materials may also be used.

[0062] The semiconductor chip 250 may include an integrated circuit die in which hundreds to millions or more elements are integrated within a single chip. In this case, the integrated circuit may include, but is not limited to, an SoC.

[0063] Each of the multiple electrical coupling metals 280 can be formed from a low-melting-point metal, such as a tin (Sn)-aluminum (Al)-copper (Cu) solder, but this is merely an example and the material is not particularly limited to these. Each of the multiple electrical coupling metals 280 may be a ball, a pin, or the like. Each of the multiple electrical coupling metals 280 may be formed from multiple layers or a single layer. When formed from multiple layers, it may include copper columns and solder, and when formed from a single layer, it may include tin-silver solder, but is not limited to these. The multiple electrical coupling metals 280 may be used to mount the semiconductor package 500 onto another substrate, such as a main board. The number of multiple electrical coupling metals 280 is not particularly limited and can be formed as needed.

[0064] Other details may be substantially the same as those described in the semiconductor package 100 and its manufacturing method.

[0065] In this disclosure, thickness, width, length, pitch, depth, height, etc., can be measured using a scanning microscope or optical microscope based on a polished or cut cross-section of the semiconductor package. The cut cross-section may be vertical or horizontal, and each value can be measured based on the required cut cross-section. If the values ​​are not constant, the values ​​can be determined by the average of the values ​​measured at any five points. The width of the via end can be measured on a cross-section cut along the central axis of the via in the thickness direction.

[0066] In this disclosure, the expression "cover" may include not only covering the entire surface but also covering at least a portion of it, and may include not only direct covering but also indirect covering. Similarly, the expression "fill" may include not only filling the surface completely but also filling it at least partially, for example, when there are some gaps or voids.

[0067] In this disclosure, the determination can be made including process errors, positional deviations, and measurement errors that occur during the manufacturing process. For example, substantially identical line width, spacing, thickness, and height may include not only cases where the numerical values ​​are exactly the same, but also cases where they are approximately similar. Furthermore, substantially having a specific shape may include not only cases where the shape is exactly that, but also cases where the shape is approximately that. Also, substantially coplanes may include not only cases where they are exactly on the same plane, but also cases where they are approximately on the same plane.

[0068] In this disclosure, substantially identical insulating materials may mean not only completely identical insulating materials, but also include insulating materials of the same type. Therefore, the compositions of the insulating materials may be substantially the same, but their specific composition ratios may differ slightly.

[0069] In this disclosure, "cross-section" can mean the cross-sectional shape when an object is cut vertically, or the cross-sectional shape when an object is viewed from the side. "On a plane" can mean the planar shape when an object is cut horizontally, or the planar shape when an object is viewed from the top or bottom.

[0070] In this disclosure, terms such as "lower side," "bottom," and "bottom surface" are used for convenience to mean the downward direction relative to the cross-section of the drawing, while terms such as "upper side," "upper part," and "top surface" are used to mean the opposite direction. Furthermore, terms such as "side" and "side" are used to mean the direction perpendicular to the top and bottom surfaces. However, these directions are merely for explanatory purposes, and the scope of the claims is not specifically limited by such directional descriptions; the concepts of "up" and "down" may change at any time.

[0071] In this disclosure, the term "connected" includes not only direct connections but also indirect connections via adhesive layers, etc. Furthermore, the term "electrically connected" includes both physically connected and unconnected cases. In addition, expressions such as "first," "second," etc., are used to distinguish one component from another and do not limit the order and / or importance of those components. In some cases, without departing from the scope of the rights, the first component may be named the second component, and similarly, the second component may be named the first component.

[0072] The expression "example" as used in this disclosure does not mean that each embodiment is identical to the others, but is provided to highlight and illustrate the unique and distinct features of each embodiment. However, the examples presented above do not preclude their implementation in combination with features of other examples. For example, even if a matter described in one example is not described in another example, it can be understood as a description related to the other example, unless there is a description in the other example that contradicts or inconsistes with that matter.

[0073] The terms used in this disclosure are for illustrative purposes only and are not intended to limit the disclosure. Where otherwise, singular expressions include plural expressions unless the context clearly indicates otherwise. [Explanation of symbols]

[0074] 1000 electronic equipment 1010 Mainboard 1020 Chip-related components 1030 Network-related components 1040 Other parts 1050 Camera 1060 Antenna 1070 Display 1080 Battery 1090 signal line 1100 Smartphone 1110 Motherboard 1120 parts 1121 Semiconductor Package 1130 Camera Module 1140 speakers 500 semiconductor packages 100 semiconductor packages 110 Redistribution layer 121, 122, 123, 124 circuit boards 131, 132, 133, 134 Sealing material 151, 152, 153, 154 Semiconductor chips P1, P2, P3, P4 Connection Pads V1, V2, V3, V3-1, V3-2, V4, V4-1, V4-2, V4-3 Connection Via H1, H2, H3, H4 Cavities 180 Electrically connected metals 190 Carriers 200 chip package 210, 220 redistribution layer 230 Bump 240 Molding Materials 250 semiconductor chips 280 Electrically connected metals

Claims

1. Redistribution layer and Displaced on the aforementioned redistribution layer, a first substrate having a first cavity, A first semiconductor chip having a first connection pad which is at least a portion of the first cavity and is positioned toward the redistribution layer, A first encapsulating material is disposed between the redistribution layer and the first substrate, covering at least a portion of the first semiconductor chip and filling at least a portion of the first cavity, A second substrate having a second cavity is disposed on the first substrate, A second semiconductor chip having a second connection pad which is at least a portion of the second cavity and is positioned toward the first substrate, A second encapsulating material is disposed between the first substrate and the second substrate, covering at least a portion of the second semiconductor chip and filling at least a portion of the second cavity, A first connection via that penetrates the first sealing material, is directly connected to the first connection pad, and connects the first connection pad to the rewiring layer, A semiconductor package comprising: a first substrate; a first encapsulant; and a second connection via that penetrates the second encapsulant, is directly connected to the second connection pad, and connects the second connection pad to the redistribution layer.

2. The semiconductor package according to claim 1, wherein the first semiconductor chip and the second semiconductor chip are each a memory die.

3. The first substrate and the second substrate are each organic substrates. The semiconductor package according to claim 1, wherein the organic substrate includes a copper-clad laminate or an unclad copper-clad laminate.

4. The semiconductor package according to claim 1, wherein the first connection via and the second connection via are tapered such that the width of the end connected to the redistribution layer in cross-section is wider than the width of the end connected to the first connection pad and the second connection pad, respectively.

5. The semiconductor package according to claim 1, wherein the first cavity and the second cavity are through-cavities that penetrate between one opposing surface and the other of the first substrate and the second substrate, respectively.

6. The semiconductor package according to claim 1, wherein the surface of the first substrate in contact with the second encapsulant is coplane with the surface of the first semiconductor chip in contact with the second encapsulant.

7. A third substrate is disposed on the second substrate and has a third cavity, A third semiconductor chip having a third connection pad that is at least partially located in the third cavity and is positioned toward the second substrate, A third encapsulating material is disposed between the second substrate and the third substrate, covering at least a portion of the third semiconductor chip and filling at least a portion of the third cavity, The semiconductor package according to claim 1, further comprising: a first substrate; a second substrate; a first encapsulant; a second encapsulant; and a third encapsulant; a third connection via that penetrates the first substrate and the second encapsulant and is directly connected to the third connection pad, and connects the third connection pad to the redistribution layer.

8. The aforementioned third connection via is A third-first connecting via penetrates the second substrate, the second sealing material, and the third sealing material, and is directly connected to the third connecting pad, The semiconductor package according to claim 7, comprising: a first substrate and a first encapsulant, and a third-second connecting via that penetrates the third-first connecting via and connects the third-first connecting via to the redistribution layer.

9. The semiconductor package according to claim 8, wherein, in cross-section, the width of the end of the third-first connecting via connected to the third-second connecting via is wider than the width of the end of the third-second connecting via connected to the third-first connecting via.

10. A fourth substrate is disposed on the third substrate and has a fourth cavity, A fourth semiconductor chip having a fourth connection pad that is at least partially located in the fourth cavity and is positioned toward the third substrate, A fourth encapsulating material is disposed between the third substrate and the fourth substrate, covering at least a portion of the fourth semiconductor chip and filling at least a portion of the fourth cavity, The semiconductor package according to claim 7, further comprising: a first substrate, a second substrate, a third substrate, a first encapsulant, a second encapsulant, a third encapsulant, and a fourth encapsulant, a fourth connection via that penetrates these substrates and is directly connected to a fourth connection pad, and connects the fourth connection pad to the redistribution layer.

11. The fourth connection via is A fourth-first connecting via penetrates the third substrate, the third sealing material, and the fourth sealing material, and is directly connected to the fourth connecting pad, A fourth-second connecting via penetrates the second substrate and the second sealing material and is connected to the fourth-first connecting via, The semiconductor package according to claim 10, comprising a fourth-third connecting via that penetrates the first substrate and the first encapsulant and connects the fourth-second connecting via to the redistribution layer.

12. In cross-section, The width of the end of the 4-1 connecting via connected to the 4-2 connecting via is wider than the width of the end of the 4-2 connecting via connected to the 4-1 connecting via. The semiconductor package according to claim 11, wherein the width of the end of the 4-2 connecting via connected to the 4-3 connecting via is wider than the width of the end of the 4-3 connecting via connected to the 4-2 connecting via.

13. The aforementioned redistribution layer is Multiple insulating layers, A plurality of conductive pattern layers, each disposed within the plurality of insulating layers, The semiconductor package according to claim 1, comprising a plurality of conductive via layers, each disposed within the plurality of insulating layers and each connected to one or more of the plurality of conductive pattern layers.

14. A plurality of electrically connecting metals are arranged on the opposite side of the redistribution layer from the side where the first substrate is located, and are connected to the redistribution layer, A chip package including a system-on-a-chip, further including The semiconductor package according to claim 1, wherein the redistribution layer is disposed on the chip package and connected to the chip package via the plurality of electrically connecting metals.

15. Redistribution layer and A plurality of sealing materials and a plurality of substrates are arranged alternately on the redistribution layer, A plurality of memory dies, each at least partially disposed in a cavity penetrating each of the plurality of substrates, and each at least partially covered by the plurality of sealing materials, A semiconductor package comprising: a plurality of connection vias that each penetrate one or more of the plurality of encapsulating materials and the plurality of substrates, and are solderless connected to each of the plurality of memory dies, and each of the plurality of memory dies is connected to the redistribution layer.

16. The semiconductor package according to claim 15, wherein the plurality of connection vias each have different heights.

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