Semiconductor equipment

Abstract

To provide a semiconductor device suitable for uniform heat dissipation and improved mounting reliability. [Solution] The semiconductor device A10 comprises a plurality of leads 10, each having a main surface 101 facing the thickness direction z, and extending in a first direction x perpendicular to the thickness direction, a plurality of electrodes 33 connected to the main surface of each of the plurality of leads, and a sealing resin 40 covering the plurality of leads and the semiconductor element 30. The sealing resin 40 has a bottom surface 42 of the resin on the opposite side of the semiconductor element 30 with respect to the plurality of leads in the thickness direction. The plurality of leads are spaced apart from each other in a second direction perpendicular to the thickness direction z and the first direction. Each of the plurality of leads has a first back surface 102, a second back surface 103, and a concave surface 104 facing the opposite side of the main surface of each lead in the thickness direction. The first back surface and the second back surface are separated in the first direction by the concave surface and are exposed from the bottom surface of the resin, and the concave surface is covered by the sealing resin.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices.

Background Art

[0002] As one of the package forms of semiconductor devices, QFN (Quad For Non-Lead Package) is known. Patent Document 1 discloses an example of a QFN-type semiconductor device.

[0003] The semiconductor device has a plurality of leads, and the end surfaces of each lead are exposed so as to be flush with the side surface of the sealing resin (package material). Also, the back surface of each lead is exposed so as to be flush with the bottom surface of the sealing resin. Therefore, compared with a QFP (Quad Flat Package) type in which the leads protrude from the side surface of the sealing resin, the semiconductor device can be miniaturized, and the mounting area on the wiring board can be reduced.

[0004] In the semiconductor device described in Patent Document 1, each lead supports a semiconductor element. As shown in FIG. 4 of the same document, the back surface 102 of each lead 10 extends in a long shape in the x direction and is located directly below the semiconductor element. Therefore, the heat generated from the semiconductor element concentrates directly below the semiconductor element through the lead 10 and is likely to be radiated there. There is concern that the heat radiation from the semiconductor device becomes non-uniform. Also, the back surfaces 102 of each lead 10 are spaced apart from each other in the y direction. When such a semiconductor device is soldered to a wiring board, there is a risk that adjacent back surfaces 102 (that is, leads 10) may be improperly electrically connected. To avoid such a problem, it is necessary to increase the distance between adjacent back surfaces 102. However, this hinders the miniaturization of the semiconductor device.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

[0006] In light of the circumstances described above, one of the objectives of this disclosure is to provide a semiconductor device suitable for uniform heat dissipation and improved mounting reliability. [Means for solving the problem]

[0007] A semiconductor device provided by this disclosure comprises a plurality of first leads, each having a first main surface facing one side in the thickness direction and extending in a first direction perpendicular to the thickness direction; a plurality of first electrodes connected to the first main surface of each of the plurality of first leads; and a sealing resin covering the plurality of first leads and the semiconductor element. The sealing resin has a resin bottom surface in the thickness direction that is on the opposite side of the semiconductor element with respect to the plurality of first leads. The plurality of first leads are spaced apart from each other in a second direction perpendicular to the thickness direction and the first direction. Each of the plurality of first leads has a first back surface, a second back surface, and a first concave surface facing the opposite side of the first main surface of each first lead in the thickness direction, the first back surface and the second back surface are separated in the first direction with the first concave surface in between and exposed from the resin bottom surface, and the first concave surface is covered by the sealing resin. [Effects of the Invention]

[0008] According to the above configuration, the heat dissipation performance of semiconductor elements is improved, and the semiconductor device can be mounted appropriately.

[0009] Other features and advantages of this disclosure will become more apparent from the detailed description below, with reference to the accompanying drawings. [Brief explanation of the drawing]

[0010] [Figure 1]It is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] It is a plan view (through the encapsulating resin) of the semiconductor device shown in FIG. 1. [Figure 3] It is a plan view (through the semiconductor element and the encapsulating resin) of the semiconductor device shown in FIG. 1. [Figure 4] It is a bottom view of the semiconductor device shown in FIG. 1. [Figure 5] It is a front view of the semiconductor device shown in FIG. 1. [Figure 6] It is a rear view of the semiconductor device shown in FIG. 1. [Figure 7] It is a right side view of the semiconductor device shown in FIG. 1. [Figure 8] It is a left side view of the semiconductor device shown in FIG. 1. [Figure 9] It is a partially enlarged view of FIG. 3. [Figure 10] It is a partially enlarged view of FIG. 3. [Figure 11] It is a cross-sectional view taken along line XI-XI of FIG. 3. [Figure 12] It is a cross-sectional view taken along line XII-XII of FIG. 3. [Figure 13] It is a cross-sectional view taken along line XIII-XIII of FIG. 3. [Figure 14] It is a cross-sectional view taken along line XIV-XIV of FIG. 3. [Figure 15] It is a cross-sectional view taken along line XV-XV of FIG. 3. [Figure 16] It is a perspective view showing a semiconductor device according to a second embodiment of the present disclosure. [Figure 17] It is a plan view (through the encapsulating resin) of the semiconductor device shown in FIG. 16. [Figure 18] It is a plan view (through the semiconductor element and the encapsulating resin) of the semiconductor device shown in FIG. 16. [Figure 19] It is a bottom view of the semiconductor device shown in FIG. 16. [Figure 20] It is a front view of the semiconductor device shown in FIG. 16. [Figure 21] It is a rear view of the semiconductor device shown in FIG. 16. [Figure 22] It is a right side view of the semiconductor device shown in FIG. 16. [Figure 23] It is a left side view of the semiconductor device shown in FIG. 16. [Figure 24] It is a cross-sectional view taken along line XXIV-XXIV of FIG. 18. [Figure 25] It is a cross-sectional view taken along line XXV-XXV of FIG. 18. [Figure 26] It is a cross-sectional view taken along line XXVI-XXVI of FIG. 18. [Figure 27] It is a cross-sectional view taken along line XXVII-XXVII of FIG. 18. [Figure 28] It is a cross-sectional view taken along line XXVIII-XXVIII of FIG. 18.

Embodiments for Carrying Out the Invention

[0011] Hereinafter, preferred embodiments of the present disclosure will be specifically described with reference to the drawings.

[0012] In the present disclosure, terms such as "first", "second", "third", etc. are merely used as labels and are not necessarily intended to assign an order to their objects.

[0013] In this disclosure, "object A is formed on object B" and "object A is formed on object B" include, unless otherwise specified, "object A is directly formed on object B" and "object A is formed on object B with another object interposed between object A and object B." Similarly, "object A is located on object B" and "object A is located on object B" include, unless otherwise specified, "object A is directly located on object B" and "object A is located on object B with another object interposed between object A and object B." Similarly, "object A is located on object B" includes, unless otherwise specified, "object A is located on object B in contact with object B" and "object A is located on object B with another object interposed between object A and object B." Furthermore, unless otherwise specified, "object A overlaps with object B when viewed in a certain direction" includes both "object A overlapping with all of object B" and "object A overlapping with a part of object B."

[0014] A semiconductor device A10 according to the first embodiment of this disclosure will be described based on Figures 1 to 15. The semiconductor device A10 comprises a plurality of first leads 10, a plurality of second leads 20, a plurality of third leads 25, a plurality of leads 26, a fourth lead 27, a semiconductor element 30, and a sealing resin 40. As shown in Figure 1, the package type of the semiconductor device A10 is QFN. The semiconductor element 30 is a flip-chip type LSI with a switching circuit 321 and a control circuit 322 configured inside it. In the semiconductor device A10, DC power (voltage) is converted to AC power (voltage) by the switching circuit 321. The semiconductor device A10 is used, for example, as one element in the circuit of a DC / DC converter. For ease of understanding, Figure 2 shows the sealing resin 40 being transparent, and Figure 3 shows the semiconductor element 30 and the sealing resin 40 being transparent. In these figures, the transparent semiconductor element 30 and the sealing resin 40 are shown by dashed lines (double-dotted lines), respectively.

[0015] In describing semiconductor device A10, the thickness direction of the first lead 10 is referred to as the "thickness direction z". One direction perpendicular to the thickness direction z is referred to as the "first direction x". The direction perpendicular to both the thickness direction z and the first direction x is referred to as the "second direction y". As shown in Figures 1 and 2, semiconductor device A10 has a long rectangular shape when viewed in the thickness direction z (also called a "plan view").

[0016] As shown in Figure 2, the multiple first leads 10, multiple second leads 20, multiple third leads 25, multiple leads 26 and fourth leads 27 support the semiconductor element 30 and also form terminals for mounting the semiconductor device A10 onto a wiring board. As shown in Figures 11 to 15, each of the multiple first leads 10, multiple second leads 20, multiple third leads 25, multiple leads 26 and fourth leads 27 is partially covered with sealing resin 40. The multiple first leads 10, multiple second leads 20, multiple third leads 25, multiple leads 26 and fourth leads 27 are all composed of the same lead frame. The material of the lead frame is, for example, copper (Cu) or a copper alloy.

[0017] As shown in Figures 3 and 4, each of the multiple first leads 10 extends in a first direction x. The multiple first leads 10 are arranged at predetermined intervals in a second direction y. Each of the multiple first leads 10 is an input terminal to which DC power (voltage) to be converted in semiconductor device A10 is input. The first lead 10 is the positive terminal (P terminal).

[0018] As shown in Figures 11, 12, and 14, the first lead 10 has a first main surface 101, a first back surface 102, a second back surface 103, a first concave surface 104, a first end surface 105, and a second end surface 106. The first main surface 101 faces one side in the thickness direction z and faces the semiconductor element 30. The first main surface 101 is covered with a sealing resin 40. The semiconductor element 30 is supported on the first main surface 101.

[0019] The first back surface 102, the second back surface 103, and the first concave surface 104 face the opposite side (the other side in the thickness direction z) from the first main surface 101. The first back surface 102 and the second back surface 103 are located apart in the first direction x, with the first concave surface 104 in between, and are exposed from the sealing resin 40. The first concave surface 104 is located closer to one side in the thickness direction z than the first back surface 102 and the second back surface 103, and is closer to the first main surface 101 than the first back surface 102 and the second back surface 103. The first concave surface 104 is covered by the sealing resin 40. The first end surface 105 connects to both the first main surface 101 and the first back surface 102, and faces one side in the first direction x. The second end surface 106 connects to both the first main surface 101 and the second back surface 103, and faces the other side in the first direction x. The first end face 105 and the second end face 106 are exposed from the sealing resin 40.

[0020] As shown in Figures 12 and 14, the first lead 10 includes a first terminal portion 11, a second terminal portion 12, and a first main portion 13. The first terminal portion 11 has a part of the first main surface 101, a first back surface 102, and a first end surface 105, and overlaps with the first back surface 102 when viewed in the thickness direction z. (In other words, the first terminal portion 11 forms a part of the first main surface 101, a first back surface 102, and a first end surface 105.) The second terminal portion 12 has a part of the first main surface 101, a second back surface 103, and a second end surface 106, and overlaps with the second back surface 103 when viewed in the thickness direction z. (In other words, the second terminal portion 12 forms a part of the first main surface 101, a second back surface 103, and a second end surface 106.) The first main portion 13 has a part of the first main surface 101 and a first concave surface 104, and overlaps with the first concave surface 104 when viewed in the thickness direction z. The first terminal portion 11 and the second terminal portion 12 are connected to both ends of the first main portion 13 in the first direction x. As shown in Figure 9, the dimension L1 of the first terminal portion 11 in the second direction y is larger than the dimension L3 of the first main portion 13 in the second direction y. Also, as shown in Figure 10, the dimension L2 of the second terminal portion 12 in the second direction y is larger than the dimension L3 of the first main portion 13 in the second direction y.

[0021] In each of the multiple first leads 10, the first main surface 101 on which the semiconductor element 30 is supported may be plated with, for example, silver (Ag). Furthermore, the first back surface 102, the second back surface 103, the first end surface 105, and the second end surface 106 exposed from the sealing resin 40 may be plated with, for example, tin (Sn). Alternatively, instead of tin plating, multiple metal platings layered in the order of, for example, nickel (Ni), palladium (Pd), and gold (Au) may be used.

[0022] As shown in Figures 3 and 4, each of the multiple second leads 20 extends in the first direction x. In this embodiment, the multiple second leads 20 are arranged at predetermined intervals in the second direction y. Each second lead 20 is positioned between a pair of adjacent first leads 10 in the second direction y. The multiple first leads 10 and the multiple second leads 20 are arranged alternately in the second direction y. Each of the multiple second leads 20 outputs AC power (voltage) converted by a switching circuit 321 configured in the semiconductor element 30.

[0023] As shown in Figures 11 and 13, the second lead 20 has a second main surface 201, a third back surface 202, a second concave surface 203, a third concave surface 204, a fourth concave surface 205 (see also Figure 4), a third end surface 206, and a fourth end surface 207. The second main surface 201 faces the same side as the first main surface 101 of the first lead 10 in the thickness direction z, and faces the semiconductor element 30. The second main surface 201 is covered with a sealing resin 40. The semiconductor element 30 is supported by the second main surface 201.

[0024] The third surface 202, the second concave surface 203, the third concave surface 204, and the fourth concave surface 205 face the opposite side (the other side in the thickness direction z) from the second main surface 201. The second concave surface 203 and the third concave surface 204 are located apart from the third surface 202 in the first direction x. The second concave surface 203 and the third concave surface 204 are located closer to one side in the thickness direction z than the third surface 202, and closer to the second main surface 201 than the third surface 202. The second concave surface 203 and the third concave surface 204 are covered by the sealing resin 40. The third surface 202 is located between the second concave surface 203 and the third concave surface 204 in the first direction x and is exposed from the sealing resin 40. The fourth concave surface 205 is located closer to one side in the thickness direction z than the third back surface 202, and closer to the second main surface 201 than the third back surface 202. The fourth concave surface 205 is covered by the sealing resin 40. The third end surface 206 connects to both the second main surface 201 and the second concave surface 203 and faces one side in the first direction x. The fourth end surface 207 connects to both the second main surface 201 and the third concave surface 204 and faces the other side in the first direction x. The third end surface 206 and the fourth end surface 207 are exposed from the sealing resin 40.

[0025] As shown in Figures 11 and 13, the second lead 20 includes a third terminal portion 21, a second main portion 22, a third main portion 23, and a projection portion 24. The third terminal portion 21 has a part of the second main surface 201 and a third back surface 202, and overlaps with the third back surface 202 when viewed in the thickness direction z. The second main portion 22 has a part of the second main surface 201, a second concave surface 203, and a third end surface 206, and overlaps with the second concave surface 203 when viewed in the thickness direction z. The third main portion 23 has a part of the second main surface 201, a third concave surface 204, and a fourth end surface 207, and overlaps with the third concave surface 204 when viewed in the thickness direction z. The second main portion 22 and the third main portion 23 are connected to both ends of the third terminal portion 21 in the first direction x. As shown in Figure 11, the protruding portion 24 forms a part of the second main surface 201 and the fourth concave surface 205, and protrudes from the third terminal portion 21 in the second direction y. In this embodiment, the protruding portion 24 has two parts that protrude from both ends of the third terminal portion 21 in the second direction y, and is arranged to sandwich the third terminal portion 21 in the second direction y.

[0026] As shown in Figures 3 and 4, the third terminal portion 21 is located in the center of each of the multiple second leads 20 in the first direction x. The third terminal portion 21 does not overlap with either the first terminal portion 11 or the second terminal portion 12 of the multiple first leads 10 when viewed in the second direction y.

[0027] On each of the multiple second leads 20, the second main surface 201 on which the semiconductor element 30 is supported may be plated with silver, for example. Furthermore, the third back surface 202, the third end surface 206, and the fourth end surface 207 exposed from the sealing resin 40 may be plated with tin, for example. Alternatively, instead of tin plating, multiple metal plating layers, such as nickel, palladium, and gold, may be used.

[0028] As shown in Figure 3, the multiple third leads 25 are located on one side in the second direction y of the multiple first leads 10. Each of the multiple third leads 25 is input to, for example, power (voltage) to drive the control circuit 322, or an electrical signal to be transmitted to the control circuit 322. As shown in Figures 3, 4, and 11, each of the multiple third leads 25 has a third main surface 251, a fourth back surface 252, and a fifth end surface 253. The third main surface 251 faces the same side as the first main surface 101 of the first lead 10 in the thickness direction z, and faces the semiconductor element 30. The third main surface 251 is covered with sealing resin 40. The semiconductor element 30 is supported by the third main surface 251. The fourth back surface 252 faces the opposite side (the other side in the thickness direction z) from the third main surface 251. The fourth back surface 252 is exposed from the sealing resin 40. The fifth end face 253 connects to both the third main face 251 and the fourth back surface 252, and faces one side in the second direction y. The fifth end face 253 is exposed from the sealing resin 40. As shown in Figure 8, the multiple fifth end faces 253 on the multiple third leads 25 are arranged at predetermined intervals along the first direction x.

[0029] In each of the multiple third leads 25, the third main surface 251 on which the semiconductor element 30 is supported may be plated with silver, for example. Furthermore, the fourth back surface 252 and the fifth end surface 253 exposed from the sealing resin 40 may be plated with tin, for example. Alternatively, instead of tin plating, multiple metal platings, such as nickel, palladium, and gold, layered in that order, may be used.

[0030] As shown in Figure 3, the multiple leads 26 are located between the multiple first leads 10 and the multiple third leads 25 in the second direction y. Some of the multiple leads 26 are spaced apart from each other in the first direction x. Each of the multiple leads 26 is input to, for example, a control circuit 322. As shown in Figures 3, 4, and 15, each of the multiple leads 26 has a main surface 261, a back surface 262, and an end surface 263. The main surface 261 faces the same side as the first main surface 101 of the first lead 10 in the thickness direction z and faces the semiconductor element 30. The main surface 261 is covered with a sealing resin 40. The semiconductor element 30 is supported by the main surface 261. The back surface 262 faces the opposite side from the main surface 261 (the other side in the thickness direction z). The back surface 262 is exposed from the sealing resin 40. The end face 263 connects to both the main surface 261 and the back surface 262, and faces either one or the other side of the second direction y. The end face 263 is exposed from the sealing resin 40. As shown in Figures 5 and 6, the end face 263 is aligned along the second direction y together with the first end face 105 (second end face 106) of the first lead 10 and the third end face 206 (fourth end face 207) of the second lead 20.

[0031] On each of the multiple leads 26, the main surface 261 on which the semiconductor element 30 is supported may be plated with silver, for example. Furthermore, the back surface 262 and end surface 263 exposed from the sealing resin 40 may be plated with tin, for example. Alternatively, instead of tin plating, multiple metal platings, such as nickel, palladium, and gold, may be used.

[0032] As shown in Figure 3, the fourth lead 27 is located on the other side of the second direction y from the multiple first leads 10. The fourth lead 27 is an input terminal to which DC power (voltage) to be converted is input in the semiconductor device A10. The fourth lead 27 is the negative terminal (N terminal).

[0033] As shown in Figures 3, 4, and 11, the fourth lead 27 has a fourth main surface 271, a fifth back surface 272, a fifth concave surface 273, and a plurality of sixth end surfaces 274. The fourth main surface 271 faces the same side as the first main surface 101 of the first lead 10 in the thickness direction z, and faces the semiconductor element 30. The fourth main surface 271 and the fifth back surface 272 are covered with sealing resin 40. The semiconductor element 30 is supported by the fourth main surface 271.

[0034] The fifth back surface 272 and the fifth concave surface 273 face the opposite side (the other side in the thickness direction z) from the fourth main surface 271. In this embodiment, the fifth back surface 272 is divided into multiple regions spaced apart from each other in the first direction x. The fifth concave surface 273 is located on the fourth lead 27, closer to one side in the second direction y. The fifth concave surface 273 is closer to the fourth main surface 271 than the fifth back surface 272. The fifth concave surface 273 is covered by the sealing resin 40. Each of the plurality of sixth end surfaces 274 connects to both the fourth main surface 271 and the fifth back surface 272 and faces the other side in the second direction y. The sixth end surfaces 274 are exposed from the sealing resin 40. As shown in Figure 7, the plurality of sixth end surfaces 274 are arranged at predetermined intervals along the first direction x.

[0035] As shown in Figures 3, 4, and 11, the fourth lead 27 includes a fourth main portion 28 and a plurality of fourth terminal portions 29. The fourth main portion 28 has a portion of a fourth main surface 271 and a fifth concave surface 273 and extends in a first direction x. Each of the plurality of fourth terminal portions 29 projects from the fourth main portion 28 to the other side in a second direction y. The plurality of fourth terminal portions 29 are spaced apart. Each fourth terminal portion 29 has a portion of a fourth main surface 271, a portion of a fifth back surface 272 and a sixth end surface 274.

[0036] In the fourth lead 27, the fourth main surface 271 on which the semiconductor element 30 is supported may be plated with silver, for example. Furthermore, the fifth back surface 272 and the multiple sixth end faces 274 exposed from the sealing resin 40 may be plated with tin, for example. Alternatively, instead of tin plating, multiple metal platings, such as nickel, palladium, and gold, layered in that order may be used.

[0037] As shown in Figures 11 to 15, the semiconductor element 30 is supported by multiple first leads 10, multiple second leads 20, multiple third leads 25, multiple leads 26, and multiple fourth leads 27. The semiconductor element 30 is covered with a sealing resin 40. The semiconductor element 30 has a semiconductor substrate 31, a semiconductor layer 32, multiple first electrodes 33, multiple second electrodes 34, multiple third electrodes 35, and multiple fourth electrodes 36.

[0038] As shown in Figures 11 to 15, the semiconductor substrate 31 supports a semiconductor layer 32, a plurality of first electrodes 33, a plurality of second electrodes 34, a plurality of third electrodes 35, and a plurality of fourth electrodes 36 below it. The constituent material of the semiconductor substrate 31 is, for example, Si (silicon) or silicon carbide (SiC).

[0039] The semiconductor layer 32 is laminated on the semiconductor substrate 31 on the side facing the first main surface 101 of the first lead 10 in the thickness direction z. The semiconductor layer 32 includes multiple types of p-type and n-type semiconductors based on differences in the amount of doped elements. The semiconductor layer 32 comprises a switching circuit 321 and a control circuit 322 that conducts to the switching circuit 321. The switching circuit 321 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). In the example shown in semiconductor device A10, the switching circuit 321 is divided into two regions: a high-voltage region (upper arm circuit) and a low-voltage region (lower arm circuit). Each region is composed of one n-channel type MOSFET. The control circuit 322 comprises a gate driver for driving the switching circuit 321, a bootstrap circuit corresponding to the high-voltage region of the switching circuit 321, and controls the switching circuit 321 to drive it normally. Furthermore, the semiconductor layer 32 is further configured with a wiring layer (not shown). This wiring layer provides electrical conductivity between the switching circuit 321 and the control circuit 322.

[0040] As shown in Figures 11 to 15, the multiple first electrodes 33, multiple second electrodes 34, multiple third electrodes 35, and multiple fourth electrodes 36 are provided on the side of the first lead 10 facing the first main surface 101 in the thickness direction z. The multiple first electrodes 33, multiple second electrodes 34, multiple third electrodes 35, and multiple fourth electrodes 36 are in contact with the semiconductor layer 32.

[0041] Multiple first electrodes 33, multiple second electrodes 34, and multiple fourth electrodes 36 are conductive to the switching circuit 321 of the semiconductor layer 32. Multiple first electrodes 33 are connected to the first main surface 101 of multiple first leads 10. As a result, multiple first leads 10 are conductive to the switching circuit 321. Multiple second electrodes 34 are connected to the second main surface 201 of multiple second leads 20. As a result, multiple second leads 20 are conductive to the switching circuit 321. As shown in Figures 3, 11, 13, etc., in this embodiment, at least one second electrode 34 overlaps with the third terminal portion 21 when viewed in the thickness direction z. In the illustrated example, three second electrodes 34 overlap with the third terminal portion 21 when viewed in the thickness direction z. Multiple fourth electrodes 36 are connected to the fourth main surface 271 of the fourth lead 27. As a result, the fourth lead 27 is conductive to the switching circuit 321.

[0042] Multiple third electrodes 35 are electrically connected to the control circuit 322 of the semiconductor layer 32. In addition, some of the multiple third electrodes 35 are connected to the third main surface 251 of the multiple third leads 25. The remaining third electrodes 35 are connected to the main surface 261 of the multiple leads 26. As a result, the multiple third leads 25 and the multiple leads 26 are electrically connected to the control circuit 322. The constituent materials of the multiple first electrodes 33, multiple second electrodes 34, multiple third electrodes 35 and multiple fourth electrodes 36 include, for example, copper.

[0043] As shown in Figures 5 to 8, the sealing resin 40 has a top surface 41, a bottom surface 42, a first (resin) side surface 431, a second (resin) side surface 432, a third (resin) side surface 433, and a fourth (resin) side surface 434. The constituent material of the sealing resin 40 is, for example, black epoxy resin.

[0044] As shown in Figures 11 to 15, the top surface 41 faces the same side as the first main surface 101 of the first lead 10 in the thickness direction z. As shown in Figures 5 to 8, the bottom surface 42 faces the opposite side from the top surface 41. As shown in Figures 4 and 11 to 15, the first back surfaces 102 and 2 back surfaces 103 of the multiple first leads 10, the third back surface 202 of the multiple second leads 20, the fourth back surface 252 of the multiple third leads 25, the back surface 262 of the multiple leads 26, and the fifth back surface 272 of the fourth lead 27 are exposed from the bottom surface 42.

[0045] As shown in Figures 7 and 8, the first side surface 431 is connected to both the top surface 41 and the bottom surface 42 and faces one side in the first direction x. The second side surface 432 is connected to both the top surface 41 and the bottom surface 42 and faces the other side in the first direction x. The first side surface 431 and the second side surface 432 are spaced apart from each other in the first direction x. As shown in Figures 12 to 15, the first end faces 105 of the multiple first leads 10, the third end faces 206 of the multiple second leads 20, and the end faces 263 of some of the leads 26 are exposed from the first side surface 431 in a flush manner with the first side surface 431. Also, the second end faces 106 of the multiple first leads 10, the fourth end faces 207 of the multiple second leads 20, and the end faces 263 of some of the leads 26 are exposed from the second side surface 432 in a flush manner with the second side surface 432.

[0046] As shown in Figures 5 and 6, the third side surface 433 is connected to the top surface 41, the bottom surface 42, and the first side surfaces 431 and 432, and faces one side in the second direction y. The fourth side surface 434 is connected to the top surface 41, the bottom surface 42, and the first side surfaces 431 and 432, and faces the other side in the second direction y. The third side surface 433 and the fourth side surface 434 are spaced apart from each other in the second direction y. As shown in Figure 11, the fifth end faces 253 of the multiple third leads 25 are exposed from the third side surface 433 so as to be flush with the third side surface 433. The sixth end faces 274 of the multiple fourth terminal portions 29 of the fourth lead 27 are exposed from the fourth side surface 434 so as to be flush with the fourth side surface 434.

[0047] Next, the effects and advantages of this embodiment will be described.

[0048] The semiconductor device A10 comprises a plurality of first leads 10 extending in a first direction x and to which a plurality of first electrodes 33 of a semiconductor element 30 are connected, and a sealing resin 40 covering a portion of the plurality of first leads 10. Each of the plurality of first leads 10 has a first back surface 102, a second back surface 103, and a first concave surface 104 facing away from the first main surface 101 in the thickness direction z. The first back surface 102 and the second back surface 103 are separated by the first concave surface 104 in the first direction x and are exposed from the bottom surface 42 of the sealing resin 40. The first concave surface 104 is covered by the sealing resin 40. The plurality of first leads 10 are arranged at intervals in the second direction y. When the semiconductor device A10 is mounted on a wiring board, the first back surface 102 and the second back surface 103 of the plurality of first leads 10 become the joints with the wiring board. In this embodiment, the multiple first back surfaces 102 and second back surfaces 103 of each of the multiple first leads 10 are distributed in both the first direction x and the second direction y. With this configuration, the heat generated by the semiconductor element 30 can be more effectively dispersed and dissipated. Therefore, the semiconductor device A10 can dissipate the heat from the semiconductor element 30 more uniformly. In addition, the multiple first back surfaces 102 and second back surfaces 103 serve as junctions when mounted on the wiring board. This increases the number of junctions and improves mounting reliability.

[0049] The semiconductor device A10 includes a second lead 20 extending in a first direction x. The second lead 20 has a second main surface 201 to which multiple second electrodes 34 of the semiconductor element 30 are connected, and a third back surface 202, a second concave surface 203, and a third concave surface 204 that face away from the second main surface 201 in the thickness direction z. The second concave surface 203 and the third concave surface 204 are separated in the first direction x with the third back surface 202 in between. The third back surface 202 is exposed from the bottom surface 42 of the sealing resin 40. When the semiconductor device A10 is mounted on a wiring board, the third back surface 202 of the second lead 20 becomes the joint with the wiring board. The third back surface 202 is located midway along the first direction x of the second lead 20 extending in the first direction x. With this configuration, the second concave surface 203 of the second lead 20 can be prevented from coming into close proximity with the first back surface 102 and the second back surface 103 of the multiple first leads 10, while improving mounting reliability.

[0050] As shown in Figures 3 and 4, in this embodiment, the second lead 20 is positioned between a pair of adjacent first leads 10 in the second direction y. The semiconductor device A10 has a plurality of second leads 20, and the plurality of first leads 10 and plurality of second leads 20 are arranged alternately in the second direction y. With this configuration, it is prevented that the first back surfaces 102 or the second back surfaces 103 of adjacent pairs of first leads 10 are in close proximity to each other. Also, it is prevented that the first back surface 102 or the second back surface 103 of adjacent first leads 10 and second leads 20 are in close proximity to the third back surface 202. Therefore, a larger number of first back surfaces 102, second back surfaces 103, and third back surfaces 202 can be efficiently arranged. This is more preferable in terms of improving the heat dissipation and mounting reliability of the semiconductor device A10.

[0051] The first lead 10 includes a first terminal portion 11 having a first back surface 102 and a second terminal portion 12 having a second back surface 103. The second lead 20 includes a third terminal portion 21 having a third back surface 202. The third terminal portion 21 of the second lead 20 does not overlap with any of the first terminal portions 11 and second terminal portions 12 of the multiple first leads 10 when viewed in the second direction y. With this configuration, the proximity of the first back surface 102 or second back surface 103 to the third back surface 202 of adjacent first leads 10 and second leads 20 is more reliably prevented.

[0052] The first lead 10 includes a first main portion 13 having a first concave surface 104. The dimensions L1 and L2 of the first terminal portion 11 and the second terminal portion 12 in the second direction y are larger than the dimension L3 of the first main portion 13 in the second direction y. With this configuration, the arrangement pitch of adjacent first leads 10 with the second lead 20 in between in the second direction y can be reduced. This is preferable for miniaturizing the semiconductor device A10.

[0053] With respect to the second electrode 34 connected to the second main surface 201 of the second lead 20, at least one of the second electrodes 34 overlaps with the third terminal portion 21 when viewed in the thickness direction z. With this configuration, the semiconductor element 30 can be supported by the third terminal portion 21, and the supported state of the semiconductor element 30 becomes stable.

[0054] The second lead 20 includes a projection 24 that protrudes from the third terminal portion 21 in the second direction y. The projection 24 forms a part of the second main surface 201 and a fourth concave surface 205 that faces away from the second main surface 201. The fourth concave surface 205 is covered with sealing resin 40. With this configuration, which includes a projection 24 connected to the third terminal portion 21, the second lead 20 can be prevented from coming out of the bottom surface 42, and the connection state of the multiple second electrodes 34 connected to the second main surface 201 can be properly maintained.

[0055] A semiconductor device A20 according to the second embodiment of this disclosure will be described based on Figures 16 to 28. In the drawings from Figure 16 onward, elements that are the same as or similar to those in the semiconductor device A10 of the above embodiment are denoted by the same reference numerals as in the above embodiment, and their descriptions are omitted as appropriate. In the description of the components of the semiconductor device A20, in order to avoid confusion with the components of the semiconductor device A10 described above, for example, the first "lead" mentioned is referred to as the "fifth lead" instead of the "first lead." The same applies to other components.

[0056] The semiconductor device A20 comprises a plurality of fifth leads 50, leads 54, a sixth lead 60, a pair of seventh leads 70, a plurality of leads 80, a semiconductor element 30, and a sealing resin 40. As shown in Figure 16, the package type of the semiconductor device A20 is QFN. The semiconductor element 30 is a flip-chip type LSI with a switching circuit 321 and a control circuit 322 configured inside. In the semiconductor device A20, DC power (voltage) is converted to AC power (voltage) by the switching circuit 321. The semiconductor device A20 is used, for example, as one element in the circuit of a DC / DC converter. For ease of understanding, Figure 17 shows the sealing resin 40 being transparent, and Figure 18 shows the semiconductor element 30 and the sealing resin 40 being transparent. In these figures, the transparent semiconductor element 30 and the sealing resin 40 are shown by dashed lines (double dotted lines), respectively.

[0057] In describing semiconductor device A20, the thickness direction of the fifth lead 50 is referred to as the "thickness direction z". One direction perpendicular to the thickness direction z is referred to as the "first direction x". The direction perpendicular to both the thickness direction z and the first direction x is referred to as the "second direction y". As shown in Figures 16 and 17, semiconductor device A20 is square in shape when viewed in the thickness direction z.

[0058] As shown in Figure 17, the multiple fifth leads 50, lead 54, sixth lead 60, a pair of seventh leads 70, and multiple leads 80 support the semiconductor element 30 and form terminals for mounting the semiconductor device A20 onto a wiring board. As shown in Figures 23 to 28, each of the multiple first leads 10, multiple second leads 20, multiple third leads 25, multiple leads 26, and fourth leads 27 is partially covered with sealing resin 40. The multiple fifth leads 50, lead 54, sixth lead 60, a pair of seventh leads 70, and multiple leads 80 are all made from the same lead frame. The material of the lead frame is, for example, copper or a copper alloy.

[0059] As shown in Figures 18 and 19, the multiple fifth leads 50 are arranged on one side and the other side of the second direction y in the semiconductor device A20. In this embodiment, two (a pair) of fifth leads 50 are arranged on one side of the second direction y, and the other two (a pair) of fifth leads 50 are arranged on the other side of the second direction y. In this embodiment, each of the multiple fifth leads 50 extends approximately in the second direction y. The pair of fifth leads 50 located on one side of the second direction y are spaced apart in the first direction x. The pair of fifth leads 50 located on the other side of the second direction y are also spaced apart in the first direction x. Each of the multiple fifth leads 50 outputs AC power (voltage) converted by a switching circuit 321 configured in the semiconductor element 30.

[0060] As shown in Figure 24, the fifth lead 50 has a fifth main surface 501, a sixth back surface 502, a seventh back surface 503, a sixth concave surface 504, and a seventh end surface 505. The seventh end surface 505 faces one side in the thickness direction z and faces the semiconductor element 30. The seventh end surface 505 is covered with a sealing resin 40. The semiconductor element 30 is supported on the fifth main surface 501.

[0061] The sixth back surface 502, the seventh back surface 503, and the sixth concave surface 504 face the opposite side (the other side in the thickness direction z) from the fifth main surface 501. The sixth back surface 502 and the seventh back surface 503 are located apart in the second direction y, with the sixth concave surface 504 in between, and are exposed from the sealing resin 40. The sixth concave surface 504 is located closer to one side in the thickness direction z than the sixth back surface 502 and the seventh back surface 503, and is closer to the fifth main surface 501 than the sixth back surface 502 and the seventh back surface 503. The sixth concave surface 504 is covered by the sealing resin 40. The seventh end surface 505 is connected to both the fifth main surface 501 and the sixth back surface 502, and faces one or the other side in the second direction y. The seventh end surface 505 is exposed from the sealing resin 40.

[0062] As shown in Figure 24, the fifth lead 50 includes a sixth terminal portion 51, a seventh terminal portion 52, and a sixth main portion 53. The sixth terminal portion 51 has a part of the fifth main surface 501, a sixth back surface 502, and a seventh end surface 505, and overlaps with the sixth back surface 502 when viewed in the thickness direction z. The seventh terminal portion 52 has a part of the fifth main surface 501 and a seventh back surface 503, and overlaps with the seventh back surface 503 when viewed in the thickness direction z. The sixth main portion 53 has a part of the fifth main surface 501 and a sixth concave surface 504, and overlaps with the sixth concave surface 504 when viewed in the thickness direction z. The sixth terminal portion 51 and the seventh terminal portion 52 are connected to both ends of the sixth main portion 53 in the second direction y.

[0063] In each of the multiple fifth leads 50, the fifth main surface 501 on which the semiconductor element 30 is supported may be plated with silver, for example. Furthermore, the sixth back surface 502, the seventh back surface 503, and the seventh end surface 505 exposed from the sealing resin 40 may be plated with tin, for example. Alternatively, instead of tin plating, multiple metal platings, such as nickel, palladium, and gold, layered in that order may be used.

[0064] As shown in Figures 18 and 19, lead 54 extends in the second direction y. In this embodiment, lead 54 is located midway along the semiconductor device A20 in the first direction x. Lead 54 is an input terminal to which DC power (voltage) to be converted is input in the semiconductor device A20. Lead 54 is the positive terminal (P terminal).

[0065] As shown in Figure 26, the lead 54 has a main surface 541, a back surface 542, a back surface 543, a concave surface 544, an end surface 545, and an end surface 546. The main surface 541 faces the same side as the fifth main surface 501 of the fifth lead 50 in the thickness direction z, and faces the semiconductor element 30. The main surface 541 is covered with a sealing resin 40. The semiconductor element 30 is supported by the main surface 541.

[0066] The back surfaces 542 and 543 and the concave surface 544 face the opposite side (the other side in the thickness direction z) from the main surface 541. The back surfaces 542 and 543 are located apart in the second direction y, with the concave surface 544 in between, and are exposed from the sealing resin 40. The back surface 542 is located on one side of the second direction y, and the back surface 543 is located on the other side of the second direction y. The concave surface 544 is located closer to one side in the thickness direction z than the back surfaces 542 and 543, and is closer to the main surface 541 than the back surfaces 542 and 543. The concave surface 544 is covered by the sealing resin 40. The end surface 545 connects to both the main surface 541 and the back surface 542 and faces one side in the second direction y. The end surface 546 connects to both the main surface 541 and the back surface 543 and faces the other side in the second direction y. End faces 545 and 546 are exposed from the sealing resin 40.

[0067] In the lead 54, the main surface 541 on which the semiconductor element 30 is supported may be plated with silver, for example. Furthermore, the back surface 542, back surface 543, end surface 545, and end surface 546 exposed from the sealing resin 40 may be plated with tin, for example. Alternatively, instead of tin plating, multiple metal plating layers, such as nickel, palladium, and gold, may be used.

[0068] The sixth lead 60 extends in the second direction y, as shown in Figures 18 and 19. In this embodiment, the sixth lead 60 is located midway along the first direction x of the semiconductor device A20. The sixth lead 60 is an input terminal to which DC power (voltage) to be converted is input in the semiconductor device A20. The sixth lead 60 is the negative terminal (N terminal).

[0069] As shown in Figure 25, the sixth lead 60 has a sixth main surface 601, an eighth back surface 602, an eighth end surface 603, and a ninth end surface 604. The sixth main surface 601 faces the same side as the fifth main surface 501 of the fifth lead 50 in the thickness direction z, and faces the semiconductor element 30. The sixth main surface 601 is covered with sealing resin 40. The semiconductor element 30 is supported by the sixth main surface 601.

[0070] The eighth back surface 602 faces the opposite side (the other side in the thickness direction z) from the sixth main surface 601. The eighth back surface 602 is exposed from the sealing resin 40. In this embodiment, the sixth main surface 601 and the eighth back surface 602 are arranged along the entire length of the semiconductor device A20 in the second direction y. The eighth end surface 603 connects to both the sixth main surface 601 and the eighth back surface 602 and faces one side in the second direction y. The ninth end surface 604 connects to both the sixth main surface 601 and the eighth back surface 602 and faces the other side in the second direction y. The ninth end surface 604 and the ninth end surface 604 are exposed from the sealing resin 40.

[0071] In the sixth lead 60, the sixth main surface 601 on which the semiconductor element 30 is supported may be plated with silver, for example. Furthermore, the eighth back surface 602, the eighth end surface 603, and the ninth end surface 604 exposed from the sealing resin 40 may be plated with tin, for example. Alternatively, instead of tin plating, multiple metal plating layers, such as nickel, palladium, and gold, may be used.

[0072] The pair of seventh leads 70 are positioned midway along the second direction y of the semiconductor device A20, as shown in Figures 18 and 19. Each of the seventh leads 70 extends in the first direction x. One seventh lead 70 is located on one side of the first direction x, and the other seventh lead 70 is located on the other side of the first direction x. Each of the seventh leads 70 is input to, for example, power (voltage) to drive the control circuit 322, or an electrical signal to be transmitted to the control circuit 322.

[0073] As shown in Figure 27, each of the pair of seventh leads 70 has a seventh main surface 701, a ninth back surface 702, and a tenth end surface 703. The seventh main surface 701 faces the same side as the fifth main surface 501 of the fifth lead 50 in the thickness direction z, and faces the semiconductor element 30. The seventh main surface 701 is covered with a sealing resin 40. The semiconductor element 30 is supported by the seventh main surface 701.

[0074] The ninth back surface 702 faces the opposite side (the other side in the thickness direction z) from the seventh main surface 701. The ninth back surface 702 is exposed from the sealing resin 40. The tenth end surface 703 connects to both the seventh main surface 701 and the ninth back surface 702 and faces the first direction x. More specifically, the tenth end surface 703 of one seventh lead 70 faces one side of the first direction x, and the tenth end surface 703 of the other seventh lead 70 faces the other side of the first direction x. The tenth end surface 703 is exposed from the sealing resin 40.

[0075] On each of the pair of seventh leads 70, the seventh main surface 701 on which the semiconductor element 30 is supported may be plated with silver, for example. Furthermore, the ninth back surface 702 and the tenth end surface 703 exposed from the sealing resin 40 may be plated with tin, for example. Alternatively, instead of tin plating, multiple metal platings, such as nickel, palladium, and gold, may be used.

[0076] As shown in Figures 18 and 19, the multiple leads 80 are arranged on one and the other side of the semiconductor device A20 in the first direction x, and on one and the other side of the second direction y (in other words, on the peripheral edge of the semiconductor device A20 when viewed in the thickness direction z). Each of the multiple leads 80 is input to, for example, a control circuit 322. As shown in Figure 28, each of the multiple leads 80 has a main surface 801, a back surface 802, and an end surface 803. The main surface 801 faces the same side as the fifth main surface 501 of the fifth lead 50 in the thickness direction z, and faces the semiconductor element 30. The main surface 801 is covered with sealing resin 40. The semiconductor element 30 is supported by the main surface 801. The back surface 802 faces the opposite side from the main surface 801 (the other side in the thickness direction z). The back surface 802 is exposed from the sealing resin 40. The end face 803 connects to both the main surface 801 and the back surface 802, and faces either one side of the first direction x, the other side of the first direction x, one side of the second direction y, or the other side of the second direction y. The end face 803 is exposed from the sealing resin 40.

[0077] On each of the multiple leads 80, the main surface 801 on which the semiconductor element 30 is supported may be plated with silver, for example. Furthermore, the back surface 802 and end surface 803 exposed from the sealing resin 40 may be plated with tin, for example. Alternatively, instead of tin plating, multiple metal platings, such as nickel, palladium, and gold, layered in that order, may be used.

[0078] As shown in Figures 24 to 28, the semiconductor element 30 is supported by a plurality of fifth leads 50, leads 54, a sixth lead 60, a pair of seventh leads 70, and a plurality of leads 80. The semiconductor element 30 is covered with a sealing resin 40. The semiconductor element 30 has a semiconductor substrate 31, a semiconductor layer 32, a plurality of fifth electrodes 37, a plurality of electrodes 371, a plurality of sixth electrodes 38, a plurality of seventh electrodes 39, and a plurality of electrodes 391.

[0079] As shown in Figures 24 to 28, the semiconductor substrate 31 supports a semiconductor layer 32, a plurality of fifth electrodes 37, a plurality of electrodes 371, a plurality of sixth electrodes 38, a plurality of seventh electrodes 39, and a plurality of electrodes 391 below it. The constituent material of the semiconductor substrate 31 is, for example, Si (silicon) or silicon carbide (SiC).

[0080] The semiconductor layer 32 is laminated on the semiconductor substrate 31 on the side facing the fifth main surface 501 of the fifth lead 50 in the thickness direction z. The semiconductor layer 32 includes multiple types of p-type and n-type semiconductors based on differences in the amount of doped elements. The semiconductor layer 32 comprises a switching circuit 321 and a control circuit 322 that conducts to the switching circuit 321. The switching circuit 321 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). In the example shown in semiconductor device A20, the switching circuit 321 is divided into two regions: a high-voltage region (upper arm circuit) and a low-voltage region (lower arm circuit). Each region is composed of one n-channel type MOSFET. The control circuit 322 comprises a gate driver for driving the switching circuit 321, a bootstrap circuit corresponding to the high-voltage region of the switching circuit 321, and controls the switching circuit 321 to drive it normally. Furthermore, the semiconductor layer 32 is further configured with a wiring layer (not shown). This wiring layer provides electrical conductivity between the switching circuit 321 and the control circuit 322.

[0081] As shown in Figures 24 to 28, the multiple fifth electrodes 37, multiple electrodes 371, multiple sixth electrodes 38, multiple seventh electrodes 39, and multiple electrodes 391 are provided on the side of the fifth lead 50 facing the fifth main surface 501 in the thickness direction z. The multiple fifth electrodes 37, multiple electrodes 371, multiple sixth electrodes 38, multiple seventh electrodes 39, and multiple electrodes 391 are in contact with the semiconductor layer 32.

[0082] Multiple fifth electrodes 37, multiple electrodes 371, and multiple sixth electrodes 38 are conductive to the switching circuit 321 of the semiconductor layer 32. Multiple fifth electrodes 37 are connected to the fifth main surface 501 of multiple fifth leads 50. As a result, multiple fifth leads 50 are conductive to the switching circuit 321. As shown in Figures 18, 24, etc., in this embodiment, when viewed in the thickness direction z, at least one fifth electrode 37 overlaps with the seventh terminal portion 52 (seventh back surface 503). Multiple electrodes 371 are connected to the main surface 541 of the lead 54. As a result, the lead 54 is conductive to the switching circuit 321. Multiple sixth electrodes 38 are connected to the sixth main surface 601 of the sixth lead 60. As a result, the sixth lead 60 is conductive to the switching circuit 321.

[0083] Multiple seventh electrodes 39 and multiple electrodes 391 are electrically connected to the control circuit 322 of the semiconductor layer 32. Multiple seventh electrodes 39 are connected to the seventh main surface 701 of a pair of seventh leads 70. Multiple electrodes 391 are connected to the main surface 801 of multiple leads 80. As a result, the pair of seventh leads 70 and the multiple leads 80 are electrically connected to the control circuit 322. The constituent material of the multiple fifth electrodes 37, multiple electrodes 371, multiple sixth electrodes 38, multiple seventh electrodes 39 and multiple electrodes 391 includes, for example, copper.

[0084] As shown in Figures 17 and 18, the semiconductor element 30 has a rectangular shape when viewed in the thickness direction z. The first element side surface 301 has a second element side surface 302, a third element side surface 303, and a fourth element side surface 304. The first element side surface 301 and the second element side surface 302 are spaced apart from each other in the first direction x. The first element side surface 301 faces one side of the first direction x. The second element side surface 302 faces the other side of the first direction x. The third element side surface 303 and the fourth element side surface 304 are connected to both the first element side surface 301 and the second element side surface 302, respectively. The third element side surface 303 and the fourth element side surface 304 are spaced apart from each other in the second direction y. The third element side surface 303 faces one side of the second direction y. The fourth element side surface 304 faces the other side of the second direction y. In this embodiment, the outer edges of the semiconductor substrate 31 and the semiconductor layer 32, viewed in the thickness direction z, constitute the first element side surface 301, the second element side surface 302, the third element side surface 303, and the fourth element side surface 304.

[0085] In this embodiment, as shown in Figure 18, the region enclosed by the first element side surface 301, the second element side surface 302, the third element side surface 303, and the fourth element side surface 304 is equally divided into two in both the first direction x and the second direction y, defining four divided regions Da. In the thickness direction z, at least one seventh back surface 503 is arranged in each of the four divided regions Da. In the thickness direction z, at least one fifth electrode 37 overlaps the seventh back surface 503 arranged in each divided region Da. Furthermore, in this embodiment, the pair of fifth leads 50 arranged on one side in the second direction y, and the four seventh back surfaces 503 included in the pair of fifth leads 50 arranged on one side in the second direction y, are arranged in different divided regions Da in the thickness direction z.

[0086] The sixth lead 60 is located in the first direction x between a pair of seventh back surfaces 503 located on one side of the first direction x and a pair of seventh back surfaces 503 located on the other side of the first direction x, among the four seventh back surfaces 503 arranged in the four divided regions Da.

[0087] Each of the four seventh back surfaces 503 arranged in the four divided regions Da extends elongated in the second direction y. Of the four seventh back surfaces 503 arranged in the four divided regions Da, a pair of seventh back surfaces 503 located on one side of the first direction x and a pair of seventh back surfaces 503 located on the other side of the first direction x overlap each other when viewed in the second direction y. In other words, the four seventh back surfaces 503 arranged in the four divided regions Da are arranged symmetrically with respect to a certain straight line (center line) extending parallel to the first direction x, and are also arranged symmetrically with respect to a certain straight line (center line) extending parallel to the second direction y.

[0088] As shown in Figures 20 to 23, the sealing resin 40 has a top surface 41, a bottom surface 42, a first side surface 431, a second side surface 432, a third side surface 433, and a fourth side surface 434. The constituent material of the sealing resin 40 is, for example, a black epoxy resin.

[0089] As shown in Figures 24 to 28, the top surface 41 faces the same side as the fifth main surface 501 of the fifth lead 50 in the thickness direction z. As shown in Figures 20 to 23, the bottom surface 42 faces the opposite side from the top surface 41. As shown in Figures 19 and 24 to 28, the sixth back surface 502 and seventh back surface 503 of the multiple fifth leads 50, the back surfaces 542 and 543 of the lead 54, the eighth back surface 602 of the sixth lead 60, the ninth back surface 702 of the pair of seventh leads 70, and the back surface 802 of the multiple leads 80 are exposed from the bottom surface 42.

[0090] As shown in Figures 22 and 23, the first side surface 431 connects to both the top surface 41 and the bottom surface 42 and faces one side in the first direction x. The second side surface 432 connects to both the top surface 41 and the bottom surface 42 and faces the other side in the first direction x. The first side surface 431 and the second side surface 432 are spaced apart from each other in the first direction x. As shown in Figures 27 and 28, the 10th end face 703 of one of the seventh leads 70 and the end faces 803 of some of the multiple leads 80 are exposed from the first side surface 431 in a flush manner with the first side surface 431. Also, the 10th end face 703 of the other seventh lead 70 and the end faces 803 of some of the multiple leads 80 are exposed from the second side surface 432 in a flush manner with the second side surface 432.

[0091] As shown in Figures 20 and 21, the third side surface 433 is connected to the top surface 41, the bottom surface 42, and the first side surfaces 431 and 432, and faces one side in the second direction y. The fourth side surface 434 is connected to the top surface 41, the bottom surface 42, and the first side surfaces 431 and 432, and faces the other side in the second direction y. The third side surface 433 and the fourth side surface 434 are spaced apart from each other in the second direction y. As shown in Figures 24 to 26, the seventh end face 505 of some of the fifth leads 50, the end face 545 of the lead 54, and the eighth end face 603 of the sixth lead 60 are exposed from the third side surface 433 so as to be flush with the third side surface 433. From the fourth side surface 434, the seventh end face 505 of some of the fifth leads 50, the end face 546 of lead 54, and the ninth end face 604 of the sixth lead 60 are exposed so as to be flush with the fourth side surface 434.

[0092] Next, the effects and advantages of this embodiment will be described.

[0093] The semiconductor device A20 comprises a plurality of fifth leads 50 to which a plurality of fifth electrodes 37 are connected, and a sealing resin 40 that covers a portion of the plurality of fifth leads 50. Each of the plurality of fifth leads 50 has a sixth back surface 502, a seventh back surface 503, and a sixth concave surface 504 that face away from the fifth main surface 501 in the thickness direction z. The sixth back surface 502 and the seventh back surface 503 are separated in the second direction y with the sixth concave surface 504 in between, and are exposed from the bottom surface 42 of the sealing resin 40. The sixth concave surface 504 is covered by the sealing resin 40. The seventh end surface 505 is connected to both the fifth main surface 501 and the sixth back surface 502, and is exposed from the sealing resin 40 so as to be flush with either the third side surface 433 or the fourth side surface 434 of the sealing resin 40. As a result, the fifth lead 50 includes a sixth terminal portion 51 located at the end (third side surface 433 or fourth side surface 434) in the second direction y of the sealing resin 40 and having a sixth back surface 502, and a seventh terminal portion 52 located inside the semiconductor device A20 in the second direction y from the sixth terminal portion 51 and having a seventh back surface 503. With this configuration, the semiconductor element 30 is prevented from being cantilevered by the fifth lead 50 via a plurality of fifth electrodes 37, and the semiconductor element 30 is stably supported by the plurality of fifth leads 50.

[0094] In this embodiment, the region enclosed by the first element side surface 301, the second element side surface 302, the third element side surface 303, and the fourth element side surface 304 of the semiconductor element 30 is equally divided into two in both the first direction x and the second direction y, defining four divided regions Da. In the thickness direction z, at least one seventh back surface 503 is arranged in each of the four divided regions Da. With this configuration, a seventh terminal portion 52 having the seventh back surface 503 is arranged in each divided region Da. Therefore, the semiconductor element 30 can be supported stably and in a balanced manner.

[0095] Viewed in the thickness direction z, the seventh back surface 503 located in each divided region Da overlaps with at least one fifth electrode 37. With this configuration, the semiconductor element 30 is directly supported by the seventh terminal portion 52 having the seventh back surface 503 via multiple fifth electrodes 37. This makes the support state of the semiconductor element 30 more stable.

[0096] The semiconductor device A20 includes a sixth lead 60 that extends in a second direction y and to which a plurality of sixth electrodes 38 are connected. The sixth lead 60 has a sixth main surface 601, an eighth back surface 602, an eighth end surface 603, and a ninth end surface 604. The eighth end surface 603 connects to both the sixth main surface 601 and the eighth back surface 602 and faces one side of the second direction y. The ninth end surface 604 connects to both the sixth main surface 601 and the eighth back surface 602 and faces the other side of the second direction y. The sixth main surface 601 and the eighth back surface 602 are arranged along the entire length of the semiconductor device A20 in the second direction y. With this configuration, the area of ​​the eighth back surface 602 can be made relatively large, which can improve the heat dissipation of the semiconductor element 30 and the mounting reliability.

[0097] The sixth lead 60 is located in the middle of the semiconductor device A20 in the first direction x. More specifically, in the first direction x, the sixth lead 60 is located between a pair of seventh back surfaces 503 located on one side of the first direction x and a pair of seventh back surfaces 503 located on the other side of the first direction x, among the four seventh back surfaces 503 arranged in four divided regions Da. With this configuration, the semiconductor device 30 can be supported by the four fifth leads 50, each having four seventh back surfaces 503 arranged in the four divided regions Da, and the sixth lead 60 located in the middle of the semiconductor device A20 in the first direction x. Therefore, the support state of the semiconductor device 30 becomes even more stable.

[0098] The semiconductor device A20 includes a pair of seventh leads 70 that extend in a first direction x and to which a plurality of seventh electrodes 39 are connected. The semiconductor device A20 is positioned in the middle in a second direction y. More specifically, of the pair of seventh leads 70, one seventh lead 70 is located on one side of the first direction x, and the other seventh lead 70 is located on the other side of the first direction x. As shown in Figures 18 and 19, the pair of seventh leads 70 are positioned in the second direction y between a pair of seventh back surfaces 503 located on one side of the second direction y and a pair of seventh back surfaces 503 located on the other side of the second direction y, among the four seventh back surfaces 503 arranged in four divided regions Da. With this configuration, the four seventh back surfaces 503 (seventh terminal portions 52), the sixth lead 60, and the pair of seventh leads 70 are arranged in a balanced manner with bias suppressed. Therefore, the semiconductor element 30 can be supported more stably.

[0099] The semiconductor device relating to this disclosure is not limited to the embodiments described above. The specific configuration of each part of the semiconductor device relating to this disclosure can be modified in various ways.

[0100] This disclosure includes embodiments described in the following appendix.

[0101] Note 1. Each has a first main surface facing one side in the thickness direction, and a plurality of first leads extending in a first direction perpendicular to the thickness direction, A semiconductor element having a plurality of first electrodes connected to the first main surface of each of the plurality of first leads, The system comprises the plurality of first leads and a sealing resin covering the semiconductor element, The sealing resin has a resin bottom surface on the opposite side of the semiconductor element, with respect to the plurality of first leads in the thickness direction. The plurality of first leads are spaced apart from each other in a second direction perpendicular to the thickness direction and the first direction. Each of the plurality of first leads has a first back surface, a second back surface, and a first concave surface facing away from the first main surface of each first lead in the thickness direction, the first back surface and the second back surface are separated in the first direction with the first concave surface in between and exposed from the resin bottom surface, and the first concave surface is covered by the sealing resin, a semiconductor device. Note 2. It further comprises having a second main surface and at least one second lead extending in the first direction, The second lead is at least partially covered by the sealing resin, The semiconductor element has a plurality of second electrodes connected to the second main surface, The second lead has a third back surface, a second concave surface, and a third concave surface on the side opposite to the second main surface in the thickness direction, The third back surface is exposed from the resin bottom surface, The semiconductor device according to Appendix 1, wherein the second concave surface and the third concave surface are separated in the first direction, with the third back surface in between, and are covered by the sealing resin. Note 3. The semiconductor device according to Appendix 2, wherein the plurality of first leads include two adjacent first leads that sandwich the second lead in the second direction. Note 4. The at least one second lead is a plurality of second leads spaced apart from each other in the second direction, The semiconductor device according to Appendix 3, wherein the plurality of first leads and the plurality of second leads are arranged alternately in the second direction. Note 5. Each of the plurality of first leads includes a first terminal portion that forms a part of the first main surface and the first back surface of each first lead, and a second terminal portion that forms a part of the first main surface and the second back surface of each first lead. The semiconductor device according to Appendix 4, wherein each of the plurality of second leads includes a third terminal portion that forms a part of the second main surface and the third back surface of each second lead. Note 6. The semiconductor device according to Appendix 5, wherein the third terminal portion of each of the plurality of second leads does not overlap with either the first terminal portion or the second terminal portion of each of the plurality of first leads when viewed in the second direction. Note 7. The semiconductor device according to Appendix 6, wherein, viewed in the thickness direction, at least one of the plurality of second electrodes overlaps with the third terminal portion of one of the plurality of second leads. Note 8. Each of the plurality of second leads includes a projection that protrudes in the second direction from the third terminal portion of each second lead, the projection forming a part of the second main surface of each second lead and a fourth concave surface facing the opposite side from the second main surface, the fourth concave surface being covered with the sealing resin, as described in Appendix 7. Note 9. Each of the plurality of first leads includes a first main portion that forms a part of the first main surface and the first concave surface of each first lead and overlaps with the first concave surface when viewed in the thickness direction. The semiconductor device according to any one of appendices 6 to 8, wherein in each of the first leads, the dimensions of the first terminal portion and the second terminal portion in the second direction are larger than the dimensions of the first main portion in the second direction. Note 10. Each of the plurality of first leads has a first end face connected to the first main surface and the first back surface of the first lead and facing one side in the first direction, and a second end face connected to the first main surface and the second back surface and facing the other side in the first direction. Each of the plurality of second leads has a third end face connected to the second main surface and the second concave surface of the second lead and facing one side in the first direction, and a fourth end face connected to the second main surface and the third concave surface and facing the other side in the first direction. The sealing resin has a first resin side surface and a second resin side surface that are connected to the bottom surface of the resin and are spaced apart from each other in the first direction, and facing one side and the other side in the first direction, respectively. A semiconductor device according to any one of appendices 4 to 9, wherein the first end face and the third end face are exposed from the first resin side surface so as to be flush with the first resin side surface, and the second end face and the fourth end face are exposed from the second resin side surface so as to be flush with the second resin side surface. Note 11. Each has a third main surface and a fourth back surface that face opposite each other in the thickness direction, and further comprises a plurality of third leads located on one side in the second direction from the plurality of first leads, At least a portion of each of the plurality of third leads is covered with the sealing resin. The semiconductor device according to Appendix 10, wherein the semiconductor element has a plurality of third electrodes, and at least one of the plurality of third electrodes is connected to the third main surface of one of the plurality of third leads. Note 12. Each of the plurality of third leads has a fifth end face that is connected to the third main surface and the fourth back surface of each third lead and faces one side in the second direction. The sealing resin has a third resin side surface and a fourth resin side surface that are connected to the resin bottom surface, the first resin side surface and the second resin side surface, and are spaced apart from each other in the second direction. The fourth back surface of each of the plurality of third leads is exposed from the resin bottom surface, The semiconductor device according to Appendix 11, wherein the fifth end face of each of the plurality of third leads is exposed from the third resin side surface so as to be flush with the third resin side surface. Note 13. The present invention further comprises a fourth lead having a fourth main surface and a fifth back surface facing opposite directions in the thickness direction, and a fourth lead located on the other side in the second direction from the plurality of first leads, At least a portion of the fourth lead is covered with the sealing resin, The fifth back surface is exposed from the resin bottom surface, The semiconductor device is the semiconductor device described in Appendix 12, wherein the semiconductor element has a plurality of fourth electrodes connected to the fourth main surface. Note 14. The fourth lead includes a fourth main portion and a plurality of fourth terminal portions, the fourth main portion forming a part of the fourth main surface and a fifth concave surface facing the opposite side of the fourth main surface and extending in the first direction, the plurality of fourth terminal portions are spaced apart from each other in the first direction, each of the plurality of fourth terminal portions protruding from the fourth main portion to the other side in the second direction and forming a part of the fourth main surface and a part of the fifth back surface, The fifth concave surface is covered with the sealing resin. Each of the plurality of fourth terminal portions has a sixth end face that connects to the fourth main surface and the fifth back surface and faces the other side in the second direction. The semiconductor device according to Appendix 13, wherein the sixth end face of each of the plurality of fourth terminal portions is exposed from the fourth resin side surface so as to be flush with the fourth resin side surface. Note 15. The semiconductor element includes a semiconductor substrate and a semiconductor layer stacked on the semiconductor substrate, and the semiconductor layer comprises a switching circuit and a control circuit that conducts to the switching circuit. The semiconductor device according to Appendix 13 or 14, wherein the plurality of first electrodes, the plurality of second electrodes, and the plurality of fourth electrodes are conductive to the switching circuit, and the plurality of third electrodes are conductive to the control circuit. Note 16. The plurality of first leads and the fourth lead are input terminals to which DC power to be converted is input. The semiconductor device described in Appendix 15, wherein the plurality of second leads are output terminals to which AC power converted by the switching circuit is output. Note 17. Multiple fifth leads, each having a fifth principal surface facing the thickness direction, A semiconductor element having a plurality of fifth electrodes, wherein the plurality of fifth electrodes are connected to the fifth main surface of each of the plurality of fifth leads, The system comprises the plurality of fifth leads and a sealing resin covering the semiconductor element, The sealing resin has a resin bottom surface on the opposite side of the semiconductor element with respect to the plurality of fifth electrodes in the thickness direction, a first resin side surface and a second resin side surface connected to the resin bottom surface and spaced apart from each other in a first direction perpendicular to the thickness direction, and a third resin side surface and a fourth resin side surface spaced apart from each other in a second direction perpendicular to the thickness direction and the first direction. Each of the plurality of fifth leads has a sixth back surface, a seventh back surface, and a sixth concave surface facing away from the fifth main surface of each fifth lead in the thickness direction, and a seventh end surface facing the second direction, the sixth back surface and the seventh back surface are separated in the second direction with the sixth concave surface in between and exposed from the resin bottom surface, the sixth concave surface is covered by the sealing resin, and the seventh end surface is connected to the fifth main surface and the sixth back surface and exposed from the sealing resin so as to be flush with either the third resin side surface or the fourth resin side surface, a semiconductor device. Note 18. The semiconductor element has a first element side surface and a second element side surface that are spaced apart from each other in the first direction, and a third element side surface and a fourth element side surface that are spaced apart from each other in the second direction and connected to the first element side surface and the second element side surface. The semiconductor device according to Appendix 17, wherein, when viewed in the thickness direction, the region enclosed by the first element side surface, the second element side surface, the third element side surface, and the fourth element side surface is equally divided into two regions in the first and second directions, and at least one of the seventh back surfaces of each of the plurality of fifth leads is disposed in each of these four divided regions. Note 19. The semiconductor device according to Appendix 18, wherein, when viewed in the thickness direction, at least one of the seventh back surfaces located in each of the four divided regions overlaps with at least one of the plurality of fifth electrodes. Note 20. The plurality of fifth leads include a first pair of fifth leads and a second pair of fifth leads, wherein the seventh end face of each of the first pair of fifth leads is flush with the third resin side surface, and the seventh end face of each of the second pair of fifth leads is flush with the fourth resin side surface. The semiconductor device according to Appendix 19, wherein the seventh back surfaces of the fifth leads of the first pair and the fifth leads of the second pair are arranged in the four divided regions when viewed in the thickness direction. Note 21. It has a sixth main surface and an eighth back surface facing opposite directions in the thickness direction, and further comprises a sixth lead extending in the second direction, A portion of the sixth lead is covered by the sealing resin, The semiconductor element has a plurality of sixth electrodes connected to the sixth main surface, The sixth lead connects to the sixth main surface and the eighth back surface, and has an eighth end surface and a ninth end surface facing one side and the other side in the second direction, The eighth end face is exposed from the third resin side surface so as to be flush with the third resin side surface. The semiconductor device according to Appendix 20, wherein the ninth end face is exposed from the fourth resin side surface so as to be flush with the fourth resin side surface. Note 22. The seventh back surfaces, each arranged in the four divided regions, are divided into a first pair of seventh back surfaces and a second pair of seventh back surfaces, and the seventh back surfaces of the first pair are spaced apart from the seventh back surfaces of the second pair in the first direction. The semiconductor device according to Appendix 21, wherein the sixth lead is located between the seventh back surface of the first pair and the seventh back surface of the second pair in the first direction. Note 23. Each of the seven back surfaces, which are arranged in the four divided regions, extends in the second direction. The semiconductor device according to Appendix 21 or 22, wherein the seventh back surface, which is arranged in each of the four divided regions, is arranged symmetrically with respect to a straight line extending parallel to the first direction and symmetrically with respect to a straight line extending parallel to the second direction. Note 24. Each has a seventh main surface and a ninth back surface facing opposite directions in the thickness direction, and further comprises a pair of seventh leads extending in the first direction, The semiconductor element has a plurality of seventh electrodes connected to the seventh main surface of each of the pair of seventh leads, A portion of each of the pair of seventh leads is covered with the sealing resin. Each of the pair of seventh leads has a tenth end face that is connected to the seventh main surface and the ninth back surface of each seventh lead and faces the first direction. The tenth end faces of each of the pair of seventh leads face opposite each other in the first direction. The seventh back surfaces, each positioned in one of the four divided regions, are divided into the seventh back surfaces of the third pair and the seventh back surfaces of the fourth pair, and the seventh back surfaces of the third pair are spaced apart from the seventh back surfaces of the fourth pair in the second direction. The semiconductor device according to Appendix 23, wherein the pair of seventh leads are located between the third pair of seventh back surfaces and the fourth pair of seventh back surfaces in the second direction. Note 25. The semiconductor element comprises a semiconductor substrate and a semiconductor layer stacked on the semiconductor substrate in the thickness direction. The semiconductor layer comprises a switching circuit and a control circuit that conducts to the switching circuit. The plurality of fifth electrodes and the plurality of sixth electrodes are electrically connected to the switching circuit. The semiconductor device described in Appendix 24, wherein the plurality of seventh electrodes are electrically connected to the control circuit. Note 26. The sixth lead is an input terminal to which DC power to be converted is input, The semiconductor device described in Appendix 25, wherein the plurality of fifth leads are output terminals to which AC power converted by the switching circuit is output. [Explanation of symbols]

[0102] A10, A20: Semiconductor equipment 10: First lead 101: First main surface 102: First reverse side 103: Second reverse side 104: First concave side 105: First end surface 106: Second end surface 11: First terminal part 12: Second terminal part 13: First subject 20: Second lead 201: Second main surface 202: Third reverse side 203: 2nd concave surface 204: 3rd concave surface 205: Fourth concave surface 206: Third end surface 207: Fourth end surface 21: Third terminal part 22: Second subject 23: Third subject 24: Protruding part 25: Third lead 251: Third main face 252: Fourth reverse side 253: Fifth end face 26: Lead 261: Main side 262: Reverse side 263: End face 27: Fourth lead 271: Fourth main face 272: Fifth reverse side 273: 5th concave surface 274: 6th end surface 28: Fourth main section 29: Fourth terminal section 30: Semiconductor element 301: Side view of the first element 302: Side view of the second element 303: Side view of the third element 304: Side view of the fourth element 31: Semiconductor substrate 32: Semiconductor layer 321: Switching circuit 322: Control circuit 33: First electrode 34: 2nd electrode 35: 3rd electrode 36: 4th electrode 37: 5th electrode 371: Electrode 38: 6th electrode 39: 7th electrode 391: Electrode 40: Sealing resin 41: Top surface 42: Bottom 431: First side 432:Second side 433:Third side 434: Fourth side 50: Fifth lead 501: Fifth main side 502: Sixth reverse side 503: Reverse side of the 7th surface 504: Concave side of the 6th surface 505: 7th end face 51: 6th terminal part 52: 7th terminal section 53: 6th main section 54: Lead 541: Main surface 542: Reverse side 543: Reverse side 544: Concave surface 545: End surface 546: End face 60: 6th lead 601: 6th main face 602: 8th reverse side 603: 8th end face 604: 9th end face 70: 7th lead 701: 7th main face 702: 9th reverse side 703: 10th end face 80: Lead 801: Main surface 802: Reverse side 803: End face Da:Divided area L1: Dimension (dimension of the first terminal in the second direction) L2: Dimension (dimension of the second terminal in the second direction) L3: Dimension (dimension of the first main part in the second direction) x: First direction y: Second direction z: Thickness direction

Claims

1. Multiple fifth leads, each having a fifth principal surface facing the thickness direction, A semiconductor element having a plurality of fifth electrodes, wherein the plurality of fifth electrodes are connected to the fifth main surface of each of the plurality of fifth leads, The system comprises the plurality of fifth leads and a sealing resin covering the semiconductor element, The sealing resin has a resin bottom surface on the opposite side of the semiconductor element with respect to the plurality of fifth electrodes in the thickness direction, a first resin side surface and a second resin side surface connected to the resin bottom surface and spaced apart from each other in a first direction perpendicular to the thickness direction, and a third resin side surface and a fourth resin side surface spaced apart from each other in a second direction perpendicular to the thickness direction and the first direction. Each of the plurality of fifth leads has a sixth back surface, a seventh back surface, and a sixth concave surface facing away from the fifth main surface of each fifth lead in the thickness direction, and a seventh end surface facing the second direction, the sixth back surface and the seventh back surface are separated in the second direction with the sixth concave surface in between and exposed from the resin bottom surface, the sixth concave surface is covered by the sealing resin, and the seventh end surface is connected to the fifth main surface and the sixth back surface and exposed from the sealing resin so as to be flush with either the third resin side surface or the fourth resin side surface, a semiconductor device.

2. The semiconductor element has a first element side surface and a second element side surface that are spaced apart from each other in the first direction, and a third element side surface and a fourth element side surface that are spaced apart from each other in the second direction and connected to the first element side surface and the second element side surface. The semiconductor device according to claim 1, wherein, when viewed in the thickness direction, the region enclosed by the first element side surface, the second element side surface, the third element side surface, and the fourth element side surface is equally divided into two regions in the first and second directions, and at least one of the seventh back surfaces of each of the plurality of fifth leads is disposed in each of these four divided regions.

3. The semiconductor device according to claim 2, wherein, when viewed in the thickness direction, at least one of the seventh back surfaces arranged in each of the four divided regions overlaps with at least one of the plurality of fifth electrodes.

4. The plurality of fifth leads include a first pair of fifth leads and a second pair of fifth leads, wherein the seventh end face of each of the first pair of fifth leads is flush with the third resin side surface, and the seventh end face of each of the second pair of fifth leads is flush with the fourth resin side surface. The semiconductor device according to claim 3, wherein the seventh back surfaces of the fifth leads of the first pair and the fifth leads of the second pair are arranged in the four divided regions when viewed in the thickness direction.

5. It has a sixth main surface and an eighth back surface facing opposite directions in the thickness direction, and further comprises a sixth lead extending in the second direction, A portion of the sixth lead is covered by the sealing resin, The semiconductor element has a plurality of sixth electrodes connected to the sixth main surface, The sixth lead is connected to the sixth main surface and the eighth back surface, and has an eighth end surface and a ninth end surface facing one side and the other side in the second direction, The eighth end face is exposed from the third resin side surface so as to be flush with the third resin side surface. The semiconductor device according to claim 4, wherein the ninth end face is exposed from the fourth resin side surface so as to be flush with the fourth resin side surface.

6. The seventh back surface, which is arranged in each of the four divided regions, is divided into the seventh back surface of the first pair and the seventh back surface of the second pair, and the seventh back surface of the first pair is spaced apart from the seventh back surface of the second pair in the first direction. The semiconductor device according to claim 5, wherein the sixth lead is located between the seventh back surface of the first pair and the seventh back surface of the second pair in the first direction.

7. Each of the seven back surfaces, which are arranged in the four divided regions, extends in the second direction. The semiconductor device according to claim 5 or 6, wherein the seventh back surface, which is arranged in each of the four divided regions, is arranged symmetrically with respect to a straight line extending parallel to the first direction and symmetrically with respect to a straight line extending parallel to the second direction.

8. Each has a seventh main surface and a ninth back surface facing opposite directions in the thickness direction, and further comprises a pair of seventh leads extending in the first direction, The semiconductor element has a plurality of seventh electrodes connected to the seventh main surface of each of the pair of seventh leads, A portion of each of the pair of seventh leads is covered with the sealing resin. Each of the pair of seventh leads has a tenth end face that is connected to the seventh main surface and the ninth back surface of each seventh lead and faces the first direction. The tenth end faces of each of the pair of seventh leads face opposite each other in the first direction. The seventh back surfaces, each arranged in the four divided regions, are divided into the seventh back surfaces of the third pair and the seventh back surfaces of the fourth pair, and the seventh back surfaces of the third pair are spaced apart from the seventh back surfaces of the fourth pair in the second direction. The semiconductor device according to claim 7, wherein the pair of seventh leads are located between the back surfaces of the third pair and the back surfaces of the fourth pair in the second direction.

9. The semiconductor element comprises a semiconductor substrate and a semiconductor layer stacked on the semiconductor substrate in the thickness direction. The semiconductor layer comprises a switching circuit and a control circuit that conducts to the switching circuit. The plurality of fifth electrodes and the plurality of sixth electrodes are electrically connected to the switching circuit. The semiconductor device according to claim 8, wherein the plurality of seventh electrodes are electrically connected to the control circuit.

10. The sixth lead is an input terminal to which DC power to be converted is input, The semiconductor device according to claim 9, wherein the plurality of fifth leads are output terminals to which AC power converted by the switching circuit is output.

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