A semiconductor chip management device, a semiconductor chip management method, and a semiconductor chip manufacturing method.

Abstract

To improve the traceability of semiconductor chips. [Solution] A semiconductor chip management device is provided, comprising: an acquisition unit for acquiring an image of the metal portion of a semiconductor chip; an image processing unit for extracting external features of the metal portion from the image; and a recording unit for recording the external features as identification information of the semiconductor chip. The recording unit may record the external features in association with the manufacturing history of the semiconductor chip. The semiconductor chip has a semiconductor substrate and a protective film provided above the upper surface of the semiconductor substrate and covering at least a part of the metal portion, and the acquisition unit may acquire an image of the metal portion covered by the protective film.

Description

Technical Field

[0001] The present invention relates to a semiconductor chip management device, a semiconductor chip management method, and a semiconductor chip manufacturing method.

Background Art

[0002] Patent Document 1 describes "a semiconductor integrated circuit capable of directly writing individual management information and test information of chips during the manufacturing process to all chips, reading this information when a failure occurs after the assembly process, and using it as basic data for failure analysis." Patent Document 2 describes "a method of overlapping and collating image data of the back grinding marks of a semiconductor wafer previously captured by an image capturing device and image data of the back grinding marks of an LSI chip to identify the acquisition position of the LSI chip on the semiconductor wafer." Patent Document 3 describes "a method of collating image data of contact marks 12, or contact marks 12 and dicing marks 13, with each image data stored in a storage unit 22 to identify the formation position of the LSI chip on the semiconductor wafer." Patent Document 1: Japanese Patent Application Laid-Open No. 2000-228341 Patent Document 2: Japanese Patent Application Laid-Open No. 2004-055882 Patent Document 3: Japanese Patent Application Laid-Open No. 2007-165389

Summary of the Invention

Problems to be Solved by the Invention

[0003] Improve the traceability of semiconductor chips.

Means for Solving the Problems

[0004] To solve the above problems, a first embodiment of the present invention provides a semiconductor chip management device equipped with an acquisition unit for acquiring an image of the metal portion of a semiconductor chip. The semiconductor chip management device may be equipped with an image processing unit for extracting external features of the metal portion from the image. Any of the above semiconductor chip management devices may be equipped with a recording unit for recording the external features as identification information of the semiconductor chip.

[0005] In any of the above semiconductor chip management devices, the recording unit may record the external characteristics and the manufacturing history of the semiconductor chip in association.

[0006] In any of the above semiconductor chip management devices, the semiconductor chip may have a semiconductor substrate and a protective film provided above the upper surface of the semiconductor substrate and covering at least a portion of the metal portion. In any of the above semiconductor chip management devices, the acquisition unit may acquire an image of the metal portion covered by the protective film.

[0007] The management device for any of the above semiconductor chips may include a polyimide-based material in the protective film.

[0008] In any of the above semiconductor chip management devices, the metal portion may be a main electrode located above the upper surface of the semiconductor substrate.

[0009] In any of the above semiconductor chip management devices, the protective film may be provided with a main opening that exposes the main electrode. In any of the above semiconductor chip management devices, the semiconductor chip may have a signal pad that is separated from the main electrode and is provided between the main opening and the first edge of the semiconductor chip in a top view. In any of the above semiconductor chip management devices, the acquisition unit may acquire an image of the main electrode between the second edge that intersects the first edge and the signal pad.

[0010] In any of the above semiconductor chip management devices, the semiconductor chip may be provided above the upper surface of the semiconductor substrate and may have a gate runner that transmits a gate signal. In any of the above semiconductor chip management devices, the acquisition unit may acquire an image of the main electrode between the gate runner and the signal pad.

[0011] In any of the above semiconductor chip management devices, the semiconductor chip may have a marker provided along its edge. In any of the above semiconductor chip management devices, the protective film may be provided with a main opening that exposes the main electrode. In any of the above semiconductor chip management devices, the acquisition unit may acquire an image of the main electrode between the marker and the main opening.

[0012] In any of the above semiconductor chip management devices, the acquisition unit may acquire an image of a region within 2000 μm from the edge of the main electrode.

[0013] In any of the above semiconductor chip management devices, the acquisition unit may acquire an image at a position 100 μm or more away from the edge of the main electrode.

[0014] In any of the above semiconductor chip management devices, the acquisition unit may acquire an image of a region within 2000 μm from the corner of the main electrode.

[0015] In any of the above semiconductor chip management devices, the semiconductor chip may have a main electrode provided above the upper surface of the semiconductor substrate and a signal pad provided above the upper surface of the semiconductor substrate and separated from the main electrode. In any of the above semiconductor chip management devices, the metal portion may be the signal pad.

[0016] In any of the above semiconductor chip management devices, the signal pad may be a gate pad.

[0017] In any of the above semiconductor chip management devices, the acquisition unit may acquire images of the metal portion covered by the protective film at multiple locations.

[0018] In any of the above semiconductor chip management devices, the semiconductor chip may have a main electrode provided above the upper surface of the semiconductor substrate and a signal pad provided above the upper surface of the semiconductor substrate and separated from the main electrode. In any of the above semiconductor chip management devices, the metal portion may include the main electrode and the signal pad. In any of the above semiconductor chip management devices, the acquisition unit may acquire images of both the main electrode covered with the protective film and the signal pad covered with the protective film.

[0019] In any of the above semiconductor chip management devices, the area of ​​the main electrode included in the image of the main electrode may be larger than the area of ​​the signal pad included in the image of the signal pad.

[0020] In any of the above semiconductor chip management devices, a diode may be provided on the semiconductor substrate. In any of the above semiconductor chip management devices, the main electrode may be the anode electrode of the diode. In any of the above semiconductor chip management devices, the external feature may be the grain boundary pattern of the metal portion. In any of the above semiconductor chip management devices, the image processing unit may binarize the image. In any of the above semiconductor chip management devices, the recording unit may record the binarized image.

[0021] A second aspect of the present invention provides a method for managing semiconductor chips. In the above semiconductor chip management method, an image of the metal portion of the semiconductor chip may be acquired. In the above semiconductor chip management method, a grain boundary pattern of the metal portion may be extracted from the image. In either of the above semiconductor chip management methods, the grain boundary pattern may be recorded as identification information of the semiconductor chip.

[0022] In the method for managing any of the semiconductor chips described above, the acquisition of the image may be performed during the appearance inspection of the semiconductor chip.

[0023] In a third aspect of the present invention, a method for manufacturing a semiconductor chip is provided. In the method for manufacturing a semiconductor chip, a metal portion may be formed on the semiconductor chip. In the method for manufacturing a semiconductor chip, an image of the metal portion of the semiconductor chip may be acquired. In the method for manufacturing any of the semiconductor chips, a grain boundary pattern of the metal portion may be extracted from the image. In the method for manufacturing any of the semiconductor chips, the grain boundary pattern may be recorded as identification information of the semiconductor chip.

[0024] In the method for manufacturing any of the semiconductor chips described above, the acquisition of the image may be performed during the appearance inspection of the semiconductor chip.

[0025] The above summary of the invention does not list all the necessary features of the present invention. Also, sub - combinations of these feature groups can also be inventions.

Brief Description of the Drawings

[0026] [Figure 1] It is a conceptual diagram showing an individual identification method of a semiconductor chip 30 in a comparative example. [Figure 2] It is a conceptual diagram showing an individual identification method of a semiconductor chip 30 of the present invention. [Figure 3] It is a diagram showing an example of a management device 100 in an embodiment of the present invention. [Figure 4] It is a diagram for explaining an image acquisition position in a top view of a semiconductor chip 30. [Figure 5] It is a diagram showing an example of a cross - section taken along line E - E' of FIG. 4. [Figure 6] It is an enlarged view of region A in FIG. 4. [Figure 7] It is a diagram showing an example of a cross - section taken along line C - C' of FIG. 6. [Figure 8] It is an enlarged view of region B in FIG. 4. [Figure 9]This figure shows an example of the D-D' section in Figure 8. [Figure 10] This figure shows an example of a manufacturing flow for a semiconductor chip 30 to which the control method of the present invention is applied. [Figure 11] This figure shows an example of the matching flow for a semiconductor chip 30. [Modes for carrying out the invention]

[0027] The present invention will be described below through embodiments of the invention, but these embodiments are not intended to limit the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0028] In this specification, the terms "identical" or "equal" may include cases where there are errors due to manufacturing variations, etc. Such errors are, for example, within 10%.

[0029] Figure 1 is a conceptual diagram showing a method for individual identification of semiconductor chips 30 in a comparative example. In the manufacturing of semiconductor devices, numerous semiconductor devices formed on a single semiconductor wafer are diced into chips during the dicing process, picked up, and stored in trays. Each semiconductor chip 30 is assigned a unique chip ID that includes the wafer lot number, wafer number, and XY coordinates within the wafer. The chip ID is linked to the chip tray number and tray address to which it is stored. In this example, the tray address is represented by XY coordinates. This tracking data is recorded electronically as a tracking data file.

[0030] In this example, individual semiconductor chips 30 are identified by the tray number and tray address in which the chip is stored. Notches may be provided to determine the orientation of the X and Y axes of the tray address. The chip ID can be identified from the tray number and tray address, and the manufacturing history can be investigated by tracing back from the chip ID to the wafer lot number, wafer number, and XY coordinates within the wafer.

[0031] However, in this example, it becomes difficult to individually identify the semiconductor chip 30 after it has been removed from the tray. Therefore, it is difficult to track the manufacturing history of the chip after it has been removed from the tray. To enable tracking of the manufacturing history of each chip even after it has been removed from the tray, one method is to laser engrave or ink mark an individual identification number onto the semiconductor chip 30 (see Patent Document 1), but this is not practical due to reasons such as contamination and dust generation during engraving. In addition, tracking methods have been proposed that involve matching with grinding marks on the back surface of the wafer (see Patent Document 2) or matching with dicing marks or probe marks (see Patent Document 3), but these have problems such as difficulty in determining accuracy and difficulty in tracking during destructive analysis after packaging.

[0032] Figure 2 is a conceptual diagram illustrating a method for identifying individual semiconductor chips 30 according to the present invention. In this example, individual semiconductor chips 30 are identified based on the external characteristics of the metal portion of the semiconductor chip 30. The metal portion may be a main electrode (surface electrode) provided on the upper surface of the semiconductor chip 30, a signal pad such as a gate pad, or metal wiring. The main electrode is the current through which the main current flows in the semiconductor chip 30. The main current is, for example, the collector current or drain current in a transistor, or the anode-cathode current in a diode. A minute signal flows through the signal pad to control the operation of the semiconductor chip 30 or to measure the operation of the semiconductor chip 30. The minute signal is, for example, a control signal such as a base signal or gate signal in a transistor, or a detection signal indicating the magnitude of the main current of the semiconductor chip 30, or the temperature of the semiconductor chip 30. Metal wiring is wiring connected to the main electrode or signal pad, and transmits signals such as gate signals.

[0033] The external features of a metal part may include, for example, the surface irregularities of the metal part, the distribution of brightness on the surface of the metal part, the shape of the surface of the metal part, or a combination of these external features. The surface pattern of the metal part may be a linear pattern and may include at least one piece of information such as the position of the line, the shape of the line, the branching position of the line, and the intersection position of the line. The linear pattern may be a streak on the metal part or a grain boundary pattern, as described later. In this example, the external features are a grain boundary pattern, which is an example of a surface pattern of a metal part, but unless the context specifically describes something particular to grain boundary patterns, the grain boundary pattern may be replaced with other external features. Generally, alloy materials containing Al or Cu are used as materials for metal parts such as surface electrodes of semiconductor devices. Various alloy films are usually deposited by sputtering, and since the growth of alloy films deposited by sputtering is generally in island mode, grain boundaries appear on the surface of the alloy film. Since these grain boundaries occur randomly, the grain boundary pattern is unique to each semiconductor chip 30. Therefore, individual semiconductor chips 30 can be identified. In this specification, the pattern formed by grain boundaries may be referred to as a grain boundary pattern. In this example, an image of the alloy film portion of each semiconductor chip 30 is acquired, and individual semiconductor chips 30 are identified from the grain boundary pattern of the image. However, as mentioned above, individual identification of semiconductor chips 30 may be performed using the external characteristics of the metal part, and in addition to the grain boundary pattern, surface irregularities and brightness distribution may also be extracted. Furthermore, wiring shape, alignment mark quality, etc., may also be used for individual identification.

[0034] The semiconductor chip 30 on the far left of the figure represents the semiconductor chip 30 during the manufacturing process. As an example, the semiconductor chip 30 after electrical characteristics testing may be used. In this example, images of two locations on the semiconductor chip 30, namely the main electrode 52 and the signal pad 42, are captured.

[0035] The two schematic diagrams located to the right of the semiconductor chip 30 represent images of the metallic portion. The upper image is an image of the surface of the main electrode 52, and the lower image is an image of the surface of the signal pad 42. The thick lines and black dots in each image represent grain boundary patterns, i.e., grain boundary patterns on the surface of the metallic portion. As an example, the grain size of the crystal grains is between 10 μm and 500 μm. In this example, both images are in color.

[0036] The two schematic diagrams located to the right of the image in question represent images obtained by processing the original image. For example, the data size of an image can be reduced by binarizing it. In this example, since the grain boundary pattern is used as identification information, the identification information is easily preserved even after binarization. In other words, binarization is suitable because the identification information and binarization are compatible. The binarized image may be linked to the aforementioned chip ID and the results of electrical characteristic tests. However, image processing is not limited to binarization. For example, processing such as conversion to grayscale, noise reduction, and contrast enhancement may also be performed.

[0037] The semiconductor chip 30 on the far right of the diagram represents a semiconductor chip 30 after shipment. Even with a semiconductor chip 30 after shipment, it is possible to identify individual semiconductor chips 30 by acquiring an image of the same region as the binarized image obtained on the semiconductor chip 30 after testing and comparing the grain boundary patterns.

[0038] According to this example, individual semiconductor chips 30 removed from the tray can also be identified, enabling tracing of the manufacturing history over a wide range and allowing for the provision of highly reliable devices. In particular, with power semiconductor devices, even if the surface design is the same, differences in drift layer specifications can result in completely different characteristics. According to this example, it is possible to prevent defects in the characteristics of the final product due to mix-ups of models or characteristic ranks during the packaging process. Furthermore, since this method does not involve stamping identification numbers on the substrate, it is possible to trace the manufacturing history without increasing the number of manufacturing steps.

[0039] Figure 3 shows an example of a management device 100 in an embodiment of the present invention. The management device 100 manages the semiconductor chip 30. The management device 100 in this example includes an acquisition unit 22, an image processing unit 24, and a recording unit 26.

[0040] The acquisition unit 22 acquires an image of the metal portion of the semiconductor chip 30. The acquisition unit 22 may acquire an image of a specified position on the metal portion of the semiconductor chip 30. The acquisition unit 22 may have an imaging unit and may acquire an image captured by an external camera. In this example, the acquisition unit 22 has an imaging unit and captures an image of the metal portion of the semiconductor chip 30. The acquisition unit 22 may be an imaging device having an alignment function and may acquire an image captured using said imaging device.

[0041] Figure 2 and subsequent figures illustrate an example in which the acquisition unit 22 acquires an image captured by an imaging device equipped with a bright-field inspection mechanism. However, the acquisition unit 22 may also acquire images captured by other imaging means, such as a scanning electron microscope inspection mechanism, a dark-field inspection mechanism, or a confocal inspection mechanism.

[0042] The image processing unit 24 extracts external features, including grain boundary patterns of the metal parts, from the image acquired by the acquisition unit 22. The image processing unit 24 may extract grain boundary patterns by extracting areas in the image where the intensity or color tone of pixels differs from other areas. The image processing unit 24 may extract grain boundary patterns by recognizing patterns in the image using known machine learning or deep learning. The image processing unit 24 may extract unique patterns such as spirals or loops as grain boundary patterns. The image processing unit 24 may extract lines that form a closed circuit in the image, or lines that do not terminate anywhere other than the edges of the image, as grain boundary patterns. The image processing unit 24 may perform binarization. The image processing unit 24 may perform binarization of the intensity of each pixel in a color image by comparing the intensity of each pixel with a preset threshold. The image processing unit 24 may extract grain boundary patterns from the color image in Figure 2, or from a binarized image.

[0043] The recording unit 26 records the grain boundary pattern as identification information for the semiconductor chip 30. The recording unit 26 may record the grain boundary pattern in association with the manufacturing history of the semiconductor chip 30. Examples of manufacturing history include the lot number of the wafer used, the ID of the wafer used, the coordinates within the wafer, the date and time of manufacture, the manufacturing location (line), the manufacturing equipment, the date and time of inspection, the inspection results, and electrical characteristics. In other words, it may include any information necessary to identify the manufacturing process and characteristics of the semiconductor chip 30. The recording unit 26 may record a binarized image as identification information. The recording unit 26 may record an image of the grain boundary pattern extracted from the binarized image as identification information, and may generate feature quantities that can be extracted from the grain boundary pattern, such as the position of intersections in the grain boundary pattern, and record these feature quantities of the grain boundary pattern as identification information.

[0044] By associating grain boundary patterns with manufacturing history, it becomes possible to trace the manufacturing history. This makes it easier to investigate the cause if, for example, an abnormality is found in the product, and shortens the time it takes to identify the cause. As a result, rapid feedback to the manufacturing process is possible, leading to improved product quality.

[0045] The acquisition unit 22 may acquire an image of the semiconductor chip 30 to be identified. The semiconductor chip 30 to be identified is, for example, the semiconductor chip 30 after shipment as shown in Figure 2. The image processing unit 24 may extract the grain boundary pattern of the metal portion from the image of the semiconductor chip 30 to be identified. The management device 100 may further include a determination unit 28. The determination unit 28 compares the grain boundary pattern recorded in the recording unit 26 with the grain boundary pattern of the semiconductor chip 30 to be identified and determines whether the grain boundary patterns match. In this example, the acquisition unit 22 acquires an image of the semiconductor chip 30 in chip form, but the acquisition unit 22 may also acquire an image of the semiconductor chip 30 in wafer form (before dicing).

[0046] Figure 4 illustrates the image acquisition position in a top view of the semiconductor chip 30. The semiconductor chip 30 has a semiconductor substrate 10, a main electrode 52, plating 56, and a protective film 80. The semiconductor chip 30 may further include a signal pad 42, plating 46, gate runner 68, and marker 70.

[0047] The semiconductor substrate 10 may contain transistors or diodes. The transistors may be, for example, MOSFETs or IGBTs. The diodes may be Schottky barrier diodes or PN junction diodes. The semiconductor substrate 10 may contain only transistors, only diodes, or both transistors and diodes, such as in an RC-IGBT. Furthermore, it may also contain elements such as memory or logic ICs. In this example, the semiconductor substrate 10 contains a MOSFET.

[0048] In a top view, the semiconductor substrate 10 has a first edge 61 and a second edge 62. The semiconductor substrate 10 in this example has two first edges 61 and second edges 62. The first edge 61 and the second edge 62 intersect. In this example, the first edge 61 and the second edge 62 are orthogonal. The first edge 61 and the second edge 62 are the edges of the semiconductor chip 30. In Figure 4, the direction parallel to the first edge 61 is the X-axis, the direction parallel to the second edge 62 is the Y-axis, and the direction orthogonal to the first edge 61 and the second edge 62 is the Z-axis.

[0049] The main electrode 52 is located above the upper surface of the semiconductor substrate 10. The main electrode 52 may be the electrode with the largest area when viewed from above. The main electrode 52 may be the electrode through which the main current flows. The main electrode 52 may be an electrode located above the active portion. The active portion may be a region where a channel is formed. In this example, the main electrode 52 is the source electrode. Most of the active portion is located in a position that overlaps with the plating 56. If a diode is provided on the semiconductor substrate 10, the main electrode 52 may be the anode electrode or the cathode electrode.

[0050] The protective film 80 is provided above the upper surface of the semiconductor substrate 10 and covers at least a portion of the metal part. The main electrode 52 is an example of the aforementioned metal part. Also, if the semiconductor chip 30 has a signal pad 42, the signal pad 42 may also be an example of a metal part. In Figure 4, the protective film 80 has a coarse hatching pattern.

[0051] The protective film 80 is provided with a main opening 82 that exposes the main electrode 52. The main opening 82 may be the largest opening in terms of area. The main opening 82 may be the largest opening that exposes the main electrode 52. Plating 56 is provided above the main electrode 52 in the main opening 82.

[0052] The signal pads 42 are located above the upper surface of the semiconductor substrate 10 and are separated from the main electrodes 52. Multiple signal pads 42 may be provided. In this example, two signal pads 42 are provided. In this example, the signal pads 42 are located between the main opening 82 and the first edge 61 of the semiconductor chip 30 when viewed from above. In addition, the signal pads 42 in this example are arranged along the first edge 61.

[0053] The signal pad 42 may include any pads other than the main electrode 52. Examples of signal pads 42 include gate pads, sense pads, anode pads for temperature sensing, and cathode pads for temperature sensing. In Figure 4, the signal pad 42 is shown with dark hatching. However, in the top view, the hatching is not applied to the parts that overlap with the plating 46.

[0054] The protective film 80 may be provided with sub-apertures 84 that expose the signal pads 42. In this example, the protective film 80 is provided with two sub-apertures 84. The sub-apertures 84 in this example are also provided between the main aperture 82 and the first edge 61 of the semiconductor chip 30. The area of ​​the sub-apertures 84 is smaller than the area of ​​the main aperture 82. In the sub-apertures 84, plating 46 is provided above the signal pads 42.

[0055] The main electrode 52 is provided over a wider area than the main opening 82. In this example, the main electrode 52 is also provided between the signal pad 42 and the second end edge 62 in the X-axis direction, and between the signal pads 42. The area between the signal pad 42 and the second end edge 62, and between the signal pads 42, in the X-axis direction does not have to be an active area.

[0056] The main electrode 52 and the signal pad 42 are separated at a position overlapping with the protective film 80. Figure 4 shows the edge of the main electrode 52 around the signal pad 42. In this example, the signal pad 42 is surrounded by the main electrode 52. The signal pad 42 does not have to be surrounded by the main electrode 52. The signal pad 42 may be provided between the main electrode 52 and the first end edge 61. For convenience, the outer edge of the main electrode 52 is not shown in Figure 4, but the outer edge of the main electrode 52 may be slightly inside the outer edge of the protective film 80.

[0057] The gate runner 68 is located above the upper surface of the semiconductor substrate 10 and transmits the gate signal. The gate runner 68 is separated from the main electrode 52. The gate runner 68 may be located in a position where at least a portion overlaps with the protective film 80. In Figure 4, a portion of the gate runner 68 located in a position overlapping with the protective film 80 is shown by a dashed line. The gate runner 68 and the signal pad 42 may overlap at least a portion in the X-axis direction.

[0058] The marker 70 may be provided along the edge. The marker 70 may be provided outside of any electrode and pad in a top view. In this specification, "outside" refers to the side closer to the edge of the semiconductor chip 30. In this example, the marker 70 is provided at the corner of the semiconductor chip 30. In a top view, the marker 70 may be provided between the corner of the semiconductor chip 30 and the corner of the main electrode 52. The marker 70 is used, for example, to determine the orientation of the semiconductor chip 30 during package assembly.

[0059] The acquisition unit 22 may acquire an image of the metal portion covered by the protective film 80. As the assembly of the semiconductor chip 30 progresses, the protective film 80, plating 56, and plating 46 are formed on top of the metal portion. Since the parts not covered by the protective film 80 are covered by plating 56 or plating 46, it becomes impossible to acquire an image of the metal portion. On the other hand, an image of the metal portion covered by the protective film 80 can be acquired even after the semiconductor chip 30 has been packaged. Therefore, for example, even after the semiconductor chip 30 has been shipped, if the package is dismantled leaving the protective film 80 intact, an image of the metal portion covered by the protective film 80 can be acquired, making it possible to identify the semiconductor chip 30. This enables rapid and highly accurate failure analysis in the event of a problem. In addition, the protective film 80 suppresses changes in the surface of the metal portion over time, so the grain boundary pattern is less likely to change.

[0060] The protective film 80 may, for example, include a polyimide-based material. The protective film 80 may be a translucent polyimide-based organic protective film. Translucency means that the grain boundary pattern can be identified.

[0061] The metal part may be the main electrode 52. The acquisition unit 22 may acquire an image of the main electrode 52 covered with the protective film 80. If a diode is provided on the semiconductor substrate 10, the acquisition unit 22 may acquire an image of the anode electrode covered with the protective film 80 as the main electrode 52. The metal part may be a signal pad 42. The acquisition unit 22 may acquire an image of the signal pad 42 covered with the protective film 80. If a diode is provided on the semiconductor substrate 10, the signal pad 42 may not be provided. In that case, the metal part may be the anode electrode or the cathode electrode.

[0062] The following conditions 1 to 5 can be used as indicators to determine the location of image acquisition on the upper surface of the semiconductor chip 30. Condition 1: A place where alignment is easy. Condition 2: Location with low current density Condition 3: A place where the temperature is unlikely to rise. Condition 4: A location that is less likely to be damaged during demolition. Condition 5: A location where the imaging area can be secured.

[0063] Condition 1 concerns alignment during matching. The presence of landmarks other than grain boundary patterns in the image makes image acquisition and matching alignment easier, improving accuracy.

[0064] Condition 2 states that when the current density is low, migration is less likely to occur, and the grain boundary pattern is less likely to change. As a result, the accuracy of the matching improves. Condition 3 also states that if the temperature does not rise easily, for example in a place where heat is easily dissipated, the grain boundary pattern is less likely to change. Condition 4 refers to a location where the grain boundary pattern is less likely to change or the imaging area is less likely to be damaged, for example, by damage during package disassembly. Condition 5 states that if the area of ​​the metal part included in the image is small, and is about the same size as the crystal grain, the number of grain boundary patterns included in the image will decrease, making it difficult to match whether or not they are in the same position. In other words, it is desirable to secure an area of ​​metal that is several times or more the size of the crystal grain.

[0065] The acquisition unit 22 may acquire an image of the main electrode 52 between the second edge 62 and the signal pad 42. The location indicated by position 1 or position 2 in the figure is an example of the area between the second edge 62 and the signal pad 42. Position 1 or position 2 can secure a larger area than, for example, the area between the main opening 82 and the second edge 62 (Condition 5). The acquisition unit 22 may acquire an image of the main electrode 52 within 1000 μm of the signal pad 42, and may include the signal pad 42 in the image. By acquiring an image that includes a part of the signal pad 42, the signal pad 42 can serve as a landmark, making alignment easier (Condition 1).

[0066] The acquisition unit 22 may acquire an image of the main electrode 52 between the gate runner 68 and the signal pad 42. The acquisition unit 22 may acquire an image of the main electrode 52 within 1000 μm of the gate runner 68, and may include the gate runner 68 in the image. In this case, the gate runner 68 serves as a landmark, making alignment easier (Condition 1). The acquisition unit 22 may also acquire an image of the main electrode 52 between other wiring, such as temperature sensing wiring, and the signal pad 42.

[0067] The acquisition unit 22 may acquire an image of the main electrode 52 between the marker 70 and the main aperture 82. This image may include the portion of the main electrode 52 through which one of the lines connecting the marker 70 and the main aperture 82 passes. Position 3 in the figure is an example of the space between the marker 70 and the main aperture 82. The acquisition unit 22 may acquire an image of the main electrode 52 within 1000 μm of the marker 70, or it may acquire an image including the marker 70. This makes alignment easier as the marker 70 serves as a reference (Condition 1).

[0068] The acquisition unit 22 may acquire an image of the main electrode 52 at a location away from the active area. The location indicated by position 4 in the figure is an example of a location away from the active area. At locations away from the active area, the current density is low, so the grain boundary pattern is less likely to change (Condition 2). Also, because it is close to the edge of the semiconductor chip 30, heat dissipation is easier and the temperature does not rise easily (Condition 3).

[0069] Figure 5 shows an example of the E-E' cross section of Figure 4. The E-E' cross section is a YZ cross section that crosses position 4. In Figure 5, the semiconductor chip 30 has a semiconductor substrate 10, a main electrode 52, and a protective film 80. In Figure 5, the internal element structure and the bottom surface of the semiconductor substrate 10 are omitted from the illustration.

[0070] The main electrode 52 and the protective film 80 are located above the upper surface 21 of the semiconductor substrate 10. The ends of the main electrode 52 are covered by the protective film 80. Figure 5 shows the distances d1 and d2 in the Y-axis direction from the negative Y-axis end of the main electrode 52. Distance d1 is an example of the upper limit of the imaging range, and distance d2 is an example of the lower limit of the imaging range. The imaging range is the area of ​​the main electrode 52 included in the image of the main electrode 52. As an example, the imaging range is a rectangle with sides of 50 μm or more and 1000 μm or less.

[0071] The acquisition unit 22 may acquire an image of the region within 2000 μm from the edge of the main electrode 52. That is, the distance d1 may be 2000 μm. The closer to the edge of the main electrode 52, the smaller the current density (condition 2). Also, because heat dissipation is easier, the temperature does not rise easily (condition 3). The distance d1 may be 1000 μm or 500 μm. At least a part of the imaging range may be within the range of distance d1 or less, and the entire imaging range may be within the range of distance d1 or less.

[0072] The acquisition unit 22 may acquire an image at a position 100 μm or more away from the end of the main electrode 52. That is, the distance d2 may be 100 μm. By ensuring a distance from the end of the main electrode 52, it becomes less susceptible to damage during dismantling (Condition 4). Also, even if destructive testing is performed, the imaging area is less likely to be damaged (Condition 4). The distance d2 may be 500 μm or 1000 μm. At least a part of the imaging area may be in a range of distance d2 or more, and the entire imaging area may be in a range of distance d2 or more.

[0073] Figure 5 is a cross-sectional view between the signal pads 42 in Figure 4, but the above relationship may also be applied when imaging is performed between the signal pads 42 and the second edge 62 in Figure 4. That is, the imaging range at position 1 or position 2 in Figure 4 may also satisfy the relationship between distance d1 or distance d2. The same applies to the imaging range at position 3.

[0074] Figure 6 is an enlarged view of region A in Figure 4. Region A is the area around the corner of the main electrode 52, including position 3. In Figure 6, the semiconductor chip 30 comprises plating 56, main electrode 52, protective film 80, and semiconductor substrate 10.

[0075] Most of the main electrode 52 is covered by the plating 56 formed in the main opening 82 of the protective film 80. Also, as in Figure 5, the ends of the main electrode 52 are covered by the protective film 80. In Figure 6, hatching is applied along the ends of the protective film 80. Additionally, thin hatching is applied to the portion of the main electrode 52 that is not covered by the plating 56.

[0076] Plating 56 is provided above the main electrode 52 at the main opening 82 of the protective film 80. The upper surface 21 of the semiconductor substrate 10 is exposed outside the end of the main electrode 52. However, a portion of the upper surface 21 of the semiconductor substrate 10 is covered by the protective film 80. A marker 70 is provided above the upper surface 21 of the semiconductor substrate 10 that is not covered by the protective film 80.

[0077] Figure 6 shows an example of the imaging range at position 3 with a dotted line. The distance from the corner of the main electrode 52 to the imaging range is represented by d3. The acquisition unit 22 may acquire an image of the region within 2000 μm from the corner of the main electrode 52. That is, the distance d3 may be 2000 μm or less. Being close to the corner of the main electrode makes alignment easier by using the corner as a guide (Condition 1). The distance d3 may be 1000 μm or less.

[0078] Furthermore, as an example, the width d4 of the main electrode 52 between the main aperture 82 and the first or second edge 61 or 2nd edge 62 is about 100 μm, which may not be sufficient to secure an adequate imaging range. The area around the corners of the main electrode 52 allows for a wider imaging range, making matching easier (condition 5). The distance d3 may be 500 μm. At least a portion of the imaging range may be within the range of distance d3 or less, and the entire imaging range may be within the range of distance d3 or less.

[0079] Figure 7 shows an example of the C-C' cross section of Figure 6. The C-C' cross section is an XZ cross section that crosses the imaging range at position 3. In Figure 7, the semiconductor chip 30 has a semiconductor substrate 10, a main electrode 52, plating 56, and a protective film 80. In Figure 7, the internal element structure and the bottom surface of the semiconductor substrate 10 are omitted from the illustration.

[0080] In the C-C' section, the plating 56 is formed up to the edge of the main opening 82. Since the plating 56 is opaque, the portion of the main electrode 52 that overlaps with the protective film 80 outside the plating 56 is selected as the imaging range.

[0081] Figure 8 is an enlarged view of region B in Figure 4. Region B is the area around the signal pad 42. In Figure 8, the semiconductor chip 30 comprises plating 46, signal pad 42, protective film 80, semiconductor substrate 10, and main electrode 52.

[0082] Most of the signal pad 42 is covered by the plating 46 formed in the sub-opening 84 of the protective film 80. The edges of the signal pad 42 are also covered by the protective film 80. In Figure 8, hatching is applied along the edges of the protective film 80. Darker hatching is applied to the parts of the signal pad 42 that are not covered by the plating 46.

[0083] The signal pad 42 is separated from the main electrode 52. The upper surface 21 of the semiconductor substrate 10 is exposed between the signal pad 42 and the main electrode 52. The protective film 80 covers a portion of the signal pad 42, the upper surface 21 of the semiconductor substrate 10, and the main electrode 52. In Figure 8, the main electrode 52 is given a thin hatching.

[0084] The acquisition unit 22 may acquire an image of the signal pad 42. The current flowing through the signal pad 42 is smaller than that of the main electrode 52 (Condition 2). Also, since the signal pad 42 is separated from the main electrode 52, heat is less likely to be transferred from the main electrode 52 (Condition 3). Therefore, the grain boundary pattern is less likely to change. Figure 8 shows an example of the imaging range of the signal pad 42. The acquisition unit 22 may acquire an image of only the signal pad 42, or it may acquire an image that includes part of the signal pad 42.

[0085] The signal pad 42 may be a gate pad. The signal pad 42 may be an anode pad or cathode pad for temperature sensing, a pad for current sensing, or a screening pad. In any case, since it is separated from the main electrode 52, the grain boundary pattern is less likely to change.

[0086] Figure 9 shows an example of the D-D' cross-section in Figure 8. The D-D' cross-section is the XZ cross-section that traverses the imaging range in Figure 8. In Figure 9, the semiconductor chip 30 has a semiconductor substrate 10, a signal pad 42, a main electrode 52, a plating 46, and a protective film 80. In Figure 9, the internal element structure and the bottom surface of the semiconductor substrate 10 are omitted from the illustration.

[0087] In the D-D' section, the plating 46 extends to the end of the sub-aperture 84. Since the plating 46 is opaque, the portion of the signal pad 42 that does not overlap with the plating 46 but overlaps with the protective film 80 is selected as the imaging range.

[0088] The acquisition unit 22 may acquire images of the metal parts covered with the protective film 80 at multiple locations. For example, because there is a risk of changes in the particle size pattern due to temperature rise or damage during dismantling, acquiring images from multiple locations increases the likelihood of successful matching. In particular, images of the metal parts may be acquired according to different conditions from conditions 1 to 5 described above. For example, images may be acquired from any of the easily aligned positions 1 to 3 and from position 4 where the current density is low. This further increases the likelihood of successful matching. The acquisition unit 22 may acquire images from three or more locations, or even four or more locations.

[0089] The acquisition unit 22 may acquire images of both the main electrode 52 covered with the protective film 80 and the signal pad 42 covered with the protective film 80. This further increases the likelihood of successful matching.

[0090] The area of ​​the main electrode 52 included in the image of the main electrode 52 may be larger than the area of ​​the signal pad 42 included in the image of the signal pad 42. A larger area makes matching easier (condition 5). Because the main electrode 52 has a large area, it can capture a wide area. In the explanation of Figures 4 to 9, the semiconductor chip 30 was provided with plating 56 and plating 46, but the semiconductor chip 30 may be assembled by wire bonding or the like and may not have plating. Even in that case, the acquisition unit 22 may acquire images of the positions described in Figures 4 to 9. This will allow the same effect as in Figures 4 to 9 to be obtained.

[0091] Figure 10 shows an example of a manufacturing flow of a semiconductor chip 30 to which the control method of the present invention is applied. The manufacturing flow of this example includes a dicing process S100, a pickup process S102, an electrical characteristics test process S104, a tracking image acquisition process S106, an image processing process S108, an identification information-image linking process S110, a final appearance process S112, and a transfer and packaging process S114. In the tracking image acquisition process S106, the image processing process S108, and the identification information-image linking process S110, the processes described in Figures 1 to 9 may be performed.

[0092] In the dicing process S100, the wafer is diced and separated into individual semiconductor chips 30. The metal parts, such as the main electrode 52 and signal pads 42, are formed before the dicing process S100. In the pickup process S102, the individual semiconductor chips 30 are picked up, and in the electrical characteristics test process S104, the electrical characteristics of the semiconductor chips 30 are tested. Semiconductor chips 30 that are judged to have good electrical characteristics proceed to the next process.

[0093] In the tracking image acquisition step S106, an image of the metal portion is acquired. In the image processing step S108, the grain boundary pattern of the metal portion is extracted from the image acquired in the tracking image acquisition step S106. Binarization may also be performed in the image processing step S108.

[0094] In the identification information-image linking step S110, the grain boundary pattern is recorded as identification information for the semiconductor chip 30. The grain boundary pattern may be associated with the manufacturing history described above. In addition, the image or binarized image acquired in the tracking image acquisition step S106 may be saved.

[0095] In the final appearance process S112, a visual inspection is performed. Visual inspection is an inspection to ensure the reliability of semiconductor devices by visually checking the surface condition of the semiconductor chip 30 during the wafer process and after dicing, and detecting defects, scratches, abnormalities, etc. In the transfer and packaging process S114, the semiconductor chips 30 that have passed the visual inspection are transferred and packaged in shipping trays and shipped.

[0096] The image acquisition in the tracking image acquisition process S106 may be performed during the visual inspection of the semiconductor chip 30. As an example of visual inspection, an automated visual inspection device combining a camera and image processing is used to capture a surface image of the semiconductor chip 30, and the image is analyzed to automatically detect defects. These defects are typically several tens of micrometers in size, close to the size of a crystal grain. Therefore, the image acquired during the visual inspection may be used to extract the grain boundary pattern. Alternatively, an additional image for extracting the grain boundary pattern may be taken during the visual inspection. This allows for image acquisition without increasing the number or complexity of manufacturing processes. Image acquisition may be performed using an automated visual inspection device with an alignment function.

[0097] The process from tracking image acquisition step S106 to the final appearance inspection step S112 may be performed entirely automatically by an automated appearance inspection device. However, the manufacturing flow shown in Figure 10 is only a part of the manufacturing flow of the semiconductor chip 30. Furthermore, imaging may be performed on the semiconductor chip 30 in wafer state after surface electrode wiring formation. In that case, the tracking image acquisition step S106 may be performed before the dicing step S100, and the identification information-image linking step S110 may be performed from the tracking image acquisition step S106. In that case, the image acquisition in the tracking image acquisition step S106 may be performed during the appearance inspection of the wafer state before dicing.

[0098] Figure 11 shows an example of a matching flow for a semiconductor chip 30. In the matching flow, for example, individual identification of semiconductor chips 30 after shipment is performed. The matching flow in this example comprises a sample preprocessing step S200, an imaging alignment step S202, a matching image acquisition step S204, an image processing step S206, a matching position extraction step S208, a matching step S210, and a determination step S212.

[0099] In the sample preprocessing step S200, the package is disassembled and the semiconductor chip 30 is removed. There is a risk of damage at this time, so condition 4 is used as an indicator as described above. In the imaging alignment step S202, the position to be imaged within the metal part of the semiconductor chip 30 is adjusted. At this time, if the markers specified by condition 1 and the imaging area of ​​sufficient size specified by condition 5 are secured, it becomes easier to align and verify the image.

[0100] Once alignment is complete, the matching image acquisition step S204 captures an image of the metal part. Here, the same position as captured in the tracking image acquisition step S106 is captured under the same conditions. The captured image is processed in the image processing step S206. Binarization may be performed in the image processing step S206.

[0101] In the matching position extraction step S208, a range or specific grain boundary pattern used for matching is extracted from the image. In the matching step S210, the grain boundary pattern recorded as identification information in the identification information-image linking step S110 (Figure 5) is compared with the grain boundary pattern extracted in the matching position extraction step S208. In particular, matching may be performed based on unique patterns such as helices and loops in the metal parts. Furthermore, if shipping information for the semiconductor chip 30 is available, the matching target can be narrowed down based on that data, thereby improving matching accuracy and shortening matching time.

[0102] In the determination step S212, it is determined whether the two grain boundary patterns match, and individual identification is performed. At this time, if the grain boundary pattern changes, the number of misidentifications increases, so the above-mentioned indicators are conditions 2 and 3. In addition, image acquisition in the matching flow may also be performed by an automated visual inspection device with alignment functionality.

[0103] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0104] It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of symbols]

[0105] 10...Semiconductor substrate, 21...Top surface, 22...Acquisition unit, 24...Image processing unit, 26...Recording unit, 28...Determination unit, 30...Semiconductor chip, 42...Signal pad, 46...Plating, 52...Main electrode, 56...Plating, 61...First edge, 62...Second edge, 68...Gate runner, 70...Marker, 80...Protective film, 82...Main opening, 84...Sub-opening, 100...Management device

Claims

1. An acquisition unit that acquires an image of the metal part of the semiconductor chip, An image processing unit that extracts the external features of the metal part from the aforementioned image, A recording unit that records the aforementioned external characteristics as identification information of the semiconductor chip. A management device for semiconductor chips equipped with the following features.

2. The recording unit records the external characteristics and the manufacturing history of the semiconductor chip in association. A semiconductor chip management device according to claim 1.

3. The aforementioned semiconductor chip is Semiconductor substrate and A protective film is provided above the upper surface of the semiconductor substrate and covers at least a portion of the metal portion. It has, The acquisition unit acquires an image of the metal portion covered by the protective film. A semiconductor chip management device according to claim 1.

4. The protective film includes a polyimide-based material. A semiconductor chip management device according to claim 3.

5. The aforementioned metal portion is a main electrode provided above the upper surface of the semiconductor substrate. A semiconductor chip management device according to claim 3.

6. The protective film is provided with a main opening that exposes the main electrode. The semiconductor chip has a signal pad that is separated from the main electrode and, in a top view, is provided between the main opening and the first edge of the semiconductor chip. The acquisition unit acquires an image of the main electrode between the second edge that intersects the first edge and the signal pad. A semiconductor chip management device according to claim 5.

7. The semiconductor chip is provided above the upper surface of the semiconductor substrate and has a gate runner that transmits a gate signal. The acquisition unit acquires an image of the main electrode between the gate runner and the signal pad. A semiconductor chip management device according to claim 6.

8. The semiconductor chip has markers provided along its edges, The protective film is provided with a main opening that exposes the main electrode. The acquisition unit acquires an image of the main electrode between the marker and the main opening. A semiconductor chip management device according to claim 5.

9. The acquisition unit acquires an image of the region within 2000 μm from the end of the main electrode. A semiconductor chip management device according to claim 5.

10. The acquisition unit acquires an image at a position 100 μm or more away from the end of the main electrode. A semiconductor chip management device according to claim 5.

11. The acquisition unit acquires an image of the region within 2000 μm from the corner of the main electrode. A semiconductor chip management device according to claim 5.

12. The aforementioned semiconductor chip is A main electrode provided above the upper surface of the semiconductor substrate, A signal pad is provided above the upper surface of the semiconductor substrate and is separated from the main electrode. It has, The aforementioned metal part is the signal pad. A semiconductor chip management device according to claim 3.

13. The aforementioned signal pad is a gate pad. A semiconductor chip management device according to claim 12.

14. The acquisition unit acquires images of the metal portion covered with the protective film at multiple locations. A semiconductor chip management device according to claim 3.

15. The aforementioned semiconductor chip is A main electrode provided above the upper surface of the semiconductor substrate, A signal pad is provided above the upper surface of the semiconductor substrate and is separated from the main electrode. It has, The metal portion includes the main electrode and the signal pad. The acquisition unit acquires images of both the main electrode covered with the protective film and the signal pad covered with the protective film. A semiconductor chip management device according to claim 14.

16. The area of ​​the main electrode included in the image of the main electrode is larger than the area of ​​the signal pad included in the image of the signal pad. A semiconductor chip management device according to claim 15.

17. A diode is provided on the semiconductor substrate. The main electrode is the anode electrode of the diode. A semiconductor chip management device according to claim 5.

18. The aforementioned external feature is the grain boundary pattern of the metal portion. A semiconductor chip management device according to any one of claims 1 to 17.

19. The image processing unit binarizes the image, The recording unit records the binarized image. A semiconductor chip management device according to claim 18.

20. By acquiring an image of the metal part of the semiconductor chip, The grain boundary pattern of the metal portion is extracted from the aforementioned image. The grain boundary pattern is recorded as identification information for the semiconductor chip. Methods for managing semiconductor chips.

21. The aforementioned image is acquired during the visual inspection of the semiconductor chip. A method for managing semiconductor chips according to claim 20.

22. By forming a metal part on a semiconductor chip, An image of the metal portion of the semiconductor chip is obtained. The grain boundary pattern of the metal portion is extracted from the aforementioned image. The grain boundary pattern is recorded as identification information for the semiconductor chip. A method for manufacturing semiconductor chips.

23. The aforementioned image is acquired during the visual inspection of the semiconductor chip. A method for manufacturing a semiconductor chip according to claim 22.

Images