Voltage sensor simulation circuit, voltage sensor simulation method, and simulator

Abstract

To accurately simulate the detection signal of a voltage sensor. [Solution] A voltage sensor simulation circuit comprising: a power converter having phase PWM control signals for each phase, each containing an arm element, between a positive bus and a negative bus; a calculator that calculates the arm voltage for each phase output from the arm of each phase in accordance with the PWM control signal for each phase, using the polarity of the output current of each phase of the power converter, the DC bus voltage between the positive bus and the negative bus, and the on voltage between the main terminals of the arm element; and a generation circuit that generates a sensor simulation signal for each phase, which is a signal that simulates the detection signal for each phase output from a voltage sensor that detects the output voltage of each phase of the power converter, by adding or subtracting the arm voltage of each phase.

Description

[Technical Field]

[0001] This disclosure relates to a voltage sensor simulation circuit, a voltage sensor simulation method, and a simulator. [Background technology]

[0002] A method is known for calculating the output AC voltage of each phase of a multiphase inverter by substituting the values ​​of the PWM control signals and the input DC voltages into an equation that represents the quantitative relationship between the PWM control signals, which are the control signals for each phase of the multiphase inverter, the input DC voltage to the multiphase inverter, and the output AC voltages of each phase of the multiphase inverter. A technique is known for simulating the state of a virtual multiphase inverter defined by the inverter model in real time by periodically performing a step of calculating the state of the inverter model defined by the equation using this method. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2006-149043 [Overview of the project] [Problems that the invention aims to solve]

[0004] However, conventional calculation methods for determining the output AC voltage of each phase of a multiphase inverter make it difficult to accurately simulate the detection signals for each phase output from voltage sensors that detect the output voltage of each phase of a power converter such as a multiphase inverter.

[0005] This disclosure aims to accurately simulate the detection signal of a voltage sensor. [Means for solving the problem]

[0006] This disclosure is, A power converter having phase arms, each containing an arm element, between a positive bus and a negative bus, is controlled by a PWM control signal for each phase, the polarity of the output current of each phase of the power converter, the DC bus voltage between the positive bus and the negative bus, and the on-voltage between the main terminals of the arm element, and a calculator that calculates the arm voltage of each phase output from the arm of each phase in accordance with the PWM control signal of each phase. A voltage sensor simulation circuit is provided, comprising: a generation circuit that generates a sensor simulation signal for each phase, which is a signal that simulates the detection signal for each phase output from a voltage sensor that detects the output voltage of each phase of the power converter, by adding or subtracting the arm voltage of each phase.

[0007] This disclosure is, The arithmetic unit uses the PWM control signals for each phase that control a power converter having arms for each phase, each containing an arm element, between the positive bus and the negative bus, the polarity of the output current of each phase of the power converter, the DC bus voltage between the positive bus and the negative bus, and the on-voltage between the main terminals of the arm element to calculate the arm voltage for each phase that is output from the arm of each phase in accordance with the PWM control signal for each phase. The generation circuit provides a voltage sensor simulation method that generates simulated sensor signals for each phase, which are signals that simulate the detection signals for each phase output from a voltage sensor that detects the output voltage of each phase of the power converter, by adding or subtracting the arm voltage of each phase.

[0008] This disclosure is, A calculator that simulates the output current of each phase output from a power converter in accordance with the PWM control signals of each phase that control a power converter having arms of each phase, each containing an arm element, between the positive bus and the negative bus, The power converter includes a generation circuit that generates sensor simulation signals for each phase, which are signals that simulate the detection signals for each phase output from a voltage sensor that detects the output voltage of each phase of the power converter. The calculator uses the PWM control signal of each phase, the polarity of the simulated output current of each phase, the DC bus voltage between the positive bus and the negative bus, and the on-voltage between the main terminals of the arm element to calculate the arm voltage of each phase output from the arm of each phase according to the PWM control signal of each phase. The generation circuit provides a simulator that generates the sensor simulation signal of each phase by adding and subtracting the arm voltages of each phase.

Advantages of the Invention

[0009] According to the present disclosure, the detection signal of the voltage sensor can be accurately simulated.

Brief Description of the Drawings

[0010] [Figure 1] It is a diagram showing a configuration example of a power conversion device. [Figure 2] It is a diagram showing a configuration example of a simulation system including a simulator according to the first embodiment. [Figure 3] It is a diagram showing a configuration example of a voltage sensor simulation circuit according to the first embodiment. [Figure 4] It is a diagram showing an inverter main circuit (for one phase). [Figure 5] It is a diagram showing an example of a table for generating the waveform of the arm voltage VuN. [Figure 6] It is a diagram showing the relationship between the polarity of the output current and the on-voltage of the arm element. [Figure 7] It is a diagram showing a circuit (for one phase) for calculating the on-voltage Von. [Figure 8] It is a diagram showing the relationship between the polarity of the output current and the on-voltage of the arm element. [Figure 9] It is a diagram showing the on-voltage characteristics with respect to the instantaneous value of the phase current. [Figure 10] It is a diagram showing a configuration example of a circuit for generating the arm voltage VuN. [Figure 11] It is a diagram showing an example of values output to DA1 and DA2. [Figure 12]It is a diagram showing the generation operation waveform of the arm voltage VuN (iu > 0). [Figure 13] It is a diagram showing the generation operation waveform of the arm voltage VuN (iu < 0). [Figure 14] It is a diagram showing the generation operation waveform of the arm voltage VuN (iu > i_th). [Figure 15] It is a diagram showing the generation operation waveform of the arm voltage VuN (-i_th ≤ iu ≤ i_th). [Figure 16] It is a diagram showing the generation operation waveform of the arm voltage VuN (iu < -i_th). [Figure 17] It is a diagram showing the relationship between the output current iu (phase current), a predetermined positive value "i_th", and a predetermined negative value "-i_th". [Figure 18] It is a diagram showing the operation waveform of the arm voltage VuN (iu > 0) when the output current iu is less than a predetermined value. [Figure 19] It is a diagram showing the operation waveform of the arm voltage VuN (iu < 0) when the output current iu is less than a predetermined value. [Figure 20] It is an equivalent circuit of an off-state arm element. [Figure 21] It is a diagram showing the state when the dead time period td1 (Figs. 18 and 19) starts immediately after the upper arm gate command changes from on to off. [Figure 22] It is a diagram showing the state when the dead time period td2 (Figs. 18 and 19) starts immediately after the lower arm gate command changes from on to off. [Figure 23] It is a diagram showing a first specific example of a simulation system including a simulator according to the first embodiment. [Figure 24] It is a configuration diagram of an arithmetic block that defines a main circuit model. [Figure 25] It is a diagram showing the generation logic of Iu_P1. [Figure 26] It is a diagram showing the generation logic of Iu_P2. [Figure 27] It is a diagram showing a generation table of the peak value VP(U) and the bottom value VN(U) of the arm voltage VuN. [Figure 28] This figure shows an example configuration of a voltage sensor simulation circuit equipped with a generation circuit. [Figure 29] This diagram shows the relationship between phase current and logic signals (iu_P1, iu_P2). [Figure 30] This diagram shows the logic for generating the switching signal for an analog switch. [Modes for carrying out the invention]

[0011] The embodiments will be described below.

[0012] <Power converter> Figure 1 shows an example configuration of a power conversion device. The power conversion device 101 shown in Figure 1 converts input power from a power source into AC power to drive a motor M. The power conversion device 101 shown in Figure 1 is used as a motor drive device to drive the motor M.

[0013] Motor M is an electric motor having multiple coils. For example, Motor M is a three-phase motor having U-phase coils, V-phase coils, and W-phase coils. Motor M is an induction motor, but it may also be a synchronous motor. Motor M is an example of a load to which power is supplied from a power converter.

[0014] The power converter 101 comprises a DC power supply 10, a power converter 20, a voltage sensor 40, and a control device 50. The control device 50 is located outside the housing of the power converter 101 and may be connected to the power converter 20 and the voltage sensor 40 by wire or wireless means.

[0015] The power converter 101 comprises a main circuit including a DC power supply 10 and a power converter 20. The DC power supply 10 supplies DC power to the power converter 20. The DC power supply 10 may include a converter that converts externally supplied AC or DC to DC, or a rectifier circuit that converts externally supplied AC to DC. The DC power supply 10 may include a DC link connecting the converter or rectifier circuit and the power converter 20.

[0016] The power converter 20 is an inverter circuit that converts the DC input from the DC power supply 10 into AC, and supplies the converted AC to the motor M. The power converter 20 has multiple arm elements Q_U, Q_V, Q_W, Q_X, Q_Y, and Q_Z. The multiple arm elements Q_U, Q_V, Q_W, Q_X, Q_Y, and Q_Z are switching elements that turn on or off according to the corresponding PWM control signal from among multiple PWM control signals Gu, Gv, Gw, Gx, Gy, and Gz supplied from the control device 50. PWM is an abbreviation for pulse width modulation.

[0017] In the following explanation, multiple arm elements Q_U, Q_V, Q_W, Q_X, Q_Y, and Q_Z may be collectively referred to as multiple arm elements Q. Alternatively, one of the multiple arm elements Q_U, Q_V, Q_W, Q_X, Q_Y, and Q_Z may be referred to as arm element Q.

[0018] The power converter 20 has arms for each phase between the positive bus P and the negative bus N, each containing at least one arm element Q. In this example, the power converter 20 has three phase arms 20u, 20v, and 20w. The U-phase arm 20u contains arm elements Q_U and Q_X. The V-phase arm 20v contains arm elements Q_V and Q_Y. The W-phase arm 20w contains arm elements Q_W and Q_Z.

[0019] The power converter 20 is a power conversion circuit that converts the input DC to AC by switching multiple arm elements Q. The power converter 20 rotates the rotor of the motor M by supplying AC drive current (three-phase drive current in the case of a three-phase motor M) to the motor M.

[0020] Multiple arm elements Q are semiconductor elements for power conversion. For example, each of the multiple arm elements Q is a switching element having a transistor and a diode (FWD) connected in antiparallel to that transistor. Specific examples of transistors include power semiconductors such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The diode may be a parasitic diode.

[0021] The voltage sensor 40 detects the output voltage (phase voltage) of each phase of the power converter 20. The voltage sensor 40 detects the phase voltages Vu, Vv, and Vw generated in each of the three-phase output lines connecting the three-phase power converter 20 and the three-phase motor M. In this example, the voltage sensor 40 detects the three-phase phase voltages Vu, Vv, and Vw by dividing them using resistors R1 and R2, and outputs the three-phase detection signals Vu_d, Vv_d, and Vw_d to the control device 50 by isolating the divided three-phase detection voltages with an isolation circuit. The three-phase detection signals Vu_d, Vv_d, and Vw_d represent the detected values ​​of the three-phase phase voltages Vu, Vv, and Vw.

[0022] The voltage sensor 40 may also be one that detects the phase voltage using other known detection methods.

[0023] The control device 50 generates multiple control signals to control the power converter 20. In this example, the control device 50 is a motor control circuit that generates multiple gate drive signals (PWM control signals Gu, Gv, Gw, Gx, Gy, Gz for each phase) to drive the gates of multiple arm elements Q in the power converter 20 that drive the motor M. The control device 50 may or may not include a gate driver. If the control device 50 does not include a gate driver, it supplies the multiple PWM control signals Gu, Gv, Gw, Gx, Gy, Gz to a gate driver included in the main circuit.

[0024] The control device 50 generates multiple PWM control signals Gu, Gv, Gw, Gx, Gy, and Gz to control the power converter 20, for example, by using V / f control to keep the ratio of the output voltage V to the output frequency f from the power converter 20 to the motor M constant. The control device 50 generates PWM control signals Gu, Gv, Gw, Gx, Gy, and Gz for each phase, for example, so that the deviation between the three-phase detection signals Vu_d, Vv_d, and Vw_d and a predetermined target output voltage value is zero. The control device 50 controls the ratio of the output voltage V to the output frequency f to keep it constant by supplying the PWM control signals Gu, Gv, Gw, Gx, Gy, and Gz thus generated to the corresponding arm elements Q of the power converter 20.

[0025] The control device 50 may also generate PWM control signals Gu, Gv, Gw, Gx, Gy, and Gz for each phase that control the power converter 20 by using vector control that utilizes the detected phase current values ​​of each phase based on detection by a current sensor (not shown).

[0026] <Simulator> Figure 2 shows a first configuration example of a simulation system equipped with a simulator according to the first embodiment. The simulation system 301 includes a control device 50 and a simulator 201. In the simulation system 301, the main circuit (DC power supply 10 and power converter 20), motor M, and voltage sensor 40 in Figure 1 are replaced by the simulator 201. The simulator 201 is a device that simulates the operating states of the main circuit and motor M in real time based on the PWM control signals Gu, Gv, Gw, Gx, Gy, and Gz for each phase input to the simulator 201 from the control device 50 of the actual machine. The simulator 201 is, for example, a HILS (Hardware In the Loop Simulator or Hardware In the Loop System).

[0027] Simulator 201 includes memory for storing programs that define a main circuit model 211 that simulates the operating state of the main circuit and a motor model 212 that simulates the operating state of motor M. Alternatively, simulator 201 includes an application-specific integrated circuit that defines the main circuit model 211 and motor model 212. Simulator 201 simulates the operating states of the main circuit and motor M, respectively, by executing such a program or by designing a circuit for such a specific application.

[0028] The simulator 201 feeds back the simulated operating state in real time to the control device 50 of the actual machine. The simulator 201 feeds back the output voltage of each phase of the power converter 20 as the simulated operating state. For this reason, a program or circuit is implemented in the simulator 201 that defines a voltage sensor model 213 that simulates the operating state of the voltage sensor 40 that detects the output voltage of each phase of the power converter 20. The voltage sensor model 213 generates sensor simulation signals Vu_det, Vv_det, and Vw_det (Figure 2) for each phase, which are signals that simulate the detection signals Vu_d, Vv_d, and Vw_d (Figure 1) output from the voltage sensor 40 for each phase.

[0029] This disclosure provides a technology for generating highly accurate sensor-simulated signals Vu_det, Vv_det, and Vw_det.

[0030] Figure 3 shows an example configuration of a voltage sensor simulation circuit according to the first embodiment. The voltage sensor simulation circuit 220 generates sensor simulation signals Vu_det, Vv_det, and Vw_det. The voltage sensor simulation circuit 220 is provided, for example, in the simulator 201 described above. The voltage sensor simulation circuit 220 comprises an arithmetic unit 60 and a generation circuit 70. The arithmetic unit 60 is a circuit that defines the main circuit model 211 and motor model 212 described above. The arithmetic unit 60 simulates the operating states of the power converter 20 and motor M based on the PWM control signals Gu, Gv, Gw, Gx, Gy, and Gz for each phase input from the control device 50. The generation circuit 70 is a circuit that defines the voltage sensor model 213 described above. Based on the calculation results by the arithmetic unit 60, the generation circuit 70 generates the sensor simulation signals Vu_det, Vv_det, and Vw_det for each phase to be output to the control device 50.

[0031] Figure 4 shows the inverter main circuit (for one phase). In the following explanation, the U-phase arm 20u will be used as a representative example. However, since the V-phase and W-phase have the same configuration, operation, and effects as the U-phase, the explanations for the V-phase and W-phase will be omitted by referring to the explanation for the U-phase.

[0032] The arithmetic unit 60 calculates the U-phase arm voltage VuN using the U-phase PWM control signals Gu,Gx that control the arm 20u, the polarity of the U-phase output current iu of the power converter 20, the DC bus voltage Edc between the positive bus P and the negative bus N, and the on-voltage Von of the arm element Q.

[0033] The PWM control signals Gu and Gx are real-time signals input from the control device 50. The PWM control signal Gu is input for controlling the switching of the upper arm element Q_U. The PWM control signal Gx is input for controlling the switching of the lower arm element Q_X.

[0034] The polarity of the output current iu indicates the direction in which the output current iu flows. A positive output current iu represents the U-phase current flowing out from the upper arm element Q_U or the lower arm element Q_X of arm 20u. A negative output current iu represents the U-phase current flowing into the upper arm element Q_U or the lower arm element Q_X of arm 20u.

[0035] The on-voltage Von represents the voltage between the main terminals of the upper arm element Q_U or the lower arm element Q_X when it is in the on state. The main terminals refer to the distance between the collector C and the emitter E, or between the drain D and the source S.

[0036] The arm voltage VuN is the voltage output from the midpoint 20m of the U-phase arm 20u in accordance with the U-phase PWM control signals Gu,Gx. The arm voltage VuN corresponds to the potential difference between the negative bus N and the midpoint 20m.

[0037] There is a relationship between the U-phase PWM control signals Gu,Gx, the polarity of the U-phase output current iu, the DC bus voltage Edc applied to arm 20u, and the on-voltage Von of arm element Q, as shown in Figure 5 (details of Figure 5 will be described later). Based on this relationship, the arithmetic unit 60 uses the U-phase PWM control signals Gu,Gx, the polarity of the U-phase output current iu, the DC bus voltage Edc applied to arm 20u, and the on-voltage Von of arm element Q to calculate the U-phase arm voltage VuN shown in Figure 5. Since the same relationship as shown in Figure 5 also holds for the V-phase and W-phase, the arithmetic unit 60 generates the V-phase arm voltage VvN and the W-phase arm voltage VwN using the same generation method as for the U-phase arm voltage VuN. The generation circuit 70 generates sensor simulation signals Vu_det, Vv_det, and Vw_det for each phase, which represent the detected values ​​of the three-phase phase voltages Vu, Vv, and Vw, by substituting the generated arm voltages VuN, VvN, and VwN into the following equations (1) to (3).

[0038]

number

[0039] Thus, the voltage sensor simulation circuit 220 according to the first embodiment generates the sensor simulation signals Vu_det, Vv_det, and Vw_det for each phase by executing a voltage sensor simulation method that utilizes the relationship shown in Figure 5 and equations (1) to (3).

[0040] <Method for simulating voltage sensors> Next, we will explain in detail the voltage sensor simulation method performed by the voltage sensor simulation circuit 220. The voltage sensor simulation method utilizes the relationship shown in Figure 5 and equations (1) to (3), so first we will explain the principle by which equations (1) to (3) hold true.

[0041] In explaining the principle by which equations (1) to (3) hold true, we will explain the relationship between the phase voltage Vu of the U-phase and the arm voltage VuN of the U-phase as a representative example, but the same considerations can be applied to the V-phase and W-phase.

[0042] The phase voltage Vu can be decomposed into the arm voltage VuN and the negative electrode potential VN0 (see Figure 1), as shown in equation (4). The negative electrode potential VN0 is the potential of the negative electrode bus N (N potential) as seen from the neutral point 41 of the three-phase load. The zero-sequence voltage V0 represents the voltage to ground at the neutral point 41. The negative electrode potential VN0 as seen from the neutral point 41 can be transformed using the arm voltages VuN, VvN, and VwN as shown in equation (5). Substituting equation (5) into equation (4) yields equation (6).

[0043]

number

[0044] Thus, according to equation (6), equation (1) above holds true. Similarly, if we consider the V phase and the W phase, we can see that equations (2) and (3) above also hold true.

[0045] Next, we will explain the principle by which Figure 5 holds true (that is, the calculation principle for the arm voltages VuN, VvN, and VwN) with reference to Figure 4.

[0046] In Figure 4, the output point U conducts to the positive busbar P via the upper arm element Q_U when the upper arm element Q_U is turned ON, and conducts to the negative busbar N via the lower arm element Q_X when the lower arm element Q_X is turned ON.

[0047] During the dead time period, which is inserted to prevent short circuits between the upper and lower arms, both the upper and lower arm elements are instructed to gate off. During this dead time period, the conduction of the diode is determined by the polarity of the output current iu, so whether the diode of the upper arm element Q_U or the diode of the lower arm element Q_X turns on is determined by the polarity of the output current iu.

[0048] When current flows between the main terminals of the arm element Q, an on-voltage Von is generated, as shown in Figure 6. The direction of the on-voltage Von is determined by the direction of the current flowing through the arm element Q. Therefore, with the emitter E as the reference, the on-voltage Von is "+Von" when the current flows from the collector C to the emitter E (current polarity A), and "-Von" when the current flows from the emitter E to the collector C (current polarity B).

[0049] These results indicate that the arm voltage VuN is determined by the relationship shown in Figure 5, depending on the PWM control signals Gu,Gx of arm 20u and the polarity of the output current iu of arm 20u. In other words, as shown in Figure 5, the arm voltage VuN is determined by nine different operating states, which are determined by the state of the PWM control signals Gu,Gx and the polarity of the output current iu.

[0050] For example, during the period when an upper arm-on command is input to gate G, in which the PWM control signal Gu is ON and the PWM control signal Gx is OFF, the upper arm element Q_U is ON and the lower arm element Q_X is OFF. Therefore, the arm voltage VuN during the upper arm-on command period is defined as "Edc-Von" when the output current iu is positive, and as "Edc+Von" when the output current iu is negative. At the moment when the output current iu crosses zero, it can be said that there is no voltage drop across the arm element Q, so the arm voltage VuN during the upper arm-on command period is defined as Edc.

[0051] During the period when a lower arm-on command is input to gate G, in which the PWM control signal Gu is off and the PWM control signal Gx is on, the upper arm element Q_U is in the off state and the lower arm element Q_X is in the on state. Therefore, the arm voltage VuN during the lower arm-on command period is defined as "-Von" when the output current iu is positive, and as "Von" when the output current iu is negative. At the moment when the output current iu crosses zero, it can be said that there is no voltage drop across the arm element Q, so the arm voltage VuN during the lower arm-on command period is defined as "0".

[0052] During the period when a dead time command is input to gate G, which turns off both the PWM control signal Gu and the PWM control signal Gx, the upper arm Q_U is in the off state and the lower arm Q_X is also in the off state. Therefore, the arm voltage VuN during the dead time period is defined as "-Von" when the output current iu is positive due to the conduction of the diode of the lower arm element Q_X, and as "Edc+Von" when the output current iu is negative due to the conduction of the diode of the upper arm element Q_U. The arm voltage VuN when the output current iu crosses zero during the dead time period retains its "previous value". The "previous value" refers to Edc during the upper arm on command period when transitioning from the upper arm on command period to the dead time period, and to 0 during the lower arm on command period when transitioning from the lower arm on command period to the dead time period.

[0053] Similarly, the arm voltage VvN of the V phase follows the same relationship as in Figure 5, depending on the polarity of the PWM control signals Gv,Gy of arm 20v and the output current iv of arm 20v. The arm voltage VwN of the W phase follows the same relationship as in Figure 5, depending on the polarity of the PWM control signals Gw,Gz of arm 20w and the output current iw of arm 20w.

[0054] Therefore, based on the relationship shown in Figure 5, the arithmetic unit 60 can generate the arm voltages VuN, VvN, and VwN for each phase, which are output from the arm of each phase in accordance with the PWM control signal of each phase, using the PWM control signal of each phase, the polarity of the output current of each phase, the DC bus voltage Edc, and the on-voltage Von. The generation circuit 70 can then generate the sensor simulation signals Vu_det, Vv_det, and Vw_det for each phase, which represent the detected values ​​of the three-phase voltages Vu, Vv, and Vw, by adding or subtracting the generated arm voltages VuN, VvN, and VwN according to equations (1) to (3) above.

[0055] Thus, in the first embodiment, the arithmetic unit 60 generates the arm voltages VuN, VvN, and VwN for each phase while considering the on-voltage Von, so it can generate the arm voltages VuN, VvN, and VwN for each phase with higher accuracy compared to when the on-voltage Von is not considered. The generation circuit 70 then adds and subtracts the arm voltages VuN, VvN, and VwN for each phase, so it can generate the sensor simulation signals Vu_det, Vv_det, and Vw_det for each phase with higher accuracy compared to when the on-voltage Von is not considered. Therefore, the three-phase detection signals Vu_d, Vv_d, and Vw_d of the voltage sensor 40 can be simulated with high accuracy.

[0056] In the case of Figure 5, the arithmetic unit 60 calculates the arm voltage VuN, which is corrected by the polarity of the output current iu and the on-voltage Von of the arm element Q. The arm voltage VuN is a voltage corrected by the on-voltage Von, and its correction sign (the sign assigned to the on-voltage Von) is determined by the polarity of the current iu. The same applies to the arm voltages VvN and VwN. Therefore, the generation circuit 70 generates the sensor simulation signals Vu_det, Vv_det, and Vw_det for each phase using the arm voltages VuN, VvN, and VwN corrected by the output current polarity and the on-voltage Von, so that the detection signals Vu_d, Vv_d, and Vw_d can be simulated with high accuracy.

[0057] In the case of Figure 5, the arithmetic unit 60 corrects the arm voltage VuN during the period when the upper arm element Q_U is turned on in response to the PWM control signal Gu, and the arm voltage VuN during the period when the lower arm element Q_X is turned on in response to the PWM control signal Gx, using the polarity of the current iu and the on-voltage Von of the arm element Q. The same applies to the arm voltages VvN and VwN. By adopting these corrected voltages as the arm voltages VuN, VvN, and VwN for each of these periods, the generation circuit 70 can generate highly accurate sensor simulation signals Vu_det, Vv_det, and Vw_det for each phase.

[0058] For example, the arithmetic unit 60 sets the arm voltage VuN when a positive current iu flows during the upper arm-on command period to a voltage value obtained by adding the on-voltage "-Von" to the DC bus voltage Edc. The arithmetic unit 60 sets the arm voltage VuN when a negative current iu flows during the upper arm-on command period to a voltage value obtained by adding the on-voltage "+Von" to the DC bus voltage Edc. The arithmetic unit 60 sets the arm voltage VuN when the current iu is zero during the upper arm-on command period to the value of the DC bus voltage Edc. This DC bus voltage Edc corresponds to the voltage of the positive bus P (positive voltage).

[0059] For example, the arithmetic unit 60 sets the arm voltage VuN when a positive current iu flows during the lower arm-on command period to a voltage value obtained by adding the on-voltage "-Von" to the zero voltage. The arithmetic unit 60 sets the arm voltage VuN when a negative current iu flows during the lower arm-on command period to a voltage value obtained by adding the on-voltage "+Von" to the zero voltage. The arithmetic unit 60 sets the arm voltage VuN when the current iu is zero during the lower arm-on command period to the value of the zero voltage. This zero voltage corresponds to the voltage of the negative bus N (negative voltage).

[0060] In the case of Figure 5, the arithmetic unit 60 corrects the arm voltage VuN during the dead time period by the polarity of the current iu and the on-voltage Von of the arm element Q. The same applies to the arm voltages VvN and VwN. By adopting these corrected voltages as the arm voltages VuN, VvN, and VwN during each of these periods, the generation circuit 70 can generate highly accurate sensor simulation signals Vu_det, Vv_det, and Vw_det for each phase.

[0061] For example, the arithmetic unit 60 sets the arm voltage VuN when a positive current iu is flowing during the dead time period to a voltage value obtained by adding the on-voltage "-Von" to the zero voltage. The arithmetic unit 60 sets the arm voltage VuN when a negative current iu is flowing during the dead time period to a voltage value obtained by adding the on-voltage "+Von" to the DC bus voltage Edc. The arithmetic unit 60 sets the arm voltage VuN when the current iu is zero during the dead time period to the previous value.

[0062] The arithmetic unit 60 may simulate the output current iu output from the power converter 20 in response to the PWM control signal, and may use the polarity of the simulated output current iu in the calculation of the arm voltage Vu. Using the polarity of the simulated output current iu in the calculation of the arm voltage Vu improves the accuracy of the calculation of the arm voltage Vu.

[0063] <Method for determining the on-voltage Von> Next, we will describe the method and circuit for determining the on-voltage Von. The following description will primarily focus on the method and circuit for determining the on-voltage Von of the U-phase, but the same applies to the V-phase and W-phase.

[0064] The arithmetic unit 60 may determine the on-voltage Von corresponding to the calculated value of the output current of the power converter 20 based on the relationship between the output current and the on-voltage Von, and use the determined on-voltage Von in the calculation of the arm voltages VuN, VvN, and VwN. This ensures that an appropriate on-voltage Von corresponding to the difference in the output current of the power converter 20 is used in the calculation of the arm voltages VuN, VvN, and VwN. Therefore, the arithmetic unit 60 can calculate highly accurate arm voltages VuN, VvN, and VwN, and the generation circuit 70 can generate highly accurate sensor simulation signals Vu_det, Vv_det, and Vw_det.

[0065] Figure 7 shows the circuit (for one phase) for calculating the on-voltage Von. In the following, the circuit for calculating the on-voltage Von of the U phase will be described as representative. However, since the V and W phases have the same configuration, operation, and effects as the U phase, the explanations for the V and W phases will be omitted by referring to the explanation for the U phase.

[0066] The arithmetic unit 60 includes an inverter simulator unit 61, a motor simulator unit 62, an instantaneous value circuit 63, and an on-voltage characteristic 64. The inverter simulator unit 61 simulates the phase voltages Vu1, Vv1, and Vw1 of each phase output from the power converter 20 to the motor M in accordance with the PWM control signals of each phase. The motor simulator unit 62 simulates the motor currents (output currents iu, iv, and iw) of each phase flowing through the motor M based on the phase voltages Vu1, Vv1, and Vw1 simulated by the inverter simulator unit 61. The instantaneous value circuit 63 outputs the instantaneous values ​​of the motor currents iu, iv, and iw of each phase. The on-voltage characteristic 64 is data that defines the relationship between the instantaneous values ​​of the motor currents iu, iv, and iw of each phase and the on-voltage Von.

[0067] The arithmetic unit 60 determines the on-voltage Von to be used in calculating the arm voltage based on the on-voltage characteristics 64 of the transistor and diode, which are stored in memory in advance, and the instantaneous value of the motor current simulated by the motor simulator unit 62. For example, the arithmetic unit 60 determines the on-voltage Von_U to be used in calculating the U-phase arm voltage VuN based on the on-voltage characteristics that define the relationship between the instantaneous value of the U-phase motor current iu and the on-voltage Von of the IGBT. (IGBT) The arithmetic unit 60 determines the on-voltage Von_U used to calculate the U-phase arm voltage VuN, based on the on-voltage characteristics that define the relationship between the instantaneous value of the U-phase motor current iu and the on-voltage Von of the FWD. (FWD) To decide.

[0068] In the inverter configuration shown in Figure 4, the current flowing through the arm element Q, focusing on the upper arm element, flows through the IGBT when iu > 0 and through the FWD when iu < 0. Therefore, the on-voltage Von_U changes depending on the polarity of the current iu. (IGBT) or on-voltage Von_U (FWD) One of these occurs as the on-voltage Von (see Figure 8).

[0069] Figure 9 shows the on-voltage characteristics with respect to the instantaneous phase current. The on-voltage Von depends on the characteristics inherent to the arm element Q, the current value through which the arm element Q flows, and the junction temperature of the arm element Q. Therefore, the arithmetic unit 60 can calculate highly accurate arm voltages VuN, VvN, and VwN by calculating the on-voltage Von of each arm element Q from the simulated instantaneous output current and the pre-stored on-voltage characteristics.

[0070] The arithmetic unit 60 estimates the junction temperature of the arm element Q using a known method. By correcting the on-voltage characteristic Von according to the estimated junction temperature, the arithmetic unit 60 can calculate a highly accurate on-voltage Von corrected by the junction temperature.

[0071] <Waveform generation circuit for arm voltages VuN, VvN, and VwN> Next, we will describe the circuits that generate the waveforms of the arm voltages VuN, VvN, and VwN. In the following, we will describe the circuit that generates the waveform of the U-phase arm voltage VuN as a representative example, but the V-phase and W-phase circuits are similar.

[0072] Figure 10 shows an example of a circuit configuration for generating the arm voltage VuN. The arithmetic unit 60 uses the PWM control signals for each phase, the polarity of the output current for each phase, the DC bus voltage Edc, and the on-voltage Von to calculate the peak value VP and bottom value VN of the arm voltage for each phase. The arithmetic unit 60 outputs these calculation results using two D / A (Digital to Analog) converters per phase. The arithmetic unit 60 has a first D / A converter that outputs the peak value VP and a second D / A converter that outputs the bottom value VN. Hereinafter, the first D / A converter may be referred to as DA1 and the second D / A converter as DA2.

[0073] Based on the relationship shown in Figure 11, the arithmetic unit 60 calculates the peak value VP and bottom value VN of the U-phase arm voltage VuN using the U-phase PWM control signal, the polarity of the U-phase output current iu, the DC bus voltage Edc, and the on-voltage Von. In a similar manner, the arithmetic unit 60 calculates the peak value VP and bottom value VN of the V-phase arm voltage VvN, and also calculates the peak value VP and bottom value VN of the W-phase arm voltage VwN. The values ​​shown in Figure 11 are the same as the values ​​shown in Figure 5. The method for calculating the peak value VP and bottom value VN of the arm voltage VuN based on the relationship shown in Figure 11 is the same as the method described above for calculating the peak value VP and bottom value VN of the arm voltage VuN based on the relationship shown in Figure 5. In the case of Figure 11, the arithmetic unit 60 calculates values ​​(peak value VP and bottom value VN) corrected by the polarity of the output current iu and the on-voltage Von of the arm element Q.

[0074] Based on the relationship shown in Figure 11, the arithmetic unit 60 outputs the calculated value of the voltage of the positive bus P (DC bus voltage Edc), corrected by the polarity of the output current iu and the on-voltage of the arm element Q, as the peak value VP from DA1. Based on the relationship shown in Figure 11, the arithmetic unit 60 outputs the calculated value of the voltage of the negative bus N (zero voltage), corrected by the polarity of the output current iu and the on-voltage of the arm element Q, as the bottom value VN from DA2.

[0075] The generation circuit 70 has a switching logic circuit 71 that switches the peak value VP for the U phase and the bottom value VN for the U phase to each other using a complementary switch 72 in response to the U phase PWM control signals Gu,Gx. The generation circuit 70 generates a signal for the U phase arm voltage VuN by switching the peak value VP for the U phase and the bottom value VN for the U phase to each other using the complementary switch 72 in response to the U phase PWM control signals Gu,Gx. The generation circuit 70 has an arm voltage VvN generation circuit and an arm voltage VwN generation circuit, which have the same configuration as the arm voltage VuN generation circuit.

[0076] <Method for generating the first waveform of arm voltages VuN, VvN, and VwN> Next, we will explain the method for generating the first waveforms of the arm voltages VuN, VvN, and VwN. Below, we will explain the method for generating the waveform of the U-phase arm voltage VuN as a representative example, but the V-phase and W-phase are similar.

[0077] Figure 12 shows the waveform of the arm voltage VuN generation operation (iu>0). Figure 13 shows the waveform of the arm voltage VuN generation operation (iu<0). The generation circuit 70 generates the signal waveform of the arm voltage VuN by selecting either the peak value VP output from DA1 or the bottom value VN output from DA2 according to the PWM control signals Gu,Gx. The switching logic circuit 71 of the generation circuit 70 generates the signal waveform of the arm voltage VuN by switching between the peak value VP output from DA1 and the bottom value VN output from DA2 using the edges of the PWM control signals Gu,Gx. The switching logic circuit 71 generates the signal waveform of the arm voltage VuN by switching between the peak value VP and the bottom value VN according to the PWM control signals Gu,Gx and the value of the output current iu.

[0078] When the output current iu is a positive current value as shown in Figure 12, the switching logic circuit 71 generates a signal waveform of the arm voltage VuN by switching between a peak value VP and a bottom value VN in accordance with the PWM control signal Gu that controls the upper arm element Q_U included in the arm 20u. When the output current iu is a positive current value, the switching logic circuit 71 detects an edge of the PWM control signal Gu that turns on the upper arm element Q_U and switches the D / A converter that determines the level of the arm voltage VuN from DA2 to DA1. As a result, the level of the signal waveform of the arm voltage VuN switches from the bottom value VN to the peak value VP. When the output current iu is a positive current value, the switching logic circuit 71 detects an edge of the PWM control signal Gu that turns off the upper arm element Q_U and switches the D / A converter that determines the level of the arm voltage VuN from DA1 to DA2. As a result, the level of the signal waveform of the arm voltage VuN switches from the peak value VP to the bottom value VN.

[0079] When the output current iu is a negative current value as shown in Figure 13, the switching logic circuit 71 generates a signal waveform of the arm voltage VuN by switching between a peak value VP and a bottom value VN in accordance with the PWM control signal Gx that controls the lower arm element Q_X included in the arm 20u. When the output current iu is a negative current value, the switching logic circuit 71 detects the edge of the PWM control signal Gx that turns on the lower arm element Q_X and switches the D / A converter that determines the level of the arm voltage VuN from DA1 to DA2. As a result, the level of the signal waveform of the arm voltage VuN switches from a peak value VP to a bottom value VN. When the output current iu is a negative current value, the switching logic circuit 71 detects the edge of the PWM control signal Gx that turns off the lower arm element Q_X and switches the D / A converter that determines the level of the arm voltage VuN from DA2 to DA1. As a result, the level of the signal waveform of the arm voltage VuN switches from a peak value VP to a bottom value VN. As a result, the signal waveform level of the arm voltage VuN switches from the bottom value VN to the peak value VP.

[0080] Similarly, the generation circuit 70 generates a signal for the V-phase arm voltage VvN by switching between the peak value VP and the bottom value VN for the V-phase in response to the V-phase PWM control signals Gv and Gy. Similarly, the generation circuit 70 generates a signal for the W-phase arm voltage VvW by switching between the peak value VP and the bottom value VN for the W-phase in response to the W-phase PWM control signals Gw and Gz.

[0081] Thus, the voltage values ​​(values ​​in the amplitude direction) of the arm voltages VuN, VvN, and VwN are generated by arithmetic calculations performed by the arithmetic unit 60, and the pulse widths in the time direction of the arm voltages VuN, VvN, and VwN are generated by the edge input of the PWM control signal input to the generation circuit 70. Since the pulse width generation process, which requires high speed, is separated from the arithmetic calculation process that generates the voltage values ​​(amplitude values), the delay in waveform generation of the arm voltages VuN, VvN, and VwN can be shortened, and highly accurate sensor simulation signals can be generated.

[0082] <Method for generating the second waveform of arm voltages VuN, VvN, and VwN> Next, we will explain the method for generating the second waveforms of the arm voltages VuN, VvN, and VwN. Below, we will explain the method for generating the waveform of the U-phase arm voltage VuN as a representative example, but the V-phase and W-phase waveforms are similar.

[0083] Figure 14 shows the waveform of the arm voltage VuN generation operation (iu > i_th). Figure 15 shows the waveform of the arm voltage VuN generation operation (-i_th ≤ iu ≤ i_th). Figure 16 shows the waveform of the arm voltage VuN generation operation (iu < -i_th). i_th is a predetermined value determined by the characteristics of the arm element Q. Figure 17 shows the relationship between the output current iu (phase current) and predetermined positive value "i_th" and predetermined negative value "-i_th".

[0084] When the output current iu is a positive current value greater than a predetermined positive value "i_th", the switching logic circuit 71 generates a signal waveform of the arm voltage VuN by switching between the peak value VP and the bottom value VN in accordance with the PWM control signal Gu that controls the upper arm element Q_U included in the arm 20u. In the case of Figure 14, the signal waveform of the arm voltage VuN is generated by the same method as described above as in the case of Figure 12. In Figure 14, the generation circuit 70 generates a signal waveform of the arm voltage VuN having pulses with the same width as the pulse width of the PWM control signal Gu by utilizing both edges of the PWM control signal Gu.

[0085] When the output current iu is a negative current value smaller than a predetermined negative value "-i_th", the switching logic circuit 71 generates a signal waveform of the arm voltage VuN by switching between a peak value VP and a bottom value VN in accordance with the PWM control signal Gx that controls the lower arm element Q_X included in the arm 20u, as shown in Figure 16. In the case of Figure 16, the signal waveform of the arm voltage VuN is generated by the same method as described above as in the case of Figure 13. In Figure 16, the generation circuit 70 generates a signal waveform of the arm voltage VuN having pulses with the same width as the pulse width of the PWM control signal Gx by utilizing both edges of the PWM control signal Gx.

[0086] When the output current iu is greater than or equal to a negative value "-i_th" and less than or equal to a positive value "i_th", as shown in Figure 15, the switching logic circuit 71 generates a signal waveform of the arm voltage VuN by switching between a peak value VP and a bottom value VN according to the edge of the PWM control signal Gu that turns on the upper arm element Q_U and the edge of the PWM control signal Gx that turns on the lower arm element Q_X. When -i_th ≤ iu ≤ i_th, the switching logic circuit 71 detects the edge of the PWM control signal Gu that turns on the upper arm element Q_U and switches the D / A converter that determines the level of the arm voltage VuN from DA2 to DA1. As a result, the level of the signal waveform of the arm voltage VuN switches from the bottom value VN to the peak value VP. When -i_th ≤ iu ≤ i_th, the switching logic circuit 71 detects the edge of the PWM control signal Gx that turns on the lower arm element Q_X and switches the D / A converter that determines the level of the arm voltage VuN from DA1 to DA2. As a result, the signal waveform level of the arm voltage VuN switches from the peak value VP to the bottom value VN. In Figure 15, the generation circuit 70 uses both rising edges of the PWM control signals Gu and Gx to generate a signal waveform of the arm voltage VuN having a pulse width equal to the pulse width of the PWM control signal Gu plus the dead time td. Thus, in Figure 15, the level of the arm voltage VuN during the dead time period is the same as the level in the period immediately preceding the dead time period.

[0087] Here, we will explain the displacement of the arm voltage VuN during the dead time period. Figure 18 shows the operating waveform of the arm voltage VuN when the output current iu is less than a predetermined value (iu>0). Figure 19 shows the operating waveform of the arm voltage VuN when the output current iu is less than a predetermined value (iu<0). td1 and td2 indicate the dead time period. During the dead time period, the upper and lower arm elements are in the off state.

[0088] Figure 20 shows the equivalent circuit of the arm element in the off state. The arm element in the off state can be equivalently replaced with a capacitor because there is parasitic capacitance between the collector C and emitter E of the IGBT.

[0089] Figure 21 shows the state at the start of the dead time period td1 (Figures 18 and 19) immediately after the upper arm gate command changes from on to off. Since the upper arm element was on immediately before the dead time period td1, the voltage between the CE of the upper arm element is zero, while the voltage between the CE of the lower arm element is charged with the DC bus voltage Edc. In this case, if the output current iu is less than a predetermined value ith, the arm voltage VuN during the dead time period td1 is maintained at approximately the voltage immediately before the start of the dead time period td1 (i.e., Edc).

[0090] Figure 22 shows the state at the start of the dead time period td2 (Figures 18 and 19) immediately after the lower arm gate command changes from on to off. Since the lower arm element was on immediately before the dead time period td2, the CE-CE of the upper arm element is charged with the DC bus voltage Edc, while the CE-CE of the lower arm element is at zero voltage. In this case, if the absolute value of the output current iu is less than a predetermined value ith, the arm voltage VuN during the dead time period td2 will be held approximately at the voltage immediately before the start of the dead time period td2 (i.e., zero voltage).

[0091] Thus, when the output current iu is less than a predetermined value ith, regardless of the polarity of the output current iu, the pulse width of the arm voltage VuN and its generation timing become equivalent to the pulse width tu obtained by extending the PWM control signal of the upper arm by a dead time td of 1 minute. Therefore, when -i_th ≤ iu ≤ i_th, the generation circuit 70 reduces the load of calculating the arm voltage level during the dead time period by setting the level of the arm voltage VuN during the dead time period to the same level as the level of the period immediately preceding the dead time period. This reduction in computational load suppresses the occurrence of waveform distortion due to delays in the generation of the arm voltage waveform.

[0092] <First specific example of a simulation system equipped with a simulator> Figure 23 shows a first specific example of a simulation system equipped with a simulator according to the first embodiment. The simulation system 301 according to the first specific example simulates the inverter main circuit and the motor (induction motor) based on the PWM control signals Gu, Gv, Gw, Gx, Gy, and Gz supplied from the control device 50.

[0093] The control device 50 is a motor control circuit that outputs PWM control signals Gu, Gv, Gw, Gx, Gy, and Gz to drive the inverter main circuit in a V / f control manner according to an externally provided frequency command f*. The control device 50 performs voltage feedback control to generate the PWM control signals Gu, Gv, Gw, Gx, Gy, and Gz based on the simulated sensor signals Vu_det, Vv_det, and Vw_det for each phase that are fed back from the simulator 201.

[0094] The simulator 201 includes a calculation block 214 to which a PWM control signal output from the control device 50 is input, and a calculation block 215 to which the calculation result from the calculation block 214 is input.

[0095] The arithmetic block 214 is a circuit that defines the main circuit model. Based on the PWM control signals Gu, Gv, Gw, Gx, Gy, and Gz, the arithmetic block 214 outputs calculated values ​​(Vu_cal, Vv_cal, Vw_cal) of the phase voltages Vu, Vv, and Vw output from the power converter 20.

[0096] The calculation block 215 is a circuit that defines the motor model. Based on the calculated values ​​(Vu_cal, Vv_cal, Vw_cal), the calculation block 215 calculates the motor current (output current iu, iv, iw) and torque. The calculation block 215 outputs the calculated motor current values ​​(iu_cal, iv_cal, iw_cal) and the calculated torque value τ_cal to the D / A converter 216. The calculated values ​​(iu_cal, iv_cal, iw_cal) and the calculated torque value τ_cal are converted to analog values ​​by the D / A converter 216 and monitored by measuring instruments (not shown).

[0097] The peak value VP and bottom value VN of the arm voltage pulses for each phase are calculated by the calculation block 214, and these calculation results are converted into analog voltage values ​​VPA and VNA by the D / A converter 217. The generation circuit 70 receives the analog voltage values ​​VPA and VNA and the PWM control signals Gu, Gv, Gw, Gx, Gy, and Gz as inputs. The generation circuit 70 generates sensor simulation signals Vu_det, Vv_det, and Vw_det from the analog voltage values ​​VPA and VNA and the PWM control signals Gu, Gv, Gw, Gx, Gy, and Gz. The generated sensor simulation signals Vu_det, Vv_det, and Vw_det are input to the control device 50 as voltage feedback values.

[0098] The calculations performed in arithmetic block 214 and arithmetic block 215, as described below, are processed by the CPU, for example. Next, each block will be explained.

[0099] <Operation block that defines the main circuit model> Figure 24 is a diagram of the arithmetic block 214 that defines the main circuit model 211. The main circuit model 211 shown in Figure 24 is composed of a programming language and is calculated by the CPU. The arithmetic block 214 calculates the calculated values ​​Vu_cal, Vv_cal, and Vw_cal for each phase voltage by performing arithmetic operations using equations (7) to (9) based on the calculation results output by the arm voltage calculation blocks for each phase.

[0100]

number

[0101] The calculated voltage values ​​for each phase, Vu_cal, Vv_cal, and Vw_cal, are input into the calculation block that defines the motor model. The following explanation will use the U phase as a representative example.

[0102] Each phase arm voltage calculation block generates an arm voltage VuN with a peak value VP(U) and a bottom value VN(U), described later, at the timings shown in Figures 12 and 13, based on the input PWM control signal and the calculated output current. The peak value VP(U) and bottom value VN(U) calculated by the arm voltage calculation block are also used in the generation circuit 70 shown in Figure 23, and are therefore output outside the calculation block 214. The calculation block 214 in Figure 24 generates and outputs the output current polarity signals (Iu_P1, Iv_P1, Iw_P1) and the inverter's small output current signals (Iu_P2, Iv_P2, Iw_P2) using logic described later.

[0103] Figure 25 shows the generation logic for Iu_P1. Iu_P1 is a signal indicating the polarity of iu_cal. Figure 26 shows the generation logic for Iu_P2. Iu_P2 is a signal indicating whether the absolute value of iu_cal is less than or equal to a predetermined value ith.

[0104] Here, in the arm voltage calculation block of Figure 24, the aforementioned peak value VP(U) and bottom value VN(U) are determined as shown in Figure 27, according to the calculated current value iu_cal. The assumed value of the DC bus voltage is pre-assigned to Edc. Von_U(IGBT) and Von_U(FWD) are determined from the instantaneous value of the calculated current value iu_cal and the on-voltage characteristics shown in Figure 9.

[0105] Although not shown in the diagram, the on-voltage characteristics may be modified to include temperature dependence by using the on-voltage characteristics with the temperature of the arm element as a parameter and the detected value of that temperature.

[0106] <Operation block that defines the motor model> The input of the arithmetic block 215 shown in FIG. 23 is the phase voltage calculation values (Vu, Vv, Vw) calculated by the aforementioned arithmetic block 214. The motor model is configured in the same programming language as the main circuit model and is calculated by the same microcomputer as the arithmetic block 214. The arithmetic block 215 calculates and outputs the motor current and torque respectively by using the following equations (10) to (14). The motor constants in the following equations (10) to (14) are stored in advance in the memory of the CPU.

[0107] It is known that the voltage-current equation of an induction motor is expressed by Equation (10).

[0108]

Number

[0109] When Equation (10) is rearranged with respect to the current, it is transformed into Equation (11). This equation is a differential equation for i αs , i βs , i αr , i βr . By solving this, the motor current with respect to the motor input voltage can be calculated. Since it is widely known that the calculation means of this differential equation can be realized by using the Euler method, the Runge-Kutta method, etc., a detailed explanation is omitted. Also, since the voltage input from the main circuit model is a three-phase quantity, it is converted into two-phase voltage by using Equation (12) and substituted into Equation (11).

[0110] By substituting the calculation results (i αs , i βs ) of Equation (11) into Equations (13) and (14), the three-phase motor current (iu_cal, iv_cal, iw_cal) and the motor generated torque are obtained.

[0111]

Number

[0112] Here, Vu, Vv, and Vw are the calculated three-phase stator voltage values ​​input to this block, iu_cal, iv_cal, and iw_cal are the calculated three-phase stator current values ​​output by this block, and τ is the calculated motor output torque value output by this block. These outputs are input to the D / A converter 216, converted to analog voltages, and monitored by measuring instruments, etc.

[0113] <Generation circuit> Next, the generation circuit 70 shown in Figure 23 will be described. The aforementioned arithmetic block 214 calculates the output voltage using software (CPU). On the other hand, in order to minimize the waveform generation delay, the generation circuit 70 calculates the voltage value in the amplitude direction, which requires arithmetic calculations, using software (CPU), and generates the pulse width in the time width direction using the edges of the PWM control signal.

[0114] The generation circuit 70 generates the simulated sensor signals Vu_det, Vv_det, and Vw_det for each phase using equations (1) to (3). The following explanation will use the U phase as a representative example, but the process is similar for the other phases.

[0115] Figure 28 shows an example configuration of a voltage sensor simulation circuit equipped with a generation circuit. The peak value VP(U) and bottom value VN(U) are digital values ​​obtained by the calculation block 214 that defines the main circuit model. These digital values ​​are converted into analog electrical signals by the D / A converter 217.

[0116] The peak value VP(U) and bottom value VN(U), converted into analog electrical signals, are switched and output from the analog switch 2 by a switching signal Qu generated by the switching logic circuit 71, thereby obtaining the arm voltage VuN.

[0117] The generation circuit 70 includes an addition / subtraction circuit that implements the above equations (1) to (3). The addition / subtraction circuit generates the sensor simulation signals Vu_det, Vv_det, and Vw_det for each phase when the generated VuN, VvN, and VwN are input. The addition / subtraction circuit that implements the above equations (1) to (3) is realized by a known circuit formed by a plurality of operational amplifiers 1 as shown in FIG. 28. The voltage sensor simulation signals Vu_det, Vv_det, and Vw_det thus obtained are output as feedback signals to the control device 50.

[0118] Next, a method for generating the switching signal Qu of the analog switch 2 will be described.

[0119] FIG. 29 is a diagram showing the relationship between the phase current and the logic signals (iu_P1, iu_P2). The arithmetic unit 60 sets iu_P1 to "0" when iu_cal < -i_th, and sets iu_P1 to "1" when iu_cal > i_th. The arithmetic unit 60 sets iu_P1 to "1" when -i_th ≤ iu_cal < i_th, and sets iu_P1 to "0" in other ranges. The arithmetic unit 60 sets iu_P2 to "1" when -i_th ≤ iu_cal < i_th, and sets iu_P2 to "0" in other ranges. By combining these signals, three ranges A1, A2, and A3 shown in FIG. 30 are obtained. The switching logic circuit 71 generates the switching signal Qu of the analog switch 2 in each range.

[0120] As described above, the embodiments have been described. However, the above embodiments are presented as examples, and the present invention is not limited by the above embodiments. The above embodiments can be implemented in various other forms, and various combinations, omissions, replacements, changes, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalent scope.

[0121] For example, the arm element is not limited to power transistors such as IGBTs or MOSFETs, but may also be a diode, thyristor, gate turn-off thyristor, triac, etc. [Explanation of symbols]

[0122] 10 DC power supply 20 Power Converters 40 Voltage Sensor 50 Control device 60 Arithmetic unit 61 Inverter Simulator Section 62 Motor Simulator Section 63 Instantaneous Value Circuit 64 On-voltage characteristics 70 Generation circuit 101 Power converter 201 Simulator 211 Main Circuit Model 212 Motor Models 213 Voltage Sensor Model 214,215 arithmetic blocks 220 Voltage Sensor Simulation Circuit 301 Simulation System

Claims

1. A power converter having phase arms, each containing an arm element, between a positive bus and a negative bus, is controlled by a PWM control signal for each phase, the polarity of the output current of each phase of the power converter, the DC bus voltage between the positive bus and the negative bus, and the ON voltage between the main terminals of the arm element, and a calculator that calculates the arm voltage for each phase output from the arm of each phase in accordance with the PWM control signal for each phase. A voltage sensor simulation circuit comprising: a generation circuit that generates a sensor simulation signal for each phase, which is a signal that simulates the detection signal for each phase output from a voltage sensor that detects the output voltage of each phase of the power converter, by adding or subtracting the arm voltage of each phase.

2. The voltage sensor simulation circuit according to claim 1, wherein the arm voltage of each phase is a voltage corrected by the polarity and the on-voltage.

3. The voltage sensor simulation circuit according to claim 2, wherein the calculator uses the arm voltage during the period when the upper arm element included in the arm is turned on in response to the PWM control signal, and the arm voltage during the period when the lower arm element included in the arm is turned on in response to the PWM control signal, as voltages corrected by the polarity and the on voltage.

4. The voltage sensor simulation circuit according to claim 3, wherein the calculator determines the arm voltage during the dead time period in which the upper and lower arm elements included in the arm are turned off in response to the PWM control signal, and the arm voltage is corrected by the polarity and the on voltage.

5. The voltage sensor simulation circuit according to any one of claims 1 to 4, wherein the calculator simulates the output current output from the power converter in response to the PWM control signal, and uses the polarity of the simulated output current to calculate the arm voltage.

6. The voltage sensor simulation circuit according to any one of claims 1 to 4, wherein the calculator determines the on-voltage corresponding to the calculated value of the output current based on the relationship between the output current and the on-voltage, and uses the determined on-voltage to calculate the arm voltage.

7. The aforementioned arithmetic unit uses the PWM control signal, the polarity, the DC bus voltage, and the ON voltage to calculate the peak and bottom values ​​of the arm voltages for each phase. The voltage sensor simulation circuit according to any one of claims 1 to 4, wherein the generation circuit generates a signal of the arm voltage by switching the peak value and the bottom value in accordance with the PWM control signal.

8. A first D / A converter that outputs the peak value of the arm voltage, The system includes a second D / A converter that outputs the bottom value of the arm voltage, The voltage sensor simulation circuit according to claim 6, wherein the generation circuit generates a signal of the arm voltage by selecting either the peak value output from the first D / A converter or the bottom value output from the second D / A converter according to the PWM control signal.

9. The voltage sensor simulation circuit according to claim 7, wherein the generation circuit generates a signal of the arm voltage by switching the peak value and the bottom value according to the PWM control signal and the value of the output current.

10. The aforementioned generation circuit is When the output current is a positive current value, the peak value and the bottom value are switched according to the PWM control signal that controls the upper arm element included in the arm, thereby generating the arm voltage signal. The voltage sensor simulation circuit according to claim 9, wherein when the output current is a negative current value, a signal of the arm voltage is generated by switching the peak value and the bottom value in accordance with the PWM control signal that controls the lower arm element included in the arm.

11. The aforementioned generation circuit is When the output current is a positive current value greater than a predetermined positive value, the peak value and the bottom value are switched in accordance with the PWM control signal that controls the upper arm element included in the arm, thereby generating the arm voltage signal. When the output current is a negative current value smaller than a predetermined negative value, the peak value and the bottom value are switched in accordance with the PWM control signal that controls the lower arm element included in the arm, thereby generating the arm voltage signal. The voltage sensor simulation circuit according to claim 10, wherein when the output current is greater than or equal to the negative value and less than or equal to the positive value, the peak value and the bottom value are switched according to the edge of the PWM control signal that turns on the upper arm element and the edge of the PWM control signal that turns on the lower arm element to generate a signal for the arm voltage.

12. The arithmetic unit uses the PWM control signals for each phase that control a power converter having arms for each phase, each containing an arm element, between the positive bus and the negative bus, the polarity of the output current of each phase of the power converter, the DC bus voltage between the positive bus and the negative bus, and the ON voltage between the main terminals of the arm element to calculate the arm voltage for each phase that is output from the arm of each phase in accordance with the PWM control signal for each phase. Voltage sensor simulation method, wherein the generation circuit generates simulated sensor signals for each phase, which are signals that simulate the detection signals for each phase output from a voltage sensor that detects the output voltage of each phase of the power converter, by adding or subtracting the arm voltage of each phase.

13. A calculator that simulates the output current of each phase output from a power converter in accordance with the PWM control signals of each phase that control a power converter having arms of each phase, each containing an arm element, between the positive and negative buses, The power converter includes a generation circuit that generates a sensor simulation signal for each phase, which is a signal that simulates the detection signal for each phase output from a voltage sensor that detects the output voltage of each phase of the power converter. The calculator uses the PWM control signals for each phase, the polarity of the simulated output currents for each phase, the DC bus voltage between the positive bus and the negative bus, and the ON voltage between the main terminals of the arm elements to calculate the arm voltage for each phase that is output from the arm of each phase in accordance with the PWM control signals for each phase. The generation circuit is a simulator that generates the sensor simulation signals for each phase by adding or subtracting the arm voltages of each phase.

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