Photoelectric conversion devices and equipment

Abstract

It is possible to reduce noise or power consumption when reading signals from pixels. [Solution] A photoelectric conversion device comprising: a photoelectric conversion unit that accumulates charge in response to incident light, a pixel that generates a photoelectric conversion signal in response to the accumulated charge and outputs the generated photoelectric conversion signal; a sample-and-hold unit that samples and holds a first photoelectric conversion signal and a second photoelectric conversion signal output from the pixel; and an oversampling type conversion unit that performs analog-to-digital (AD) conversion of the first photoelectric conversion signal and the second photoelectric conversion signal output from the sample-and-hold unit, characterized in that, in the processing from the generation of the first photoelectric conversion signal and the AD conversion of the first photoelectric conversion signal and the second photoelectric conversion signal, the gain set in response to the first photoelectric conversion signal and the gain set in response to the second photoelectric conversion signal are different.

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion device and an apparatus.

Background Art

[0002] There is a solid-state imaging device having a delta-sigma (ΔΣ) type analog-to-digital (AD) conversion circuit, which is one of oversampling type AD conversion circuits. Patent Document 1 discloses a solid-state imaging device capable of coping with a wide input voltage range by providing two capacitive elements for storing signals from pixels and outputting a weighted average of the voltages stored in the two capacitive elements.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in a photoelectric conversion device configured with an oversampling type AD conversion circuit including a ΔΣ type AD conversion circuit as shown in Patent Document 1, there is room for improvement in optimizing the operation of AD conversion.

[0005] An object of the present invention is to provide a photoelectric conversion device capable of reducing noise or power consumption when reading a signal from a pixel.

Means for Solving the Problems

[0006] According to one disclosure of this specification, a photoelectric conversion device includes a photoelectric conversion unit that accumulates charge in response to incident light, a pixel that outputs a plurality of photoelectric conversion signals and a reset level signal of the photoelectric conversion unit in response to the accumulated charge, a sample-and-hold unit that samples and holds a first photoelectric conversion signal and a second photoelectric conversion signal output from the pixel, and an oversampling type conversion unit that performs analog-to-digital (AD) conversion of the first photoelectric conversion signal and the second photoelectric conversion signal output from the sample-and-hold unit, wherein the first photoelectric conversion signal and the second photoelectric conversion signal are output from the pixel after In the process of converting the first photoelectric conversion signal and the second photoelectric conversion signal to AD, the first gain set in accordance with the first photoelectric conversion signal and the second gain set in accordance with the second photoelectric conversion signal are different, the reset level signal has the first gain and the second gain set respectively, and the conversion unit performs AD conversion on the difference between the first photoelectric conversion signal and the reset level signal with the first gain set, and the difference between the second photoelectric conversion signal and the reset level signal with the second gain set. [Effects of the Invention]

[0007] According to the present invention, it is possible to reduce noise or power consumption when reading signals from pixels. [Brief explanation of the drawing]

[0008] [Figure 1] Block diagram illustrating the photoelectric converter according to the first embodiment. [Figure 2] Circuit diagram illustrating the photoelectric converter according to the first embodiment. [Figure 3] Circuit diagram illustrating the photoelectric converter according to the first embodiment. [Figure 4] Drive timing chart illustrating the photoelectric converter according to the first embodiment. [Figure 5] Circuit diagram illustrating a reference photoelectric converter. [Figure 6]Circuit diagram illustrating a photoelectric converter according to a modified example of the first embodiment. [Figure 7] Circuit diagram illustrating the photoelectric converter according to the second embodiment. [Figure 8] Drive timing chart illustrating the photoelectric converter according to the second embodiment. [Figure 9] Schematic diagram illustrating the equipment according to the third embodiment. [Modes for carrying out the invention]

[0009] The embodiments described below will be explained with reference to the drawings. Note that the embodiments described below do not limit the invention to the claims. While multiple features are described in the embodiments, not all of these features are essential to the invention, and the features may be combined arbitrarily. Furthermore, in the attached drawings, the same or similar configurations are given the same reference numeral, and redundant explanations are omitted. In addition, the embodiments described below will focus on sensors for imaging as examples of photoelectric conversion devices. However, each embodiment is not limited to sensors for imaging and can be applied to other examples of photoelectric conversion devices. Examples include imaging devices, distance measuring devices (devices for distance measurement using focus detection or TOF (Time of Flight)), and photometric devices (devices for measuring the amount of incident light).

[0010] In this specification, terms indicating specific directions or positions (e.g., “up,” “down,” “right,” “left,” and other terms including these terms) are used as needed. The use of these terms is for the purpose of facilitating the understanding of embodiments with reference to the drawings, and the meaning of these terms does not limit the technical scope of the invention.

[0011] In this specification, when it is stated that "member A and member B are electrically connected," it is not limited to cases where member A and member B are directly connected. For example, even if another member C is connected between member A and member B, it is sufficient that they are electrically connected.

[0012] <First Embodiment> A photoelectric conversion device according to the first embodiment of the present invention will be described with reference to Figures 1 to 4.

[0013] Figure 1 is an example of a block diagram of the photoelectric conversion device according to this embodiment.

[0014] The photoelectric converter has a pixel substrate 1 and a circuit board 2 on which circuits are mounted. Pixel sections 5 are arranged on the pixel substrate 1. Multiple pixels 10, each containing a photoelectric converter that generates an electric charge corresponding to the incident light, are arranged in a matrix on the pixel section 5. The output from the multiple pixels is output to the circuit board 2 via vertical signal lines 30. The circuit board 2 may be stacked on the pixel substrate 1, or the above-mentioned components arranged on the pixel substrate 1 and the circuit board 2 may be arranged on the same substrate. Here, the column direction refers to the up and down direction in Figure 1, and the vertical signal lines 30 refer to the direction in which they extend from the pixel substrate 1 to the circuit board 2. The row direction refers to the left and right direction in Figure 1, and is perpendicular to the vertical signal lines 30.

[0015] The circuit board 2 is equipped with a current source 40, a sample-and-hold unit 50, a conversion unit 60, a data processing unit 90, and an output unit 100. The current source 40 is positioned corresponding to each of the vertical signal lines 30. The current source 40 supplies a bias current via the vertical signal lines 30 to the pixel 10 selected for reading out the pixel signal. The vertical signal lines 30 transfer the pixel signal corresponding to the charge generated by the photoelectric conversion unit of the pixel 10 from the pixel 10 to the sample-and-hold unit 50.

[0016] The sample hold unit 50 samples and holds the pixel signals generated by each pixel 10 via the vertical signal lines 30 from the pixel unit 5. In the present embodiment, the sample hold unit 50 includes two sample hold circuits. The first sample hold circuit samples and holds a pixel signal corresponding to the reset level (hereinafter, the signal at the reset level) when the photoelectric conversion unit is reset. The second sample hold circuit samples and holds a pixel signal corresponding to the imaging signal obtained when the photoelectric conversion operation is performed in the photoelectric conversion unit (hereinafter, the photoelectric conversion signal). The first sample hold circuit and the second sample hold circuit are provided for each of the vertical signal lines 30, respectively.

[0017] Each of the plurality of conversion units 60 includes an AD conversion circuit that AD-converts the pixel signal output from the sample hold unit 50. One of the plurality of conversion units 60 is connected corresponding to each of the plurality of vertical signal lines 30. Here, as the AD conversion circuit, a slope type AD conversion circuit, a successive comparison type AD conversion circuit, a ΔΣ type AD conversion circuit, etc. are used, but it is not limited thereto. In the present embodiment, a form using an oversampling type AD conversion circuit will be described.

[0018] The data processing unit 90 processes the digital signal output from the conversion unit 60. The data processing unit 90 can also perform digital processing such as correction processing and complement processing on the digital signal output from the conversion unit 60. The output unit 100 outputs the signal processed by the data processing unit 90 to the outside.

[0019] FIG. 2 is an example of a circuit diagram of the pixel 10 included in the photoelectric conversion device according to the present embodiment. Note that the present disclosure can be applied to both surface illumination type and back illumination type sensors.

[0020] Pixel 10 includes a photoelectric conversion unit 400, a transfer transistor 410, a reset transistor 455, an amplification transistor 430, and a selection transistor 440. The photoelectric conversion unit 400 is, for example, a photodiode. One of the main electrodes of the photoelectric conversion unit 400 is connected to a reference voltage 450, and it photoelectrically converts the received light into an amount of charge (for example, photoelectrons) corresponding to the amount of light, and stores it.

[0021] The other of the main electrodes of the photoelectric conversion unit 400 is electrically connected to the gate electrode of the amplification transistor 430 via the transfer transistor 410. Node 420, to which the gate electrode of the amplification transistor 430 is electrically connected, functions as a floating diffusion (FD). The floating diffusion unit (FD unit) receives the charge generated by the photoelectric conversion unit 400 and functions as a charge-voltage conversion unit that converts the input charge into a signal voltage. Hereinafter, node 420 may also be referred to as FD unit 420.

[0022] A transfer signal TX is supplied to the gate electrode of the transfer transistor 410. When the transfer transistor 410 becomes conductive in response to the transfer signal TX, the charge accumulated in the photoelectric conversion unit 400 is transferred to the FD unit node 420.

[0023] The reset transistor 455 is connected between the power supply voltage 460 and node 420. When a transistor is described as being connected between A and B, it means that one of its main electrodes (source and drain) is connected to A, and the other main electrode is connected to B. The transistor's gate electrode is not connected to either A or B.

[0024] A reset signal RES is supplied to the gate electrode of the reset transistor 455. When the reset transistor 455 becomes conductive in response to the reset signal RES, the charge held in the FD section 420 is swept out. As a result, the voltage of node 420 is reset to the power supply voltage 460. This reset operation resets the pixels.

[0025] The gate electrode of the amplification transistor 430 is connected to node 420, one of its main electrodes is connected to the power supply voltage 460, and the other of its main electrodes is connected to the selection transistor 440. The gate electrode of the amplification transistor 430 is the input to a source follower circuit that reads out the signal obtained by the photoelectric conversion of the photoelectric conversion unit 400. The other of the main electrodes of the amplification transistor 430 is connected to the vertical signal line 30 via the selection transistor 440. The amplification transistor 430 and the current source 40 connected to the vertical signal line 30 constitute a source follower that converts the voltage at node 420 to the voltage at the vertical signal line 30.

[0026] The selection transistor 440 is connected between the amplification transistor 430 and the vertical signal line 30. The gate electrode of the selection transistor 440 is supplied with a selection signal SEL. The selection transistor 440 becomes conductive in response to the selection signal SEL, thereby selecting the pixel 10. In the selected state, a signal based on the voltage of node 420 is output as a pixel signal to the vertical signal line 30 via the amplification transistor 430.

[0027] The circuit configuration of pixel 10 is not limited to the configuration shown in Figure 2. For example, the selection transistor 440 may be connected between the power supply voltage 460 and the amplification transistor 430. Also, if multiple vertical signal lines 30 are arranged in one pixel row, one pixel 10 may have multiple selection transistors 440 connected to different vertical signal lines 30. Furthermore, the configuration shown in Figure 2 is a so-called 4-transistor (4Tr.) type configuration in which pixel 10 comprises a transfer transistor 410, a reset transistor 455, an amplification transistor 430, and a selection transistor 440. However, it is not limited to this. For example, the selection transistor 440 may be omitted, and a 3Tr. type configuration may be used in which the amplification transistor 430 also functions as a selection transistor by controlling the voltage of node 420. Alternatively, a 5Tr. type or higher configuration with an increased number of transistors may be used.

[0028] When the control signal RES is applied to the pixel 10, the voltage at node 420 is reset by the reset transistor 455. When the pixel is reset, a reset level signal corresponding to the reset level when the photoelectric conversion unit 400 was reset may be output from the pixel. In addition, a photoelectric conversion signal that can correspond to the imaging signal generated by photoelectric conversion in response to the light incident on the photoelectric conversion unit 400 may be output from the pixel.

[0029] Figure 3 is an example of a circuit diagram of the sample-and-hold unit 50 and the conversion unit 60 of the photoelectric conversion device according to this embodiment. Figure 3 shows the sample-and-hold unit 50 and the conversion unit 60 arranged in correspondence with the vertical signal line 30. In this embodiment, one sample-and-hold unit 50 and one conversion unit 60 are arranged on one vertical signal line 30, respectively.

[0030] The sample-and-hold unit 50 includes a first sample-and-hold circuit 210 and a second sample-and-hold circuit 211. The first sample-and-hold circuit 210 samples and holds a reset level signal output from a pixel when the photoelectric conversion unit 400 is reset, as will be explained later. The second sample-and-hold circuit 211 samples and holds a photoelectric conversion signal generated in response to the light incident on the photoelectric conversion unit.

[0031] The first sample-and-hold circuit 210 includes a capacitive element 120 and an inverting amplifier 220. Switch 110 controls the connection between the vertical signal line 30 and the capacitive element 120 according to the control signal Smp_n. The inverting amplifier 220 can be configured by a combination of a common-source circuit and a source follower circuit. The inverting amplifier 220 includes transistors 130, 140, 150, 160, 230, switches 170, 180, 190, and a current source 200. Switch 170 is connected between the input and output of the common-source circuit composed of transistors 130, 140, 150, 160 and is controlled by the control signal Smpa_n. According to the control signal Hld_n, a reset level signal is output through the inverting amplifier 220.

[0032] The second sample-and-hold circuit 211 may have a configuration similar to the first sample-and-hold circuit 210, but differs mainly in the addition of switches 112 and 192 and a capacitive element 122. The second sample-and-hold circuit 211 includes capacitive elements 121 and 122 that hold pixel signals from the vertical signal line 30 and an inverting amplifier 221. Switches 111 and 112 control the connections between the vertical signal line 30 and the capacitive elements 121 and 122, respectively, according to control signals Smp_s1 and Smp_s2.

[0033] The inverting amplifier 221, like the inverting amplifier 220, can be constructed using a combination of a common-source circuit and a source follower circuit. The inverting amplifier 221 includes transistors 131, 141, 151, 161, 231, switches 171, 181, 191, 192, and a current source 201. Switch 171 is connected between the input and output of the common-source circuit composed of transistors 131, 141, 151, and 161, and is controlled by the control signal Smpa_s. The photoelectric conversion signal is output through the inverting amplifier 221 according to the control signals Hld_s1 to Hld_s2.

[0034] A resistor 240 is electrically connected between the output terminal of the first sample-and-hold circuit 210 and the output terminal of the second sample-and-hold circuit 211. Consider the case where the first sample-and-hold circuit 210 outputs a reset level signal and the second sample-and-hold circuit 211 outputs a photoelectric conversion signal. Let Vn be the voltage at the output terminal of the first sample-and-hold circuit 210, i.e., the voltage of the reset level signal, and Vs be the voltage at the output terminal of the second sample-and-hold circuit 211, i.e., the voltage of the photoelectric conversion signal. Let R be the resistance of the resistor 240. Then, the current I flowing through the resistor 240 is expressed by the following (Equation 1). I = (Vn - Vs) / R (Equation 1) This current I is input to the conversion unit 60. At this time, the current I flowing through the resistor element 240 is proportional to the difference between the voltage Vn of the reset level signal and the voltage Vs of the photoelectric conversion signal, as shown in Equation 1. Therefore, CDS (correlated double sampling) is performed when the current I is input to the conversion unit 60.

[0035] The conversion unit 60 is an oversampling type AD conversion circuit, for example, a ΔΣ type AD conversion circuit. The ΔΣ type AD conversion circuit includes a first integrator, a second integrator, a quantizer 370, and a decimation filter 380. In the conversion unit 60, the first integrator includes an integrating capacitor 320. The second integrator includes a voltage-to-current conversion circuit (Gm cell) 330 that converts voltage to current and an integrating capacitor 360. An AD converter 305, which includes a current source 300 and a switch 310, is connected to the input node of the first integrator.

[0036] The AD converter 305 controls the current to the first integrator in accordance with the digital signal via the second integrator and quantizer 370. The input node of the second integrator is connected to the AD converter 345, which includes a current source 340 and a switch 350. The AD converter 345 controls the current to the second integrator in accordance with the result of quantizing the output of the second integrator by the quantizer 370.

[0037] In the conversion unit 60, the quantizer 370 feeds back the previous quantized value to the second and first integrators via the AD converters 305 and 345. In this way, by feeding back the previous quantized value to the AD converters 305 and 345 and passing the signal through the integrators twice, a second-order noise shaping characteristic can be obtained. Furthermore, by removing high-frequency noise with the decimation filter 380 located after the quantizer 370, a highly accurate AD conversion output can be obtained.

[0038] Figure 4 is an example of a drive timing chart showing the operating timing of the sample-and-hold unit 50 and the conversion unit 60 of the photoelectric conversion device according to this embodiment. In Figure 4, the horizontal axis represents time and the vertical axis represents voltage. The control signal RES is a signal that resets the pixel 10. The transfer signal TX controls the reading of signals from the photoelectric conversion unit 400. The control signals Smpa_n, Smp_n, Smpa_s, Smp_s1, Smp_s2, Hld_n, Hld_s, Hld_s1, and Hld_s2 control the switches of the first sample-and-hold circuit 210 and the second sample-and-hold circuit 211. In the following explanation, in the waveforms of Figure 4, the corresponding switches are described as being ON when the control signal is at a high level (for example, the state of the RES waveform between time t1 and time t2), and OFF when the control signal is at a low level. Note that the ON state of a switch refers to a state in which there is conduction between the input node and the output node of the switch. On the other hand, the "off" state of a switch refers to a state where there is no conductivity between the input node and the output node of the switch.

[0039] Between times t1 and t2, the control signal RES in Figure 2 becomes high, turning on the reset transistor 455 and resetting the FD section 420. The control signal SEL shown in Figure 2 is also controlled, and accordingly the voltage across the vertical signal line 30 becomes the reset level voltage Vn. Also, at time t1, the control signals Smp_n and Smpa_n become high, turning on switches 110 and 170 of the first sample-and-hold circuit 210. Next, at time t3, when the control signal Smpa_n transitions from high to low, the reset level voltage Vn is sampled and stored in the capacitive element 120. Then, at time t4, the control signal Smp_n transitions from high to low, turning off switch 110, and disconnecting the capacitive element 120 from the vertical signal line 30.

[0040] Between times t5 and t6, the control signal TX in Figure 2 becomes high, and the transfer transistor 410 turns on. During this time, the charge generated in the photoelectric conversion unit 400 by the light incident between times t2 and t6 is transferred to the FD unit 420. In other words, the period between times t2 and t6 is the exposure period. The voltage of the FD unit 420 decreases in proportion to the amount of charge. In response to the control signal SEL, the voltage of the FD unit 420 is output to the vertical signal line 30 via the amplification transistor 430.

[0041] As a result, the voltage across the vertical signal line 30 becomes the voltage Vs1 of the first photoelectric conversion signal. Also, at time t5, the control signals Smp_s and Smpa_s1 become high, and switches 111 and 171 in the second sample-and-hold circuit 211 for the photoelectric conversion signal are turned ON. Next, at time t7, when the control signal Smpa_s transitions from high to low, switch 171 is turned OFF, the voltage Vs1 of the first photoelectric conversion signal is sampled and stored in the capacitive element 121. Then, at time t8, the control signal Smp_s1 transitions from high to low, switch 111 is turned OFF, and the capacitive element 121 is disconnected from the vertical signal line 30.

[0042] Furthermore, when switch 171 is turned off at time t7, the voltage across switch 171 is always approximately the same regardless of the voltage of the vertical signal line 30. Therefore, no charge injection occurs due to turning off switch 171, and no voltage error occurs in the voltage Vs1 of the first photoelectric conversion signal stored in capacitive element 121. Also, when switch 111 is turned off at time t8, both ends of capacitive element 121 are in a high impedance state. Therefore, there is no effect from turning off switch 111. In this way, the generation of an error voltage in the voltage Vs1 of the first photoelectric conversion signal can be suppressed.

[0043] Between times t9 and t10, the control signal TX in Figure 2 becomes high again, and the transfer transistor 410 turns on. During this time, the charge generated in the photoelectric conversion unit 400 by the light incident between times t6 and t10 is additionally transferred to the FD unit 420. In other words, in addition to the exposure period from time t2 to time t6, the exposure period is from time t6 to time t10. The voltage of the FD unit 420 decreases further depending on the amount of charge. As a result, the voltage of the vertical signal line 30 decreases and becomes the voltage Vs2 of the second photoelectric conversion signal. Also, at time t9, the control signals Smp_s and Smpa_s2 become high, and switches 112 and 171 in the second sample-and-hold circuit 211 for the photoelectric conversion signal turn on.

[0044] Next, at time t11, when the control signal Smpa_s transitions from a high level to a low level, the voltage Vs2 of the second photoelectric conversion signal is sampled and stored in the capacitive element 122. Then, at time t12, the control signal Smp_s2 transitions from a high level to a low level, the switch 112 turns off, and the capacitive element 122 is disconnected from the vertical signal line 30.

[0045] Furthermore, when switch 171 is turned off at time t11, the voltage across switch 171 is always approximately the same regardless of the voltage of the vertical signal line 30. Therefore, no charge injection occurs due to turning off switch 171, and no voltage error occurs in the voltage Vs2 of the second photoelectric conversion signal stored in capacitive element 122. Also, when switch 112 is turned off at time t12, both ends of capacitive element 122 are in a high impedance state. Therefore, there is no effect from turning off switch 112. In this way, the generation of an error voltage in the voltage Vs2 of the second photoelectric conversion signal can be suppressed.

[0046] At time t13, the control signal Hld_n becomes high level, and switches 180 and 190 are turned on, causing the capacitive element 120 in the first sample-and-hold circuit 210 to output a reset level signal voltage Vn. Also at the same time t13, the control signals Hld_s1 and Hld_s become high level, and switches 181 and 191 are turned on, causing the capacitive element 121 in the second sample-and-hold circuit 211 to output a first photoelectric conversion signal voltage Vs1.

[0047] As described above, the input current to the conversion unit 60 is a current corresponding to the difference between the voltage Vn of the reset level signal at the output terminal of the first sample-and-hold circuit 210 and the voltage Vs1 of the first photoelectric conversion signal at the output terminal of the second sample-and-hold circuit 211. The conversion unit 60 performs AD conversion on the current corresponding to the difference between voltage Vn and voltage Vs1.

[0048] At time t14, the control signal Hld_s1 becomes low, and switch 191 turns off. Then, at time t15, the control signal Hld_s2 becomes high, and switch 192 turns on, causing the capacitive element 122 in the second sample-and-hold circuit 211 to output the voltage Vs2 of the second photoelectric conversion signal.

[0049] As described above, the input current to the conversion unit 60 is a current corresponding to the difference between the voltage Vn of the reset level signal at the output terminal of the first sample-and-hold circuit 210 and the voltage Vs2 of the second photoelectric conversion signal at the output terminal of the second sample-and-hold circuit 211. The conversion unit 60 performs AD conversion on the current corresponding to the difference between voltage Vn and voltage Vs2.

[0050] Then, at time t16, the control signal Hld_n goes low, and switches 180 and 190 turn off. Also at the same time at time t16, the control signal Hld_s goes low, and switch 181 turns off. Also at the same time at time t16, the control signal Hld_s2 goes low, and switch 192 turns off.

[0051] Here, since the first photoelectric conversion signal and the second photoelectric conversion signal are pixel signals corresponding to different accumulation times, they are unlikely to have the same output amplitude except in the unexposed dark state. The exposure period (t2~t10) for accumulating the charge corresponding to the second photoelectric conversion signal is longer than the exposure period (t2~t6) for accumulating the charge corresponding to the first photoelectric conversion signal. Therefore, if there is no significant change in the amount of light incident on the photoelectric conversion unit 400, the voltage Vs2 will be a signal with a larger output amplitude than the voltage Vs1. In other words, the first photoelectric conversion signal and the second photoelectric conversion signal have different ranges of output amplitude. Thus, this embodiment makes it possible to read out multiple photoelectric conversion signals (first photoelectric conversion signal and second photoelectric conversion signal) with different charge accumulation times, and to obtain signals with a high dynamic range. Furthermore, high dynamic range images (HDR images) and high dynamic range videos (HDR videos) can be generated using signals with a high dynamic range. The output amplitude referred to here corresponds to the voltage difference relative to the voltage of the signal output by the pixel 10 when the FD unit 420 is reset, with the voltage of this reference voltage being used as the reference voltage. For subsequent output amplitudes, unless otherwise specified, the reference voltage can be the signal output by the pixel 10 when the FD unit 420 is reset. Typically, this signal level is near the power supply voltage 460.

[0052] Furthermore, as described above, this embodiment suppresses the generation of error voltages in the first and second photoelectric conversion signals, thereby suppressing quality degradation of signals with a high dynamic range. This also suppresses quality degradation of HDR images and HDR videos generated using signals with a high dynamic range.

[0053] The resistive element 240 electrically connected between the output terminal of the first sample-and-hold circuit 210 and the output terminal of the second sample-and-hold circuit 211 may be a variable resistor circuit. In other words, the output amplitude level of the signal input to the conversion unit 60 can be adjusted according to the resistance value, in which case the resistive element 240 functions as a gain setting unit. The resistance value of the resistive element 240 is changed at the time t13-t14 when the capacitive element 121 reads the voltage Vs1 of the first photoelectric conversion signal and at the time t15-16 when the capacitive element 122 reads the voltage Vs2 of the second photoelectric conversion signal. By changing the resistance value and thus changing the set gain, noise reduction or power reduction can be achieved according to the output amplitude level. This will be explained below.

[0054] If the resistance value is relatively smaller at time t13-t14 than at time t15-t16, the thermal noise generated in the resistive element 240 can be reduced, thereby reducing the noise in the voltage Vs1 of the first photoelectric conversion signal. On the other hand, if the resistance value is relatively larger at time t13-t14 than at time t15-t16, the output current to the conversion unit 60 can be reduced, thereby reducing power. Thus, the above effects are obtained because the gain set in response to the first photoelectric conversion signal is greater than the gain set in response to the second photoelectric conversion signal.

[0055] In this embodiment, during the processing from the generation of the first photoelectric conversion signal and the second photoelectric conversion signal until AD conversion, it is possible to set different gains for the first photoelectric conversion signal and the second photoelectric conversion signal. That is, it is possible to read out multiple photoelectric conversion signals with different gains, thereby reducing noise or power consumption. Note that the gains may be different by means other than varying the resistance value of the resistor element 240. For example, the gains may be different by varying the current value output from the current source 300. However, when switching the current value output from the current source 300, a certain amount of time is required for the current value to stabilize after the current value is switched. Therefore, signal processing can be performed at a faster speed when switching the resistance value of the resistor element 240 compared to when switching the current value output from the current source 300.

[0056] Furthermore, in this embodiment, by sharing the second sample-and-hold circuit 211 between the capacitive element 121 and the capacitive element 122, it is possible to read out the first photoelectric conversion signal and the second photoelectric conversion signal without increasing the operating power.

[0057] Furthermore, in this embodiment, by reading out the first photoelectric conversion signal and the second photoelectric conversion signal using a common resistive element 240, level fluctuations due to temperature and process variations are more easily synchronized. This suppresses the superposition of different variations between the first and second photoelectric conversion signals, for example, thereby suppressing quality degradation of signals with a high dynamic range. Consequently, it is possible to suppress the degradation of image quality of HDR images and HDR videos generated using signals with a high dynamic range.

[0058] Furthermore, in this embodiment, a resistor 240 for setting the gain when reading out the first and second photoelectric conversion signals is placed after the first sample-and-hold circuit 210 and the second sample-and-hold circuit 211. With this configuration, even when the resistance value of the resistor 240 is varied when reading out the first and second photoelectric conversion signals, highly accurate CDS can be performed. This will be explained below.

[0059] Here, a reference example is shown in Figure 5. The photoelectric conversion device shown in Figure 5 has a gain setting circuit 1000, a capacitive element 1030 for storing a reset level signal, a capacitive element 1040 for storing a first photoelectric conversion signal, and a capacitive element 1050 for storing a second photoelectric conversion signal. The gain setting circuit 1000 includes an operational amplifier 1001, a resistor 1002, and a variable resistor 1003. A switch 1060 is electrically connected between the gain setting circuit 1000 and the capacitive element 1030, and when the switch 1060 is ON, the signal output from the gain setting circuit 1000 is input to the capacitive element 1030 via the switch 1060. A switch 1070 is electrically connected between the gain setting circuit 1000 and the capacitive element 1040, and when the switch 1070 is ON, the signal output from the gain setting circuit 1000 is input to the capacitive element 1040 via the switch 1070. Furthermore, a switch 1080 is electrically connected between the gain setting circuit 1000 and the capacitive element 1050. When switch 1080 is ON, the signal output from the gain setting circuit 1000 is input to the capacitive element 1050 via switch 1080. In other words, in the configuration of Figure 5, the gain setting circuit 1000 is placed before, rather than after, the capacitive elements 1030, 1040, and 1050. Note that capacitive elements 1030, 1040, and 1050 correspond to capacitive elements 120, 121, and 122 shown in Figure 3, respectively. Note that switches 1060, 1070, and 1080 correspond to switches 110, 111, and 112 shown in Figure 3, respectively.

[0060] Consider the configuration shown in Figure 5, where CDS is performed on the first and second photoelectric conversion signals, read out with different gains, using a common reset level signal. In this case, since the gain setting circuit 1000 is located before the capacitive element 1030, it is not possible to change the gain corresponding to the reset level signal stored in the capacitive element 1030. Therefore, the gain corresponding to at least one of the first and second photoelectric conversion signals is different from the gain corresponding to the reset level signal. Consequently, the accuracy of CDS using at least one of the first and second photoelectric conversion signals, which corresponds to a gain different from the gain corresponding to the reset level signal, decreases. For example, if the reset level signal and the first photoelectric conversion signal are read out using the first gain, and the second photoelectric conversion signal is read out using the second gain, the accuracy of CDS for the second photoelectric conversion signal decreases. This is because different gains are applied to the pixel signal and the offset component of the operational amplifier 1001 when reading out the reset level signal and the second photoelectric conversion signal.

[0061] On the other hand, consider the case in the configuration shown in Figure 3 where CDS is performed on the first and second photoelectric conversion signals, read out using different gains, using a common reset level signal. In this case, since the resistor element 240 that sets the gain is located after the first sample-and-hold circuit 210 and the second sample-and-hold circuit 211, it is possible to change the gain corresponding to the reset level signal stored in the capacitive element 120. Therefore, even if the gains corresponding to the first and second photoelectric conversion signals are different, the gain corresponding to the reset level signal can be set to the same gain as the gains corresponding to the first and second photoelectric conversion signals, respectively. Thus, even when CDS is performed on the first and second photoelectric conversion signals, read out using different gains, using a common reset level signal, CDS using the first and second photoelectric conversion signals can be performed with high accuracy.

[0062] A photoelectric conversion device according to a modified version of the first embodiment of the present invention will be described with reference to Figure 6. Note that components similar to those in the first embodiment are denoted by the same reference numerals, and their descriptions may be omitted or simplified.

[0063] A modification of the first embodiment has a different pixel circuit configuration. Figure 6 is an example of a circuit diagram of a pixel 10 in the photoelectric conversion device according to this modification.

[0064] As shown in Figure 6, the pixel 10 may have a transistor 456 (floating diffusion capacitance switching transistor 456 (FD capacitance switching transistor 456)) that switches the capacitance value of the FD section 420. During the readout period, for example, at time t9 in Figure 4, the capacitance value of the FD 420 is changed by switching the on / off state of the FD capacitance switching transistor 456 by the signal FDINC. At this time, the FD capacitance switching transistor 456 functions as a gain changing unit (gain setting unit) that changes the capacitance value of the FD section 420, and switches the capacitance value of the FD section 420 when outputting the first photoelectric conversion signal and the second photoelectric conversion signal, respectively.

[0065] Alternatively, another capacitive element may be connected to the FD unit 420 via a transistor, and the capacitance value may be changed by switching the transistor on and off. The gain changing unit can output and hold pixel signals with different voltage conversion gains to the capacitive elements 121 and 122. Then, HDR images and HDR videos can be acquired using signals with different voltage gains.

[0066] Furthermore, by switching the resistance value of resistor element 240 to the high-gain pixel signal output with the FD capacitance switching transistor 456 turned off, it is possible to set a relatively larger gain. In this case, a signal with a higher dynamic range can be obtained. Then, HDR images and HDR videos can be generated using the signal with a higher dynamic range.

[0067] <Second Embodiment> A photoelectric conversion device according to a second embodiment of the present invention will be described with reference to Figures 7 and 8. Note that components similar to those in the first embodiment are denoted by the same reference numerals, and their descriptions may be omitted or simplified.

[0068] This embodiment differs from the first embodiment in that one pixel has a configuration in which multiple photoelectric conversion units. Figure 7 is an example of a circuit diagram of a pixel 10 in the photoelectric conversion device according to this embodiment. This disclosure can be applied to both front-illuminated and back-illuminated sensors.

[0069] As shown in Figure 7, the pixel 10 further includes a photoelectric conversion unit 401 and a transfer transistor 411. The photoelectric conversion unit 401 is, for example, a photodiode. One of the main electrodes of the photoelectric conversion unit 401 is connected to a reference voltage 450, and it photoelectrically converts the received light into an amount of charge (for example, photoelectrons) corresponding to the amount of light, and stores it.

[0070] The other of the main electrodes of the photoelectric conversion unit 401 is electrically connected to the gate electrode of the amplification transistor 430 via the transfer transistor 411. Node 420, to which the gate electrode of the amplification transistor 430 is electrically connected, functions as a floppy disk (FD). The FD unit functions as a charge-voltage conversion unit that converts the charge generated by the photoelectric conversion unit 400 into a signal voltage. Pixel 10 is configured to share the FD unit 420 between the photoelectric conversion unit 400 and the photoelectric conversion unit 401. If we consider each pixel to have two photoelectric conversion units and one FD unit arranged in a column, then pixel 10 in Figure 7 corresponds to, for example, two pixels arranged in a column like the pixel 10 in Figure 2.

[0071] A transfer signal TXA is supplied to the gate electrode of the transfer transistor 410. When the transfer transistor 410 becomes conductive in response to the transfer signal TXA, the charge accumulated in the photoelectric conversion unit 400 is transferred to the FD unit 420. A transfer signal TXB is supplied to the gate electrode of the transfer transistor 411. When the transfer transistor 411 becomes conductive in response to the transfer signal TXB, the charge accumulated in the photoelectric conversion unit 401 is transferred to the FD unit 420.

[0072] In this embodiment, the pixel signal output from the photoelectric conversion unit 400 is held in the capacitive element 121, and the pixel signal output from the photoelectric conversion unit 401 is held in the capacitive element 122. With this configuration, it becomes possible to read out two rows of pixel signals during a unit readout period, thereby increasing the readout speed.

[0073] The circuit configuration of pixel 10 is not limited to the configuration shown in Figure 7. For example, the selection transistor 440 may be connected between the power supply voltage 460 and the amplification transistor 430. Also, if multiple vertical signal lines 30 are arranged in one pixel row, one pixel 10 may have multiple selection transistors 440 connected to different vertical signal lines 30. Furthermore, the configuration shown in Figure 2 is a so-called 4-transistor (4Tr.) type configuration in which pixel 10 comprises a transfer transistor 410, a reset transistor 455, an amplification transistor 430, and a selection transistor 440. However, it is not limited to this. For example, the selection transistor 440 may be omitted, and a 3Tr. type configuration may be used in which the amplification transistor 430 also functions as a selection transistor by controlling the voltage of node 420. Also, a 5Tr. type or higher configuration with an increased number of transistors may be used.

[0074] Figure 8 is an example of a drive timing chart showing the operating timing of the sample-and-hold unit 50 and the conversion unit 60 of the photoelectric conversion device according to this embodiment. In Figure 8, the horizontal axis represents time and the vertical axis represents voltage. The control signal RES is a signal that resets the pixel 10. The transfer signal TXA controls the reading of signals from the photoelectric conversion unit 400, and the transfer signal TXB controls the reading of signals from the photoelectric conversion unit 401. The control signals Smpa_n, Smp_n, Smpa_s, Smp_s1, Smp_s2, Hld_n, Hld_s, Hld_s1, and Hld_s2 control the switches of the first sample-and-hold circuit 210 and the second sample-and-hold circuit 211, respectively. In the following explanation, in the waveforms of Figure 8, the corresponding switches are ON when the control signal is at a high level (for example, the state of the RES waveform between time t1 and time t2), and OFF when the control signal is at a low level. Note that the "on" state of a switch means that the switch is in a conductive state, and the "off" state means that the switch is in a non-conductive state.

[0075] Between times t1 and t2, the control signal RES in Figure 7 becomes high, turning on the reset transistor 455 and resetting the FD section 420. The control signal SEL shown in Figure 7 is also controlled, and accordingly the voltage across the vertical signal line 30 becomes the reset level voltage Vn. Also, at time t1, the control signals Smp_n and Smpa_n become high, turning on switches 110 and 170 of the first sample-and-hold circuit 210. Next, at time t3, when the control signal Smpa_n transitions from high to low, the reset level voltage Vn is sampled and stored in the capacitive element 120. Then, at time t4, the control signal Smp_n transitions from high to low, the switch 110 turns off, and the capacitive element 120 is disconnected from the vertical signal line 30.

[0076] Between times t5 and t6, the control signal TXA in Figure 7 becomes high, and the transfer transistor 410 turns on. During this time, the charge generated in the photoelectric conversion unit 400 by the light incident between times t2 and t6 is transferred to the FD unit 420. In other words, the period between times t2 and t6 is the exposure period. The voltage of the FD unit 420 decreases according to the amount of charge. In response to the control signal SEL, the voltage of the FD unit 420 is output to the vertical signal line 30 via the amplification transistor 430.

[0077] As a result, the voltage across the vertical signal line 30 becomes the voltage Vs1 of the first photoelectric conversion signal. Also, at time t5, the control signals Smp_s and Smpa_s1 become high, and switches 111 and 171 in the second sample-and-hold circuit 211 for the photoelectric conversion signal are turned ON. Next, at time t7, when the control signal Smpa_s transitions from high to low, switch 171 is turned OFF, the voltage Vs1 of the first photoelectric conversion signal is sampled and stored in the capacitive element 121. Then, at time t8, the control signal Smp_s1 transitions from high to low, switch 111 is turned OFF, and the capacitive element 121 is disconnected from the vertical signal line 30.

[0078] Furthermore, when switch 171 is turned off at time t7, the voltage across switch 171 is always approximately the same regardless of the voltage of the vertical signal line 30. Therefore, no charge injection occurs due to turning off switch 171, and no voltage error occurs in the voltage Vs1 of the first photoelectric conversion signal stored in capacitive element 121. Also, when switch 111 is turned off at time t8, both ends of capacitive element 121 are in a high impedance state. Therefore, there is no effect from turning off switch 111. In this way, the generation of an error voltage in the voltage Vs1 of the first photoelectric conversion signal can be suppressed.

[0079] Between times t9 and t10, the control signal TXB in Figure 7 becomes high, and the transfer transistor 411 turns on. During this time, the charge generated in the photoelectric conversion unit 401 by the light incident between times t2 and t10 is transferred to the FD unit 420. The voltage in the FD unit 420 decreases further depending on the amount of charge. As a result, the voltage of the vertical signal line 30 decreases and becomes the voltage Vs2 of the second photoelectric conversion signal. Also, at time t9, the control signals Smp_s and Smpa_s2 become high, and switches 112 and 171 in the second sample-and-hold circuit 211 for the photoelectric conversion signal turn on.

[0080] Next, at time t11, when the control signal Smpa_s transitions from a high level to a low level, the voltage Vs2 of the second photoelectric conversion signal is sampled and stored in the capacitive element 122. Then, at time t12, the control signal Smp_s2 transitions from a high level to a low level, the switch 112 turns off, and the capacitive element 122 is disconnected from the vertical signal line 30. In other words, the voltage Vs2 of the second photoelectric conversion signal, based on the charge generated by the photoelectric conversion unit 400 and the photoelectric conversion unit 401, is stored in the capacitive element 122.

[0081] Furthermore, when switch 171 is turned off at time t11, the voltage across switch 171 is always approximately the same regardless of the voltage of the vertical signal line 30. Therefore, no charge injection occurs due to turning off switch 171, and no voltage error occurs in the voltage Vs2 of the second photoelectric conversion signal stored in capacitive element 122. Also, when switch 112 is turned off at time t12, both ends of capacitive element 122 are in a high impedance state. Therefore, there is no effect from turning off switch 112. In this way, the generation of an error voltage in the voltage Vs2 of the second photoelectric conversion signal can be suppressed.

[0082] At time t13, the control signal Hld_n becomes high level, and switches 180 and 190 are turned on, causing the capacitive element 120 in the first sample-and-hold circuit 210 to output a reset level signal voltage Vn. Also at the same time t13, the control signals Hld_s1 and Hld_s become high level, and switches 181 and 191 are turned on, causing the capacitive element 121 in the second sample-and-hold circuit 211 to output a first photoelectric conversion signal voltage Vs1.

[0083] As described above, the input current to the conversion unit 60 is a current corresponding to the difference between the voltage Vn of the reset level signal at the output terminal of the first sample-and-hold circuit 210 and the voltage Vs1 of the photoelectric conversion signal at the output terminal of the second sample-and-hold circuit 211. The conversion unit 60 performs AD conversion on the current corresponding to the difference between voltage Vn and voltage Vs1.

[0084] At time t14, the control signal Hld_s1 becomes low, and switch 191 turns off. Then, at time t15, the control signal Hld_s2 becomes high, and switch 192 turns on, causing the capacitive element 122 in the second sample-and-hold circuit 211 to output the voltage Vs2 of the second photoelectric conversion signal.

[0085] As described above, the input current to the conversion unit 60 is a current corresponding to the difference between the voltage Vn of the reset level signal at the output terminal of the first sample-and-hold circuit 210 and the voltage Vs2 of the photoelectric conversion signal at the output terminal of the second sample-and-hold circuit 211. The conversion unit 60 performs AD conversion on the current corresponding to the difference between voltage Vn and voltage Vs2.

[0086] Then, at time t16, the control signal Hld_n goes low, and switches 180 and 190 turn off. Also at the same time at time t16, the control signal Hld_s goes low, and switch 181 turns off. Also at the same time at time t16, the control signal Hld_s2 goes low, and switch 192 turns off.

[0087] Here, the first photoelectric conversion signal corresponds to the charge generated by the photoelectric conversion unit 400, and the second photoelectric conversion signal corresponds to the charge generated by both the photoelectric conversion unit 400 and the photoelectric conversion unit 401. In other words, the first photoelectric conversion signal is output from one of the multiple photoelectric conversion units, and the second photoelectric conversion signal is output from both of the multiple photoelectric conversion units. After time t16, the difference between the digital signal corresponding to the current corresponding to the difference between voltage Vn and voltage Vs1 and the digital signal corresponding to the current corresponding to the difference between voltage Vn and voltage Vs2 is taken to obtain a digital signal corresponding to the charge generated by the photoelectric conversion unit 401. Alternatively, the first photoelectric conversion signal may correspond to the charge generated by the photoelectric conversion unit 400, and the second photoelectric conversion signal may correspond to the charge generated by the photoelectric conversion unit 401. In other words, the first photoelectric conversion signal may be output from one of the multiple photoelectric conversion units, and the second photoelectric conversion signal may be output from the other of the multiple photoelectric conversion units.

[0088] Thus, this embodiment makes it possible to read out pixel signals corresponding to two rows of pixels during a unit readout period, thereby enabling faster readout operations. The pixel signals that can be read out during a unit readout period may be pixel signals corresponding to multiple rows of pixels or pixel signals corresponding to multiple columns of pixels, depending on the pixel configuration.

[0089] Furthermore, as described above, this embodiment suppresses the generation of error voltages in the first and second photoelectric conversion signals, thereby suppressing signal quality degradation.

[0090] The resistive element 240 electrically connected between the output terminal of the first sample-and-hold circuit 210 and the output terminal of the second sample-and-hold circuit 211 may be a variable resistor circuit. In other words, the output amplitude level of the signal input to the conversion unit 60 can be adjusted according to the resistance value, in which case the resistive element 240 functions as a gain setting unit. The resistance value of the resistive element 240 is changed at the time t13-t14 when the capacitive element 121 reads the voltage Vs1 of the first photoelectric conversion signal and at the time t15-16 when the capacitive element 122 reads the voltage Vs2 of the second photoelectric conversion signal. Similar to the first embodiment, this embodiment makes it possible to read out multiple photoelectric conversion signals with different gains, thereby reducing noise or power consumption.

[0091] Furthermore, the gain may be varied by means other than varying the resistance value of the resistor element 240. For example, the gain may be varied by varying the current value output from the current source 300. However, when switching the current value output from the current source 300, a certain amount of time is required for the current value to stabilize after the switch. Therefore, signal processing can be performed at a faster speed when switching the resistance value of the resistor element 240 compared to when switching the current value output from the current source 300.

[0092] Furthermore, in this embodiment, by sharing the second sample-and-hold circuit 211 between the capacitive element 121 and the capacitive element 122, it is possible to read out the first photoelectric conversion signal and the second photoelectric conversion signal without increasing the operating power.

[0093] Furthermore, in this embodiment, by reading out the first photoelectric conversion signal and the second photoelectric conversion signal using a common resistive element 240, level fluctuations due to temperature and process variations are more easily synchronized. This suppresses the superposition of different variations between the first and second photoelectric conversion signals, thus suppressing signal quality degradation.

[0094] Furthermore, in this embodiment, a resistor 240 for setting the gain when reading out the first photoelectric conversion signal and the second photoelectric conversion signal is placed after the first sample-and-hold circuit 210 and the second sample-and-hold circuit 211. With this configuration, even when the resistance value of the resistor 240 is varied when reading out the first photoelectric conversion signal and the second photoelectric conversion signal, highly accurate CDS can be performed.

[0095] Furthermore, one microlens may be provided corresponding to one pixel 10, i.e., the photoelectric conversion unit 400 and the photoelectric conversion unit 401. In this case, the photoelectric conversion unit 400 and the photoelectric conversion unit 401 may function as pixels for phase difference detection. By having the photoelectric conversion unit 400 and the photoelectric conversion unit 401 function as pixels for phase difference detection, the focus of the subject can be detected. In this case, the first photoelectric conversion signal described above becomes the autofocus (AF) signal, and the second photoelectric conversion signal becomes the imaging signal. Furthermore, even when the photoelectric conversion unit 400 and the photoelectric conversion unit 401 function as pixels for phase difference detection, it is possible to read out multiple photoelectric conversion signals with different gains. For example, by relatively increasing the gain corresponding to the first photoelectric conversion signal, it is possible to improve AF accuracy. However, if the resistance value of the resistive element 240 is reduced in order to increase the gain, the current output to the conversion unit 60 may exceed the current value of the current source 300. Furthermore, if the current output to the conversion unit 60 exceeds the current value of the current source 300, the current output to the conversion unit 60 may exceed the range of AD-convertible current values. Here, the output amplitude range of the second photoelectric conversion signal, which consists of two photoelectric conversion units, is generally larger than the output amplitude range of the first photoelectric conversion signal, which is the signal of one photoelectric conversion unit. Therefore, even if the current corresponding to the first photoelectric conversion signal using a certain gain does not exceed the range of AD-convertible current values, the current corresponding to the second photoelectric conversion signal using the same gain may exceed the range of AD-convertible current values. Thus, by increasing the gain when reading out the first photoelectric conversion signal and decreasing the gain when reading out the second photoelectric conversion signal, AF accuracy can be improved while ensuring that the signal does not deviate from the range of AD-convertible current values. Accordingly, this embodiment makes it possible to read out multiple photoelectric conversion signals with different gains, and in doing so, AF accuracy can be improved while ensuring that the signal does not deviate from the range of AD-convertible current values.

[0096] In Figure 7, the areas of the photoelectric conversion unit 400 and the photoelectric conversion unit 401 may be different. The amount of charge that a photoelectric conversion unit with a large area and a photoelectric conversion unit with a small area can hold will be different. That is, the amount of charge generated by a photoelectric conversion unit with a large area and a photoelectric conversion unit with a small area for the same amount of incident light will be different. Therefore, the photoelectric conversion unit 400 and the photoelectric conversion unit 401 can output signals with different output amplitude ranges.

[0097] In Figure 7, the pixel 10 may further include an FD capacitance switching transistor 456, and the on / off state of the FD capacitance switching transistor 456 may be switched during the pixel signal readout period to read out pixel signals with different voltage conversion gains. In this case as well, the photoelectric conversion unit 400 and the photoelectric conversion unit 401 can output signals with different output amplitude ranges from each other. This is due, for example, to the difference in thresholds between the reset transistor 455 and the FD capacitance switching transistor 456. When the threshold of the reset transistor 455 is relatively high, the FD capacitance switching transistor 456 is ON, and the output amplitude range is larger for pixel signals with lower voltage conversion gains. This is because the voltage of the FD unit 420 can be reduced to a level lower than the reset level.

[0098] <Third Embodiment> The third embodiment is applicable to the first and second embodiments. Figure 9(a) is a schematic diagram illustrating a device 9191 equipped with the semiconductor device 930 of this embodiment. The photoelectric converter (imaging device) of each embodiment described above can be used for the semiconductor device 930. The device 9191 equipped with the semiconductor device 930 will be described in detail. The semiconductor device 930 may include a semiconductor device 910. In addition to the semiconductor device 910, the semiconductor device 930 may include a package 920 that houses the semiconductor device 910. The package 920 may include a substrate to which the semiconductor device 910 is fixed, and a lid such as glass facing the semiconductor device 910. The package 920 may further include bonding members such as bonding wires and bumps that connect terminals provided on the substrate and terminals provided on the semiconductor device 910.

[0099] The device 9191 may include at least one of the following: an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, shutter, or mirror, and includes an optical system that directs light to the semiconductor device 930. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0100] The processing unit 960 processes the signals output from the semiconductor device 930. The processing unit 960 is a semiconductor device such as a CPU or ASIC that constitutes an AFE (analog front end) or DFE (digital front end). The display device 970 is an EL display device or liquid crystal display device that displays the information (image) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or semiconductor device that stores the information (image) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or a hard disk drive.

[0101] The mechanical device 990 has movable parts or propulsion parts such as motors and engines. The device 9191 displays signals output from the semiconductor device 930 on the display device 970 or transmits them to the outside using a communication device (not shown) provided in the device 9191. For this purpose, it is preferable that the device 9191 further includes a storage device 980 and a processing device 960, separate from the memory circuits and arithmetic circuits of the semiconductor device 930. The mechanical device 990 may be controlled based on signals output from the semiconductor device 930.

[0102] Furthermore, the device 9191 is suitable for electronic devices such as information terminals with shooting capabilities (e.g., smartphones and wearable devices) and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). In a camera, the mechanical device 990 can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in a camera can move the semiconductor device 930 for vibration damping.

[0103] Furthermore, the device 9191 may be a transport device such as a vehicle, ship, or aircraft (drone, aircraft, etc.). The mechanical device 990 in the transport device may be used as a mobile device. The device 9191 as a transport device is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) through its imaging function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing to operate the mechanical device 990 as a mobile device based on information obtained from the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring instrument such as a distance sensor, an analytical instrument such as an electron microscope, office equipment such as a copier, or industrial equipment such as a robot.

[0104] According to the embodiments described above, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. Increasing value here means at least one of the following: addition of functions, improvement of performance, improvement of characteristics, improvement of reliability, improvement of manufacturing yield, reduction of environmental impact, cost reduction, miniaturization, and weight reduction.

[0105] Therefore, by using the semiconductor device 930 according to this embodiment in the device 9191, the value of the device can also be improved. For example, by mounting the semiconductor device 930 on a transport device, excellent performance can be obtained when taking external images of the transport device or measuring the external environment. Therefore, when manufacturing and selling transport devices, deciding to mount the semiconductor device according to this embodiment on the transport device is advantageous in improving the performance of the transport device itself. In particular, the semiconductor device 930 is suitable for transport devices that use information obtained from the semiconductor device to assist in driving and / or perform automated driving.

[0106] Furthermore, the photoelectric conversion system and mobile body of this embodiment will be explained using Figures 9(b) and (c).

[0107] Figure 9(b) shows an example of a photoelectric conversion system for an in-vehicle camera. The photoelectric conversion system 8 includes a photoelectric conversion device 80. The photoelectric conversion device 80 is a photoelectric conversion device (imaging device) as described in any of the embodiments above. The photoelectric conversion system 8 includes an image processing unit 801 that performs image processing on a plurality of image data acquired by the photoelectric conversion device 80, and a parallax acquisition unit 802 that calculates parallax (phase difference of parallax image) from the plurality of image data acquired by the photoelectric conversion system 8. Here, the photoelectric conversion system 8 may include an optical system (not shown) that guides light to the photoelectric conversion device 80, such as a lens, shutter, or mirror. In addition, a plurality of photoelectric conversion units that are substantially conjugate to the pupil of the optical system may be arranged in pixels of the photoelectric conversion device 80. For example, a plurality of photoelectric conversion units substantially conjugate to the pupil may be arranged corresponding to one microlens. Multiple photoelectric conversion units receive light beams that have passed through different positions in the pupil of the optical system, and the photoelectric conversion device 80 outputs image data corresponding to the light beams that have passed through different positions. The parallax acquisition unit 802 may then calculate the parallax using the output image data. The photoelectric conversion system 8 also includes a distance acquisition unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means for acquiring distance information to an object. That is, distance information is information related to parallax, defocus amount, distance to an object, etc. The collision determination unit 804 may use any of this distance information to determine the possibility of collision. Note that the distance information may be acquired by ToF (Time of Flight). The distance information acquisition means may be implemented by specially designed hardware or by a software module. Furthermore, it may be implemented using FPGAs (Field Programmable Gate Arrays) or ASICs (Application Specific Integrated Circuits), or a combination thereof.

[0108] The photoelectric conversion system 8 is connected to the vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 8 is also connected to the control ECU 820, which is a control device that outputs a control signal to generate braking force on the vehicle based on the judgment result of the collision judgment unit 804. The photoelectric conversion system 8 is also connected to the warning device 830, which issues a warning to the driver based on the judgment result of the collision judgment unit 804. For example, if the collision judgment result of the collision judgment unit 804 indicates a high probability of collision, the control ECU 820 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 830 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel.

[0109] In this embodiment, the photoelectric conversion system 8 images the area around the vehicle, for example, in front of or behind it. Figure 9(c) shows the photoelectric conversion system 8 when imaging the area in front of the vehicle (imaging range 850). The vehicle information acquisition device 810 sends instructions to the photoelectric conversion system 8 or the photoelectric conversion device 80. This configuration can further improve the accuracy of distance measurement.

[0110] The above example illustrates control to prevent collisions with other vehicles, but it can also be applied to control systems that automatically follow other vehicles or automatically drive to prevent vehicles from straying from their lanes. Furthermore, the photoelectric conversion system 8 can be applied not only to vehicles such as automobiles, but also to mobile objects (mobile devices) such as ships, aircraft, or industrial robots. In addition, it can be applied not only to mobile objects but also to a wide range of devices that utilize object recognition, such as intelligent transportation systems (ITS).

[0111] In this specification, expressions such as “A or B,” “at least one of A and B,” “at least one of A and / or B,” and “one or more of A and / or B” include all possible combinations of the enumerated items unless otherwise explicitly defined. That is, the above expressions are understood to disclose all cases including at least one A, at least one B, and both at least one A and at least one B. This also applies to combinations of three or more elements.

[0112] The embodiments described above can be modified as appropriate without departing from the technical concept. Furthermore, the disclosures in this specification include not only what is described herein, but also all matters that can be understood from this specification and the drawings attached thereto. The disclosures in this specification also include the complement of the concepts described herein. That is, if this specification states, for example, "A is greater than B," then even if the statement "A is not greater than B" is omitted, this specification can be said to disclose that "A is not greater than B." This is because the statement "A is greater than B" presupposes that the case where "A is not greater than B" is being considered.

[0113] Furthermore, the disclosure of this embodiment includes the following configuration.

[0114] (Composition 1) A photoelectric conversion device comprising: a photoelectric conversion unit that accumulates charge in response to incident light, a pixel that generates a photoelectric conversion signal in response to the accumulated charge and outputs the generated photoelectric conversion signal; a sample-and-hold unit that samples and holds a first photoelectric conversion signal and a second photoelectric conversion signal output from the pixel; and an oversampling type conversion unit that performs analog-to-digital (AD) conversion of the first photoelectric conversion signal and the second photoelectric conversion signal output from the sample-and-hold unit, characterized in that, in the processing from the generation of the first photoelectric conversion signal and the second photoelectric conversion signal until the AD conversion of the first photoelectric conversion signal and the second photoelectric conversion signal, the gain set in response to the first photoelectric conversion signal and the gain set in response to the second photoelectric conversion signal are different.

[0115] (Configuration 2) The photoelectric conversion device according to configuration 1, characterized in that the first photoelectric conversion signal and the second photoelectric conversion signal have different output amplitude ranges.

[0116] (Composition 3) The photoelectric conversion device according to configuration 1 or 2, characterized in that the output amplitude range of the first photoelectric conversion signal is smaller than that of the second photoelectric conversion signal, and the gain of the first photoelectric conversion signal is set to be larger than that of the second photoelectric conversion signal.

[0117] (Composition 4) The photoelectric conversion device according to any one of configurations 1 to 3, characterized in that the time for which the photoelectric conversion unit accumulates the charge is different, and the time for which the charge corresponding to the first photoelectric conversion signal is accumulated is different from the time for which the charge corresponding to the second photoelectric conversion signal is accumulated.

[0118] (Composition 5) The photoelectric conversion device according to any one of configurations 1 to 4, characterized in that the first photoelectric conversion signal has a shorter charge accumulation time than the second photoelectric conversion signal, and the first photoelectric conversion signal is set to have a larger gain than the second photoelectric conversion signal.

[0119] (Composition 6) The photoelectric conversion device according to any one of configurations 1 to 5, characterized in that the conversion unit performs AD conversion on the difference between the first photoelectric conversion signal and the second photoelectric conversion signal and the reset level signal of the photoelectric conversion unit.

[0120] (Composition 7) The photoelectric conversion apparatus according to any one of configurations 1 to 6, characterized in that the sample-and-hold section includes a first sample-and-hold circuit for sampling and holding the reset level signal, and a second sample-and-hold circuit for sampling and holding the first photoelectric conversion signal and the second photoelectric conversion signal, respectively.

[0121] (Composition 8) The photoelectric conversion apparatus according to any one of configurations 1 to 7, characterized in that the first photoelectric conversion signal and the second photoelectric conversion signal are each held in two capacitors included in the second sample-and-hold circuit.

[0122] (Composition 9) The photoelectric conversion device according to any one of configurations 1 to 8, characterized in that the sample-and-hold section includes an inverting amplifier, and the first photoelectric conversion signal and the second photoelectric conversion signal are output via the inverting amplifier.

[0123] (Composition 10) The photoelectric conversion device according to any one of configurations 1 to 9, further comprising a gain setting unit for setting the aforementioned gain, wherein the gain setting unit sets the gain corresponding to the first photoelectric conversion signal and the gain corresponding to the second photoelectric conversion signal, respectively.

[0124] (Composition 11) The photoelectric conversion apparatus according to any one of configurations 1 to 10, characterized in that the gain setting unit is electrically connected between the output terminals of each of the multiple sample-and-hold circuits included in the sample-and-hold unit.

[0125] (Composition 12) The photoelectric conversion device according to any one of configurations 1 to 11, characterized in that the gain setting unit includes a variable resistor circuit, and the gain corresponding to the first photoelectric conversion signal and the gain corresponding to the second photoelectric conversion signal are set by changing the resistance value of the variable resistor circuit.

[0126] (Composition 13) The photoelectric conversion device according to any one of configurations 1 to 12, wherein the pixel includes a floating diffusion section into which the charge is input, and a floating diffusion capacitance switching section for switching the capacitance value of the floating diffusion section, and the capacitance values ​​of the floating diffusion section are switched when the pixel outputs the first photoelectric conversion signal and the second photoelectric conversion signal, respectively.

[0127] (Composition 14) The photoelectric conversion device according to any one of configurations 1 to 13, characterized in that the pixel includes a plurality of photoelectric conversion units, the photoelectric conversion signal output from one of the plurality of photoelectric conversion units is the first photoelectric conversion signal, and the photoelectric conversion signal output from the other of the plurality of photoelectric conversion units is the second photoelectric conversion signal.

[0128] (Composition 15) The photoelectric conversion device according to any one of configurations 1 to 14, characterized in that the pixel includes a plurality of photoelectric conversion units, the photoelectric conversion signal output from one of the plurality of photoelectric conversion units is the first photoelectric conversion signal, and the photoelectric conversion signals output from the plurality of photoelectric conversion units are the second photoelectric conversion signals.

[0129] (Composition 16) A photoelectric conversion device according to any one of configurations 1 to 15, characterized in that microlenses are arranged corresponding to the pixels, and the plurality of photoelectric conversion units are arranged corresponding to the microlenses.

[0130] (Composition 17) A photoelectric conversion device according to any one of configurations 1 to 16, characterized in that the amount of charge generated by the plurality of photoelectric conversion units is different for light incident during the same period.

[0131] (Composition 18) A photoelectric conversion device according to any one of configurations 1 to 17, characterized in that the plurality of pixels are arranged in the row direction and the column direction, and the plurality of photoelectric conversion units are arranged in the column direction.

[0132] (Composition 19) A device comprising a photoelectric converter according to any one of configurations 1 to 18, further comprising at least one of the following: an optical device for guiding light to the photoelectric converter; a control device for controlling the photoelectric converter; a processing device for processing signals output from the photoelectric converter; a display device for displaying information obtained from the photoelectric converter; a storage device for storing information obtained from the photoelectric converter; and a mechanical device that operates based on the information obtained from the photoelectric converter. [Explanation of symbols]

[0133] 10 pixels 50 Sample Hold Section 60 Conversion section 400 Photoelectric conversion unit

Claims

1. A photoelectric conversion unit that accumulates charge in response to incident light, and a pixel that outputs a plurality of photoelectric conversion signals and a reset level signal for the photoelectric conversion unit in response to the accumulated charge, A sample-and-hold unit that samples and holds the first photoelectric conversion signal and the second photoelectric conversion signal output from the aforementioned pixel, An oversampling type conversion unit that performs analog-to-digital (AD) conversion of the first photoelectric conversion signal and the second photoelectric conversion signal output from the sample-and-hold unit, A photoelectric conversion device comprising, In the process from when the first photoelectric conversion signal and the second photoelectric conversion signal are output from the pixel until the first photoelectric conversion signal and the second photoelectric conversion signal are AD converted, the first gain set in accordance with the first photoelectric conversion signal and the second gain set in accordance with the second photoelectric conversion signal are different. The reset level signal is set by the first gain and the second gain, respectively. The conversion unit performs AD conversion on the difference between the first photoelectric conversion signal and the reset level signal with the first gain set, and the difference between the second photoelectric conversion signal and the reset level signal with the second gain set. A photoelectric conversion device characterized by the following features.

2. The photoelectric conversion device according to claim 1, characterized in that the pixel outputs the reset level signal, the first photoelectric conversion signal, and the second photoelectric conversion signal in this order, and does not output the reset level signal during the period from after the output of the first photoelectric conversion signal ends until the output of the second photoelectric conversion signal begins.

3. The device includes a plurality of photoelectric conversion units that accumulate charge in response to incident light, and microlenses arranged in correspondence with the plurality of photoelectric conversion units, and a pixel that outputs a photoelectric conversion signal in response to the accumulated charge, A sample-and-hold unit that samples and holds a first photoelectric conversion signal output from one of the plurality of photoelectric conversion units and a second photoelectric conversion signal output from the plurality of photoelectric conversion units. An oversampling type conversion unit that performs analog-to-digital (AD) conversion of the first photoelectric conversion signal and the second photoelectric conversion signal output from the sample-and-hold unit, A photoelectric conversion device comprising, In the process from when the first photoelectric conversion signal and the second photoelectric conversion signal are output from the pixel until the first photoelectric conversion signal and the second photoelectric conversion signal are converted using AD conversion, the first gain set in accordance with the first photoelectric conversion signal and the second gain set in accordance with the second photoelectric conversion signal are different. A photoelectric conversion device characterized by the following features.

4. The photoelectric conversion device according to claim 1 or 3, characterized in that the first photoelectric conversion signal and the second photoelectric conversion signal have different output amplitude ranges.

5. The photoelectric conversion device according to claim 4, characterized in that the output amplitude range of the first photoelectric conversion signal is smaller than that of the second photoelectric conversion signal, and the first gain is larger than that of the second gain.

6. The photoelectric conversion device according to claim 1, characterized in that the time for which the photoelectric conversion unit accumulates the charge is different, and the time for which the charge corresponding to the first photoelectric conversion signal is accumulated is different from the time for which the charge corresponding to the second photoelectric conversion signal is accumulated.

7. The photoelectric conversion device according to claim 6, characterized in that the first photoelectric conversion signal has a shorter charge accumulation time than the second photoelectric conversion signal, and the first gain is greater than the second gain.

8. The photoelectric conversion device according to claim 3, characterized in that the conversion unit performs AD conversion on the difference between the first photoelectric conversion signal, the second photoelectric conversion signal, and the reset level signal of the photoelectric conversion unit.

9. The photoelectric conversion apparatus according to claim 1 or 8, characterized in that the sample-and-hold unit includes a first sample-and-hold circuit for sampling and holding the reset level signal, and a second sample-and-hold circuit for sampling and holding the first photoelectric conversion signal and the second photoelectric conversion signal, respectively.

10. The photoelectric conversion apparatus according to claim 9, characterized in that the first photoelectric conversion signal and the second photoelectric conversion signal are each held in two capacitors included in the second sample-and-hold circuit.

11. The photoelectric conversion apparatus according to claim 8, wherein the reset level signal includes a first reset level signal corresponding to the first photoelectric conversion signal and a second reset level signal corresponding to the second photoelectric conversion signal, and the gain set in accordance with the first reset level signal and the gain set in accordance with the second reset level signal are different.

12. The photoelectric conversion device according to claim 1 or 3, characterized in that the sample-and-hold unit includes an inverting amplifier, and the first photoelectric conversion signal and the second photoelectric conversion signal are output via the inverting amplifier.

13. The photoelectric conversion apparatus according to claim 1 or 3, further comprising a gain setting unit for setting the first gain and the second gain, wherein the gain setting unit sets the first gain and the second gain, respectively.

14. The photoelectric conversion apparatus according to claim 13, characterized in that the gain setting unit is electrically connected between the output terminals of each of the multiple sample-and-hold circuits included in the sample-and-hold unit.

15. The photoelectric conversion device according to claim 13, wherein the gain setting unit includes a variable resistor circuit, and the first gain and the second gain are set by changing the resistance value of the variable resistor circuit.

16. The photoelectric conversion device according to claim 1 or 3, wherein the pixel includes a floating diffusion section into which the charge is input, and a floating diffusion capacitance switching section for switching the capacitance value of the floating diffusion section, and the capacitance values ​​of the floating diffusion section are switched when the pixel outputs the first photoelectric conversion signal and the second photoelectric conversion signal, respectively.

17. The photoelectric conversion device according to claim 1, characterized in that the pixel includes a plurality of photoelectric conversion units, the photoelectric conversion signal output from one of the plurality of photoelectric conversion units is the first photoelectric conversion signal, and the photoelectric conversion signal output from the other of the plurality of photoelectric conversion units is the second photoelectric conversion signal.

18. The photoelectric conversion device according to claim 1, characterized in that the pixel includes a plurality of photoelectric conversion units, the photoelectric conversion signal output from one of the plurality of photoelectric conversion units is the first photoelectric conversion signal, and the photoelectric conversion signals output from the plurality of photoelectric conversion units are the second photoelectric conversion signals.

19. The photoelectric conversion device according to claim 17 or 18, characterized in that microlenses are arranged corresponding to the pixels, and the plurality of photoelectric conversion units are arranged corresponding to the microlenses.

20. The photoelectric conversion device according to claim 3, 17, or 18, characterized in that the amount of charge generated by the plurality of photoelectric conversion units is different for light incident during the same period.

21. The photoelectric conversion device according to claim 3, 17, or 18, characterized in that the plurality of pixels are arranged in the row direction and the column direction, and the plurality of photoelectric conversion units are arranged in the column direction.

22. A device comprising a photoelectric converter according to claim 1 or 3, An optical device that guides light to the aforementioned photoelectric converter, A control device for controlling the aforementioned photoelectric converter, A processing device that processes the signal output from the aforementioned photoelectric converter, A display device that displays information obtained by the aforementioned photoelectric converter. A storage device for storing information obtained by the photoelectric converter, and The apparatus is characterized by further comprising at least one of the following: a mechanical device that operates based on information obtained from the photoelectric converter.

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