Ceramic electronic components

Abstract

To provide ceramic electronic components that can suppress performance degradation. [Solution] The ceramic electronic component comprises a laminated chip in which dielectric layers and internal electrode layers are alternately stacked, and between the dielectric layer and the internal electrode layer, concentration peaks of two or more metals different from the main component metal of the internal electrode layer exist at positions in different stacking directions between the dielectric layer and the internal electrode layer, and between the interface of the internal electrode layer and the concentration peak of the first metal among the two or more metals is greater than or equal to the atomic radius of the first metal and less than or equal to 2 nm.

Description

[Technical Field]

[0001] This invention relates to ceramic electronic components. [Background technology]

[0002] With the miniaturization of electronic devices, there is a growing demand for further miniaturization of ceramic electronic components such as multilayer ceramic capacitors used in these devices. To increase the capacitance value, which is a fundamental characteristic, one of the following methods can be considered: (1) increasing the dielectric constant of the dielectric layer, (2) increasing the capacitance-specified area, or (3) thinning the dielectric layer. When the dielectric constant and element size are fixed, a thinner dielectric layer is advantageous because it allows for a larger capacitance value per layer, and by thinning the dielectric layer and internal electrode layer, it becomes possible to increase the number of layers that can be stacked within the fixed thickness. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2003-7562 [Overview of the project] [Problems that the invention aims to solve]

[0004] On the other hand, thinning the dielectric layer increases the electric field strength applied to the dielectric layer even at the same operating voltage, which may reduce insulation reliability. Furthermore, thinning the internal electrode layer may reduce its continuity. Thus, ceramic electronic components may experience performance degradation.

[0005] To address these issues, the performance degradation of ceramic electronic components can be suppressed by appropriately selecting multiple metal elements for use in the internal electrode layer. However, simply including multiple metal elements in the internal electrode layer may not be sufficient to suppress the performance degradation of ceramic electronic components.

[0006] This invention has been made in view of the above problems, and aims to provide a ceramic electronic component that can suppress performance degradation. [Means for solving the problem]

[0007] The ceramic electronic component according to the present invention comprises a laminated chip in which dielectric layers and internal electrode layers are alternately stacked, and is characterized in that, between the dielectric layers and the internal electrode layers, there exist concentration peaks of two or more metals different from the main component metal of the internal electrode layer at positions in the stacking direction of the dielectric layers and the internal electrode layers.

[0008] In the above-described ceramic electronic component, the interval between the dielectric layer and the internal electrode layer may be the interval from the minimum value of the differential of the concentration of the main component metal in the internal electrode layer to the maximum value of the differential of the concentration of the main component ceramic in the dielectric layer, when the concentration of the component elements is measured from the internal electrode layer toward the dielectric layer.

[0009] In the above-mentioned ceramic electronic component, the thickness of the dielectric layer may be 0.6 μm or less.

[0010] In the above-mentioned ceramic electronic component, the distance from the interface of the internal electrode layer to the concentration peak of the first metal among the two or more metals may be 0.1 nm or more and 2 nm or less.

[0011] Between the dielectric layer and the internal electrode layer of the ceramic electronic component described above, the interval from the concentration peak of the first metal to the concentration peak of the second metal among the two or more metals may be 0.1 nm or more and 2 nm or less.

[0012] In the above-mentioned ceramic electronic component, the distance from the concentration peak of the second metal to the interface of the dielectric layer between the dielectric layer and the internal electrode layer may be 0.1 nm or more and 2 nm or less.

[0013] In the above ceramic electronic component, the main component metal of the internal electrode layer may be Ni.

[0014] In the above ceramic electronic component, the dielectric layer may contain barium titanate.

[0015] In the above ceramic electronic component, the concentration peaks of the two or more kinds of metals may include the concentration peaks of Au and Sn.

[0016] The method for manufacturing a ceramic electronic component according to the present invention includes a step of forming a lamination unit by forming an internal electrode pattern on a dielectric green sheet, a step of forming a laminate by laminating a plurality of the lamination units, and a step of firing the laminate. When forming the internal electrode pattern, patterns of two or more kinds of metals different from the main component metal of the internal electrode pattern are sequentially formed by sputtering on both main surfaces of the internal electrode pattern.

Effect of the Invention

[0017] According to the present invention, it is possible to provide a ceramic electronic component capable of suppressing performance degradation.

Brief Description of the Drawings

[0018] [[ID=2​​​​​​​​​​​​​​​​ [Figure 7] (a) and (b) are diagrams illustrating the lamination process. [Figure 8] This diagram provides a detailed explanation of the deposition of an internal electrode pattern onto a dielectric green sheet. [Figure 9] This is a Weibull plot. [Figure 10] This is a diagram showing the continuity rate. [Figure 11] (a) is a cross-sectional SEM image of Example 1, and (b) is a cross-sectional SEM image of Example 4. [Modes for carrying out the invention]

[0019] The embodiments will be described below with reference to the drawings.

[0020] (First Embodiment) Figure 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100 according to the first embodiment. Figure 2 is a cross-sectional view taken along line AA in Figure 1. Figure 3 is a cross-sectional view taken along line BB in Figure 1. As illustrated in Figures 1 to 3, the multilayer ceramic capacitor 100 comprises a multilayer chip 10 having a substantially rectangular parallelepiped shape and external electrodes 20a and 20b provided on two opposing end faces of either of the multilayer chip 10. Of the four faces of the multilayer chip 10 other than the two end faces, the two faces other than the top and bottom faces in the stacking direction are referred to as side faces. The external electrodes 20a and 20b extend to the top, bottom, and two side faces of the multilayer chip 10 in the stacking direction. However, the external electrodes 20a and 20b are spaced apart from each other.

[0021] The multilayer chip 10 has a structure in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 containing a base metal material are alternately stacked. The edges of each internal electrode layer 12 are alternately exposed at the end face of the multilayer chip 10 where the external electrode 20a is provided and at the end face where the external electrode 20b is provided. As a result, each internal electrode layer 12 is alternately conductive to the external electrode 20a and the external electrode 20b. Consequently, the multilayer ceramic capacitor 100 has a structure in which multiple dielectric layers 11 are stacked via internal electrode layers 12. In the laminate of dielectric layers 11 and internal electrode layers 12, the outermost layer in the stacking direction is an internal electrode layer 12, and the top and bottom surfaces of the laminate are covered by a cover layer 13. The cover layer 13 is mainly composed of a ceramic material. For example, the main components of the cover layer 13 are the same as those of the dielectric layer 11 and the ceramic material.

[0022] The dimensions of the multilayer ceramic capacitor 100 are, for example, 0.25 mm in length, 0.125 mm in width, and 0.125 mm in height, or 0.4 mm in length, 0.2 mm in width, and 0.2 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.110 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.1 mm in height, or 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height, or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height, but are not limited to these dimensions.

[0023] The dielectric layer 11 mainly consists of a ceramic material having a perovskite structure represented by the general formula ABO3. Note that this perovskite structure is an ABO3 structure that deviates from the stoichiometric composition. 3-α This includes, for example, BaTiO3 (barium titanate), CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), MgTiO3 (magnesium titanate), and Ba forming a perovskite structure. 1-x-y Ca x Sry Ti 1-z Zr z At least one selected from O3 (0≤x≤1, 0≤y≤1, 0≤z≤1) etc. can be used. Ba 1-x-y Ca x Sr y Ti 1-z Zr z O3 includes barium strontium titanate, barium calcium titanate, barium zirconate, barium titanium zirconate, calcium titanium zirconate, barium calcium titanium zirconate, etc.

[0024] As illustrated in FIG. 2, in the region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other, capacitance is generated in the multilayer ceramic capacitor 100. Therefore, the region where the capacitance is generated is referred to as the capacitance region 14. That is, the capacitance region 14 is the region where adjacent internal electrode layers 12 connected to different external electrodes face each other.

[0025] The region where the internal electrode layers 12 connected to the external electrode 20a face each other without passing through the internal electrode layer 12 connected to the external electrode 20b is referred to as the end margin 15. Also, the region where the internal electrode layers 12 connected to the external electrode 20b face each other without passing through the internal electrode layer 12 connected to the external electrode 20a is also the end margin 15. That is, the end margin 15 is the region where the internal electrode layers 12 connected to the same external electrode face each other without passing through the internal electrode layer 12 connected to a different external electrode. The end margin 15 is a region where no capacitance is generated. <0000!133>

[0026] As illustrated in FIG. 3, in the multilayer chip 10, the region from the two side surfaces of the multilayer chip 10 to the internal electrode layer 12 is referred to as the side margin 16. That is, the side margin 16 is the region provided to cover the ends where the plurality of internal electrode layers 12 laminated in the above laminate structure extend to the two side surfaces. The side margin 16 is also a region where no capacitance is generated.

[0027] To make the multilayer ceramic capacitor 100 smaller and larger in capacity, it is preferable to form the dielectric layer 11 thinly. For example, the thickness of each dielectric layer 11 is 0.05 μm or more and 5 μm or less, or 0.1 μm or more and 3 μm or less, or 0.2 μm or more and 1 μm or less, or 0.6 μm or less. The thickness of the dielectric layer 11 can be measured by observing the cross-section of the multilayer ceramic capacitor 100 with an SEM (scanning electron microscope), measuring the thickness at 10 points for each of 10 different dielectric layers 11, and deriving the average value of all measurement points.

[0028] Figure 4 is a diagram illustrating the details near the boundary between the internal electrode layer 12 and the dielectric layer 11. As illustrated in Figure 4, the internal electrode layer 12 is covered by a first coating layer 17. The first coating layer 17 is covered by a second coating layer 18. For example, the first coating layer 17 is formed on the first main surface, which is one of the main surfaces of the internal electrode layer 12 (the upper main surface in Figure 4), and the second coating layer 18 is formed on the first coating layer 17. Alternatively, the first coating layer 17 is formed below the second main surface, which is the other main surface of the internal electrode layer 12 (the lower main surface in Figure 4), and the second coating layer 18 is formed below the first coating layer 17. Note that the first coating layer 17 does not necessarily have to cover the entire first and second main surfaces of the internal electrode layer 12; it may partially cover the first and second main surfaces of the internal electrode layer 12. Furthermore, the second coating layer 18 does not necessarily have to cover the entire first coating layer 17; it may partially cover the first coating layer 17.

[0029] The first coating layer 17 is a layer containing a relatively large amount of a first metal, which is different from the main component metal of the internal electrode layer 12. The second coating layer 18 is also a layer containing a relatively large amount of a second metal, which is different from the main component metal of the internal electrode layer 12. The first metal and the second metal are different. In each of the layers, the internal electrode layer 12, the first coating layer 17, and the second coating layer 18, there is not just a single metal, but each metal is partially diffused into each layer. The main component metal of the internal electrode layer 12 may be a base metal such as nickel (Ni) or copper (Cu), or it may be a noble metal.

[0030] Figures 5(a) to 5(c) illustrate the analysis results obtained by line analysis of the concentration of each component element at each sample point along the stacking direction of the dielectric layer 11 and the internal electrode layer 12 in TEM images. In the example in Figures 5(a) to 5(c), Ni is used as the main component metal of the internal electrode layer 12, the first coating layer 17 contains a relatively large amount of gold (Au), the second coating layer 18 contains a relatively large amount of tin (Sn), and barium titanate is used as the main component ceramic of the dielectric layer 11.

[0031] In Figure 5(a), the horizontal axis represents the distance in the stacking direction, and the vertical axis represents the concentration (at%) of each component. "0 nm" on the horizontal axis indicates the position expected to be the interface between the internal electrode layer 12 and the first coating layer 17. As the distance on the horizontal axis increases, the stacking direction approaches the dielectric layer 11. As illustrated in Figure 5(a), at a distance of "0 nm," the concentration of Ni, the main component metal of the internal electrode layer 12, is the highest. As the stacking direction approaches the dielectric layer 11, the Ni concentration decreases, peaks appear in the Au and Sn concentrations, and the titanium (Ti) and oxygen (O) concentrations increase. Note that in the example in Figure 5(a), the data has been averaged and smoothed over 9 points to reduce noise.

[0032] Figure 5(b) shows the results of differentiating the Ni and Ti concentrations in Figure 5(a). By identifying the point of steepest change, the interface of the internal electrode layer 12 and the interface of the dielectric layer 11 can be identified. In the example in Figure 5(b), the position where the derivative of the Ni concentration is smallest is the interface of the internal electrode layer 12. Also, the position where the derivative of the Ti concentration is largest is the interface of the dielectric layer 11. This indicates that there is a large amount of Au and Sn between the interface of the dielectric layer 11 and the interface of the internal electrode layer 12.

[0033] Figure 5(c) is a graph showing the results from Figure 5(a) with the vertical axis on a logarithmic scale. As illustrated in Figure 5(c), peaks of Au concentration and Sn concentration appear between the interface of the dielectric layer 11 and the interface of the internal electrode layer 12. The peak of Au concentration is located closer to the Ni interface than the peak of Sn concentration. The peak of Sn concentration is located closer to the Ti interface than the peak of Au concentration. In this way, between the interface of the dielectric layer 11 and the interface of the internal electrode layer 12, the concentration peak of the first metal, which is relatively abundant in the first coating layer 17, and the concentration peak of the second metal, which is relatively abundant in the second coating layer 18, are located at different positions in the stacking direction of the dielectric layer 11 and the internal electrode layer 12. Specifically, the concentration peak of the first metal is located on the interface side of the internal electrode layer 12, and the concentration peak of the second metal is located on the interface side of the dielectric layer 11.

[0034] With this configuration, the effects of the first metal and the second metal are exerted individually. For example, if the first metal has the effect of suppressing the degradation of reliability of the dielectric layer 11 and the second metal has the effect of suppressing the degradation of continuity of the internal electrode layer 12, the effect of suppressing the degradation of reliability and the effect of suppressing the degradation of continuity will be higher compared to the case where an alloy layer in which the first and second metals are uniformly mixed is provided. Also, if the first metal has the effect of suppressing the degradation of reliability of the dielectric layer 11 and the second metal also has the effect of suppressing the degradation of reliability of the dielectric layer 11, the effect of suppressing the degradation of reliability will be higher compared to the case where an alloy layer in which the first and second metals are uniformly mixed is provided. In this way, the effect of the first metal and the effect of the second metal are exerted individually, thereby suppressing the degradation of performance of the multilayer ceramic capacitor 100. This effect is particularly pronounced when the dielectric layer 11 is formed thinly (for example, 0.6 μm or less) and sufficient insulation is not guaranteed. Furthermore, the amount of precious metal used can be reduced by combining a precious metal with a base metal, or by combining base metals, as the first and second metals.

[0035] When Ni or Cu is used as the main component metal of the internal electrode layer 12, for example, metals that suppress the decrease in the insulation reliability of the dielectric layer 11 include arsenic (As), Au, cobalt (Co), chromium (Cr), Cu, iron (Fe), indium (In), iridium (Ir), magnesium (Mg), osmium (Os), palladium (Pd), platinum (Pt), rhenium (Re), rhodium (Rh), ruthenium (Ru), selenium (Se), Sn, tellurium (Te), tungsten (W), yttrium (Y), and zinc (Zn).

[0036] When Ni or Cu is used as the main component metal of the internal electrode layer 12, for example, metals that suppress the decrease in the continuity of the internal electrode layer 12 include silver (Ag), Cr, Ir, Mg, molybdenum (Mo), Os, Pd, Pt, Re, Rh, Ru, Y, and W.

[0037] When Ni or Cu is used as the main component metal of the internal electrode layer 12, examples of metals that have the effect of barriering diffusion between the internal electrode layer 12 and the dielectric layer 11 include tantalum (Ta) and Ti.

[0038] When Ni or Cu is used as the main component metal of the internal electrode layer 12, for example, Cr, Ta, and Ti can be used as metals to ensure adhesion between the internal electrode layer 12 and the dielectric layer 11.

[0039] When Ni or Cu is used as the main component metal of the internal electrode layer 12 and a perovskite oxide such as barium titanate is used as the main component ceramic of the dielectric layer 11, for example, Cu can be used as a metal to alleviate the lattice mismatch between the internal electrode layer 12 and the dielectric layer 11.

[0040] In order to form one layer of the first metal, a distance of at least the atomic radius of the first metal is required. Therefore, it is preferable to set a lower limit on the distance from the interface of the internal electrode layer 12 to the concentration peak of the first metal in the stacking direction. On the other hand, if the distance is too large, the effect will begin to saturate. Therefore, it is preferable to set an upper limit on the distance. In the stacking direction, the distance from the interface of the internal electrode layer 12 to the concentration peak of the first metal is, for example, 0.1 nm to 2 nm, 0.1 nm to 1.5 nm, and 0.1 nm to 1 nm. In the stacking direction, the distance from the concentration peak of the first metal to the concentration peak of the second metal is, for example, 0.1 nm to 2 nm, 0.1 nm to 1.5 nm, and 0.1 nm to 1 nm. In the stacking direction, the distance from the concentration peak of the second metal to the interface of the dielectric layer 11 is, for example, 0.1 nm to 2 nm, 0.1 nm to 1.5 nm, and 0.1 nm to 1 nm. The above example showed the case where there are two types of concentration peaks, but the same intervals apply when multiple peaks are present.

[0041] The thickness of the internal electrode layer 12 is, for example, 10 nm or more and 1000 nm or less, 20 nm or more and 500 nm or less, and 50 nm or more and 300 nm or less. The thickness of the internal electrode layer 12 can be measured by observing the cross-section of the multilayer ceramic capacitor 100 with an SEM, measuring the thickness at 10 points for each of the 10 different internal electrode layers 12, and deriving the average value of all measurement points.

[0042] Furthermore, the number of metals whose concentration peaks appear at different positions in the stacking direction between the internal electrode layer 12 and the dielectric layer 11 is not limited to two. Three or more metal concentration peaks may appear at different positions in the stacking direction between the internal electrode layer 12 and the dielectric layer 11. In this case, the effects of each of the three or more metals can be obtained.

[0043] Next, the manufacturing method of the multilayer ceramic capacitor 100 will be described. Figure 6 is a diagram illustrating the flow of the manufacturing method of the multilayer ceramic capacitor 100.

[0044] (Process for producing raw material powder) First, a dielectric material is prepared to form the dielectric layer 11. The A-site and B-site elements contained in the dielectric layer 11 are usually present in the form of a sintered body of ABO3 particles. For example, BaTiO3 is a tetragonal compound having a perovskite structure and exhibits a high dielectric constant. This BaTiO3 can generally be obtained by synthesizing barium titanate by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. Various methods have been conventionally known for synthesizing the main component ceramic of the dielectric layer 11, such as the solid-phase method, the sol-gel method, and the hydrothermal method. In this embodiment, any of these can be employed.

[0045] A predetermined additive compound is added to the obtained ceramic powder according to the purpose. Examples of additive compounds include oxides of Mg, manganese (Mn), vanadium (V), Cr, rare earth elements (Y, samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holomium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)), or oxides containing Co, Ni, lithium (Li), boron (B), sodium (Na), potassium (K), or silicon (Si), or glass containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon.

[0046] For example, a ceramic material can be prepared by wet-mixing a ceramic raw material powder with a compound containing an additive, followed by drying and pulverization. For example, the ceramic material obtained as described above may be subjected to pulverization as needed to adjust the particle size, or the particle size may be adjusted by combining this with a classification process. A dielectric material can be obtained through the above steps.

[0047] (Lamination process) Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained dielectric material and wet-mixed. Using the resulting slurry, a dielectric green sheet 52 is coated onto the substrate 51 by, for example, a die coater or doctor blade method and then dried. The substrate 51 is, for example, a PET (polyethylene terephthalate) film.

[0048] Next, as illustrated in Figure 7(a), an internal electrode pattern 53 is deposited on the dielectric green sheet 52. In Figure 7(a), as an example, four layers of the internal electrode pattern 53 are deposited on the dielectric green sheet 52 at predetermined intervals. The dielectric green sheet 52 on which the internal electrode pattern 53 has been deposited is used as the stacking unit.

[0049] Next, the dielectric green sheet 52 is peeled off the substrate 51, and the stacking units are stacked as illustrated in Figure 7(b).

[0050] Next, a predetermined number of cover sheets 54 (for example, 2 to 10 layers) are laminated on the top and bottom of the laminate obtained by stacking the laminate units, and then heat-pressed together and cut to a predetermined chip size (for example, 1.0 mm × 0.5 mm). In the example in Figure 7(b), the cut is made along the dotted line. The cover sheet 54 may have the same composition as the dielectric green sheet 52, or it may have different additive compounds.

[0051] (Firing process) The ceramic laminate thus obtained is subjected to binder removal treatment in an N2 atmosphere, and then a metal paste that will serve as the base layer for the external electrodes 20a and 20b is applied by the dip method, and the oxygen partial pressure is 10 -5 ~10 -8 The capacitor is fired in an atm reducing atmosphere at 1100-1300°C for 10 minutes to 2 hours. In this way, a multilayer ceramic capacitor 100 is obtained.

[0052] (Re-oxidation process) Subsequently, a re-oxidation treatment may be performed in an N2 gas atmosphere at 600°C to 1000°C.

[0053] (Plating process) Subsequently, the external electrodes 20a and 20b may be coated with metals such as Cu, Ni, or Sn by plating.

[0054] Figure 8 is a diagram illustrating in detail the deposition of the internal electrode pattern 53 onto the dielectric green sheet 52. As illustrated in Figure 8, on both main surfaces of the internal electrode pattern 53, a first pattern 55 of the first metal, which is relatively abundant in the first coating layer 17, is deposited by sputtering, and a second pattern 56 of the second metal, which is relatively abundant in the second coating layer 18, is deposited on the first pattern 55 by sputtering. For example, the second pattern 56 is deposited on the dielectric green sheet 52 by sputtering. Next, the first pattern 55 is deposited on the second pattern 56 by sputtering. Next, the internal electrode pattern 53 is deposited on the first pattern 55 by sputtering. Next, the first pattern 55 is deposited on the internal electrode pattern 53 by sputtering. Next, the second pattern 56 is deposited on the first pattern 55 by sputtering.

[0055] According to the manufacturing method of the multilayer ceramic capacitor 100 of this embodiment, by depositing each pattern by sputtering as shown in Figure 8, mixing of the metals in each layer is suppressed. As a result, even if the metals diffuse from one another during the firing process, a structure like that exemplified in Figure 4 can be obtained near the interface of the internal electrode layer 12 obtained after the firing process. In this case, when line analysis of the elemental concentrations at each sample point along the stacking direction in the TEM image is performed, the concentration peaks of the second metal, which is relatively abundant in the first coating layer 17, and the concentration peaks of the second metal, which is relatively abundant in the second coating layer 18, will be located at different positions between the interface of the internal electrode layer 12 and the interface of the dielectric layer 11. As a result, the effects of the first metal and the effects of the second metal will be exerted individually.

[0056] In the embodiments described above, multilayer ceramic capacitors were explained as an example of ceramic electronic components, but the invention is not limited to them. For example, other electronic components such as varistors and thermistors may be used. [Examples]

[0057] Below, a multilayer ceramic capacitor according to the embodiment was fabricated and its characteristics were investigated.

[0058] (Example 1) A dielectric material was obtained by adding additives to barium titanate powder and thoroughly wet-mixing and grinding it in a ball mill. A dielectric green sheet was coated onto a PET substrate using the doctor blade method with a butyral-based organic binder and toluene and ethyl alcohol as solvents. A 200 nm thick pattern was deposited on the surface of the dielectric green sheet by sputtering. To provide a coating layer of dissimilar metals on the Ni surface of the internal electrode pattern, an Au layer and a Sn layer were deposited separately before and after the Ni layer. The thickness of the Au and Sn layers was 1 nm on both the front and back surfaces, while the Ni layer was 196 nm thick. A masking method using a metal mask was employed for patterning. 100 layers of dielectric green sheets with internal electrode patterns were stacked so that the internal electrode patterns were alternately offset, cut to a predetermined size, and a metal conductive paste for external electrodes was applied to the two end faces where the internal electrode patterns were exposed. The capacitor was then fired to obtain a multilayer ceramic capacitor.

[0059] The composition near the boundary between the dielectric layer and the internal electrode layer of the obtained multilayer ceramic capacitors was analyzed using line analysis with STEM-EDS (scanning transmission electron microscope). The variability of the measurement data was averaged out by averaging approximately nine points. In the region spanning the boundary, the interface was defined as the position where the concentration change was steepest. That is, the interface was defined as the position showing the maximum / minimum value of the distance derivative of the concentration. For Ni and Ti, the interface positions extracted by the above procedure were different, with a gap of approximately 0.5 nm. The concentrations of Au and Sn both had peak maxima, and their peak positions were located between the Ni and Ti interfaces. The respective peak positions were different from each other, with a gap of approximately 0.2 nm in this device.

[0060] (Example 2) In Example 2, a 1 nm thick Fe layer was deposited by sputtering instead of a 1 nm thick Sn layer. Other conditions were the same as in Example 1. In Example 2, concentration peaks of Au and Fe were observed at different positions between the Ni and Ti interface.

[0061] (Example 3) In Example 3, a 1 nm thick Cr layer was deposited by sputtering instead of a 1 nm thick Sn layer. Other conditions were the same as in Example 1. In Example 3, concentration peaks of Au and Cr were observed at different positions between the Ni and Ti interface.

[0062] (Example 4) In Example 4, the coating layer consisted of three layers. Before and after depositing the 194 nm Ni layer, 1 nm Au, Cr, and Sn layers were deposited by sputtering, respectively. Other conditions were the same as in Example 1. In Example 4, concentration peaks of Au, Cr, and Sn were observed at different positions between the Ni and Ti interfaces.

[0063] (Comparative Example 1) In Comparative Example 1, when forming the internal electrode pattern, a 200 nm thick film was formed using only Ni, and the Au and Sn coating layers were not formed. Other conditions were the same as in Example 1.

[0064] (Comparative Example 2) In Comparative Example 2, when forming the internal electrode pattern, a 198 nm Ni layer was formed, and a 1 nm first metal Au layer was formed before and after the Ni layer formation. Other conditions were the same as in Example 1.

[0065] For Examples 1-4 and Comparative Examples 1 and 2, HALT (Highly Accelerated Life) tests were conducted at 125°C / 18V to measure the dielectric breakdown lifetime. Figure 9 is a Weibull plot showing the relationship between the time to failure and the cumulative failure rate for Examples 1 and Comparative Examples 1 and 2. As shown in Figure 9, the dielectric breakdown lifetime is extended in Examples 1 and Comparative Example 2 compared to Comparative Example 1. This is thought to be because both Au and Sn have an effect on improving the lifetime. Compared to Comparative Example 2, the dielectric breakdown lifetime is further extended in Example 1. This is thought to be because coating layers of both Au and Sn were deposited. However, the difference between the dielectric breakdown lifetime of Comparative Example 2 and Example 1 is larger than the difference between the dielectric breakdown lifetime of Comparative Example 1 and Comparative Example 2. This suggests that the presence of different concentration peaks for both Au and Sn between the dielectric layer and the internal electrode layer results in a synergistic effect on the extension.

[0066] For Examples 1-4 and Comparative Examples 1 and 2, reliability was judged as very good ("◎") if the lifespan was an order of magnitude longer than that of Comparative Example 1, reliability was judged as good ("〇") if the lifespan was several times longer than that of Comparative Example 1, and reliability was judged as poor ("×") if the lifespan was equal to or less than that of Comparative Example 1.

[0067] Next, the continuity of the internal electrode layer was measured for Examples 1-4 and Comparative Examples 1 and 2. Figure 10 is a diagram showing the continuity. As illustrated in Figure 10, in an observation area of ​​length L0 in a certain internal electrode layer 12, the lengths L1, L2, ..., Ln of the metal portion are measured and summed, and the ratio of the metal portion, ΣLn / L0, can be defined as the continuity of that layer. Figure 11(a) is a cross-sectional SEM image of Example 1. Figure 11(b) is a cross-sectional SEM image of Example 4. In Figures 11(a) and 11(b), the shaded area 19 is a discontinuity in the internal electrode layer 12. Cr is known to be effective in suppressing the fracture of the internal electrode layer 12. From the comparison results between Figure 11(a) and Figure 11(b), a clear difference in the continuity of the internal electrode layer 12 can be confirmed, and it can be understood that the continuity was improved by placing Cr between the dielectric layer 11 and the internal electrode layer 12. In Example 1, the continuity rate was measured at 70%. In Example 2, the continuity rate was measured at 68%. In Example 3, the continuity rate was measured at 95%. In Example 4, the continuity rate was measured at 92%. In Comparative Example 1, the continuity rate was measured at 75%. In Comparative Example 2, the continuity rate was measured at 65%.

[0068] For Examples 1-4 and Comparative Examples 1 and 2, a sample was judged to pass if it was judged to be at least very good ("◎") in terms of reliability. A sample was judged to pass if the continuity rate exceeded 65% even if the reliability was judged to be good ("〇"). A sample was judged to fail if the continuity rate was 65% or less even if the reliability was judged to be good ("〇"), or if the reliability was judged to be poor ("×"). The results are shown in Table 1. [Table 1]

[0069] Examples 1 to 4 were judged to be satisfactory. For Example 1, sufficient reliability was obtained because the concentration peaks of Au and Sn, which suppress the decrease in insulation reliability, were located at different positions between the dielectric layer and the internal electrode layer. For Example 2, sufficient reliability was obtained because the concentration peaks of Au and Fe, which suppress the decrease in insulation reliability, were located at different positions between the dielectric layer and the internal electrode layer. For Example 3, reliability was improved and the continuity was increased by placing Au and Cr between the dielectric layer and the internal electrode layer and having their concentration peaks at different positions. For Example 4, sufficient reliability was obtained because the concentration peaks of Au and Sn, which suppress the decrease in insulation reliability, were located at different positions between the dielectric layer and the internal electrode layer, and the continuity was increased further because the concentration peak of Cr was located at a different position. Note that the order in which the two or more metals used for sputtering are sputtered may be changed in the sputtering method shown in each example.

[0070] Comparative Example 1 was judged to be unsatisfactory. This is thought to be because sufficient reliability could not be obtained because a metal that suppresses the degradation of insulation reliability was not placed between the dielectric layer and the internal electrode layer. Comparative Example 2 was also judged to be unsatisfactory. This is thought to be because sufficient reliability could not be obtained because only one type of metal that suppresses the degradation of insulation reliability was placed between the dielectric layer and the internal electrode layer.

[0071] Although embodiments of the present invention have been described in detail above, the present invention is not limited to these specific embodiments, and various modifications and changes are possible within the scope of the gist of the present invention as described in the claims. [Explanation of symbols]

[0072] 10 stacked chips 11 Dielectric layer 12 Internal electrode layer 13. Cover layer 14 capacity area 15 End margin 16 Side margins 20a,20b external electrode 51 Base material 52 Dielectric Green Sheet 53 Internal electrode pattern 100 Multilayer Ceramic Capacitors

Claims

[Claim 1] The device comprises a multilayer chip in which dielectric layers and internal electrode layers are alternately stacked. Between the dielectric layer and the internal electrode layer, concentration peaks of two or more metals different from the main component metal of the internal electrode layer exist at positions in the stacking direction of the dielectric layer and the internal electrode layer. A ceramic electronic component characterized in that, among the two or more metals mentioned above, one of the metals is Sn, and the remaining metals are one or more of As, Au, Co, Cr, Cu, Fe, In, Ir, Mg, Os, Pd, Pt, Re, Rh, Ru, Se, Te, W, Y, Zn, Ag, Mo, and Ta.

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