Hybrid oxide semiconductor polysilicon transistors for high-density 2T0C gain cell eDRAM

Abstract

The present invention provides a device having a 2-transistor, 0-capacitor gain cell implementation, and a method for manufacturing the same. [Solution] The provided device includes a back-end obline-fitted 2-transistor 0-capacitor gain cell, which includes a write transistor and a read transistor electrically connected to the write transistor. The write transistor includes an oxide semiconductor channel, and the read transistor includes a polysilicon channel.

Description

Technical Field

[0001] (Cross - Reference to Related Applications) This application claims priority based on U.S. Provisional Application No. 63 / 709,875, filed with the United States Patent and Trademark Office on October 21, 2024, and the disclosure thereof is incorporated herein by reference in its entirety.

Background Art

[0002] The superiority of artificial intelligence (AI) in modern society has enabled a wide range of transformative and new applications in areas ranging from natural language processing to cancer diagnosis. Today's AI algorithms are very memory - constrained. However, the limited main memory capacity and bandwidth have become bottlenecks, and high costs are associated with data movement from DRAM.

[0003] There is a need for fast, high - density, and high - energy - efficient memory that helps reduce the current energy - intensive architecture used in AI accelerators. High - density and large - capacity on - chip memory can reduce the main memory capacity and bandwidth bottlenecks.

Summary of the Invention

[0004] One aspect is to provide a high - reliability, back - end - of - line (BEOL) - compatible two - transistor zero - capacitor (2T0C) gain cell implementation for high - density embedded dynamic random access memory (eDRAM).

[0005] According to one aspect of one or more embodiments, a device is provided having a 2-transistor 0-capacitor gain cell in a back-end obline structure, the 2-transistor 0-capacitor gain cell including a write transistor and a read transistor electrically connected to the write transistor. The write transistor includes an oxide semiconductor channel, and the read transistor includes a polysilicon channel.

[0006] According to another aspect of one or more embodiments, a system is provided comprising a front-end obline structure having a logic chip, and a back-end obline structure on the front-end obline structure, the back-end obline structure comprising a layer. The layer has a 2-transistor 0-capacitor gain cell comprising a read transistor and a write transistor electrically connected to the read transistor. The write transistor comprises an oxide semiconductor channel, and the read transistor comprises a polysilicon channel.

[0007] According to one or more embodiments, a method is provided which comprises manufacturing a first structure using a front-end obline process, the first structure comprising a logic chip; manufacturing a first tier using a back-end obline process, the first tier having a read transistor for a 2-transistor 0-capacitor gain cell; and manufacturing a second tier on the first tier using a back-end obline process, the second tier having a write transistor for the 2-transistor 0-capacitor gain cell. [Brief explanation of the drawing]

[0008] The above and / or other embodiments will become clearer and more readily apparent from the following description of various embodiments, made in connection with the attached drawings, including the following figures. [Figure 1] This shows a 2-transistor 0-capacitor (2T0C) gain cell according to one embodiment. [Figure 2] An example of a semiconductor memory device according to some embodiments is shown. [Figure 3] Figures 3 and 4 show plan views of the tiers of an exemplary layout of the 2T0C gain cell of Figure 1, according to some embodiments. [Figure 4] Figures 3 and 4 show plan views of the tiers of an exemplary layout of the 2T0C gain cell of Figure 1, according to some embodiments. [Figure 5] Figure 1 shows a plan view of an exemplary composite layout of a 2T0C gain cell according to one of the embodiments. [Figure 6] A cross-sectional view taken along line A-A' in Figure 5 is shown, according to one of the embodiments. [Figure 7] A cross-sectional view taken along line B-B' in Figure 5 is shown, according to one of the embodiments. [Figure 8] A cross-sectional view taken along line C-C' in Figure 5 is shown, according to one of the embodiments. [Figure 9] A cross-sectional view taken along line D-D' in Figure 5 is shown, according to one of the embodiments. [Figure 10] Figures 10 and 11 show plan views of the tiers of an exemplary layout of the 2T0C gain cell of Figure 1, according to some embodiments. [Figure 11] Figures 10 and 11 show plan views of the tiers of an exemplary layout of the 2T0C gain cell of Figure 1, according to some embodiments. [Figure 12] Figures 12 and 13 show cross-sectional views of an example of an embedded dynamic random access memory (eDRAM) according to some embodiments. [Figure 13] Figures 12 and 13 show cross-sectional views of an example of an embedded dynamic random access memory (eDRAM) according to some embodiments. [Figure 14] This shows a cross-sectional view of an example of a semiconductor memory device according to some embodiments. [Figure 15] This shows a monolithic integrated 3D eDRAM according to one of the embodiments. [Figure 16]This shows a 3D eDRAM with heterogeneous integration according to some embodiments. [Figure 17] A flowchart is shown illustrating a method for manufacturing embedded dynamic random access memory (eDRAM) according to some embodiments. [Figure 18] A flowchart is shown illustrating a method for manufacturing embedded dynamic random access memory (eDRAM) according to some embodiments. [Modes for carrying out the invention]

[0009] When used in this specification, the phrase “at least one of A, B, or C” includes, within its scope, “A only,” “B only,” “C only,” “A and B,” “B and C,” “A and C,” and “A, B, and C.” To be understood, the terms “first,” “second,” “third,” etc., may be used here to describe various elements, components, areas, layers, and / or sections, but these elements, components, areas, layers, or sections should not be limited by these terms. These terms are used to distinguish one element, component, area, layer, or section from another element, component, area, layer, or section, and do not represent any particular order unless the order is specifically stated. Accordingly, the “first” element, component, area, layer, or section described below may be referred to as the “second” element, component, area, layer, or section without departing from the spirit and scope of this disclosure. Please note that the components in the drawings are not necessarily drawn to scale, and some components may be exaggerated for clarity of explanation.

[0010] This disclosure relates to a hybrid 2-transistor 0-capacitor (2T0C) gain cell, and more specifically, to an embedded dynamic random access memory (eDRAM) using the same.

[0011] 2T0C gain cell eDRAM is an on-chip memory option in which transistors function as both memory elements and amplification sources providing gain. 2T0C gain cells can include types of cells that use two transistors and zero capacitors for data storage. Unlike one-transistor-one-capacitor (1T1C) DRAM cells, which rely on capacitors to store charge, 2T0C gain cells store data using the gate capacitance of the read transistor. 2T0C gain cells are well-suited to 3D stacked memory architectures and offer the advantages of using lower power and being easier to manufacture because capacitors do not need to be fabricated.

[0012] The writing transistor for a 2T0C gain cell can utilize the low off-state current that can be enabled by oxide-semiconductor (OS) based transistors. However, OS-based transistors may have reliability issues such as negative bias temperature instability (NBTI) and / or positive bias temperature instability (PBTI). NBTI may involve a mechanism in which the p-channel degrades over time due to the application of a negative gate voltage under increasing temperature. This degradation causes a shift in the transistor's threshold voltage and a decrease in drain current, which can lead to circuit malfunction. NBTI is influenced by temperature, gate voltage, time, gate oxide thickness, device area, and geometry, and is primarily caused by the generation of interface traps at the silicon-oxide interface. Interface traps are generated when the Si-H bond is broken due to an applied electric field and the presence of holes. PBTI occurs when a positive voltage is applied to the transistor's gate under increasing temperature. PBTI can lead to a shift in the transistor's threshold voltage. A shift in the threshold voltage can reduce the transistor's drive current and increase leakage. PBTI is caused by electrons being trapped within the gate dielectric material. These trapped electrons create a negative charge that degrades transistor performance. Some OS-based transistor-based gain cell eDRAMs can degrade due to NBTI and PBTI stability issues.

[0013] To address the stability issues associated with OS-based transistors, 2T0C gain cells are sometimes implemented using both OS-based and crystalline silicon-based transistors. However, high-temperature processing is used to manufacture crystalline silicon-based transistors, and therefore, they are not back-end-of-line (BEOL) compliant, but rather implemented in front-end-of-line (FEOL) structures that allow for high-temperature processing. Crystalline silicon-based transistors take up additional FEOL area, resulting in an area penalty, which can be disadvantageous for high-density memory.

[0014] The various embodiments herein provide a hybrid 2T0C gain cell implementation that is BEOL compliant and can be used in high density eDRAM. The hybrid 2T0C gain cell includes an OS-based write transistor and a polysilicon-based read transistor, which suppress concerns about reliability and are fully BEOL compliant. In some embodiments, to address reliability issues, a polysilicon channel material can be used for the read transistor of the 2T0C gain cell. The OS has some NBTI but has severe PBTI. Compared to the OS, polysilicon has improved NBTI and PBTI performance. The write transistor of the 2T0C gain cell is less affected by PBTI, and due to its low leakage, the write transistor can be OS-based. On the other hand, the read transistor of the 2T0C gain cell is susceptible to both NBTI and PBTI, and thus, although high leakage is not as much of an issue in the read transistor, polysilicon provides better performance than an OS-based one. In some embodiments, an OS-based write transistor can be stacked with a polysilicon-based transistor to form a stacked structure for the 2T0C gain cell, and the stacked structure is a BEOL stacked structure compatible with the BEOL process. In some embodiments, the 2T0C gain cells can be stacked to form 3D embedded DRAM. The various embodiments provide a fully BEOL compliant high density memory with improved reliability compared to memories using OS-based transistors and crystalline silicon-based transistors due to the improved NBTI and PBTI performance of polysilicon.

[0015] Figure 1 shows an example of a 2T0C gain cell according to one embodiment. In one embodiment, the 2T0C gain cell 1 may include a write transistor Tw and a read transistor Tr. The write transistor Tw has a gate electrically connected to the write word line (WWL), a first source / drain electrically connected to the write bit line (WBL), and a second source / drain electrically connected to the storage node (SN). The read transistor Tr has a gate electrically connected to the storage node SN, a first source / drain electrically connected to the read bit line (RBL), and a second source / drain electrically connected to the read word line (RWL). In one embodiment, the gate of the write transistor Tw can be directly connected to the WWL, the first source / drain of the write transistor Tw can be directly connected to the WBL, the second source / drain of the write transistor Tw can be directly connected to the storage node SN, the gate of the read transistor Tr can be directly connected to the storage node SN, the first source / drain of the read transistor Tr can be directly connected to the RBL, and the second source / drain of the read transistor Tr can be directly connected to the RWL.

[0016] In one embodiment, the writing transistor Tw may be an OS-based transistor. In one embodiment, the OS-based transistor may have an oxide semiconductor channel. For example, the oxide semiconductor may be selected from, but is not limited to, IGZO (InGaZnO), Sn-IGZO, IWO (InWO), IZO (InZnO), ZTO (ZnSnO), ZnO, YZO (yttrium-doped zinc oxide), IGSO (InGaSiO), InO, SnO, TiO, ZnON, MgZnO, ZrInZnO, HfInZnO, SnInZnO, AlSnInZnO, SiInZnO, AlZnSnO, GaZnSnO, or ZrZnSnO, or a combination thereof.

[0017] In one embodiment, the read transistor Tr can be a polysilicon (poly-Si) based transistor that is BEOL compatible. In one embodiment, the poly-Si based transistor can have a poly-Si channel. In some embodiments, the poly-Si based transistor is formed using low temperature polysilicon (LTPS) that is compatible with a BEOL process using a lower temperature (e.g., less than about 400° C) than the relatively high temperatures (e.g., greater than 1000° C) used in FEOL processes.

[0018] In one embodiment, the 2T0C gain cell 1 may be formed as part of a stacked structure. In one embodiment, the stacked structure may be a BEOL stacked structure having monolithic integration compatible with a BEOL process. For example, the write transistor Tw may be formed in a tier (layer) of the BEOL structure of the semiconductor memory device, distinct from the read transistor Tr, as will be described in more detail later. For example, multiple tiers may be formed within the BEOL structure of the semiconductor memory device using a low-temperature process (e.g., processing at temperatures below approximately 400°C). As used here, a tier may represent a stacked functional block or active device surface, such as a transistor tier. In some contexts, a tier may correspond to a level or metal interconnect layer of the BEOL stacked structure. In one embodiment, the read transistor Tr may be formed in a first tier of multiple tiers, and the write transistor Tw may be formed in a second tier of multiple tiers. In one embodiment, the first tier may be hybrid-bonded to the second tier. In one embodiment, the second tier containing the write transistor Tw may be located on top of the first tier containing the read transistor Tr. However, this is merely an example, and in some embodiments, a tier containing a read transistor Tr may be located above a tier containing a write transistor Tw. In one embodiment, the read transistor Tr in the first tier may be electrically connected to the write transistor Tw in the second tier by a vertical electrical connection, such as a via, formed between the first and second tiers. In one embodiment, the storage node SN of the 2T0C gain cell 1 may be provided by the parasitic capacitance of a via between the first and second tiers. A description of various layout structures of the 2T0C gain cell 1 is provided in more detail below.

[0019] In one embodiment, during a write operation, the voltages on RWL and RBL may be set to zero, and the read transistor Tr may be turned off. A high potential may be applied to WWL, and the write transistor Tw may be turned on. A voltage may be applied to WBL, and this voltage may be written to SN. For example, in one embodiment, if WBL is at a high potential, SN may be charged to a voltage close to the power supply voltage (VDD), and if WBL is at a low potential, SN may be discharged to ground potential (VSS). The voltage in SN determines the gate voltage of the read transistor Tr. After a voltage has been written to SN, a low potential may be applied to WWL to turn off the write transistor Tw. Thus, a charge remains in SN due to the parasitic capacitance in SN, and the potential is stored in SN.

[0020] In one embodiment, during a read operation, a low potential may be supplied to the WWL, causing the write transistor Tw to turn off. In one embodiment, a voltage such as VDD or VSS may be applied to the RBL to precharge it to the voltage (e.g., VDD or VSS), allowing the potential at SN to be read on the RWL. For example, if a high potential is stored for SN, the read transistor Tr turns on, allowing a first level to be sensed on the RWL. If a low potential is stored for SN, the read transistor remains off, allowing a second level to be sensed on the RWL. Although the above-described write and read operations are explained by referring to the use of a high potential to turn on the write transistor Tw and the read transistor Tr, this explanation is merely an example, and in some embodiments, a low potential may be used to turn on the write transistor Tw and the read transistor Tr.

[0021] Figure 2 shows a semiconductor memory device according to one embodiment. According to one embodiment, the semiconductor memory device 100 may include a memory cell array (MCA), control logic 10, an RWL decoder 20, a WWL decoder 30, a precharger and write driver 40, a plurality of sense amplifiers (SA) 50, and a column decoder 60. The MCA may include a plurality of memory cells (MC) arranged in a grid structure. In one embodiment, each MC may be a 2T0C gain cell 1 as shown in Figure 1. In one embodiment, each MC may be arranged in a BEOL stacked structure as described herein. Each MC may be electrically connected to the RWL decoder 20 via a corresponding RWL, to the WWL decoder 30 via a corresponding WWL, to the precharger and write driver 40 via a corresponding RBL and a corresponding WBL, and to a corresponding one of a plurality of sense amplifiers 50 via a corresponding RBL. The plurality of sense amplifiers 50 may be electrically connected to the column decoder 60.

[0022] The control logic 10 can control each of the RWL decoder 20, WWL decoder 30, precharger and write driver 40, multiple SAs 50, and column decoder 60 based on one or more control signals received from outside the semiconductor memory device 100.

[0023] The RWL decoder 20 receives a read word line control signal from the control logic 10 and can apply a potential to one of the multiple RWLs based on the read word line control signal.

[0024] The WWL decoder 30 receives a write word line control signal from the control logic 10 and can apply a potential to one of the multiple WWLs based on the write word line control signal.

[0025] The precharger and write driver 40 receives a precharge control signal from the control logic 10 and can precharge one or more of the RBLs based on the precharge control signal. The precharger and write driver 40 also receives a write control signal from the control logic 10 and can assert or deassert one of the WBLs based on the write control signal.

[0026] Multiple SA50s, under the control of the control logic 10, can sense stored data from one of the SNs of multiple MCs, amplify the data, and output the data to the column decoder 60. The column decoder 60 can receive a column control signal from the control logic 10 and output the data (DATA) to the outside of the semiconductor memory device 100.

[0027] In one embodiment, during the writing operation of the memory cell (MC), the control logic 10 can control the RWL decoder 20, the precharger, and the write driver 40 to apply a low potential to one of the RWL and RBL of the MC, thereby turning off the read transistor Tr of the memory cell MC. The control logic 10 can also control the WWL decoder 30 to apply a high potential to the WWL of the MC, thereby turning on the write transistor Tw of the MC. The control logic 10 can control the precharger and the write driver 40 to supply a high or low potential to the WBL of the MC according to the data to be written to the MC, and the voltage corresponding to the data to be written is stored in SN. For example, in one embodiment, when the control logic 10 controls the precharger and the write driver 40 to assert the WBL of the MC, the storage node SN of the memory cell MC is charged to VDD, and when the control logic 10 controls the precharger and the write driver 40 to apply a low potential to the WBL, the SN of the MC is discharged to VSS. After a voltage is written to the SN of the MC, the control logic 10 controls the WWL decoder 30 to apply a low potential to the WWL of the MC's writing transistor Tw. Therefore, a charge remains on the MC's SN due to the parasitic capacitance in the SN, and the potential is stored by the MC's SN. The writing operation is described for one of several MCs. However, the writing operation for the remaining MCs is the same, and a repeated explanation is omitted for brevity.

[0028] In one embodiment, during the MC read operation, the control logic 10 controls the WWL decoder 30 to apply a low potential to the MC's WWL and turn off the MC's write transistor Tw. The control logic 10 controls the RWL decoder 20 to apply VDD or VSS to the MC's RWL, allowing the RWL to be precharged to VDD or VSS, and the data stored in the MC's SN can be read out onto the MC's RBL by the corresponding sense amplifier 50. For example, if the MC's SN stores a high potential, the read transistor Tr turns on and a first level can be sensed on the RBL by the sense amplifier 50; if the storage node SN stores a low potential, the read transistor remains off and a second level can be sensed on the RBL by the sense amplifier 50. The read operation has been described for one of several MCs. However, the read operation for the remaining MCs is the same, and repeated explanations are omitted for brevity.

[0029] Figures 3 and 4 show plan views of the tiers of an exemplary layout of the 2T0C gain cell of Figure 1, according to some embodiments. Figure 5 shows a plan view of an exemplary composite layout of the 2T0C gain cell of Figure 1, according to some embodiments. For example, Figure 5 shows a plan view of a composite layout combining the tiers shown in Figures 3 and 4. Figures 6-9 show cross-sectional views taken along lines A-A', B-B', C-C', and D-D' in Figure 5, respectively, according to some embodiments. Referring to Figures 1 and 6, in one embodiment, the 2T0C gain cell 1 can be formed in a stacked structure. In one embodiment, the stacked structure may be a BEOL stacked structure compatible with a BEOL process. For example, as described above, multiple tiers may be formed within the BEOL structure of a semiconductor memory device. In one embodiment, each of the multiple tiers may include an insulating layer and transistors formed within the insulating layer. Each tier may be a transistor tier formed using a low-temperature process (e.g., a BEOL process using temperatures below about 400°C).

[0030] In one embodiment, the tiers may include a first tier (Tier 1) and a second tier (Tier 2). In one embodiment, as shown in Figure 6, Tier 1 may include an insulating layer 210, a gate line 220, a gate insulating layer 225, a first source / drain region 230, a second source / drain region 240, and a channel region 280. In one embodiment, the gate line 220, the first source / drain region 230, and the second source / drain region 240 may correspond to the gate, first source / drain, and second source / drain of the readout transistor Tr shown in Figure 1, respectively.

[0031] In one embodiment, the gate line 220, gate insulating layer 225, first source / drain region 230, second source / drain region 240, and channel region 280 may be located within the insulating layer 210. In one embodiment, as shown in Figure 6, the channel region 280 may be located between the first source / drain region 230 and the second source / drain region 240 in a first direction D1. In one embodiment, as shown in Figure 7, the sidewalls of the channel region 280 in a second direction D2 may be surrounded by the insulating layer 210. When used in this specification, the first direction D1 may intersect with the second direction D2, and the third direction D3 may be perpendicular to each of the first and second directions D1 and D2. The third direction D3 may be referred to as the up and down direction.

[0032] In one embodiment, as shown in Figures 6 and 7, the gate line 220 may be positioned on the channel region 280 in a third direction D3. In one embodiment, the gate line 220 may completely cover the channel region 280 in a first direction D1. The gate line 220 may be positioned on the channel region 280 with a gate insulating layer 225 between the gate line 220 and the channel region 280 in a third direction D3. In one embodiment, the gate line 220 may be in contact with the gate insulating layer 225, and the gate insulating layer 225 may be in contact with the channel region 280. The gate line 220, the gate insulating layer 225, the first source / drain region 230, the second source / drain region 240, and the channel region 280 may each extend in a second direction D2. In one embodiment, the top surfaces of the gate line 220, the first source / drain region 230, and the second source / drain region 240 may be covered by an insulating layer 210.

[0033] In one embodiment, as shown in Figure 8, vias 290 can extend through the insulating layer 210 to connect the second source / drain region 240 to the RBL. In one embodiment, the RBL may be directly connected to the second source / drain region 240 by vias 290. In some embodiments, a wiring pattern may be connected to vias 290 to connect to the RBL.

[0034] In one embodiment, the channel region 280 may be the region between the first source / drain 230 and the second source / drain 240, and may be included in the active region where the gate line 220 of the readout transistor Tr, the first source / drain 230, and the second source / drain 240 are formed. In one embodiment, the channel region 280 may include polysilicon (polySi). For example, the polySi may be low-temperature polySi suitable for BEOL processes that use lower temperatures (e.g., less than about 400°C) than the relatively high temperatures (e.g., above 1000°C) used in FEOL processes.

[0035] Referring again to Figures 1 and 6, in one embodiment, Tier 2 can be located on Tier 1. For example, Tier 2 may be located on the insulating layer 210 of Tier 1. In one embodiment, Tier 2 may overlap with Tier 1 in a third direction D3. In one embodiment, as shown in Figure 6, Tier 2 may include an insulating layer 310, a gate line 320, a gate insulating layer 325, a first source / drain region 330, a second source / drain region 340, and a channel region 380.

[0036] In one embodiment, the gate line 320, the first source / drain region 330, and the second source / drain region 340 may correspond to the gate, first source / drain, and second source / drain of the writing transistor Tw shown in Figure 1, respectively.

[0037] In one embodiment, the gate line 320, gate insulating layer 325, first source / drain region 330, second source / drain region 340, and channel region 380 may be located within the insulating layer 310. In one embodiment, as shown in Figure 7, the channel region 380 may be located between the first source / drain region 330 and the second source / drain region 340 in the second direction D2.

[0038] In one embodiment, as shown in Figure 7, the gate line 320 may be positioned on the channel region 380 in a third direction D3. In one embodiment, the gate line 320 may completely cover the channel region 380 in a second direction D2. The gate line 320 may be positioned on the channel region 380 with a gate insulating layer 325 between the gate line 320 and the channel region 380 in a third direction D3. In one embodiment, the gate line 320 may be in contact with the gate insulating layer 325, and the gate insulating layer 325 may be in contact with the channel region 380. The gate line 320, the gate insulating layer 325, the first source / drain region 330, the second source / drain region 340, and the channel region 380 may each extend in a first direction D1. In one embodiment, as shown in Figure 7, the top surfaces of the gate line 320, the first source / drain region 330, and the second source / drain region 340 may be covered by an insulating layer 310. In one embodiment, as shown in Figure 7, a via 360 can extend through the insulating layer 310 to electrically connect the WWL to the gate line 320. In one embodiment, the WWL can be directly connected to the gate line 320 via the via 360. As shown in Figure 7, the second source / drain region 340 of the write transistor Tw can be electrically connected to the gate line 220 of the read transistor Tr by a via 250. In one embodiment, the via 250 can be directly connected to the second source / drain region 340 of the write transistor Tw and also directly connected to the gate line 220 of the read transistor Tr.

[0039] In one embodiment, as shown in Figure 9, a via 390 can extend through the insulating layer 310 to connect the first source / drain region 330 to the WBL. In one embodiment, the WBL can be directly connected to the first source / drain region 330 by the via 390. In some embodiments, a wiring pattern may be connected to the via 390 to connect to the WBL.

[0040] In one embodiment, the channel region 380 may include an oxide semiconductor. For example, the oxide semiconductor may be selected from, but is not limited to, IGZO (InGaZnO), Sn-IGZO, IWO (InWO), IZO (InZnO), ZTO (ZnSnO), ZnO, YZO (yttrium-doped zinc oxide), IGSO (InGaSiO), InO, SnO, TiO, ZnON, MgZnO, ZrInZnO, HfInZnO, SnInZnO, AlSnInZnO, SiInZnO, AlZnSnO, GaZnSnO, or ZrZnSnO, or a combination thereof.

[0041] In one embodiment, the channel region 380 may be the region between the first source / drain 330 and the second source / drain 340, and may be included in the active region where the gate line 320 of the write transistor Tw, the first source / drain 330, and the second source / drain 340 are formed. In one embodiment, the channel region 380 may be perpendicular to the channel region 280 in a plan view, as is best seen in Figures 3-5.

[0042] Figure 10 shows a plan view of the tiers of an exemplary layout of the 2T0C gain cell of Figure 1, taken along A-A' in Figure 5, according to one embodiment. Figure 11 shows a plan view of the tiers of an exemplary layout of the 2T0C gain cell of Figure 1, taken along B-B' in Figure 5. Figures 10 and 11 correspond to the cross-sectional views shown in Figures 6 and 7, respectively, except that the components of the read transistor Tr are mounted in Tier 2 and the components of the write transistor Tw are mounted in Tier 1. In one embodiment, Tier 2 overlaps Tier 1 vertically in the third direction D3. In Figure 10, components similar to those in Figure 6 are indicated by the same reference numerals, and in Figure 11, components similar to those in Figure 7 are indicated by the same reference numerals; their repeated descriptions are omitted for brevity.

[0043] As shown in Figure 10, the first source / drain region 230, the channel region 280, and the second source / drain region 240 of the read transistor Tr may be located on the insulating layer 310. Unlike in the stacked structure of Figure 6, vias 250 can extend from the bottom of the gate line 220 of the read transistor Tr to the top of the second source / drain region 340 of the write transistor Tw.

[0044] In one embodiment, to realize an MC arranged in the grid structure of the MCA shown in Figure 2, a plurality of read transistors Tr are arranged in Tier 1, spaced apart from each other in both the first direction D1 and the second direction D2, and a plurality of write transistors Tw are arranged in Tier 2, spaced apart from each other in both the first direction D1 and the second direction D2, and each can be stacked on top of the read transistors Tr. In other words, the read transistors Tr in Tier 1 and the write transistors Tw in Tier 2 can be repeated in both the first direction D1 and the second direction D2 to realize the MCA shown in Figure 2.

[0045] Figure 12 shows a cross-sectional view of an example eDRAM taken along line A-A' in Figure 5, according to one embodiment. Figure 13 shows a cross-sectional view of an example eDRAM taken along line B-B' in Figure 5, according to one embodiment. Figures 12 and 13 correspond to the cross-sectional views shown in Figures 6 and 7, respectively. In Figure 12, components similar to those in Figure 6 are referred to by the same reference numerals, and in Figure 13, components similar to those in Figure 7 are referred to by the same reference numerals; their repeated descriptions are omitted for brevity. In one embodiment, the eDRAM may include a plurality of eDRAM layers stacked in a third direction D3. For example, the plurality of eDRAM layers may include a first eDRAM layer (eDRAM Layer 1), a second eDRAM layer (eDRAM Layer 2), ..., an Xth eDRAM layer (eDRAM Layer X), stacked in a third direction D3. Each of the eDRAM Layers 1, 2, ..., and X may include the BEOL stacked structure shown in Figures 6-9. For example, in one embodiment, as shown in Figure 6, eDRAM Layer 1 may include Tier 1, which mounts the read transistor Tr shown in Figure 1, and Tier 2, which mounts the write transistor Tw shown in Figure 1, and Tier 2 may be stacked on top of Tier 1 in the third direction D3. As shown in Figure 6, eDRAM Layer 2 may include Tier 1, which mounts the read transistor Tr shown in Figure 1, and Tier 2, which mounts the write transistor Tw shown in Figure 1, and Tier 2 may be stacked on top of Tier 1. As shown in Figure 6, eDRAM Layer X may include Tier 1, which mounts the read transistor Tr shown in Figure 1, and Tier 2, which mounts the write transistor Tw shown in Figure 1, and Tier 2 may be stacked on top of Tier 1. In some embodiments, one or more of the layers may have a BEOL stacked structure, as shown in Figure 10, in which Tier 2 is stacked on Tier 1, with Tier 1 mounting the write transistor Tw shown in Figure 1 and Tier 2 mounting the read transistor Tr shown in Figure 1.In some embodiments, each of the multiple eDRAM layers may have a BEOL stacked structure, as shown in Figure 10, in which Tier 2 is stacked on Tier 1, with Tier 1 mounting the write transistor Tw shown in Figure 1 and Tier 2 mounting the read transistor Tr shown in Figure 1.

[0046] In one embodiment, to realize the MCA shown in Figure 2, a plurality of read transistors Tr are arranged in Tier 1, spaced apart from each other in both the first direction D1 and the second direction D2, and a plurality of write transistors Tw are arranged in Tier 2, spaced apart from each other in both the first direction D1 and the second direction D2, and each can be stacked on top of the read transistors Tr.

[0047] In one embodiment, each of the eDRAM Layer 1, eDRAM Layer 2, ..., eDRAM Layer X may include a plurality of read transistors Tr arranged in Tier 1 spaced apart from each other in both the first direction D1 and the second direction D2, and a plurality of write transistors Tw arranged in Tier 2 spaced apart from each other in both the first direction D1 and the second direction D2, and each stacked on top of the read transistors Tr, in order to achieve the 3D arrangement of memory cells MC in the MCA shown in Figure 2.

[0048] Figure 14 shows a cross-sectional view of an example of a semiconductor memory device according to some embodiments.

[0049] In one embodiment, the semiconductor memory device 1000 may include a first structure 500 and a second structure 600. The first structure 500 has a top surface (SF), and the second structure 600 may be placed on the top surface (SF) of the first structure 500. In one embodiment, the first structure 500 may be FEOL compliant, and therefore, the first structure 500 may be manufactured using a FEOL process at a temperature higher than, for example, 1000°C. In one embodiment, the second structure 600 may be BEOL compliant, and therefore, the second structure 600 may be manufactured using a BEOL process at a temperature lower than, for example, about 400°C.

[0050] In one embodiment, the first structure 500 may include a substrate 510 and an upper dielectric layer 560 on the substrate 510. The substrate 510 may be a silicon substrate and may include a plurality of PMOS transistors 515 within the substrate 510 separated by a shallow trench isolation (STI) structure 520. Each PMOS transistor 515 may include a P-well 530. The P-well may have N-doped regions 535 and 540 therein as the source and drain of the PMOS transistor 515. A gate 550 may be located on the P-well 530. A plurality of vias 570 may be located on the gate 550 and the N-doped well 535 so as to extend to the top surface SF of the FEOL structure 500. However, the first structure 500 is merely an example, and in some embodiments, the first structure 500 may be configured differently, as long as the first structure includes one or more transistors. In some embodiments, the one or more transistors may be contained in one or more logic chips.

[0051] The second structure 600 may include a plurality of connection layers 610. One or more of the plurality of connection layers 610 may include an insulating layer 620, one or more wiring patterns 630, and one or more vias 640. The plurality of connection layers 610 may include a BEOL-compliant stacked structure as described above. For example, according to the embodiments of Figures 1 and 6 described above, one of the plurality of connection layers 610 may include the read transistor Tr shown in Figure 1 in Tier 1, and another of the plurality of connection layers 610 may include the write transistor Tw shown in Figure 1 in Tier 2. In some embodiments, according to the embodiments of Figures 1 and 10 described above, one of the plurality of connection layers 610 may include the write transistor Tw shown in Figure 1 in Tier 1, and another of the plurality of connection layers 610 may include the read transistor Tr shown in Figure 1 in Tier 2.

[0052] According to various embodiments, a hybrid 2T0C gain cell may include an OS-based write transistor stacked with a polysilicon-based read transistor to form a stacked structure, the stacked structure being BEOL-compliant. In some embodiments, multiple hybrid 2T0C gain cells can be repeatedly stacked to form a 3D embedded DRAM in monolithic integration. Various embodiments provide high-density memory that is fully BEOL-compliant and offers improved reliability.

[0053] Figure 15 shows a system having monolithic integration according to some embodiments. In one embodiment, system 1500 may implement 3D eDRAM. In one embodiment, system 1500 may be implemented as a single chip. In one embodiment, system 1500 may include a first structure 1510 and a second structure 1520. In one embodiment, the second structure 1520 may include a plurality of 2T0C gain cells as illustrated and described with respect to Figures 1 and 6. For example, in some embodiments, the second structure 1520 may include a plurality of eDRAM structures as illustrated and described with respect to Figures 12 and 13, spaced apart in a direction parallel to the first structure 1510. In one embodiment, the second structure 1520 may include a first eDRAM layer 1530 and a second eDRAM layer 1540. Although two eDRAM layers are shown in Figure 15, embodiments are not limited to two eDRAM layers, and in some embodiments, a plurality of eDRAM layers may be provided, as shown by the dotted lines in Figure 15.

[0054] In one embodiment, the first structure 1510 can be a FEOL-compliant FEOL structure, and therefore, the first structure 1510 can be manufactured using a FEOL process at a temperature higher than, for example, about 1000°C. The first structure 1510 may include one or more transistors. In one embodiment, the first structure 1510 may include one or more logic chips. For example, one or more logic chips may include one or more transistors.

[0055] In one embodiment, the second structure 1520 can be a BEOL-compliant structure, and therefore the second structure 1520 can be manufactured using a BEOL process at a temperature lower than, for example, about 400°C. The first eDRAM layer 1530 can be on the top surface of the first structure 1510, and the second eDRAM layer 1540 can be on the top surface of the first eDRAM layer 1530. In one embodiment, the first eDRAM layer 1530 can be formed on the first structure 1510, and the second eDRAM layer 1540 can be formed on the first eDRAM layer 1530. In some embodiments, the first eDRAM layer 1530 may be hybrid-bonded to the first structure 1510, and the second eDRAM layer 1540 may be hybrid-bonded to the first eDRAM layer 1530.

[0056] In one embodiment, the first eDRAM layer 1530 may include a first layer 1533 on a first structure 1510 and a second layer 1536 on the first layer 1533. In one embodiment, as shown in Figure 15, the first layer 1533 may be on the top surface of the first structure 1510. In one embodiment, the first layer 1533 may include a plurality of Tier 1s. For example, each of the Tier 1s may include a read transistor Tr, as illustrated and described with respect to Figures 1 and 6. In one embodiment, the plurality of Tier 1s of the first layer 1533 may be spaced apart from each other in a direction parallel to the top surface of the first structure 1510, as shown in Figure 15. In one embodiment, the second layer 1536 may each include a plurality of Tier 2s on a plurality of Tier 1s of the first layer 1533. For example, each of the Tier 2s may include a write transistor Tw, as illustrated and described with respect to Figures 1 and 6. In one embodiment, multiple Tier 2s may be spaced apart from each other in a direction parallel to the top surface of the first structure 1510, as shown in Figure 15. In one embodiment, a combination of one of the multiple Tier 1s of the first layer 1533 and one of the multiple Tier 2s of the second layer 1536 corresponds to the 2T0C gain cell 1 in Figure 1 formed in the stacked structure shown in Figure 6. In other words, the first eDRAM layer 1530 may include multiple 2T0C gain cells 1 spaced apart from each other in a direction parallel to the top surface of the first structure 1510. Figure 15 shows the 2T0C gain cells 1 of the first eDRAM layer 1530 having a stacked structure according to Figure 6, but this stacked structure is merely an example, and in some embodiments, the system may include 2T0C gain cells 1 having a stacked structure illustrated and described with respect to Figure 10.

[0057] The second eDRAM layer 1540 may include the first layer 1543 and the second layer 1546. The first layer 1543 of the second eDRAM layer 1540 may be located on the second layer 1536 of the first eDRAM layer 1530. In one embodiment, as shown in Figure 15, the first layer 1543 of the second eDRAM layer 1540 may be located on the top surface of the second layer 1536 of the first eDRAM layer 1530. In one embodiment, the first layer 1543 may include a plurality of Tier 1s. For example, each of the Tier 1s may include a read transistor Tr, as illustrated and described with respect to Figures 1 and 6. In one embodiment, the plurality of Tier 1s of the first layer 1543 may be spaced apart from each other in a direction parallel to the top surface of the first structure 1510, as shown in Figure 15. In one embodiment, the second layer 1546 may include a plurality of Tier 2s on a plurality of Tier 1s of the first layer 1543. For example, each of the Tier 2s may include a write transistor Tw, as illustrated and described with respect to Figures 1 and 6. In one embodiment, the plurality of Tier 2s may be spaced apart from each other in a direction parallel to the top surface of the first structure 1510, as shown in Figure 15. In one embodiment, a combination of one of the Tier 1s of the first layer 1543 and one of the plurality of Tier 2s of the second layer 1546 corresponds to the 2T0C gain cell 1 in Figure 1 formed in the stacked structure shown in Figure 6. In other words, the second eDRAM layer 1540 may include a plurality of 2T0C gain cells 1 spaced apart from each other in a direction parallel to the top surface of the first structure 1510. Figure 15 shows a 2T0C gain cell 1 in a second eDRAM layer 1540 having a stacked structure according to Figure 6, but this stacked structure is just one example, and in some embodiments, the system may include a 2T0C gain cell 1 having a stacked structure illustrated and described with respect to Figure 10.

[0058] As described above, in one embodiment, the first eDRAM layer 1530 may be hybrid bonded to the first structure 1510 such that the first layer 1533 is hybrid bonded to the first structure 1510. In one embodiment, the second eDRAM layer 1540 may be hybrid bonded to the first eDRAM layer 1530 such that the first layer 1543 of the second eDRAM layer 1540 is hybrid bonded to the second layer 1536 of the first eDRAM layer 1530.

[0059] Figure 16 shows a heterogeneous integrated system according to some embodiments. In one embodiment, system 1600 may be a 3D eDRAM and may include a first chiplet (Chiplet-1) 1610 and a plurality of second chiplets (Chiplet-2) 1620. In one embodiment, Chiplet-1 1610 may be a FEOL structure manufactured by a FEOL process. In one embodiment, Chiplet-1 1610 may include one or more transistors. In one embodiment, Chiplet-1 1610 may include one or more logic chips. For example, one or more logic chips may include one or more transistors.

[0060] In one embodiment, multiple Chiplet-2 1620 may be manufactured separately from the manufacture of Chiplet-1 1610. In one embodiment, each of the multiple Chiplet-2 1620 may be a BEOL structure manufactured in a BEOL process. In one embodiment, each of the multiple Chiplet-2 1620 may be manufactured separately from the manufacture of Chiplet-1 1610. In one embodiment, each of the multiple Chiplet-2 1620 may be manufactured separately from each other.

[0061] In one embodiment, a plurality of Chiplet-2 1620 may be arranged in a first row 1624 on Chiplet-1 1610, spaced apart in a first direction parallel to the top surface of Chiplet-1 1610. In one embodiment, the plurality of Chiplet-2 1620 may be further arranged in a second direction, spaced apart from each other in a second direction parallel to the top surface of Chiplet-1 1610 and intersecting the first direction. In one embodiment, each of the plurality of Chiplet-2 1620 in the first row 1624 may have a hybrid bond 1630 with Chiplet-1 1610.

[0062] In some embodiments, multiple Chiple-2 1620 may be spaced apart in a first and / or second direction and arranged in a second row 1627 so as to correspond to multiple Chiple-2 1620 in a first row 1624. In other words, multiple Chiple-2 1620 can be stacked in a third direction orthogonal to the first and second directions to form a 3D eDRAM structure. In one embodiment, each of the multiple Chiple-2 in the second row 1627 may have a hybrid junction 1630 with a corresponding one of the multiple Chiple-2 1620 in the first row 1624, thus forming a heterogeneous 3D eDRAM.

[0063] In one embodiment, each of the multiple Chiplet-2 1620 may have a 2T0C gain cell 1 as shown in Figures 1 and 6, and thus may include a Tier 1 having a read transistor Tr and a Tier 2 having a write transistor Tw on Tier 1. Figure 16 shows a Chiplet-2 1620 having a 2T0C gain cell 1 with a stacked structure illustrated and described with respect to Figure 6, but this stacked structure is merely an example, and in some embodiments, the Chiplet-2 1620 may include a 2T0C gain cell 1 with a stacked structure illustrated and described with respect to Figure 10.

[0064] Figure 17 shows a flowchart illustrating a method for manufacturing an eDRAM according to some embodiments. In one embodiment, the method for manufacturing an eDRAM may include processes S10-S30. In one embodiment, the method for manufacturing an eDRAM may be used to manufacture a 3D eDRAM having monolithic integration as shown in Figure 15.

[0065] In process S10, the first structure can be manufactured. For example, in one embodiment, the first structure may be manufactured using a FEOL process. The FEOL process may be performed at a temperature higher than approximately 1000°C. The first structure may correspond to the first structure 500 shown in Figure 14, the first structure 1510 shown in Figure 15, or Chiplet-1 in Figure 16. In one embodiment, the first structure may include one or more transistors. In one embodiment, the first structure may include one or more logic chips. For example, one or more logic chips may include one or more transistors.

[0066] In process S20, Tier 1 can be manufactured on the first structure. In one embodiment, Tier 1 may be manufactured using a BEOL process. The BEOL process may be performed at a temperature lower than approximately 400°C. For example, Tier 1 may be the Tier 1 illustrated and described with respect to Figures 1 and 6, or the Tier 1 illustrated and described with respect to Figures 1 and 10. In some embodiments, Tier 1 may correspond to the first layer 1533 shown in Figure 15 and may include multiple Tier 1s, and manufacturing Tier 1 may include manufacturing multiple Tier 1s of the first layer 1533 on the top surface of the first structure 1510 in Figure 15. In one embodiment, the multiple Tier 1s may be spaced apart from each other in a direction parallel to the top surface of the first structure 1510, as shown in Figure 15.

[0067] In process S30, Tier 2 can be manufactured on Tier 1. In one embodiment, Tier 2 may be manufactured using a BEOL process. The BEOL process may be performed at a temperature lower than approximately 400°C. For example, Tier 2 may be the Tier 2 illustrated and described with respect to Figures 1 and 6, or the Tier 2 illustrated and described with respect to Figures 1 and 10. In some embodiments, Tier 2 may correspond to the second layer 1536 shown in Figure 15, and each may include multiple Tier 2s on multiple Tier 1s of the first layer 1533, and manufacturing Tier 2 may include manufacturing multiple Tier 2s on multiple Tier 1s, as shown in Figure 15. In one embodiment, the multiple Tier 2s may be spaced apart from each other in a direction parallel to the top surface of the first structure 1510, as shown in Figure 15.

[0068] Figure 18 shows a flowchart illustrating a method for manufacturing an eDRAM according to one embodiment. In one embodiment, the method for manufacturing an eDRAM may include processes S110-S130.

[0069] In process S110, the first chiplet can be manufactured. In one embodiment, the first chiplet may correspond to Chiplet-1 in Figure 16. The first chiplet can be manufactured using the FEOL process. The FEOL process can be carried out at a temperature higher than approximately 1000°C.

[0070] In process S120, a second chiplet can be manufactured. In one embodiment, the second chiplet may correspond to Chiplet-2 in Figure 16 and may be manufactured as a separate chiplet from the first chiplet. In one embodiment, the second chiplet may be manufactured by a BEOL process. The BEOL process may be performed at a temperature lower than approximately 400°C. For example, in some embodiments, the second chiplet may include a tier 1 having a read transistor Tr and a tier 2 having a write transistor Tw, and may correspond to Chiplet-2 illustrated and described with respect to Figure 16, for example. In some embodiments, the manufacturing of the second chiplet may include manufacturing a plurality of Chiplet-2s, as described above with respect to Figure 16.

[0071] In process S130, the first chiplet and the second chiplet are joined together by hybrid bonding to form a 3D eDRAM with heterogeneous integration.

[0072] Exemplary implementation Ahhh.

[0073] Various exemplary implementations are described by referring to the following numbered sections.

[0074] 1. A hybrid 2T0C gain cell eDRAM having a stack of tiers having a first tier and a second tier, wherein one of the first tier and the second tier in the hybrid 2T0C gain cell eDRAM has an oxide semiconductor as a write transistor, and the other of the first tier and the second tier has polysilicon as a read transistor.

[0075] 2. The hybrid 2T0C gain cell eDRAM according to item 1, wherein the first tier and the second tier are repeated to form a 3D 2T0C gain cell eDRAM.

[0076] 3. The hybrid 2T0C gain cell eDRAM according to item 1, wherein the first tier has the oxide semiconductor as the write transistor and the second tier has the polysilicon as the read transistor.

[0077] 4. The hybrid 2T0C gain cell eDRAM according to item 1, wherein the first tier has the polysilicon as the read transistor and the second tier has the oxide semiconductor as the write transistor.

[0078] 5. The hybrid 2T0C gain cell eDRAM according to item 1, wherein the oxide semiconductor comprises indium oxide.

[0079] 6. The hybrid 2T0C gain cell eDRAM according to item 1, wherein the oxide semiconductor comprises indium tin oxide.

[0080] 7. The hybrid 2T0C gain cell eDRAM according to item 1, wherein the oxide semiconductor has indium gallium zinc oxide.

[0081] 8. The hybrid 2T0C gain cell eDRAM according to item 1, wherein the oxide semiconductor has tin oxide.

[0082] 9. The hybrid 2T0C gain cell eDRAM according to item 1, wherein the oxide semiconductor comprises zinc oxide.

[0083] 10. The hybrid 2T0C gain cell eDRAM according to item 1, wherein the oxide semiconductor has Si-doped indium oxide.

[0084] 11. The hybrid 2T0C gain cell eDRAM according to item 1, wherein the oxide semiconductor has Ge-doped indium oxide.

[0085] 12. The hybrid 2T0C gain cell eDRAM according to item 1, wherein the oxide semiconductor has W-doped indium oxide.

[0086] 13. A structure having a first tier and a second tier, wherein the second tier is stacked on the first tier and connected to a storage node, the first tier has a read word line, a read bit line, a storage node, gate metal, and a transistor channel, the second tier has a write word line, a write bit line, a storage node, gate metal, and a transistor channel, the transistor channel in the first tier has polysilicon, the transistor channel in the second tier has an oxide semiconductor, and the transistor channel of the first tier and the transistor channel of the second tier are perpendicular to each other.

[0087] 14. The structure according to item 13, wherein the first tier and the second tier are repeated to form a 3D 2T0C eDRAM.

[0088] 15. A logic chip having a BEOL having the structure described in Section 13, wherein both the first tier and the second tier are manufactured and repeated.

[0089] 16. A logic chip having the structure described in Section 13, wherein both the first tier and the second tier are manufactured as separate chiplets and integrated with the logic chip through 3D heterogeneous integration.

[0090] 17. A structure having a first tier and a second tier, wherein the second tier is stacked on the first tier and connected to a storage node, the first tier has a write word line, a write bit line, a storage node, a gate metal, and a transistor channel, the second tier has a read word line, a read bit line, a storage node, a gate metal, and a transistor channel, the transistor channel in the first tier has an oxide semiconductor, the transistor channel in the second tier has polysilicon, and the transistor channel of the first tier and the transistor channel of the second tier are perpendicular to each other.

[0091] 18. The structure according to item 17, wherein the first tier and the second tier are repeated to form a 3D 2T0C eDRAM.

[0092] 19. A logic chip having a BEOL having the structure described in Section 17, wherein both the first tier and the second tier are manufactured and repeated.

[0093] 20. A logic chip having the structure described in Section 17, wherein both the first tier and the second tier are manufactured as separate chiplets and integrated with the logic chip through 3D heterogeneous integration.

[0094] 21. A hybrid 2T0C gain cell eDRAM having a stack of tiers having a first tier and a second tier, wherein one of the first tier and the second tier has an oxide semiconductor and the other of the first tier and the second tier has polysilicon.

[0095] 22. The hybrid 2T0C gain cell eDRAM described in item 21, wherein the first tier and the second tier are repeated to form a 3D 2T0C gain cell eDRAM.

[0096] 23. A structure having a first tier and a second tier, wherein the second tier is stacked on the first tier and connected to a storage node, the first tier has a read word line, a read bit line, a storage node, a gate metal, and a transistor channel, the second tier has a write word line, a write bit line, a storage node, a gate metal, and a transistor channel, the transistor channel in the first tier has polysilicon, the transistor channel in the second tier has an oxide semiconductor, and the components of the first tier and the components of the second tier are perpendicular to each other.

[0097] 24. The structure according to item 23, wherein the first tier and the second tier are repeated to form a 3D 2T0C eDRAM.

[0098] 25. The structure according to paragraph 23 or 24, wherein both the first tier and the second tier are fabricated and repeated within the BEOL of the logic chip.

[0099] 26. The structure according to any one of items 23 to 25, wherein both the first tier and the second tier are manufactured as separate chiplets and integrated with a logic chip through 3D heterogeneous integration.

[0100] 31. A hybrid 2-transistor 0-capacitor (2T0C) gain cell having a back-end ob-line (BEOL) stacked structure including a first tier and a second tier stacked on the first tier, wherein one of the first tier and the second tier has a write transistor having an oxide semiconductor channel, and the other of the first tier and the second tier has a read transistor having a polysilicon channel.

[0101] 32. The hybrid 2T0C gain cell according to item 31, wherein the oxide semiconductor channel is perpendicular to the polysilicon channel in a plan view.

[0102] 33. A hybrid 2T0C gain cell according to item 31 or 32, wherein the write transistor in one of the first and second tiers is connected by a storage node to the read transistor in the other of the first and second tiers.

[0103] 34. The second tier is a hybrid 2T0C gain cell according to any one of items 31 to 33, which overlaps the first tier in the vertical direction.

[0104] 35. A hybrid 2T0C gain cell according to any one of claims 31 to 34, wherein the first tier has the write transistor and the second tier has the read transistor.

[0105] 36. A hybrid 2T0C gain cell according to any one of claims 31 to 35, wherein the first tier has the read transistor and the second tier has the write transistor.

[0106] 37. A hybrid 2T0C gain cell according to any one of claims 31 to 36, wherein the read transistor has a gate, a first source / drain, and a second source / drain, and the write transistor has a gate, a first source / drain, and a second source / drain, and the gate of the read transistor is electrically connected to the second source / drain of the write transistor.

[0107] 38. A hybrid 2T0C gain cell according to any one of claims 31 to 37, wherein the gate line of the read transistor is connected via a via to a second source / drain region of the write transistor.

[0108] 39. A hybrid 2T0C gain cell according to any one of claims 31 to 38, wherein a portion of the gate line of the read transistor in the first tier overlaps vertically with a portion of the second source / drain region of the write transistor in the second tier, and the via connects vertically the portion of the gate line of the read transistor to the portion of the second source / drain of the write transistor.

[0109] 40. A hybrid 2T0C gain cell according to any one of claims 31 to 39, wherein the gate of the write transistor is electrically connected to the write word line, the first source / drain of the write transistor is electrically connected to the write bit line, the first source / drain of the read transistor is electrically connected to the read word line, and the second source / drain of the read transistor is electrically connected to the read bit line.

[0110] 41. The hybrid 2T0C gain cell according to any one of items 31 to 40, wherein the hybrid 2T0C gain cell stores data in a storage node which is the gate of the read transistor and the second source / drain of the write transistor.

[0111] 42. A hybrid 2T0C gain cell according to any one of items 31 to 41, wherein the first tier is a first chiplet, the second tier is a second chiplet, and the first chiplet is hybrid-bonded to the second chiplet.

[0112] 43. A hybrid 2T0C gain cell according to any one of claims 31 to 42, wherein the oxide semiconductor channel comprises at least one of indium oxide, indium tin oxide, indium gallium zinc oxide, tin oxide, zinc oxide, Ge-doped indium oxide, or W-doped indium oxide.

[0113] 44. An embedded dynamic random access memory (eDRAM) having a back-end obline (BEOL) structure comprising multiple layers, wherein each layer comprises a first tier and a second tier stacked on the first tier so as to overlap the first tier vertically, and one of the first tier and the second tier has a write transistor having an oxide semiconductor channel, and the other of the first tier and the second tier has a read transistor having a polysilicon channel.

[0114] 45. The eDRAM according to item 44, further comprising a front-end-of-line (FEOL) structure having a logic chip, wherein the logic chip is electrically connected to the write transistor and the read transistor.

[0115] 46. ​​The eDRAM according to any one of claims 44 to 45, wherein the oxide semiconductor channel is perpendicular to the polysilicon channel in a plan view.

[0116] 47. The eDRAM according to any one of claims 44 to 46, wherein the second tier has the read transistor and the first tier has the write transistor.

[0117] 48. The eDRAM according to any one of claims 44 to 47, wherein the first tier has the read transistor and the second tier has the write transistor.

[0118] 49. An embedded dynamic random access memory (eDRAM) comprising a front-end-of-line (FEOL) structure having one or more transistors formed in a substrate, and a back-end-of-line (BEOL) structure disposed on the top surface of the FEOL structure, the BEOL structure having a first tier, a second tier stacked on the first tier so as to overlap the first tier in the vertical direction, and vias connecting the first tier and the second tier, wherein the first tier has a first insulating layer and a read transistor of a 2-transistor-0-capacitor (2T0C) gain cell disposed within the first insulating layer, the read transistor having a first source / drain region and a polysilicon channel region arranged in a first direction eDRAM having a first source / drain region, an oxide semiconductor channel region, and a second source / drain region, and a gate line disposed on the polysilicon channel region and extending in a second direction perpendicular to the first direction, wherein the second tier has a second insulating layer and a write transistor of the 2T0C gain cell disposed within the second insulating layer, the write transistor having a first source / drain region, an oxide semiconductor channel region, and a second source / drain region disposed in the second direction, and a gate line disposed on the oxide semiconductor channel region and extending in the first direction, and the via electrically connects the gate line of the read transistor in the first tier to the second source / drain region of the write transistor in the second tier.

[0119] 50. The eDRAM according to paragraph 49, wherein the first source / drain region of the read transistor in the first tier is electrically connected to a read bit line, the second source / drain region of the read transistor in the first tier is electrically connected to a read word line, the first source / drain region of the write transistor in the second tier is electrically connected to a write bit line, and the gate line of the write transistor in the second tier is electrically connected to a write word line.

[0120] 51. A method for manufacturing embedded dynamic random access memory (eDRAM), comprising: manufacturing a front-end-of-line (FEOL) structure having one or more logic chips; manufacturing a first tier on the FEOL structure; and manufacturing a second tier on the first tier to form the eDRAM.

[0121] 52. The method according to paragraph 51, wherein manufacturing the first tier comprises manufacturing a plurality of first tiers on the top surface of the FEOL structure, each of the plurality of first tiers being spaced apart from one another in a first direction parallel to the top surface of the FEOL structure.

[0122] 53. The method of paragraph 52, wherein manufacturing the second tier comprises manufacturing a plurality of second tiers on a plurality of first tiers.

[0123] 54. A method for manufacturing an embedded dynamic random access memory (eDRAM), comprising: manufacturing a first chiplet including a FEOL structure having one or more logic chips; manufacturing a second chiplet including a first tier and a second tier on the first tier; and hybrid bonding the first chiplet and the second chiplet together to form a heterogeneous 3D eDRAM.

[0124] 55. The method of paragraph 54, wherein manufacturing the second chiplet comprises manufacturing a first plurality of second chiplets, each comprising the first tier and the second tier on the first tier, and the hybrid bonding comprises hybrid bonding each of the first plurality of second chiplets to the first chiplet.

[0125] 56. The method of paragraph 55, wherein manufacturing the second chiplet comprises manufacturing a second plurality of second chiplets, each comprising the first tier and the second tier on the first tier, and the hybrid bonding further comprises hybrid bonding the second plurality of chiplets to the first plurality of second chiplets, respectively.

[0126] 60. A device comprising a 2-transistor 0-capacitor (2T0C) gain cell in a back-end obline structure, the 2T0C gain cell including a write transistor and a read transistor electrically connected to the write transistor, wherein the write transistor includes an oxide semiconductor channel and the read transistor includes a polysilicon channel.

[0127] 61. The device according to item 60, wherein the oxide semiconductor channel is stacked on the polysilicon channel.

[0128] 62. The device according to item 60 or 61, wherein the read transistor is located in a first tier, the write transistor is located in a second tier, and the second tier is stacked on the first tier.

[0129] 63. The device according to any one of items 60 to 62, wherein the write transistor overlaps with the read transistor.

[0130] 64. The read transistor is connected to the write transistor by a via, The 2T0C gain cell is a device according to any one of items 60 to 63, which stores data using the parasitic capacitance of the via.

[0131] 65. The read transistor has a gate, source, and drain, and the write transistor has a gate, source, and drain. The device according to any one of claims 60 to 64, wherein the gate of the read transistor is electrically connected to the drain of the write transistor.

[0132] 66. The device according to any one of claims 60 to 65, wherein the gate line of the read transistor is connected via a via to the drain region of the write transistor.

[0133] 67. The device according to any one of claims 60 to 66, wherein a portion of the gate line of the read transistor overlaps with a portion of the drain region of the write transistor, and vias connect the portion of the gate line of the read transistor to the portion of the drain region of the write transistor.

[0134] 68. The device according to any one of claims 60 to 67, wherein the read transistor has a gate, a source, and a drain, and the write transistor has a gate, a source, and a drain, the gate of the read transistor being electrically connected to the drain of the write transistor, the gate of the write transistor being electrically connected to a write word line, the source of the write transistor being electrically connected to a write bit line, the source of the read transistor being electrically connected to a read word line, and the drain of the read transistor being electrically connected to a read bit line.

[0135] 69. The device according to any one of claims 60 to 68, wherein the gate of the read transistor is electrically connected to the drain of the write transistor, and the 2T0C gain cell stores data using the parasitic capacitance of the gate of the read transistor.

[0136] 70. The device according to any one of claims 60 to 69, wherein the read transistor is contained in a first chiplet, the write transistor is contained in a second chiplet, and the first chiplet is hybrid-bonded to the second chiplet.

[0137] 71. The device according to any one of claims 60 to 70, wherein the oxide semiconductor channel comprises at least one of indium oxide, indium tin oxide, indium gallium zinc oxide, tin oxide, zinc oxide, Ge-doped indium oxide, or W-doped indium oxide.

[0138] 72. A system comprising a front-end-of-line (FEOL) structure having a logic chip, and a back-end-of-line (BEOL) structure on the FEOL structure, the BEOL structure including a layer, wherein the layer has a 2-transistor 0-capacitor (2T0C) gain cell including a read transistor and a write transistor electrically connected to the read transistor, the write transistor including an oxide semiconductor channel, and the read transistor including a polysilicon channel.

[0139] 73. The system according to paragraph 72, wherein the logic chip is electrically connected to the write transistor and the read transistor.

[0140] 74. The system according to item 72 or 73, wherein the oxide semiconductor channel is stacked on the polysilicon channel.

[0141] 75. The system according to any one of claims 72 to 74, wherein the read transistor is located in a first tier, the write transistor is located in a second tier, and the second tier is stacked on the first tier.

[0142] 76. The system according to any one of items 72 to 75, wherein the read transistor is connected to the write transistor by vias, and the 2T0C gain cell stores data using the parasitic capacitance of the vias.

[0143] 77. A method comprising: manufacturing a first structure using a front-end-of-line (FEOL) process, the first structure including a logic chip; manufacturing a first tier using a back-end-of-line (BEOL) process, the first tier having a read transistor for a 2-transistor-0-capacitor (2T0C) gain cell; and manufacturing a second tier on the first tier using the BEOL process, the second tier having a write transistor for the 2T0C gain cell.

[0144] 78. The method according to paragraph 77, wherein the first tier is manufactured on the first structure.

[0145] 79. The method according to paragraph 77, wherein the first tier is joined to the first structure by hybrid bonding.

[0146] It should be understood that the embodiments are not limited to the various embodiments described above, and various other modifications and changes may be made within them without departing from the spirit and scope set forth in the appended claims.

Claims

1. A two-transistor zero-capacitor gain cell in a backend obline structure, comprising a write transistor and a read transistor electrically connected to the write transistor, It has, The write transistor includes an oxide semiconductor channel, and the read transistor includes a polysilicon channel. device.

2. The device according to claim 1, wherein the oxide semiconductor channel is stacked on the polysilicon channel.

3. The device according to claim 1, wherein the read transistor is located in a first tier, the write transistor is located in a second tier, and the second tier is stacked on the first tier.

4. The device according to claim 1, wherein the write transistor overlaps with the read transistor.

5. The read transistor is connected to the write transistor by vias. The aforementioned two-transistor, zero-capacitor gain cell stores data using the parasitic capacitance of the vias. The device according to claim 1.

6. The read transistor has a gate, source, and drain, and the write transistor has a gate, source, and drain. The gate of the read transistor is electrically connected to the drain of the write transistor. The device according to claim 1.

7. The device according to claim 1, wherein the gate line of the read transistor is connected to the drain region of the write transistor via a via.

8. The device according to claim 1, wherein a portion of the gate line of the read transistor overlaps with a portion of the drain region of the write transistor, and a via connects the portion of the gate line of the read transistor to the portion of the drain region of the write transistor.

9. The read transistor has a gate, source, and drain, and the write transistor has a gate, source, and drain. The gate of the read transistor is electrically connected to the drain of the write transistor. The gate of the write transistor is electrically connected to the write word line, the source of the write transistor is electrically connected to the write bit line, the source of the read transistor is electrically connected to the read word line, and the drain of the read transistor is electrically connected to the read bit line. The device according to claim 1.

10. The gate of the read transistor is electrically connected to the drain of the write transistor. The aforementioned two-transistor zero-capacitor gain cell stores data using the parasitic capacitance of the gate of the read transistor. The device according to claim 1.

11. The device according to claim 1, wherein the read transistor is included in a first chiplet, the write transistor is included in a second chiplet, and the first chiplet is hybrid-bonded to the second chiplet.

12. The device according to claim 1, wherein the oxide semiconductor channel comprises at least one of indium oxide, indium tin oxide, indium gallium zinc oxide, tin oxide, zinc oxide, Ge-doped indium oxide, or W-doped indium oxide.

13. A front-end obline structure with a logic chip, The aforementioned front-end obline structure is a back-end obline structure, and the back-end obline structure includes a layer, It has, The layer has a two-transistor zero-capacitor gain cell including a read transistor and a write transistor electrically connected to the read transistor. The write transistor includes an oxide semiconductor channel, and the read transistor includes a polysilicon channel. system.

14. The system according to claim 13, wherein the logic chip is electrically connected to the write transistor and the read transistor.

15. The system according to claim 13, wherein the oxide semiconductor channel is stacked on the polysilicon channel.

16. The system according to claim 13, wherein the read transistor is located in a first tier, the write transistor is located in a second tier, and the second tier is stacked on the first tier.

17. The read transistor is connected to the write transistor by vias. The aforementioned two-transistor, zero-capacitor gain cell stores data using the parasitic capacitance of the vias. The system according to claim 13.

18. A first structure is manufactured using a front-end-of-line process, and the first structure includes a logic chip. The first tier is manufactured using a back-end obline process, and the first tier has a readout transistor for a 2-transistor 0-capacitor gain cell. A second tier is manufactured on the first tier using the backend obline process, and the second tier has a writing transistor for the two transistors and zero capacitor gain cell. A method having the following characteristics.

19. The method according to claim 18, wherein the first tier is manufactured on the first structure.

20. The method according to claim 18, wherein the first tier is joined to the first structure by hybrid bonding.

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