Integrated circuits and monitoring systems

Abstract

Even integrated circuits that include data caches can be easily verified for software execution. [Solution] The integrated circuit 1 comprises a processor 10, a memory 12 that holds data defined in software 18 executed by the processor 10, a data cache 11 positioned between the processor 10 and the memory 12, and a recording circuit 13. The data cache 11 temporarily holds write data output from the processor 10 to be written to the memory 12. The recording circuit 13 is connected to a bus 20 between the processor 10 and the data cache 11 and records the write data.

Description

Technical Field

[0001] The present disclosure relates to an integrated circuit and a monitoring system, and can be suitably used for, for example, an integrated circuit including a data cache and a system for monitoring data held in the integrated circuit.

Background Art

[0002] Conventionally, in an integrated circuit including a processor and a memory, the execution operation of software by the processor is verified. The processor updates the values of a plurality of variables by executing software. Data indicating the values of the plurality of variables is held in the memory. Therefore, the user verifies the execution operation of the software by monitoring the data held in the memory while the processor is executing the software.

[0003] Although the conventional technology regarding the present disclosure has been described based on the general technical information known to the applicant, within the scope of the applicant's memory, the applicant does not have information that should be disclosed as prior art document information before the filing date.

Summary of the Invention

Problems to be Solved by the Invention

[0004] In an integrated circuit, a data cache may be arranged between a processor and a memory. The data cache temporarily holds write data output from the processor and written to the memory. That is, the write data is temporarily held only in the data cache and not in the memory. Therefore, even if the user monitors the data held in the memory, the execution operation of the software cannot be accurately verified.

[0005] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0006] An integrated circuit according to one embodiment comprises a processor, a first memory that holds data defined in software executed by the processor, and a data cache located between the processor and the first memory. The data cache temporarily holds write data output from the processor to be written to the first memory. The integrated circuit further comprises a recording circuit. The recording circuit is connected to a bus between the processor and the data cache and records the write data.

[0007] Another embodiment of the monitoring system comprises an integrated circuit and a monitoring device. The integrated circuit includes a first processor, a first memory that holds data defined in software executed by the first processor, and a data cache located between the first processor and the first memory. The data cache temporarily holds write data output from the first processor to be written to the first memory. The integrated circuit further includes a recording circuit. The recording circuit is connected to a bus between the first processor and the data cache and records the write data. The monitoring device includes a data reader and a user interface. The data reader accesses the recording circuit and reads the write data. The user interface visualizes the changes in the values ​​of one or more variables indicated by the write data. [Effects of the Invention]

[0008] According to one or another embodiment described above, even with an integrated circuit including a data cache, the user can more accurately verify the execution behavior of the software. [Brief explanation of the drawing]

[0009] [Figure 1] This figure shows an example of the overall configuration of the monitoring system according to the embodiment. [Figure 2] This is a diagram showing the configuration of a monitoring system related to a reference configuration. [Figure 3] This diagram illustrates data monitoring using a monitoring device. [Figure 4] This flowchart shows an example of the control process flow of an integrated circuit related to the reference form. [Figure 5] This is a block diagram illustrating the internal configuration of the monitoring system according to this embodiment. [Figure 6] This figure shows the configuration of Example 1 of the monitoring system according to this embodiment. [Figure 7] This diagram shows the data storage status in Example 1. [Figure 8] This is a diagram showing an example of the first table. [Figure 9] This figure shows the configuration of Example 2 of the monitoring system according to this embodiment. [Figure 10] This figure shows the data storage status in Example 2. [Figure 11] This figure shows an example of the second table. [Figure 12] This diagram illustrates the effect of reducing the amount of communication between the monitoring device and the monitor RAM. [Figure 13] This figure shows the configuration of Example 3 of the monitoring system according to this embodiment. [Modes for carrying out the invention]

[0010] Embodiments of this disclosure will be described in detail below with reference to the drawings. The same or corresponding parts will be denoted by the same reference numerals, and their descriptions will not be repeated.

[0011] <Overall configuration of the monitoring system> Figure 1 is a diagram showing an example of the overall configuration of a monitoring system according to an embodiment. As shown in Figure 1, the monitoring system 100 comprises an integrated circuit 1 and a monitoring device 3.

[0012] The integrated circuit 1 is a semiconductor integrated circuit including a processor and a memory. The integrated circuit 1 includes, for example, a SoC (System-on-a-chip) or a MCU (Micro Controller Unit). The integrated circuit 1 is mounted on a substrate 4, for example. The substrate 4 is incorporated into a device to which the control function realized by the integrated circuit 1 is applied. The device may include, for example, an electronic device, a production device, and a vehicle. The processor of the integrated circuit 1 executes software for realizing a control function.

[0013] The monitoring device 3 assists in verifying the execution operation of software in the integrated circuit 1. The user uses the monitoring device 3 to verify the execution operation of software in the integrated circuit 1. When it is confirmed that there is no problem in the execution operation of the software in the integrated circuit 1, the monitoring device 3 is removed from the integrated circuit 1.

[0014] The monitoring device 3 monitors data held in the integrated circuit 1 in order to assist in verifying the execution operation of software in the integrated circuit 1. The monitoring device 3 includes a debug interface 30 connected to the integrated circuit 1, a data reader 31 that reads data held in the integrated circuit 1, and an information processing device 32.

[0015] The information processing device 32 is a computer having a general-purpose architecture. The information processing device 32 includes, for example, a personal computer, a tablet, and a smartphone. The information processing device 32 visualizes the information indicated by the data read by the data reader 31. For example, the information processing device 32 visualizes the transition of the value of a variable defined in the software incorporated in the integrated circuit 1. Specifically, the information processing device 32 displays a graph representing the transition of the value of the variable or numerical values in a time series. The user verifies the execution operation of the software in the integrated circuit 1 by checking the transition of the value of the variable.

[0016] <Problems of the reference form> Before giving a detailed description of the monitoring system 100 according to the present embodiment, problems of the monitoring system according to the reference embodiment will be described with reference to FIGS. 2 to 4.

[0017] FIG. 2 is a diagram showing the configuration of the monitoring system according to the reference embodiment. The monitoring system 100Z according to the reference embodiment includes an integrated circuit 1Z and a monitoring device 3Z instead of the integrated circuit 1 and the monitoring device 3.

[0018] The integrated circuit 1Z includes a processor 10, a memory 12, and a data cache 11.

[0019] The processor 10 includes, for example, a CPU (Central Processing Unit) or a DSP (Digital Signal Processor). The processor 10 executes software 18 created to realize a desired function.

[0020] The processor 10 executes the software 18 to update data at a predetermined control period. The data is used when the processor 10 executes the software 18. Alternatively, the data is generated by the processor 10 executing the software 18. The data indicates the values of a plurality of variables defined in the software 18.

[0021] The memory 12 includes, for example, a RAM (Random Access Memory). The memory 12 holds data defined in the software 18. In the memory 12, a data piece representing the value of each variable is written to an address corresponding to the variable.

[0022] The data cache 11 is located between the processor 10 and the memory 12. The data cache 11 is connected to the processor 10 via the bus 20. The data cache 11 temporarily holds data fragments read from the memory 12 and data fragments written to the memory 12. Furthermore, the data cache 11 holds the corresponding address in the memory 12 for each data fragment.

[0023] The data cache 11 temporarily holds the write data output from the processor 10 to be written to memory 12. The data cache 11 also holds the corresponding address in memory 12 for each of the one or more data fragments contained in the write data.

[0024] The data cache 11 writes a portion of the data it holds to memory 12 according to predetermined rules. For example, when the amount of data held by the data cache 11 reaches a predetermined value, it writes data fragments that are read less frequently from the data it holds to memory 12. Alternatively, the data cache 11 writes some or all of the data it holds to memory 12 at predetermined timings. Therefore, the period from when the write data is output from the processor 10 until the write data is written to memory 12 can be sufficiently longer than the control cycle.

[0025] The data cache 11 receives a read instruction for a data fragment from the processor 10. The read instruction specifies the address corresponding to the data fragment to be read. If the data cache 11 holds the data fragment corresponding to the specified address, it directly responds to the read instruction by passing the data fragment to the processor 10. If the data cache 11 does not hold the data fragment at the specified address, it indirectly responds to the read instruction by reading the data fragment from memory 12 and passing the data fragment to the processor 10.

[0026] Figure 3 illustrates data monitoring by a monitoring device. The monitoring device 3Z monitors the data held in memory 12. As shown in Figure 3, the monitoring device 3Z periodically acquires data from memory 12 of the integrated circuit 1Z. For example, the monitoring device 3Z acquires data from memory 12 in accordance with the period in which the data to be acquired is updated. The period in which the data to be acquired is updated may be the same as the control period, or it may be an integer multiple of 2 or more of the control period. Specifically, the monitoring device 3Z reads data fragments (hereinafter referred to as "target data fragments") stored at addresses corresponding to the variables to be monitored (hereinafter referred to as "target variables") from memory 12.

[0027] However, as described above, the period from when the write data is output from the processor 10 until it is written to the memory 12 can be considerably longer than the control cycle. In other words, there is a period during which the write data output from the processor 10 is held only in the data cache 11 and not in the memory 12. During this period, the monitoring device 3Z cannot read the write data. In other words, the monitoring device 3Z reads the old data from the memory 12, not the data updated in the current control cycle. Therefore, when using the monitoring system 100Z according to the reference configuration, the user cannot accurately verify the execution operation of the software 18 by the processor 10.

[0028] In the monitoring system 100Z according to the reference configuration, it is conceivable that the data held in the data cache 11 and the data held in the memory 12 be matched in order to monitor updated data. A known method for matching the data held in the data cache 11 and the data held in the memory 12 is write-back processing. Write-back processing is the process of writing the data held in the data cache 11 to the memory 12. By executing write-back processing immediately before the timing when the monitoring device 3Z acquires data from the memory 12, the monitoring device 3Z can acquire a target data fragment that shows the latest value of the target variable.

[0029] Figure 4 is a flowchart showing an example of the control process flow of an integrated circuit related to a reference configuration. Figure 4 shows the control process flow including write-back processing.

[0030] As shown in Figure 4, the processor 10 determines whether the control cycle has elapsed (step S1). If the control cycle has not elapsed (NO in step S1), the process returns to step S1. If the control cycle has elapsed (YES in step S1), the processor 10 performs calculations according to the software 18 (step S2). This calculates the values ​​of various variables. Next, the processor 10 outputs a control command according to the calculation result (step S3). Next, the processor 10 outputs an instruction to execute write-back processing to the data cache 11 (step S4). This causes the data cache 11 to write the data it holds to the memory 12. After step S4, the process returns to step S1.

[0031] Step S4 ensures that the data held in the data cache 11 matches the data held in the memory 12. Step S4 is performed at each control cycle. Therefore, data consistency between the data cache 11 and the memory 12 is guaranteed at each control cycle. As a result, the monitoring device 3Z can obtain a target data fragment from the memory 12 that shows the latest value of the target variable.

[0032] However, the processor 10 needs to wait from the time it outputs the instruction to perform the write-back process until the write-back process is completed. As a result, the processing performance of the processor 10 decreases.

[0033] Furthermore, the user needs to incorporate debug code into the software 18 to perform the write-back process. In other words, the user's workload increases.

[0034] Furthermore, the write-back process is necessary solely for verifying the execution of software 18 in the integrated circuit 1Z. Therefore, the final product of integrated circuit 1Z, distributed after verification of software 18's execution, typically does not include debug code for performing the write-back process. As a result, the performance of integrated circuit 1Z evaluated during verification does not match the performance of the integrated circuit 1Z distributed after verification. In other words, users cannot evaluate performance equivalent to that of the final product actually distributed during verification.

[0035] Alternatively, in the monitoring system 100Z according to the reference configuration, a cache-through mode may be applied to the integrated circuit 1Z in order to monitor updated data. The cache-through mode is a mode in which write data is always written to the data cache 11 and memory 12. As a result, the monitoring device 3Z can obtain a data fragment showing the latest value of the target variable by accessing memory 12.

[0036] However, when the cache-through mode is applied to the integrated circuit 1Z, the number of accesses to memory 12 increases. As a result, the processing performance of processor 10 decreases.

[0037] Alternatively, in the monitoring system 100Z according to the reference configuration, the monitoring device 3Z may be designed to access not only the memory 12 but also the data cache 11 in order to monitor the updated data.

[0038] For example, monitoring device 3Z performs the following series of processes. First, monitoring device 3Z refers to the address held in data cache 11. If the address held in data cache 11 matches the address corresponding to the target variable, monitoring device 3Z reads a data fragment indicating the value of the target variable from data cache 11. If the address held in data cache 11 does not match the address corresponding to the target variable, monitoring device 3Z reads a data fragment indicating the value of the target variable from memory 12.

[0039] However, the timing of the monitoring device 3Z's access to the data cache 11 cannot be synchronized with the control cycle. Therefore, while the above series of processes are being executed, the target data fragment indicating the value of the target variable may be updated. Consequently, the monitoring device 3Z may not be able to obtain the latest target data fragment.

[0040] The monitoring system 100 according to this embodiment can solve the above-mentioned problems in the monitoring system 100Z according to the reference embodiment.

[0041] <Internal configuration of the monitoring system according to this embodiment> Figure 5 is a block diagram showing an overview of the internal configuration of the monitoring system according to this embodiment.

[0042] As shown in Figure 5, integrated circuit 1 comprises a processor 10, a memory 12, a data cache 11, and a recording circuit 13. In other words, integrated circuit 1 differs from integrated circuit 1Z shown in Figure 2 in that it includes a recording circuit 13. For this reason, a detailed explanation of the processor 10, data cache 11, and memory 12 is omitted. Note that the processor 10 is an example of the "first processor" described in this disclosure. The memory 12 is an example of the "first memory" described in this disclosure.

[0043] The recording circuit 13 is connected to the bus 20 between the processor 10 and the data cache 11. The recording circuit 13 records the write data output from the processor 10 to be written to the memory 12. The write data is generated when the processor 10 executes the software 18.

[0044] According to the integrated circuit 1 of this embodiment, the write data output from the processor 10 is recorded in the recording circuit 13. Therefore, the user can check the latest data by monitoring the data recorded in the recording circuit 13. As a result, the user can more accurately verify the execution operation of the software 18 by the processor 10.

[0045] Furthermore, with the integrated circuit 1 according to this embodiment, there is no need to apply write-back processing. Therefore, compared to the reference embodiment in which write-back processing is applied to the integrated circuit 1Z, the work of incorporating debug code is omitted.

[0046] Furthermore, when the processor 10 outputs the write data to the bus 20, the write data is automatically recorded in the recording circuit 13. Therefore, compared to a reference configuration in which write-back processing or cache-through mode is applied to the integrated circuit 1Z, the performance degradation of the processor 10 is suppressed.

[0047] The monitoring device 3 includes a debug interface 30, a data reader 31, a processor 33, a user interface 34, and storage 35. The processor 33, user interface 34, and storage 35 are built into the information processing device 32 shown in Figure 1.

[0048] The debug interface 30 is connected to the recording circuit 13. The data reader 31 accesses the recording circuit 13 and reads the write data recorded in the recording circuit 13.

[0049] The processor 33 executes the monitoring program 38. Specifically, the processor 33 performs data acquisition processing from the integrated circuit 1 and data visualization processing. Furthermore, the processor 33 may set the operating conditions for the recording circuit 13. Note that the processor 33 is an example of the "second processor" described in this disclosure.

[0050] The user interface 34 provides information to the user. Specifically, the user interface 34 visualizes the changes in the values ​​of one or more target variables indicated by the light data. Furthermore, the user interface 34 accepts input from the user. The user interface 34 includes, for example, a display, keyboard, mouse, and touch panel.

[0051] According to the monitoring system 100 of this embodiment, the user can check the changes in the values ​​of variables visualized by the user interface 34. As a result, the user can more accurately verify the execution operation of the software 18 by the processor 10.

[0052] <Example 1> Figure 6 shows the configuration of Example 1 of the monitoring system according to this embodiment. As shown in Figure 6, the monitoring system 100A according to Example 1 comprises an integrated circuit 1A and a monitoring device 3A.

[0053] Integrated circuit 1A is an embodiment of integrated circuit 1 shown in Figure 5. Integrated circuit 1A comprises a CPU 10A, a data cache 11, a RAM 12A, and a recording circuit 13A. CPU 10A is an example of a processor 10 shown in Figure 5. RAM 12A is an example of a memory 12 shown in Figure 5. Recording circuit 13A is an example of a recording circuit 13 shown in Figure 5.

[0054] The CPU 10A and the data cache 11 are connected to each other via the address bus 20a and the data bus 20b. The CPU 10A outputs a signal to the data bus 20b indicating the write data to be written to the RAM 12A. Furthermore, for one or more data fragments that make up the write data, the CPU 10A outputs a signal to the address bus 20a indicating the corresponding address on the RAM 12A.

[0055] The recording circuit 13A includes a buffer 14, a writing circuit 15A, and a monitor RAM 16A.

[0056] Buffer 14 is connected to the address bus 20a and the data bus 20b. Buffer 14 temporarily stores write data transmitted on the data bus 20b. Specifically, buffer 14 stores a dataset 141 for each of the one or more data fragments contained in the write data. The dataset 141 includes the data fragment and the corresponding address on RAM 12A.

[0057] The write circuit 15A writes the write data stored in the buffer 14 to the monitor RAM 16A. The write circuit 15A includes an address bus 150a, a data bus 150b, a memory circuit 151A, and a comparator circuit 152A.

[0058] One end of each of the address bus 150a and data bus 150b is connected to buffer 14. Signals indicating each data set 141 stored in buffer 14 are sequentially output to address bus 150a and data bus 150b. That is, signals indicating data fragments contained in data set 141 are output to data bus 150b. Signals indicating addresses contained in data set 141 are output to address bus 150a. The other end of data bus 150b is connected to monitor RAM 16A.

[0059] The memory circuit 151A stores one or more monitor target addresses 50 corresponding to one or more target variables. The monitor target address 50 is the address of the area in RAM 12A where the corresponding target variable is stored. The monitor target address 50 corresponds to the "first address" described in this disclosure. One or more monitor target addresses 50 are set by the monitoring device 3A.

[0060] The comparator circuit 152A is connected to the address bus 150a and the memory circuit 151A. The comparator circuit 152A includes a comparator 153A and a gate switch 154A.

[0061] One or more monitor target addresses 50 stored in the memory circuit 151A are sequentially input to the first input terminal of comparator 153A. The second input terminal of comparator 153A is connected to the address bus 150a. As a result, comparator 153A sequentially compares the address received from address bus 150a with one or more monitor target addresses 50 stored in memory circuit 151A. If the address received from address bus 150a matches any of the one or more monitor target addresses 50, comparator 153A outputs an ON signal indicating a match. If the address received from address bus 150a does not match any of the one or more monitor target addresses 50, comparator 153A outputs an OFF signal indicating a mismatch.

[0062] The input terminal of gate switch 154A is connected to address bus 150a. The output terminal of gate switch 154A is connected to monitor RAM 16A. When gate switch 154A receives an ON signal from comparator 153A, it outputs the signal input to its input terminal from its output terminal. When gate switch 154A receives an OFF signal from comparator 153A, it does not output the signal input to its input terminal from its output terminal.

[0063] As a result, if the address received from the address bus 150a matches one or more of the monitored addresses 50, the comparison circuit 152A outputs the address received from the address bus 150a to the monitor RAM 16A. If the address received from the address bus 150a does not match one or more of the monitored addresses 50, the comparison circuit 152A does not output the address received from the address bus 150a to the monitor RAM 16A.

[0064] The other end of the data bus 150b is connected to the monitor RAM 16A. In the monitor RAM 16A, only data fragments transferred along with an address are written to the area corresponding to that address. Only addresses that match the monitored address 50 are output to the monitor RAM 16A. Therefore, the write circuit 15A writes one or more target data fragments from the write data accumulated in the buffer 14 to the monitor RAM 16A. As described above, the one or more target data fragments are one or more data fragments that are written to one or more monitored addresses 50 in RAM 12A, respectively.

[0065] Figure 7 shows the data storage configuration in Example 1. Monitor RAM 16A has the same capacity as RAM 12A or a larger capacity than RAM 12A. Therefore, all addresses in Monitor RAM 16A include all addresses in RAM 12A. In the example shown in Figure 7, Monitor RAM 16A has the same capacity as RAM 12A.

[0066] Figure 7 shows an example where "Variable A" to "Variable D" are selected as target variables. As shown in Figure 7, in RAM 12A, the target data fragments representing the values ​​of "Variable A" to "Variable D" are stored at the corresponding monitor target addresses 50a to 50b, respectively. The write circuit 15A according to Embodiment 1 writes one or more target data fragments to the same address as one or more monitor target addresses 50 in monitor RAM 16A. Therefore, in monitor RAM 16A as well, the target data fragments representing the values ​​of "Variable A" to "Variable D" are stored at the same addresses as in RAM 12A (i.e., monitor target addresses 50a to 50d).

[0067] Furthermore, since a data cache 11 is located between RAM 12A and CPU 10A, the written data is temporarily held in the data cache 11. The retention time of the written data in the data cache 11 is significantly longer than the storage time of the written data in the buffer 14. The storage time of the written data in the buffer 14 is usually shorter than the control cycle. Therefore, if the written data in a certain control cycle includes a data fragment of "variable A" corresponding to the monitored address 50a, the following situation may occur after that control cycle: That is, the data fragment stored at the monitored address 50a in monitor RAM 16A may show the updated value, while the data fragment stored at the monitored address 50a in RAM 12A may show the value before the update.

[0068] The monitoring device 3A shown in Figure 6 is an embodiment of the monitoring device 3 shown in Figure 5. The monitoring device 3A includes a debug interface 30, a data reader 31, a processor 33, a user interface 34, and a first table 36. The first table 36 is stored in the storage 35 shown in Figure 5.

[0069] Figure 8 shows an example of the first table. As shown in Figure 8, the first table 36 associates the variable name, data type, and address in RAM 12A for each of the multiple variables defined in the software 18. The first table 36 is created by the tool used to develop the software 18 after the software 18 has been compiled or built.

[0070] The user interface 34 accepts the specification of one or more target variables from among several variables defined in the software 18. For example, the user interface 34 displays a list of several variables included in the first table 36. The user interface 34 prompts the user to specify a target variable from the list.

[0071] The processor 33 refers to the first table 36 and identifies one or more addresses in the RAM 12A where data fragments representing one or more target variables are written, as one or more monitor target addresses 50. The processor 33 sets one or more monitor target addresses 50 in the memory circuit 151A.

[0072] In the monitoring system 100A according to Embodiment 1, the debug interface 30 is connected to the monitor RAM 16A, not the RAM 12A. Therefore, the data reader 31 reads data from the monitor RAM 16A. As described above, write data is written to the monitor RAM 16A immediately. Therefore, the data reader 31 can obtain data fragments showing the latest values ​​for each target variable from the monitor RAM 16A.

[0073] The user interface 34 visualizes the changes in the values ​​of each target variable based on the data fragments acquired by the data reader 31. This allows the user to more accurately verify the execution of the software 18 by the CPU 10A based on the changes in the values ​​of each target variable.

[0074] Next, a comparison of the processing performance of the processor 10 in the monitoring system 100Z according to the reference embodiment and the processing performance of the CPU 10A in the monitoring system 100A according to Example 1 will be explained. The processing performance of the processor 10 or CPU 10A is evaluated by the average access ratio to the memory 12 or RAM 12A during the control cycle.

[0075] The average access ratio is calculated based on the following conditions (a) to (d). (a) In the monitoring system 100Z of the reference form, a write-back process is performed for each control cycle. The time required for the write-back process is 200 ns per 4 bytes. (b) The access time to the data cache is 25 ns per 4 bytes. (c) The amount of data to be accessed is 256 bytes. (d) The control period for executing software 18 is 1 msec.

[0076] In the monitoring system 100Z of the reference configuration, the time it takes for the processor 10 to access data (average access time) is calculated to be 206.4 μs based on the following formula (1). Average access time = {(Amount of data to access) ÷ 4} × (Time to access data cache) + (Time required for write-back processing) =(256÷4)×25+(256÷4)×200 =206400ns ···Equation (1). Therefore, the average access rate to memory 12 during the control cycle is 20.6%.

[0077] In the monitoring system 100A according to Example 1, the time it takes for the CPU 10A to access data (average access time) is calculated to be 1.6 μs based on the following equation (2). Average access time = {(Amount of data to access) ÷ 4} × (Time to access data cache) = (256 ÷ 4) × 25 =1600ns...Equation (2). Therefore, the average access rate to RAM12A during the control cycle is 0.16%.

[0078] Thus, the processing performance of the CPU 10A according to Example 1 is improved by approximately 20% compared to the processing performance of the processor 10 according to the reference embodiment.

[0079] <Example 2> Figure 9 shows the configuration of Example 2 of the monitoring system according to this embodiment. As shown in Figure 9, the monitoring system 100B according to Example 2 comprises an integrated circuit 1B and a monitoring device 3B.

[0080] Integrated circuit 1B is an embodiment of integrated circuit 1 shown in Figure 5. Integrated circuit 1B differs from integrated circuit 1A shown in Figure 6 in that it includes a recording circuit 13B instead of a recording circuit 13A. Recording circuit 13B is an example of the recording circuit 13 shown in Figure 5.

[0081] The recording circuit 13B differs from the recording circuit 13A in that it includes the writing circuit 15B and monitor RAM 16B instead of the writing circuit 15A and monitor RAM 16A. The writing circuit 15B differs from the writing circuit 15A in that it includes the storage circuit 151B and comparator circuit 152B instead of the storage circuit 151A and comparator circuit 152A.

[0082] The memory circuit 151B stores an address set 60 for each of the one or more target variables. The address set 60 includes the monitored address 50 in RAM 12A and the converted address 52 in monitor RAM 16B. In other words, the memory circuit 151B stores one or more monitored addresses 50, similar to the memory circuit 151A. Furthermore, the memory circuit 151B stores one or more converted addresses 52 in monitor RAM 16B, associated with each of the one or more monitored addresses 50. One or more converted addresses 52 are set by the monitoring device 3B.

[0083] The comparison circuit 152B sequentially reads one or more address sets 60 stored in the memory circuit 151B. The comparison circuit 152B includes a comparator 153B and a gate switch 154B.

[0084] The first input terminal of comparator 153B receives the monitored address 50 included in the address set 60. The second input terminal of comparator 153B is connected to the address bus 150a. As a result, comparator 153B sequentially compares the address received from address bus 150a with one or more monitored addresses 50 stored in memory circuit 151B. If the address received from address bus 150a matches a monitored address 50, comparator 153B outputs an ON signal indicating a match. If the address received from address bus 150a does not match a monitored address 50, comparator 153B outputs an OFF signal indicating a mismatch.

[0085] The converted address 52, included in the address set 60, is input to the input terminal of gate switch 154B. The output terminal of gate switch 154B is connected to monitor RAM 16B. When gate switch 154B receives an ON signal from comparator 153B, it outputs the signal input to its input terminal from its output terminal. When gate switch 154B receives an OFF signal from comparator 153B, it does not output the signal input to its input terminal from its output terminal.

[0086] As a result, the comparison circuit 152B outputs a converted address 52 corresponding to a certain monitor target address 50 to the monitor RAM 16B, depending on whether the address received from the address bus 150a matches that monitor target address 50. The comparison circuit 152B does not output an address to the monitor RAM 16A if the address received from the address bus 150a does not match any of the one or more monitor target addresses 50.

[0087] The other end of the data bus 150b is connected to the monitor RAM 16B. In the monitor RAM 16B, only the data fragments transferred along with the address are written to the area corresponding to that address. The monitor RAM 16B outputs a converted address 52 corresponding to the monitored address 50. The monitored address 50 indicates the area in RAM 12A where the target data fragments indicating the value of the target variable are stored. Therefore, the write circuit 15B writes one or more target data fragments from the write data accumulated in the buffer 14 to the monitor RAM 16B. At this time, one or more target data fragments are written to one or more converted addresses 52 in the monitor RAM 16B.

[0088] One or more converted addresses 52 are set so that one or more target data fragments are recorded consecutively from the starting address of the monitor RAM 16B.

[0089] Figure 10 shows the data storage status in Example 2. Figure 10 shows an example when "Variable A" to "Variable D" are selected as target variables. As shown in Figure 10, in RAM 12A, the four target data fragments representing the values ​​of "Variable A" to "Variable D" are stored at the corresponding monitor target addresses 50a to 50d, respectively. In contrast, the write circuit 15B according to Example 2 writes the four target data fragments representing the values ​​of "Variable A" to "Variable D" to the converted addresses 52a to 52d in monitor RAM 16B. Converted addresses 52a to 52d are set so that the four target data fragments are recorded consecutively from the starting address of monitor RAM 16B. Therefore, the write circuit 15B writes the four target data fragments representing the values ​​of "Variable A" to "Variable D" consecutively from the starting address of monitor RAM 16B.

[0090] Thus, in monitor RAM 16B, the memory area used is limited to the total capacity of one or more target data fragments from the starting address. Therefore, the capacity of monitor RAM 16B is less than that of RAM 12A.

[0091] The monitoring device 3B shown in Figure 9 is an embodiment of the monitoring device 3 shown in Figure 5. The monitoring device 3B differs from the monitoring device 3A shown in Figure 6 in that it further includes a second table 37. The second table 37 is stored in the storage 35 shown in Figure 5.

[0092] In Embodiment 2, the user interface 34 accepts the designation of one or more target variables from among the multiple variables defined in the software 18. The processor 33 then refers to the first table 36 to identify one or more monitor target addresses in the RAM 12A where data fragments representing one or more target variables are written. The processor 33 sets one or more monitor target addresses in the memory circuit 151B.

[0093] Furthermore, the processor 33 determines a converted address 52 for each of the one or more target variables. The converted address 52 defines an area in the monitor RAM 16B where a target data fragment indicating the value of the corresponding target variable is written. The processor 33 determines one or more converted addresses 52 such that one or more target data fragments corresponding to one or more target variables are recorded consecutively from the beginning address of the monitor RAM 16B. The processor 33 creates a second table 37 containing the determined converted addresses 52.

[0094] Figure 11 shows an example of the second table. As shown in Figure 11, the second table 37 associates the variable name, data type, and converted address for each of the one or more target variables.

[0095] In the monitoring system 100B according to Embodiment 2, the debug interface 30 is connected to the monitor RAM 16B, not the RAM 12A. Therefore, the data reader 31 reads data from the monitor RAM 16B. As in Embodiment 1, write data is written to the monitor RAM 16B immediately. Therefore, the data reader 31 can obtain the latest data fragment for each target variable from the monitor RAM 16B. In Embodiment 2, as described above, one or more data fragments are written consecutively from the starting address of the monitor RAM 16B. Therefore, if one or more data fragments contain multiple data fragments, the data reader 31 reads multiple data fragments from the monitor RAM 16B all at once. In other words, the data reader 31 reads a set of multiple data fragments (hereinafter referred to as a "data fragment set"). This reduces the amount of communication between the monitoring device 3B and the monitor RAM 16B.

[0096] Figure 12 illustrates the effect of reducing the amount of communication between the monitoring device and the monitor RAM. Figure 12 shows an example where four target variables are set.

[0097] In Example 1, as shown in Figure 7, four target data fragments representing the values ​​of the four target variables are written to four discontinuous areas of the monitor RAM 16A. Therefore, the data reader 31 outputs a signal to the monitor RAM 16A for each of the four target variables, specifying the address where the corresponding target data fragment is stored (the same address as the monitor target address 50). Then, a signal indicating the target data fragment stored at the specified address is transmitted from the monitor RAM 16A to the data reader 31. When the address is represented by 8 bytes and the data fragment is represented by 4 bytes, the amount of communication between the data reader 31 and the monitor RAM 16A is (8 + 4) × 4 = 48 bytes.

[0098] In contrast, in Example 2, as shown in Figure 10, the four target data fragments representing the values ​​of the four target variables are written to a contiguous area starting from the beginning address of the monitor RAM 16B. Therefore, the signals representing the four target data fragments are transmitted collectively from the monitor RAM 16A to the data reader 31. Consequently, if a data fragment is represented by 4 bytes, the amount of communication between the data reader 31 and the monitor RAM 16B is 4 × 4 = 16 bytes. Thus, the amount of communication in Example 2 is reduced to 33% of the amount of communication in Example 1.

[0099] As described above, the data reader 31 reads a set of multiple target data fragments (data fragment set). Therefore, the processor 33 analyzes the data fragment set by referring to the second table 37. Based on the analysis results, the processor 33 identifies the values ​​of each of the multiple target variables.

[0100] <Example 3> Figure 13 shows the configuration of Embodiment 3 of the monitoring system according to this embodiment. As shown in Figure 13, the monitoring system 100C according to Embodiment 3 differs from the monitoring system 100A shown in Figure 6 in that it includes an integrated circuit 1C instead of integrated circuit 1A.

[0101] Integrated circuit 1C is an embodiment of integrated circuit 1 shown in Figure 5. Integrated circuit 1C differs from integrated circuit 1A shown in Figure 6 in that it includes a recording circuit 13C instead of a recording circuit 13A. Recording circuit 13C is an example of the recording circuit 13 shown in Figure 5.

[0102] The recording circuit 13C differs from the recording circuit 13A in that it includes a write circuit 15C and a monitor RAM 16C instead of the write circuit 15A and monitor RAM 16A, and does not include a buffer 14.

[0103] The writing circuit 15C differs from the writing circuit 15A in that it does not have an address bus 150a and a data bus 150b. The second input terminal of the comparator 153A is connected to the address bus 20a.

[0104] The monitor RAM 16C can be accessed from the outside at a faster speed than RAM 12A. Specifically, the access speed to the monitor RAM 16C is greater than or equal to the access speed to the data cache 11. The monitor RAM 16C is connected to the data bus 20b.

[0105] According to the integrated circuit 1C of Embodiment 3, the write data output from the processor 10 to the data bus 20b is recorded in the monitor RAM 16C at the same timing as when it is held in the data cache 11. The data recorded in the monitor RAM 16C is acquired by the monitoring device 3A. This allows the user to more accurately verify the execution operation of the software 18 by the CPU 10A by checking the data acquired by the monitoring device 3A.

[0106] Although the present invention has been specifically described above based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence. [Explanation of Symbols]

[0107] 1,1A to 1C, 1Z Integrated circuits, 3,3A, 3B, 3Z Monitoring devices, 4 Boards, 10, 33 Processors, 10A CPU, 11 Data cache, 12 Memory, 12A RAM, 13, 13A to 13C Recording circuits, 14 Buffers, 15A to 15C Write circuits, 16A to 16C Monitor RAM, 18 Software, 20 Buses, 20a, 150a Address buses, 20b, 150b Data buses, 30 Debug interface, 31 Data reader, 32 Information processing unit, 34 User interface, 35 Storage, 36 First table, 37 Second table, 38 Monitoring program, 50, 50a to 50d Monitored addresses, 52, 52a to 52d Translated addresses, 60 Address set, 100, 100A to 100C, 100Z Monitoring system, 141 Dataset, 151A, 151B; Memory circuit, 152A, 152B; Comparator circuit, 153A, 153B; Comparator, 154A, 154B; Gate switch.

Claims

1. It is an integrated circuit, Processor and A first memory that holds data defined in the software executed by the aforementioned processor, The integrated circuit further comprises a data cache disposed between the processor and the first memory, the data cache temporarily holds write data output from the processor to be written to the first memory, and the integrated circuit further An integrated circuit comprising a recording circuit connected to a bus between the processor and the data cache, for recording the write data.

2. The aforementioned recording circuit is A buffer for temporarily storing the aforementioned write data, Second memory and The integrated circuit according to claim 1, further comprising a write circuit for writing the write data stored in the buffer to the second memory.

3. The integrated circuit according to claim 2, wherein the writing circuit writes one or more target data fragments from the write data, each of which is written to one or more first addresses in the first memory, to the second memory.

4. The integrated circuit according to claim 3, wherein the writing circuit writes the one or more target data fragments to the same addresses as the one or more first addresses in the second memory.

5. The aforementioned programming circuit is, The one or more first addresses are converted to one or more second addresses in the second memory, In the second memory, write the one or more target data fragments to the one or more second addresses, The integrated circuit according to claim 3, wherein the one or more second addresses are set so that the one or more target data fragments are recorded consecutively from the first address of the second memory.

6. The integrated circuit according to claim 5, wherein the capacity of the second memory is less than the capacity of the first memory.

7. The aforementioned recording circuit is A second memory that can be accessed at a faster speed than the first memory, The integrated circuit according to claim 1, further comprising a writing circuit for writing the aforementioned write data to the second memory.

8. It is a monitoring system, Integrated circuits and Equipped with a monitoring device, The aforementioned integrated circuit is The first processor and A first memory that holds data defined in the software executed by the first processor, The integrated circuit includes a data cache positioned between the first processor and the first memory, the data cache temporarily holds write data output from the first processor to be written to the first memory, and the integrated circuit further includes Includes a recording circuit connected to the bus between the first processor and the data cache, which records the write data, The monitoring device is A data reader that accesses the recording circuit and reads the written data, A monitoring system including a user interface for visualizing the changes in the values ​​of one or more variables indicated by the aforementioned light data.

9. The aforementioned recording circuit is A buffer for temporarily storing the aforementioned write data, Second memory and The circuit includes a write circuit that writes the write data stored in the buffer to the second memory, The user interface accepts the designation of one or more target variables from among the multiple variables defined in the software. The monitoring device further includes a second processor that identifies one or more first addresses in the first memory where one or more target data fragments representing one or more target variables are written, The monitoring system according to claim 8, wherein the writing circuit writes one or more target data fragments from the write data to the second memory.

10. The aforementioned programming circuit is, The one or more first addresses are converted to one or more second addresses in the second memory, In the second memory, write the one or more target data fragments to the one or more second addresses, The monitoring system according to claim 9, wherein the second processor sets one or more second addresses such that one or more target data fragments are recorded consecutively from the first address of the second memory.

11. The aforementioned one or more target variables include multiple target variables, The one or more target data pieces include a plurality of target data pieces that show the values ​​of the plurality of target variables, The data reader reads the set of multiple target data fragments all at once from the starting address of the second memory. The monitoring system according to claim 10, wherein the second processor analyzes the set and identifies the value of each of the plurality of target variables.

Images