Synchronization circuit, modulator, transmitter, synchronization control method, and program

Abstract

To recover from a clock interruption while suppressing the shock. [Solution] According to the embodiment, the synchronization circuit comprises an oscillator, a first frequency divider, a second frequency divider, a first comparator, a frequency multiplier, a third frequency divider, a second comparator, and a third comparator. The first frequency divider divides the reference clock signal to generate a first frame pulse. The second frequency divider divides the local signal of the oscillator to generate a second frame pulse. The first comparator feedback-controls the frequency of the local signal according to the phase difference between the first frame pulse and the second frame pulse. The frequency multiplier multiplies the local signal to generate a pulse signal. The third frequency divider divides the pulse signal to generate an internal clock. The second comparator switches the division ratio of the second frequency divider according to the phase difference between the system switching synchronization signal and the internal clock. The third comparator switches the division ratio of the third frequency divider according to the phase difference between the system switching synchronization signal and the internal clock.

Description

Technical Field

[0001] Embodiments of this invention relate to a synchronization circuit, a modulator, a transmission device, a synchronization control method, and a program.

Background Art

[0002] Broadcast infrastructures such as televisions and radios include STL / TTL (Studio to Transmitter Link / Transmitter to Transmitter Link) devices to transmit broadcast materials from a performance venue to a master station transmitter or from a master station transmitter to a relay transmitter. STL / TTL can be connected in series as STL→TTL→TTL→… in order to deliver signals over long distances. Devices are connected via high-frequency wireless communication (digital microwave) or an optical fiber communication interface.

[0003] The STL device includes a modulator (64QAM MOD) that 64QAM (Quadrature Amplitude Modulation) modulates a TS (Transport Stream) signal, which is a broadcast material. The modulator is supplied with a TS signal, an 8M CLK signal, and a Fsync signal from a master system, and digitally modulates the TS signal with 64QAM to output a 130 MHz IF (Intermediate Frequency) signal (digital modulation signal). Here, the Fsync signal is a system switching synchronization signal for taking switching synchronization between an active system and a standby system in the device.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The 8M CLK input to the modulator may be interrupted. In existing systems, when the PLL (Phase Lock Loop) synchronization is rebuilt during the recovery process from a clock interruption, the phase of the symbol clock (6M CLK) of the IF transmission frame is discontinuously skipped. This shocks the subsequent TTL, causing image frames to be lost. Furthermore, since the shock propagates in a chain reaction to all subsequent devices, it can result in not only frame loss but also the simultaneous occurrence of numerous alarms and disruption of broadcasting.

[0006] Therefore, the objective is to provide a synchronization circuit, modulator, transmitter, synchronization control method, and program that can recover from clock interruption while suppressing shocks. [Means for solving the problem]

[0007] According to the embodiment, the synchronization circuit is applicable to a modulator that receives a broadcast TS (Transport Stream) signal, a reference clock signal, and a system switching synchronization signal as inputs and outputs a digitally modulated signal. This synchronization circuit comprises an oscillator that generates a local signal, a first frequency divider, a second frequency divider, a first comparator, a frequency multiplier, a third frequency divider, a second comparator, and a third comparator. The first frequency divider divides the reference clock signal to generate a first frame pulse. The second frequency divider divides the local signal with a switchable division ratio to generate a second frame pulse. The first comparator controls the oscillator according to the phase difference between the first frame pulse and the second frame pulse to provide feedback control of the frequency of the local signal. The frequency multiplier multiplies the local signal to generate a pulse signal. The third frequency divider divides the pulse signal with a switchable division ratio to generate a generated internal clock. The second comparator switches and controls the division ratio of the second frequency divider according to the phase difference between the system switching synchronization signal and the generated internal clock. The third comparator includes a third comparator that switches and controls the frequency division ratio of the third frequency divider according to the phase difference between the system switching synchronization signal and the generated internal clock. [Brief explanation of the drawing]

[0008] [Figure 1]Figure 1 is a system diagram showing an example of a broadcasting system according to the embodiment. [Figure 2] Figure 2 is a block diagram showing an example of a transmitting device installed at the main station transmitting station 60. [Figure 3] Figure 3 is a block diagram showing an example of a receiving device installed at the relay transmission station 70. [Figure 4] Figure 4 is a block diagram showing an example of a synchronization circuit provided in modulators 11 and 12 shown in Figure 2. [Figure 5] Figure 5 is a timing chart illustrating the state of each signal after the 8M CLK input has been restored from an interruption. [Figure 6] Figure 6 is a timing chart illustrating the behavior of comparator 10 when a Stable input is received. [Figure 7] Figure 7 is a functional block diagram showing another example of a synchronous circuit. [Figure 8] Figure 8 is a flowchart showing an example of the processing procedure of processor 34. [Modes for carrying out the invention]

[0009] Figure 1 is a system diagram showing an example of a terrestrial digital broadcasting system according to an embodiment. Terrestrial digital broadcasting programs are transmitted using various relay methods. For example, there is a broadcast wave relay method that directly receives and relays broadcast waves from a higher-level transmission station, and a TTL (Transmitter to Transmitter Link) relay method that relays using microwave band radio frequencies as a medium.

[0010] TTL relay systems are broadly classified into TS (Transport Stream) transmission systems and IF (Intermediate Frequency) transmission systems. The TS transmission system is a digital regenerative relay system in which the TS signal is transmitted as a 64QAM (Quaternary Amplitude Modulation) signal and the TS signal is regenerated at the receiving end. The IF transmission system is a non-regenerative relay system in which the OFDM (Quaternary Frequency Division Multiplexing) signal, which is a broadcast wave, is transmitted at radio frequencies in the microwave band.

[0011] In Figure 1, broadcasting station 50 transmits a broadcast TS signal to the master transmitter 60. The master transmitter 60 transmits the broadcast TS signal from broadcasting station 50 to the relay transmitter 70 using the TS transmission method. At both ends of the TS transmission section, the master transmitter 60 is equipped with transmitting equipment, and the relay transmitter 70 is equipped with receiving equipment.

[0012] Figure 2 is a block diagram showing an example of a transmitting device installed at the master station 60. The transmitting device 100 in Figure 2 is equipped with two modulators 11 and 12. Modulator 11 functions as the master (active / No. 1) system, and modulator 12 functions as the slave (backup / No. 2) system. The TS signal, 8M CLK signal, and Fsync signal are input to both modulators 11 and 12. Under the control of the modulator control unit 13, modulators 11 and 12 each modulate the TS signal with 64QAM and output an IF signal. The transmitting device is equipped with redundant switching means that switches between the active modulator 11 and the backup modulator 12 at the timing of the Fsync signal, which is a system switching synchronization signal.

[0013] The IF signal from modulator 11 is input to the transmitter converter 14, upconverted, and converted into an RF (Radio Frequency) signal within the transmission bandwidth. Similarly, the IF signal from modulator 12 is converted into an RF signal by the transmitter converter 15. Here, the transmitter converter 14 is the master system, and the transmitter converter 15 is the slave system, and the transmitter converters 14 and 15 are controlled by the transmitter converter control unit 16.

[0014] The RF signals from the transmitter converters 14 and 15 are input to the SHF (Super High Frequency) switch 17. Under the control of the transmitter converter control unit 16, the SHF switch 17 selects one of the RF signals according to the operating status of the active / backup system and inputs it to the transmit filter 18. The transmit filter 18 shapes the RF signal waveform and controls the transmission level, then radiates it into space from the microwave antenna.

[0015] Figure 3 is a block diagram showing an example of a receiving device installed in the relay transmission station 70. In Figure 3, the RF signal arriving at the microwave antenna of the receiving device 200 is waveform-shaped by the receiving filter distributor 21 and distributed to the receiving converters 22 and 23. Under the control of the reception control unit 124, the receiving converters 22 and 23 each down-convert the RF signal and output an IF signal.

[0016] The IF signal from the receiving converter 22 is input to the demodulator 25, and the IF signal from the receiving converter 23 is input to the demodulator 26. Here, the receiving converter 22 and the demodulator 25 are the master (active / No.1) system, and the receiving converter 23 and the demodulator 26 are the slave (standby / No.2) system.

[0017] The demodulators 25 and 26 each reproduce a TS signal, an 8M CLK signal, and a Fsync signal from the IF signal. These signals are input to the TS switching distributor 27, distributed to multiple systems, and further transmitted downstream or broadcast to the broadcast area. In Figure 3, the demodulators 25 and 26 have three output systems. Also, the TS switching distributor 27 has three input systems and four output systems. The number of these systems is an example and is not limited to the illustrated number.

[0018] Generally, in the STL / TTL system, a redundant configuration of active 1 and standby 1 is adopted. Both the transmitting device 100 in Figure 2 and the receiving device 200 in Figure 3 have a redundant configuration with a No.1 system and a No.2 system.

[0019] FIG. 4 is a block diagram showing an example of a synchronization circuit provided in the modulator 11 shown in FIG. 2. In FIG. 4, the input 8M CLK and the input Fsync are the 8M CLK and Fsync input to the modulator 11 (FIG. 2). Also, the generated 8M CLK and the generated Fsync are the 8M CLK and Fsync internally generated in the synchronization circuit. The input 8M CLK and the generated 8M CLK, and the input Fsync and the generated Fsync are distinguished from each other. Hereinafter, how the generated 8M CLK and the generated Fsync approach the input 8M CLK and the input Fsync will be described. Note that the modulator 12 also includes a synchronization circuit having a similar configuration.

[0020] 8M CLK and Fsync are synchronized with each other, and have the following relationship in accordance with the specifications of terrestrial digital broadcasting. 8M CLK = 512 / 63 ≒ 8.126984 [MHz] Fsync period = 63 / 512 * 408 * 4608 = 63 / 512 * 1,880,064 = 231,336 [μs] = 231 [ms] That is, the period of Fsync is approximately 231 ms.

[0021] Now, the synchronization circuit shown in FIG. 4 includes a counter 1, a comparator 2, a 17-divider 3, a 14-divider 4, a phase comparator 5, an oscillator 6 (VCXO), a 2-divider 7, a 17-multiplier 8, a 14-divider 9, and a comparator 10. The input 8M CLK is input to the 17-divider 3, and the input Fsync is input to the comparator 2 and the comparator 10. Among these, the phase comparator 5, the oscillator 6, and the 2-divider 7 constitute a PLL. These circuits may be implemented, for example, on an FPGA (Field Programmable Gate Array).

[0022] The phase comparator 5 of the PLL receives FP6 (frame pulse 6), which is the output of the 14-division frequency divider 4, and FP8 (frame pulse 8), which is the output of the 17-division frequency divider 3. The phase comparator 5 compares the phases of FP6 and FP8 and outputs a pulse width modulation (PWM) signal corresponding to the difference. The oscillator 6 generates a 13MHz reference clock based on the duty cycle of the PWM signal. This reference clock is divided by 2 by the 2-division frequency divider 7 to generate a 6M CLK with the following frequencies (generated 6M CLK). 6M CLK = 8M CLK * 14 / 17 ≒ 6.692810[MHz]

[0023] The generated 6M CLK is input to the 17x multiplier 8 and the 14x divider 4. The 17x multiplier 8 multiplies the generated 6M CLK by 17 and outputs a 113MHz pulse signal. The 14x divider 4 divides the generated 6M CLK by 14 to generate FP6, which is output to the phase comparator 5.

[0024] Here, FP6 has the same period as FP8. However, when FAST is input from comparator 2, the 14-division divider 4 advances the phase of FP6 by setting the division ratio to 13, and when SLOW is input from comparator 2, it delays the phase of FP6 by setting the division ratio to 15. This control is performed at a predetermined period (for example, every 30 seconds), and the feedback mechanism ensures that the phases of FP6 and FP8 match, thereby synchronizing FP6 and FP8. Furthermore, when the input 8M CLK is interrupted, the phase comparator 5 fixes the pulse width to the value immediately before the interruption and continuously outputs a PWM signal.

[0025] The 113MHz pulse signal from the 17-frequency multiplier 8 is divided by 14 by the 14-frequency divider 9, generating and outputting an 8M CLK (generated 8M CLK). However, if FAST2 is input from the comparator 10, the 14-frequency divider 9 advances the phase of the generated 8M CLK by setting the division ratio to 13, and if SLOW2 is input, it delays the phase of the generated 8M CLK by setting the division ratio to 15. This control is performed every 231ms, which is the Fsync period, and the phase of the generated 8M CLK is stably adjusted.

[0026] The 8M CLK generated from the 14-frequency divider 9 is input to the comparator 10 and counter 1. Counter 1 counts up from 0 to 1880063 for each pulse of the generated 8M CLK and outputs sync_gen_cnt according to the count value. This count value is reset to 0 with the same period as Fsync (≒231ms), and the MSB of sync_gen_cnt is the timing of the generated Fsync.

[0027] Comparator 2 compares the phase of the input Fsync with the MSB (Most Significant Bit) of sync_gen_cnt. If input Fsync is faster, it outputs FAST; if it is slower, it outputs SLOW. If the phases match and this state remains stable for a predetermined period (e.g., 30 seconds), it outputs Stable. When comparator 10 receives a stable signal from comparator 2, it compares the phase of the generated 8M CLK with the input Fsync and outputs FAST2 to the 14-frequency divider 9 if the input Fsync is in phase earlier, and SLOW2 if it is in phase later.

[0028] Figure 5 is a timing chart illustrating the state of each signal after the input 8M CLK is restored from an interruption. Referring to Figure 5, we will explain the recovery from a state where the phase of input Fsync was faster than the generated Fsync when the input 8M CLK was restored.

[0029] (1) Immediately after the 8M CLK input is restored, comparator 2 (Figure 4), which compares the MSB of input Fsync with that of sync_gen_cnt, outputs FAST to the 14-frequency divider 4. (2) The 14-frequency divider 4 receives this FAST signal and delays the phase of FP6. As a result, the phases of FP6 and FP8, which were synchronized and matched with each other in the PLL, are adjusted. (3) Due to the phase adjustment in (2), the MSB of sync_gen_cnt becomes earlier, and its phase with the input Fsync becomes closer, but since the phase of the input Fsync is still faster, FAST is output. (4) As FAST was raised again in (3), the phase of FP6 was adjusted. (5) The phase adjustment in (4) causes the MSB of sync_gen_cnt and the input Fsync to match. From this point onward, FAST and SLOW will no longer be raised. (6) Because FAST / SLOW is not set, FP6 and FP8 remain stable, and the PLL outputs a stable generated 6M CLK. (7) When the MSB of sync_gen_cnt and the input Fsync become synchronized and matched and stable, comparator 2 in Figure 2 outputs Stable. After going through states (1) to (7), recovery from the clock interruption is achieved without shock. Note that the recovery from the state where the phase of input Fsync is slower than the generated Fsync when input 8M CLK is restored is omitted from the explanation as it only involves the reversal of the phase relationship with the output FP8 of the 17 frequency divider 3 (Figure 4).

[0030] Figure 6 is a timing chart illustrating the behavior of comparator 10 with a Stable input. Referring to Figure 6, we will explain how to synchronize and match the phases of the input Fsync and the generated 8M CLK, starting from a state where the input Fsync's phase is fast. Note that the explanation for the transition from a state where the input Fsync's phase is slow is omitted as it only reverses the phase relationship.

[0031] (a) Since the falling edge of the input Fsync is faster than the falling edge of the generated 8M CLK, comparator 10 (Figure 4) outputs FAST2. (b) The 14-frequency divider 9 (Figure 2) advances the phase of the generated 8M CLK upon receiving FAST2. As a result, the phases of the generated 8M CLK and the input Fsync gradually synchronize and coincide.

[0032] As described above, according to the embodiment, the timing of the Fsync generated inside the synchronous circuit can be gradually adjusted to gradually approach the timing of the input Fsync. Furthermore, the generated 8M CLK generated inside the synchronous circuit can be gradually brought closer to the phase of the input Fsync. In other words, when recovering from an 8M CLK input interruption, the 6M CLK can be gradually synchronized with the PLL.

[0033] In other words, according to this embodiment, when recovering from a state where the 8M CLK input to the synchronization circuit of modulators 11 and 12 is interrupted, the oscillator 6 (internal clock) can be gradually synchronized without skipping phases during PLL synchronization, thereby suppressing the shock to the subsequent TTL system.

[0034] In existing technologies, when a modulator recovers from an 8M CLK input interruption, the PLL is rebuilt, causing a phase jump in the 6M CLK signal, resulting in a shock to the subsequent TTL signal. In contrast, the embodiment provides a synchronization circuit, modulator, transmitter, synchronization control method, and program that can recover from a clock interruption while suppressing the shock.

[0035] It should be noted that this invention is not limited to the embodiments described above. For example, it is also possible to implement the synchronization control function that was implemented in hardware using software. (Other embodiments) Figure 7 is a functional block diagram showing another example of a synchronous circuit. In another embodiment, a configuration in which the PLL circuit is controlled by an embedded computer having memory and a processor is described. The synchronization circuit comprises an interface (I / F) section 31 that accepts input 8M CLK and input Fsync, a PLL circuit 32, a memory 33, and a processor 34. The processor 34 reads and executes program 33a stored in memory 33 to realize the synchronization control function. The processor 34 generates frame pulses FP6 and FP8 from the state of input 8M CLK and input Fsync, inputs them to the PLL circuit 32, and stabilizes the frequency and phase of the generated 8M CLK.

[0036] Figure 8 is a flowchart showing an example of the processing procedure of the processor 34. First, the processor 34 compares the MSB of sync_gen_cnt output from counter 1 with the phase of input Fsync (step S1). If input Fsync is slow, it sets the division ratio to 15 (step S2); if it is fast, it sets the division ratio to 13 (step S3); and if neither is the case, it sets the division ratio to 14 (step S4) and stores this value in an internal register. The generated 6MCLK output from the PLL circuit 32 (Figure 4) is divided by the set division ratio and input to the PLL circuit 32 as a frame pulse FP6. After 30 seconds have elapsed since the division ratio became 14 (Yes in step S5), the processor sets Stable (step S6).

[0037] Next, the processor 34 compares the phase of the generated 8MCLK with the phase of the input Fsync (step S7). If the input Fsync is slow, it sets the division ratio to 15 (step S8); if it is fast, it sets the division ratio to 13 (step S9); and if it is neither, it sets the division ratio to 14 (step S10) and stores the value in an internal register. The process from steps S7 to S11 is repeated with a period of 231 [mS], and the PLL is locked at a predetermined frequency. In this way, a synchronization circuit similar to that in Figure 4 can also be realized by software processing.

[0038] While embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications are permitted without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, as well as within the scope of the claims and their equivalents. [Explanation of symbols]

[0039] 1...Counter, 2...Comparator, 3...17-frequency divider, 4...14-frequency divider, 5...Phase comparator, 6...Oscillator, 7...2-frequency divider, 8...17-frequency multiplier, 9...14-frequency divider, 10...Comparator, 11,12...Modulator, 13...Modulator control unit, 14,15...Transmit converter, 16...Transmit converter control unit, 17...SHF switch, 18...Transmit filter, 21...Receive filter distributor, 22...Receive converter, 23...Receive converter, 25...Demodulator, 26...Demodulator, 27...TS switch distributor, 31...Interface unit, 32...PLL circuit, 33...Memory, 33a...Program, 34...Processor, 50...Broadcasting station, 60...Master station transmitter, 70...Relay transmitter, 100...Transmitter, 124...Receiver control unit, 200...Receiver.

Claims

1. In a synchronization circuit applicable to a modulator that receives a broadcast TS (Transport Stream) signal, a reference clock signal, and a system switching synchronization signal as inputs and outputs a digitally modulated signal, An oscillator that generates a local signal, A first frequency divider that divides the reference clock signal to generate a first frame pulse, A second frequency divider that divides the local signal with a switchable frequency division ratio to generate a second frame pulse, A first comparator controls the oscillator according to the phase difference between the first frame pulse and the second frame pulse to feedback control the frequency of the local signal, A frequency multiplier that multiplies the aforementioned local signal to generate a pulse signal, A third frequency divider that divides the pulse signal with a switchable frequency division ratio to generate an internal clock, A second comparator controls the frequency division ratio of the second frequency divider according to the phase difference between the system switching synchronization signal and the generated internal clock, A synchronization circuit comprising a third comparator that switches and controls the frequency division ratio of the third frequency divider according to the phase difference between the system switching synchronization signal and the generated internal clock.

2. Furthermore, the synchronization circuit according to claim 1, comprising a counter that counts up the pulses of the generated internal clock up to a predetermined value and inputs it to the second comparator.

3. The synchronization circuit according to claim 1, wherein the third frequency divider generates an internally generated clock that is synchronized with a 512 / 63 [MHz] reference clock signal.

4. The first frequency divider is a 17-frequency divider that divides a 512 / 63 [MHz] reference clock signal by 17. The second frequency divider is a 14-frequency divider that divides the local signal by 14. The aforementioned multiplier is a 17-multiplier that multiplies the local signal by 17 times. The synchronization circuit according to claim 1, wherein the third frequency divider is a 14-frequency divider that divides the pulse signal by 14.

5. The synchronization circuit according to claim 4, wherein the second frequency divider switches the frequency division ratio to 13 when the phase of the system switching synchronization signal is ahead of the phase of the generated internal clock, and switches the frequency division ratio to 15 when the phase of the system switching synchronization signal is behind the phase of the generated internal clock.

6. The first frequency divider is a 17-frequency divider that divides a 512 / 63 [MHz] reference clock signal by 17. The second frequency divider is a 14-frequency divider that divides the local signal by 14. The aforementioned multiplier is a 17-multiplier that multiplies the local signal by 17 times. The synchronization circuit according to claim 2, wherein the third frequency divider is a 14-frequency divider that divides the pulse signal by 14.

7. The synchronization circuit according to claim 4, wherein the second frequency divider switches the frequency division ratio to 13 when the phase of the system switching synchronization signal is ahead of the phase of the generated internal clock, and switches the frequency division ratio to 15 when the phase of the system switching synchronization signal is behind the phase of the generated internal clock.

8. A modulator comprising a synchronization circuit according to any one of claims 1 to 7, which digitally modulates the broadcast TS signal based on the reference clock signal and outputs a digitally modulated signal.

9. The modulator described in claim 8 is provided as the primary system and the backup system, A transmitting device comprising redundant switching means for switching between the modulator of the active system and the modulator of the backup system at the timing of the system switching synchronization signal.

10. In a synchronization control method in which a synchronization circuit comprising an interface section that receives a reference clock signal and a system switching synchronization signal, and an oscillator that generates a local signal, is controlled by a processor, The process by which the processor compares the phase of the system switching synchronization signal with the phase of the MSB (Most Significant Bit) of the count-up value of the generated internal clock generated from the local signal, A synchronization control method comprising the process of the processor comparing the phase of the system switching synchronization signal with the phase of the generated internal clock after a predetermined time has elapsed since the comparison result between the phase of the system switching synchronization signal and the phase of the MSB stabilizes, and repeating the frequency of the oscillator's local signal at predetermined intervals based on the result.

11. A program stored in the memory of an embedded computer comprising memory and a processor, which causes the processor to execute the synchronization control method described in claim 10.

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