Apparatus and method for supplying multiple waveform signals during plasma processing

Abstract

Embodiments of this disclosure generally relate to systems used in semiconductor device manufacturing processes. [Solution] Embodiments provided herein generally include apparatus and methods for synchronizing and controlling the supply of RF bias voltage signals and pulsed voltage waveforms to one or more electrodes inside a plasma processing chamber. Embodiments of the Disclosure include methods and apparatus for synchronizing a pulsed radio frequency (RF) waveform with a pulsed voltage (PV) waveform so that the pulsed RF waveform is turned on during a first stage of the PV waveform and turned off during a second stage. The first stage of the PV waveform includes a sheath collapse stage. The second stage of the PV waveform includes an ion current stage.

Description

[Technical Field]

[0001] Embodiments of this disclosure generally relate to systems and methods used in semiconductor device manufacturing. More specifically, embodiments provided herein generally include systems and methods for synchronizing radio frequency (RF) pulse waveforms with pulse voltage (PV) waveforms on one or more electrodes inside a processing chamber. [Background technology]

[0002] Reliably manufacturing high aspect ratio features is one of the key technical challenges for next-generation semiconductor devices. One method for forming high aspect ratio features is to use a plasma-assisted etching process (e.g., reactive ion etching (RIE) plasma process) to form high aspect ratio openings in a substrate material layer (e.g., a dielectric layer). In a typical RIE plasma process, plasma is formed in a processing chamber, and ions from the plasma are accelerated toward the substrate surface, forming openings in the material layer located beneath a mask layer formed on the substrate surface.

[0003] A typical reactive ion etching (RIE) plasma processing chamber includes a radio frequency (RF) bias generator that supplies an RF voltage to the power electrodes. In capacitively coupled gas discharges, the plasma is generated by using a radio frequency (RF) generator connected to power electrodes located inside an electrostatic chuck (ESC) assembly or another part of the processing chamber. Typically, an RF matching network ("RF matching") supplies RF power to a 50Ω apparent load, aligning the RF waveform supplied from the RF generator to minimize reflected power and maximize power supply efficiency. If the load impedance is not properly matched to the source (e.g., the RF generator) impedance, some of the forward-supplied RF waveform may be reflected back in the opposite direction along the same transmission line.

[0004] Many plasma processes also utilize DC voltage pulses to control the plasma sheath placed on the substrate during processing. During operation, the DC voltage pulses switch the generated plasma sheath between a state containing a thick plasma sheath and a state without a plasma sheath. Typically, the DC pulse technique is configured to supply voltage pulses at frequencies above 50 kHz (e.g., frequencies above 400 kHz). The switching of the plasma sheath by the supplied DC pulse voltage waveform causes the plasma load to have different impedance values ​​over time. It has been found that the interaction between the RF waveform and the DC pulse voltage waveform supplied simultaneously during plasma processing can lead to different plasma processing results because the RF matching portion of the RF power supply system cannot adjust the RF matching point to account for the rapidly changing plasma load impedance values ​​over time. Conventional impedance matching components and processes cannot keep up with rapid changes in the magnitude of the plasma load impedance, resulting in the detection of undesirable matching points during matching. This typically leads to fluctuations in the amount of RF power actually supplied to the plasma load due to 1) intermodulation distortion (IMD) of the RF signal and 2) undesirable high reflected RF power, which is usually found in the harmonics of the driving RF frequency. Intermodulation distortion resulting from the interaction between the RF pulse waveform and the DC pulse voltage waveform causes at least the amplitude of the RF signal to change over time. The interaction or intermodulation between the RF pulse waveform and the DC pulse voltage waveform creates further undesirable waveform components at frequencies other than the harmonic frequencies (i.e., integer multiples) of the interacting signals, such as either the RF pulse waveform or the DC pulse waveform. The generation of IMD components in the power supply system reduces the actual forward RF power supplied to the plasma load.At a minimum, rapidly changing plasma load impedance values, resulting from unavoidable differences in the power supply configuration of processing chambers and differences in power supply components, cause undesirable differences in plasma processing results, observed in a single plasma processing chamber, in similarly configured processing chambers on a single processing system, and in similarly configured plasma processing chambers within different plasma processing systems within a semiconductor manufacturing site. Furthermore, the generated IMD components are not readily considered in most power supply systems due to the wide range of frequencies that may occur during plasma processing in the same or different processing chambers, thus causing unexpected fluctuations in the power actually supplied to the plasma load during plasma processing.

[0005] Therefore, in this field, there is a need for a plasma processing device and a biasing method that can solve at least the above-mentioned problems. [Overview of the project]

[0006] This disclosure relates, in general, to a method for plasma processing, which includes applying a voltage waveform to electrodes disposed in a substrate support, wherein the voltage waveform has a first stage and a second stage, the first stage including a sheath collapse stage and the second stage including an ion current stage. The method further includes applying a pulsed radio frequency (RF) waveform to a reaction species to generate plasma within a processing area of ​​a processing chamber, and synchronizing the pulsed RF waveform with the voltage waveform such that the pulsed RF waveform is provided during one of the stages but not during the other stages. In one embodiment, the pulsed RF waveform is provided during the second stage but not during the first stage. In another embodiment, the pulsed RF waveform is provided during the first stage but not during the second stage.

[0007] The disclosure generally relates to a method for plasma processing, which includes applying a voltage waveform to electrodes disposed in a substrate support, wherein the voltage waveform has a first stage and a second stage, the first stage including a sheath collapse stage and the second stage including an ion current stage. The method further includes applying a pulsed radio frequency (RF) waveform to a reaction species to generate plasma within a processing area of ​​a processing chamber, and synchronizing the pulsed RF waveform with the voltage waveform such that the pulsed RF waveform is provided during one stage and not during other stages.

[0008] The present disclosure further includes a plasma processing system comprising: a PV waveform generator connected to a first electrode; an RF waveform generator connected to a second electrode of a plasma processing system, configured to generate plasma within a processing area; an impedance matching circuit; and a controller having a processor configured to execute computer-readable instructions, wherein the computer-readable instructions cause the system to perform the following actions: apply a PV waveform generated by the PV waveform generator; apply an RF waveform generated by the RF waveform generator; and synchronize the PV waveform with the RF waveform.

[0009] Embodiments of the present disclosure provide a method for plasma processing, comprising: applying a pulsed voltage waveform to one or more electrodes disposed within a substrate support, wherein the voltage waveform has a first stage and a second stage; applying a pulsed radio frequency (RF) waveform to one or more electrodes to generate plasma within a processing area of ​​a processing chamber; and synchronizing the pulsed RF waveform with each pulse of the pulsed voltage waveform so that the RF waveform of the pulsed radio frequency (RF) waveform is supplied only for at least a portion of the second stage of each pulse of the pulsed voltage waveform.

[0010] Embodiments of the present disclosure provide a method for plasma processing, comprising: applying a pulsed voltage waveform to one or more electrodes disposed within a substrate support, wherein the voltage waveform has a first stage and a second stage; applying a pulsed radio frequency (RF) waveform to one or more electrodes to generate plasma within a processing area of ​​a processing chamber; and synchronizing the pulsed RF waveform with each pulse of the pulsed voltage waveform so that the RF waveform of the pulsed radio frequency (RF) waveform is supplied only for at least a portion of the first stage of each pulse of the pulsed voltage waveform.

[0011] Embodiments of the present disclosure provide a plasma processing system comprising: a pulse voltage waveform generator connected to a first electrode; a radio frequency waveform generator connected to a second electrode, configured to generate plasma within the processing space of the plasma processing system; an impedance matching circuit connected between the radio frequency waveform generator and the second electrode; and a controller. The controller has a processor configured to execute computer-readable instructions stored in memory, the computer-readable instructions causing the system to apply a pulse voltage waveform to the first electrode using the pulse voltage waveform generator, wherein the pulse voltage waveform comprises a series of voltage pulses each comprising a first stage and a second stage; apply a pulse radio frequency waveform to the second electrode using the radio frequency waveform generator to generate plasma within the processing area of ​​the processing chamber; and synchronize the pulse RF waveform with each pulse of the pulse voltage waveform so that the RF waveform of the pulse radio frequency (RF) waveform is supplied only for at least a portion of the second stage of each pulse of the pulse voltage waveform.

[0012] To enable a more detailed understanding of the features of this disclosure described above, a more detailed description of this disclosure, which is briefly summarized above, can be obtained by referring to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings show only exemplary embodiments and should not be considered to limit the scope of this disclosure, and other equally valid embodiments are also permissible. [Brief explanation of the drawing]

[0013] [Figure 1] This is a schematic cross-sectional view of one or more embodiments of a processing system configured to perform the methods described herein. [Figure 2] The following describes two distinct voltage waveforms established on a substrate placed on a substrate support assembly of a processing chamber by supplying pulsed voltage waveforms to one or more electrodes inside the processing chamber according to one or more embodiments. [Figure 3A] This is a plot of forward RF bias voltage signals and intermodulation distortion (IMD) signals measured along a transmission line connected to one or more electrodes in a processing chamber, according to one embodiment. [Figure 3B] This shows an RF bias voltage signal applied to a pulse voltage waveform supplied through a transmission line connected to one or more electrodes in a processing chamber, according to one embodiment. [Figure 4] This chart shows the percentage of broadband reflections observed in two different conventional plasma processing chambers according to one embodiment. [Figure 5A] This shows a pulsed RF bias voltage signal applied to an electrode in a processing chamber according to one embodiment. [Figure 5B] Figure 5A shows a combination of a pulsed RF bias voltage signal and a pulsed RF bias voltage signal, formed by supplying a pulsed RF bias voltage signal and a pulsed voltage waveform to one or more electrodes of a processing chamber, according to one embodiment. [Figure 6]This is a flowchart illustrating a method for synchronizing PV waveforms and RF bias voltage waveforms in a plasma processing system according to one embodiment. [Modes for carrying out the invention]

[0014] To facilitate understanding, the same reference numerals were used to indicate identical elements common to multiple figures where possible. Elements and features of one embodiment are considered to be usefully incorporated into other embodiments without further description.

[0015] Embodiments of this disclosure generally relate to systems used in semiconductor device manufacturing processes. More specifically, embodiments provided herein generally include apparatus and methods for synchronizing and controlling the supply of RF bias voltage signals and pulsed voltage waveforms to one or more electrodes inside a plasma processing chamber.

[0016] Figure 1 is a schematic cross-sectional view of a plasma processing chamber assembly 10 configured to perform one or more of the plasma processing methods described herein. In some embodiments, the plasma processing chamber assembly 10 is configured for plasma-assisted etching processes such as reactive ion etching (RIE) plasma processing. The plasma processing chamber assembly 10 can also be used for other plasma-assisted processes, such as plasma-enhanced deposition processes (e.g., plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced physical vapor deposition (PEPVD), plasma-enhanced atomic layer deposition (PEALD)), plasma processing processes, plasma-based ion implantation processes, or plasma doping (PLAD) processes. In one configuration, as shown in Figure 1, the plasma processing chamber assembly 10 is configured to form a capacitively coupled plasma (CPP). However, in some embodiments, the plasma may be generated by an inductively coupled source located on the processing area of ​​the plasma processing chamber assembly 10. In this configuration, a coil may be placed on top of the ceramic lid (vacuum boundary) of the plasma processing chamber assembly 10.

[0017] The plasma processing chamber assembly 10 includes a processing chamber 100, a substrate support assembly 136, a gas supply system 182, a DC power system 183, an RF power system 189, and a system controller 126. The processing chamber 100 includes a chamber body 113 that includes a chamber lid 123, one or more sidewalls 122, and a chamber base 124. The chamber lid 123, one or more sidewalls 122, and the chamber base 124 collectively define a processing space 129. The one or more sidewalls 122 and the chamber base 124 are generally sized and shaped to form a structural support for the elements of the processing chamber 100 and are configured to withstand the pressures and additional energies applied to those elements while a vacuum environment maintained within the processing space 129 of the processing chamber 100 during plasma 101 is generated, including materials (such as aluminum, aluminum alloy, or stainless steel alloy) configured to withstand such conditions. The substrate 103 is carried into and removed from the processing space 129 through an opening (not shown) in one of the sidewalls 122. The opening is sealed with a slit valve (not shown) during plasma processing of the substrate 103. The gas supply system 182 connected to the processing space 129 of the processing chamber 100 includes a processing gas source 119 and a gas inlet 128 disposed through the chamber lid 123. The gas inlet 128 is configured to supply one or more processing gases from the plurality of processing gas sources 119 to the processing space 129.

[0018] The processing chamber 100 further includes an upper electrode (e.g., the chamber lid 123) and a lower electrode (e.g., the substrate support assembly 136) disposed within the processing space 129. The upper electrode and the lower electrode are positioned to face each other. As seen in FIG. 1, in one embodiment, a radio frequency (RF) source (e.g., the RF power system 189) is electrically connected to the lower electrode. The RF source is configured to supply an RF signal for igniting and maintaining a plasma (e.g., plasma 101) between the upper electrode and the lower electrode. In some alternative configurations, as shown in FIG. 1, the RF source (e.g., the RF power system 189) can also be electrically connected to the upper electrode.

[0019] The substrate support assembly 136 includes a substrate support 105, a substrate support base 107, an insulator plate 111, a ground plate 112, a plurality of lift pins 186, one or more substrate potential sensing assemblies 184, and a bias electrode 104. Each of the lift pins 186 is disposed through a through hole 185 formed in the substrate support assembly 136 and is used to facilitate the movement of the substrate 103 between the substrate receiving surface 105A of the substrate support 105. The substrate support 105 is formed of a dielectric material. The dielectric material can include a bulk sintered ceramic material, a corrosion-resistant metal oxide (e.g., aluminum oxide (Al2O3), titanium oxide (TiO), yttrium oxide (Y2O3)), a metal nitride material (e.g., aluminum nitride (AIN), titanium nitride (TiN)), mixtures thereof, or combinations thereof.

[0020] The substrate support base 107 is formed of a conductive material (e.g., aluminum, aluminum alloy, stainless alloy). The substrate support base 107 is electrically insulated from the chamber base 124 by the insulator plate 111 and a ground plate 112 interposed between the insulator plate 111 and the chamber base 124. In some embodiments, the substrate support base 107 is configured to adjust the temperature of both the substrate support 105 and the substrate 103 disposed on the substrate support 105 during substrate processing. In some embodiments, the substrate support base 107 includes one or more cooling channels (not shown) disposed therein that are in fluid communication and fluidly coupled to a coolant source (not shown) such as a refrigerant source or a substrate source having a relatively high electrical resistance. In other embodiments, the substrate support 105 includes a heater (not shown) for heating the substrate support 105 and the substrate 103 disposed on the substrate support 105.

[0021] The bias electrode 104 is embedded in the dielectric material of the substrate support 105. Typically, the bias electrode 104 is formed of one or more conductive components. Conductive components typically include mesh, foil, plate, or a combination thereof. Here, the bias electrode 104 functions as a chuck electrode (i.e., an electrostatic chuck electrode) used to fix the substrate 103 to the substrate receiving surface 105A of the substrate support 105 (e.g., electrostatically chuck). Generally, a structure such as parallel plates is formed by the bias electrode 104 and a layer of dielectric material placed between the bias electrode 104 and the substrate receiving surface 105A. The dielectric material can typically have an effective capacitance CE between about 5 nF and about 50 nF. Typically, the dielectric material layer (e.g., aluminum nitride (AlN), aluminum oxide (Al2O3), etc.) has a thickness between approximately 0.03 mm and approximately 5 mm, for example between approximately 0.1 mm and approximately 3 mm, for example between approximately 0.1 mm and approximately 1 mm, and even between approximately 0.1 mm and approximately 0.5 mm. The bias electrode 104 is electrically connected to a clamping network and supplies a chucking voltage. The clamping network includes a DC voltage supply unit 173 (e.g., a high-voltage DC supply unit) connected to a filter 178A of a filter assembly 178 located between the DC voltage supply unit 173 and the bias electrode 104. In one embodiment, the filter 178A is a low-pass filter and is configured to prevent RF frequency and pulse voltage (PV) waveform signals supplied by other bias components found in the processing chamber 100 during plasma processing from reaching the DC voltage supply unit 173. In one configuration, the static DC voltage is between approximately -5000V and approximately 5000V and is supplied using an electrical conductor (such as a coaxial power supply line 160). In some embodiments, the bias electrode 104 may also bias the substrate 103 to the plasma 101 using one or more pulse voltage biasing schemes, which are described in more detail below.

[0022] In some configurations, the substrate support assembly 136 further includes an edge control electrode 115. The edge control electrode 115 is formed from one or more conductive components. Conductive components typically include mesh, foil, plate, or a combination thereof. The edge control electrode 115 is positioned below the edge ring 114, surrounding the bias electrode 104 and / or positioned at a distance from the center of the bias electrode 104. Generally, in a processing chamber 100 configured to process a circuit board, the edge control electrode 115 is ring-shaped, fabricated from a conductive material, and configured to surround at least a portion of the bias electrode 104. In one configuration, when the substrate support surface of the substrate support assembly 136 is viewed in plan, the bias electrode 104 is surrounded or circumscribed by the edge control electrode 115 and does not directly electrically contact the edge control electrode 115. As seen in Figure 1, the edge control electrode 115 is positioned within the region of the substrate support 105 and biased using a pulse voltage (PV) waveform generator 175. In one configuration, as schematically shown in Figure 1, the edge control electrode 115 is biased by splitting a portion of the signal supplied from the PV waveform generator 175 to the bias electrode 104. In another configuration, the edge control electrode 115 is connected and biased using a different PV waveform generator 175 (not shown in Figure 1) than the one used for the bias electrode 104. In this configuration, the voltage waveform signals supplied from the PV waveform generators 175 can be adjusted separately and therefore have different waveform characteristics, but at the same time, they can be synchronized using a synchronization signal supplied by the system controller 126, or one of the RF waveform generators or PV waveform generators, so that the RF waveform is supplied at the same stage in the synchronized PV waveform pulse supplied by each of the PV waveform generators 175.

[0023] The DC power system 183 includes a DC voltage supply unit 173, a PV waveform generator 175, and a current source 177. The RF power system 189 includes a radio frequency (RF) waveform generator 171, an impedance matching circuit 172, and an RF filter 174. In one example, as shown in Figure 1, a power supply line 163 electrically connects the output of the RF waveform generator 171 to the impedance matching circuit 172, the RF filter 174, and the substrate support base 107. As previously stated, during plasma processing, the DC voltage supply unit 173 supplies a constant chucking voltage, while the RF waveform generator 171 supplies an RF signal to the processing area, and the PV waveform generator 175 establishes a PV waveform at the bias electrode 104. A sufficient amount of RF power is applied to the electrode (e.g., the substrate support base 107) to form a plasma 101 in the processing space 129 of the processing chamber 100, in addition to the RF bias voltage signal, also referred to herein as the RF waveform. In one configuration, the RF waveform has a frequency range between approximately 1 MHz and 200 MHz, for example, between 2 MHz and 40 MHz.

[0024] In some embodiments, the DC power system 183 further includes a filter assembly 178 for electrically isolating one or more components contained within the DC power system 183. Power supply line 160 electrically connects the output of the DC voltage supply unit 173 to the filter assembly 178. Power supply line 161 electrically connects the output of the PV waveform generator 175 to the filter assembly 178. Power supply line 162 connects the output of the current source 177 to the filter assembly 178. In some embodiments, the current source 177 is selectively connected to the bias electrode 104 by using a switch (not shown) located in power supply line 162 so that the current source 177 can supply a desired current to the bias electrode 104 during one or more stages of the voltage waveform generated by the PV waveform generator 175 (e.g., the ion current stage). As seen in Figure 1, the filter assembly 178 includes a number of separate filtering components (i.e., individual filters 178A-178C), each electrically connected to an output node via power supply line 164. In an alternative configuration, the filter assembly 178 includes a single common filter electrically connected to the output node via a power supply line 164. The power supply lines 160-164 include electrical conductors that can be in the form of flexible coaxial cables, insulated high-voltage corona-resistant hookup wires, bare wires, metal rods, electrical connectors, or any combination thereof, connected in series with rigid coaxial cables.

[0025] The system controller 126, also referred to herein as the processing chamber controller, includes a central processing unit (CPU) 133, memory 134, and support circuitry 135. The system controller 126 is used to control the process sequence used to process the substrate 103. The CPU is a general-purpose computer processor configured for use in an industrial environment to control the processing chamber and its associated subprocessors. The memory 134 described herein is generally non-volatile memory and may include random-access memory, read-only memory, hard disk drives, or other suitable forms of local or remote digital storage. The support circuitry 135 is conventionally connected to the CPU 133 and includes caches, clock circuits, input / output subsystems, power supplies, and combinations thereof. Software instructions (programs) and data may be coded and stored within the memory 134 to instruct the processor inside the CPU 133. Software programs (or computer instructions) readable by the CPU 133 in the system controller 126 determine which tasks are executable by the components within the plasma processing chamber assembly 10.

[0026] Typically, a program readable by the CPU 133 in the system controller 126 includes code that, when executed by the CPU 133, performs tasks relating to the plasma processing method described herein. The program may include instructions used to control various hardware and electrical components inside the plasma processing chamber assembly 10 in order to perform various process tasks and various process sequences used to perform the method described herein. In one embodiment, the program includes instructions used to perform one or more of the steps described later in relation to Figures 9 and 10.

[0027] Figure 2 shows two distinct voltage waveforms established on a substrate 103 placed on the substrate receiving surface 105A of the substrate support assembly 136 of the processing chamber by supplying a pulsed voltage waveform to the bias electrode 104 of the processing chamber, according to one or more embodiments. Waveform 225 is an example of an uncompensated pulsed voltage (PV) waveform established on the substrate 103 during plasma processing. Waveform 230 is an example of a compensated pulsed voltage (PV) waveform established on the substrate 103 by applying a negative slope waveform to the bias electrode 104 of the processing chamber during the "ion current phase" portion of the PV waveform cycle using a current source 177. Alternatively, a compensated pulsed voltage (PV) waveform can be established by applying a negative voltage ramp during the ion current phase of a pulsed voltage waveform generated by a PV waveform generator 175.

[0028] In Figure 2, waveforms 225 and 230 include two main stages: the ion current stage and the sheath collapse stage. Both portions of waveforms 225 and 230 (the ion current stage and the sheath collapse stage) can be established alternately and / or separately on the substrate 103 during plasma processing. At the start of the ion current stage, the supply of the negative portion of the PV waveform (e.g., the ion current portion) supplied to the bias electrode 104 by the PV waveform generator 175 causes a voltage drop on the substrate 103, forming a high-voltage sheath above the substrate 103. The high-voltage sheath allows the plasma-generated positive ions in the ion current stage to be accelerated toward the bias substrate, and in the case of an RIE process, the amount and characteristics of the etching process that occurs on the substrate surface during plasma processing can be controlled. In some embodiments, it is desirable that the ion current stage generally includes a region of pulsed voltage waveform where the voltage on the substrate is stable or has minimal fluctuations throughout the stage, as shown in waveform 230 in Figure 2. It should be noted that significant voltage fluctuations established in the substrate during the ion current phase, as indicated by the positive slope of waveform 225, undesirably cause fluctuations in the ion energy distribution (IED), and thus lead to undesirable characteristics of the etched features formed on the substrate during the RIE process.

[0029] Figure 3A is a plot 301 of the forward RF voltage waveform 331 and the intermodulation distortion (IMD) generated RF voltage waveform 326 measured along a transmission line such as transmission line 163 or 166 in Figure 1. In one example, plot 301 was generated from measurements taken at a frequency of 40 MHz ± 400 kHz at a node inside the RF power system 189, due to the supply and interaction between the RF voltage waveform 326 supplied from the RF power system 189 at a frequency of approximately 40.68 MHz and the pulsed voltage waveform supplied from the DC power system 183 (both of which are shown in Figure 3B). Plot 301 includes the envelope 370 of the forward RF voltage waveform 331 and the envelope 376 of the IMD-generated RF voltage waveform 326, all of which are generated by the supply and interaction between the RF bias voltage waveform supplied from the components inside the RF power system 189 and the pulsed voltage waveform supplied from the PV waveform generator of the DC power system 183.

[0030] During processing, the forward RF voltage waveform 331 is applied to the load (e.g., gas) in the processing space 129 of the processing chamber 100 through a transmission line such as the transmission line 165 (Figure 1). If the impedance of the load is not properly matched to the impedance of the source (such as an RF signal generator), a portion of the waveform may be reflected back along the same transmission line. Therefore, to prevent a substantial portion of the waveform from being reflected back along the transmission line, it is necessary to find the matched impedance by adjusting one or more components of the impedance matching circuit 172 and / or by adjusting the frequency of the RF bias waveform supplied by the RF waveform generator 171 to match the impedance of the load to the source during plasma processing. To properly match the impedance, the forward RF voltage and reflected RF voltage are measured at the driving RF frequency at a node inside the RF power system 189. Measurements performed using a conventional RF power supply system employing a conventional RF power supply method reveal that the envelope 370 of the forward RF voltage waveform 331 and the envelope 376 of the IMD-generated RF voltage waveform 326, which is not one of the harmonic frequencies of the driving RF frequency, can be formed. As shown in Figure 3A, the magnitude of the envelope 376 of the IMD-generated RF voltage waveform 326 undesirably changes over time, ranging from a point close to the magnitude of the envelope 370 of the forward RF voltage waveform 331 to a magnitude close to zero RF power.

[0031] Figure 3B shows an example in which the pulse voltage waveform 321 supplied to the bias electrode 104 (Figure 1) and the pulse voltage waveform 322 supplied to the edge control electrode 115 (Figure 1) further include a high-frequency RF voltage waveform 326 (e.g., a 40 MHz RF signal) applied on top of the pulse voltage waveforms 321 and 322. As described above in relation to Figure 2, the pulse voltage waveform includes two main stages: the ion current stage and the sheath collapse stage. Both parts of the pulse voltage waveform (ion current stage and sheath collapse stage) are established on the substrate 103 during plasma processing. As described above, in the RIE process, the etching process mainly takes place during the second stage of the pulse voltage waveform (e.g., the ion current stage). Between both stages of the pulse voltage waveform, fluctuations in the IMD-generated RF power components, as seen in Figure 3A, can cause fluctuations in the process results between substrates and / or chambers, potentially damaging the hardware components inside the chamber and RF power system 189.

[0032] Figure 4 is a chart showing the broadband reflection rates observed in two different conventional plasma processing chambers. The broadband reflection rate is used to measure the amount of reflected power (i.e., the amount of power not supplied to the load) due to IMD and harmonic reflections observed in the plasma processing system versus the amount of forward RF power supplied from the RF source. Curve 405 shows the rate of reflected RF power as a function of the magnitude of the pulse voltage waveform applied to the electrodes in the first processing chamber 460. Curve 410 shows the rate of reflected RF power as a function of the magnitude of the pulse voltage waveform applied to the electrodes in the second processing chamber 470. Here, the first and second processing chambers are configured substantially similarly, and the plotted results were produced by performing the same plasma processing recipe in each processing chamber. As shown in Chart 400, by using a conventional RF power supply system that utilizes a conventional RF power supply method, the rate of RF power supplied to the load varies from chamber to chamber, especially at high pulse waveform voltages. As seen in Figure 4, as the voltage level of the pulse voltage waveform voltage increases, the rate of energy loss relative to IMD increases. This is determined by the magnitude of the voltage established in the substrate during the ion current phase of the pulsed voltage waveform. Both curves 405 and 410 increase to their maximum percentage between approximately 4kV and 8kV. In this example, in a plasma process involving a supply of approximately 1500W of RF power, a chamber pressure of 9mTorr, a pulsed voltage repetition frequency of 1000Hz, and a DC power duty cycle of 59%, the percentage of energy loss to IMD observed within the RF power supply component in the first processing chamber 460 increases from approximately 2kV to a peak of approximately 4.5kV, and then begins to decrease at voltages above 4.5kV. Alternatively, if the same process recipe is run in a second processing chamber 470, the percentage of reflected RF power formed in the second processing chamber 470 increases from approximately 2kV to approximately 6kV, and then decreases at approximately 7kV. In this example, the difference in reflected RF between the first processing chamber 460 and the second processing chamber 470 can be approximately 8 percent at the more desirable higher pulsed waveform voltage levels.

[0033] Figure 5A shows the pulsed RF waveform 501 applied to electrodes placed in the processing chamber. The pulsed RF waveform 501 is a pulse where the RF power is in the first period (T ON ) RF power supply stage 512 supplied to electrodes inside the processing chamber, and RF power during the second period (T OFF The process includes two stages: an RF power "off" stage 517 in which no RF power is supplied to the electrodes. Figure 5B shows a plot of pulsed voltage waveforms and pulsed RF bias voltage signals combined due to the supply of pulsed RF bias voltage signals illustrated in Figure 5A and pulsed voltage waveforms 521 and 522, according to one embodiment. As similarly described in relation to pulsed voltage waveforms 321 and 322 in Figure 3B, in one embodiment, pulsed voltage waveforms 521 and 522 are supplied to one or more electrodes inside the processing chamber, such as bias electrode 104 and edge control electrode 115, respectively.

[0034] As shown in Figures 5A and 5B, the pulsed RF waveform 501 is synchronized with at least one of the pulsed voltage waveforms 521 and 522 and overlaps with at least a portion of the pulsed voltage waveform during the ion current phase. As illustrated, the RF power supply phase 512, and therefore the impedance matching circuit 172, is used to supply RF power from the RF waveform generator 171 only during the stable portion of the supplied pulsed voltage waveform. By supplying RF power during the stable, critical phase in which the majority of etching occurs from the perspective of RIE etching, it is prevented the impedance matching circuit 172 from attempting to find a matching point when the load impedance changes rapidly between and during different phases of the pulsed voltage waveform supply. Pulsing the RF waveform, turning it on during the ion current phase and off during the sheath collapse phase, is thought to improve the performance of the impedance matching circuit by limiting the amount of impedance fluctuation observed by the impedance matching circuit 172 when RF power is supplied to the electrodes in the processing chamber 100. Therefore, if the RF power is not pulsed and is maintained at a constant power as shown in Figure 3B, the measured reflected RF power changes in magnitude between the sheath collapse stage 327 and the ion current stage, as seen in Figure 3A. Thus, in one embodiment of the disclosure provided herein, the pulsed RF waveform 501 includes an RF signal supplied to a substantial portion of the ion current stage of the pulsed voltage waveform. In some embodiments, the duration of the RF power supply stage 512 is configured to extend over the entire length of the ion current stage. In one configuration, the RF power supplied during the RF power supply stage 512 is synchronized by using a system controller 126 so that the RF power is supplied within a region of the pulsed voltage waveform extending between the ion current stage start 332 and the ion current stage end 333. In one configuration, the PV waveform generator and the RF power supply operate in a master-slave relationship, where the master provides a timing signal (e.g., a square wave TTL signal) that triggers the slave to supply a waveform at a desired time.For example, the PV waveform generator is the master and the RF power supply is the slave, so that an RF waveform is supplied between desired portions of the PV waveform. For example, the RF power supply is the master and the PV waveform generator is the slave, so that a PV waveform signal is supplied between desired portions of the RF waveform.

[0035] In some embodiments where the RF waveform is supplied only during the sheath collapse phase, the ion energy distribution function (IEDF) is narrower than when the RF waveform is supplied during the ion current phase. This is because the energy width-expanding effect imparted to the ions in the plasma by the RF waveform supply does not occur while the sheath is being formed (the phase in which plasma-generated ions are accelerated toward the substrate surface). Using this RF waveform supply method, the ion energy can be controlled more precisely during the ion current phase of the waveform pulse.

[0036] In an alternative configuration, the pulsed RF waveform 501 is synchronized with the supply of at least one of the pulsed voltage waveforms 521 and 522 and overlaps with at least a portion of the pulsed voltage waveform during the sheath collapse phase. By pulsed the RF waveform to be on during the sheath collapse phase and off during the ion current phase, the performance of the impedance matching circuit will be improved by limiting the amount of impedance variation observed by the impedance matching circuit 172 when RF power is supplied to the electrodes in the processing chamber 100. Thus, in one embodiment of the disclosure provided herein, the pulsed RF waveform 501 includes an RF signal supplied to a substantial portion of the sheath collapse phase of the pulsed voltage waveform.

[0037] In some embodiments, as shown in Figure 5B, the duration of the RF power supply stage 512 is configured to include only a portion of the duration of the ion current stage. In this case, the RF power supply stage 512 is synchronized by the use of the system controller 126 and starts from the ion current stage 332 with a first time delay (T DELAY) After the passage of [time period], RF power is supplied, reaching the end of the ion current stage 333, and before the next pulse voltage waveform starts to be generated by the PV waveform generator 175, a second time delay (T PD ), that is, the time delay after RF power supply, is made to elapse and stop. The first time delay (T DELAY ) varies from about 1% to about 20% of the total length of the ion current stage of the pulse voltage waveform, and helps reduce the variation of the IMD-generated reflected power that occurs during the supply of the RF waveform due to the natural variation (i.e., "ringing") seen in the pulse voltage waveform during the transition from the sheath collapse stage to the ion current stage. The second time delay (T PD ) varies in the range of about 0% to about 10% of the total length of the ion current stage of the pulse voltage waveform, and can help reduce the variation of the IMD-generated reflected power due to the variation in the start of the transition from the ion current stage to the sheath collapse stage. In one example, the second time delay (T PD ) is between 0.1% and 10% of the total length of the ion current stage of the pulse voltage waveform. In some embodiments, the ion current stage occupies between about 30% and about 95% of the total period (T TP ) of the pulse voltage waveform, and typically exceeds about 80% of the total period of the pulse voltage waveform. The pulse voltage waveform can include a series of voltage pulses supplied at a repetition frequency in the range of 100 kHz or more, such as 200 kHz or more, or 400 kHz or more, or between 100 kHz and 500 kHz. In one example, the total period (T TP ) of the pulse voltage waveform is about 2.5 microseconds (μs). Regardless of whether the RF waveform is supplied during the sheath collapse stage or the ion current stage, the IMD power returning to the generator can be significantly reduced, for example, by more than 5 times, allowing the generator to reach a higher supply power before loading the output amplifier component inside the generator.

[0038] Figure 6 illustrates a method for synchronizing PV waveforms and RF waveforms in a plasma processing chamber, such as the processing chamber 100 in Figure 1. Method 600 includes processing a substrate by applying a PV waveform to an electrode, applying a pulsed RF waveform to an electrode, and synchronizing the pulsed RF waveform with the PV waveform.

[0039] In step 602, method 600 includes applying a PV waveform to an electrode such as a bias electrode 104. The PV waveform may include a series of voltage pulses. Each pulse in the series includes a first stage and a second stage. The first stage includes a sheath collapse stage, and the second stage includes an ion current stage, which are established in the substrate during processing. As shown in Figure 5B and described above, the sheath collapse stage includes a large capacitance measured in the substrate, while the ion current stage includes a small capacitance measured in the substrate.

[0040] In step 604, method 600 includes generating plasma within the processing space of a processing chamber. In some embodiments, a pulsed RF waveform is used to ignite one or more gas species flowing within the processing space 129 of the processing chamber 100 to form plasma on a substrate placed on the support surface of a substrate support by supplying an RF signal to one or more electrodes inside the processing chamber 100. In some cases, the RF waveform 501 includes an RF signal having a frequency between 1 MHz and 60 MHz. In one example, the RF waveform 501 includes an RF signal having a frequency of 40 MHz. Steps 602 and 604 can be completed substantially simultaneously or in any desired order.

[0041] In step 606, method 600 includes synchronizing a pulsed RF waveform with a PV waveform. As described above, the pulsed RF waveform is pulsed such that the RF power supply stage 512 of the pulsed RF waveform is synchronized with at least one stage of the PV waveform. In one embodiment, to perform the task of synchronizing a pulsed RF waveform with a pulsed voltage waveform, the system controller 126 supplies one or more control signals to the RF waveform generator 171 and the PV waveform generator 175 so that the supply timing of each of the waveforms generated by these components can be synchronized, such as as similarly described above in relation to Figures 5A-5B. Alternatively, in another embodiment, the RF waveform generator 171 functions as a master device and thus sends control signals to the PV waveform generator 175 so that the supply timing of each waveform generated by these components can be synchronized. In another embodiment, the PV waveform generator 175 functions as a master device and thus sends control signals to the RF waveform generator 171 so that the supply timing of each waveform generated by these components can be synchronized.

[0042] The steps performed in method 600 may be carried out for a certain period of time so that the desired plasma process can be performed on a substrate placed inside the plasma processing chamber.

[0043] While the above description applies to embodiments of the present disclosure, other embodiments and further embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the following claims.

Claims

1. A method for plasma processing, Applying a pulsed voltage waveform to one or more electrodes arranged within a substrate support, wherein the pulsed voltage waveform includes a series of voltage pulses each comprising a first stage and a second stage. In order to generate plasma within the processing area of ​​the processing chamber, a pulsed radio frequency (RF) waveform is applied to one or more electrodes, By synchronizing the pulse RF waveform with each pulse of the pulse voltage waveform, the RF waveform of the pulse radio frequency (RF) waveform is supplied only for at least a portion of the second stage of each pulse of the pulse voltage waveform. Methods that include...

2. The method according to claim 1, wherein the first step includes a sheath collapse step and the second step includes an ion current step.

3. The method according to claim 1, wherein the series of voltage pulses are supplied at a frequency of 100 kHz or higher.

4. The method according to claim 3, wherein the pulsed RF waveform includes a series of RF pulses supplied at a frequency equal to the frequency of the series of voltage pulses.

5. Applying the pulse voltage waveform to one or more electrodes Applying a first pulse voltage waveform to a first electrode disposed within the substrate support, Applying a second pulse voltage waveform to a second electrode arranged on the substrate support, wherein the second pulse voltage waveform is such that the first pulse voltage waveform and the second pulse voltage waveform each have a first stage and a second stage, The application of the first and second stages of the first and second pulse voltage waveforms to the first and second electrodes, respectively, is synchronized. It further includes, The method according to claim 1, further comprising synchronizing the pulse RF waveform with each pulse of the pulse voltage waveform, synchronizing the pulse RF waveform with each pulse of the first pulse voltage waveform, and synchronizing the pulse RF waveform with each pulse of the second pulse voltage waveform.

6. The method according to claim 5, wherein the first electrode is surrounded by the second electrode.

7. The method according to claim 1, wherein the RF waveform of the pulse RF waveform is supplied after a first time delay has elapsed, and the first time delay begins at the end of the first stage of each pulse of the pulse voltage waveform.

8. The method according to claim 7, wherein the first time delay has a length between 1% and 20% of the total length of the second stage of the pulse voltage waveform.

9. The method according to claim 1, wherein the first stage of each pulse of the pulse voltage waveform begins after a second time delay has elapsed, and the start of the second time delay begins at the end of the period during which the RF waveform of the pulse radio frequency (RF) waveform is supplied during at least a portion of the second stage.

10. The method according to claim 9, wherein the second time delay has a length between 0.1% and 10% of the total length of the second stage of the pulse voltage waveform.

11. The method according to claim 1, wherein the second step includes a sheath collapse step and the first step includes an ion current step.

12. A plasma processing system, A pulse voltage waveform generator connected to the first electrode, A radio frequency waveform generator connected to a second electrode, configured to generate plasma within the processing space of the plasma processing system, An impedance matching circuit connected between the radio frequency waveform generator and the second electrode, A controller having a processor configured to execute computer-readable instructions stored in memory, The computer-readable instructions are provided to the system, The method involves applying a pulse voltage waveform to the first electrode using the pulse voltage waveform generator, wherein the pulse voltage waveform includes a series of voltage pulses each comprising a first stage and a second stage. In order to generate plasma within the processing area of ​​the processing chamber, a pulsed radio frequency waveform is applied to the second electrode by using the radio frequency waveform generator, By synchronizing the pulsed radio frequency (RF) waveform with each pulse of the pulsed voltage waveform, the RF waveform of the pulsed RF waveform is supplied only for at least a portion of the second stage of each pulse of the pulsed voltage waveform. A plasma processing system that performs this operation.

13. The plasma processing system according to claim 12, wherein the first stage of the pulse voltage waveform includes a sheath collapse stage, and the second stage of the pulse voltage waveform includes an ion current stage.

14. The plasma processing system according to claim 12, wherein the series of voltage pulses are supplied at a frequency of 100 kHz or higher.

15. The plasma processing system according to claim 14, wherein the pulsed RF waveform includes a series of RF pulses supplied at a frequency equal to the frequency of the series of voltage pulses.

16. The plasma processing system according to claim 12, wherein the first electrode and the second electrode are arranged within a substrate support.

17. The plasma processing system according to claim 16, wherein the first electrode is surrounded by the second electrode.

18. The plasma processing system according to claim 12, wherein the RF waveform of the pulse RF waveform is executed after a first time delay has elapsed, and the first time delay begins at the end of the first stage of each pulse of the pulse voltage waveform.

19. The plasma processing system according to claim 18, wherein the first time delay has a length between 1% and 20% of the total length of the second stage of the pulse voltage waveform.

20. The plasma processing system according to claim 12, wherein the second stage of the pulse voltage waveform includes a sheath collapse stage, and the first stage of the pulse voltage waveform includes an ion current stage.

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