Solid-state imaging device, method for driving a solid-state imaging device, and electronic equipment

Abstract

This invention provides a solid-state imaging device, a driving method for a solid-state imaging device, and electronic equipment that enable sufficient high dynamic range and image quality, and that offer an AD conversion unit with a small circuit area and low power consumption for high dynamic range imaging. [Solution] The pixel signal processing unit 400 includes an AD conversion unit 430 capable of performing AD conversion processing to convert the first conversion gain signal and the second conversion gain signal of the input pixel signal from an analog signal to a digital signal, and a multiple bit memory (SRAM) unit 440. The AD conversion unit 430 determines which of the first conversion gain signal and the second conversion gain signal is required for image generation, and selects information to be stored in the memory unit 440 based on the determination information.

Description

Technical Field

[0001] The present invention relates to a solid-state imaging device, a method for driving the solid-state imaging device, and an electronic device.

Background Art

[0002] As a solid-state imaging device (image sensor) using a photoelectric conversion element that detects light and generates electric charges, a CMOS (Complementary Metal Oxide Semiconductor) image sensor has been put into practical use. The CMOS image sensor is widely applied as a part of various electronic devices such as digital cameras, video cameras, surveillance cameras, medical endoscopes, personal computers (PCs), and mobile devices such as mobile phones.

[0003] The CMOS image sensor has a FD amplifier having a photodiode (photoelectric conversion element) and a floating diffusion layer (FD: Floating Diffusion) for each pixel, and its readout is mainly of a column parallel output type in which a certain row in the pixel array is selected and read out simultaneously in the column direction.

[0004] By way of example, as a pixel configuration of a solid-state imaging device (CMOS image sensor), a basic pixel having a 4-transistor (4Tr) configuration having one transfer transistor as a transfer element, one reset transistor as a reset element, one source follower transistor as a source follower element, and one selection transistor as a selection element for one photodiode (photoelectric conversion element) can be exemplified.

[0005] [[ID=Y5]] The transfer transistor is selected and turned on during a predetermined transfer period, and transfers the charges (electrons) photoelectrically converted and accumulated in the photodiode to the floating diffusion FD. The reset transistor is selected to conduct during a predetermined reset period, resetting the floating diffusion diode (FD) to the potential of the power line. The selection transistor is selected and becomes conductive during a readout scan.

[0006] For example, during the read scan period, after the floating diffusion FD is reset to, for example, the potential of the power line (reference potential) during the reset period, the charge of the floating diffusion FD is converted into a voltage signal with a gain corresponding to the FD capacitance and output to the vertical signal line as a reference level read reset signal (reference level signal) Vrst. Next, during a predetermined transfer period, the charge (electrons) that has been photoelectrically converted and stored by the photodiode is transferred to the floating diffusion FD. Then, the charge in the floating diffusion FD is converted into a voltage signal with a gain corresponding to the FD capacitance and output to the vertical signal line as a signal level readout signal (signal level signal) Vsig. The pixel output signal is processed as a difference signal (Vsig-Vrst) using CDS (Correlated Double Sampling) in the column readout circuit.

[0007] Thus, a typical pixel readout signal (hereinafter sometimes referred to as a pixel signal) PS is formed by one reference level readout reset signal Vrst and one signal level readout signal Vsig.

[0008] Incidentally, various methods have been proposed to realize high-quality solid-state imaging devices (CMOS image sensors) with high dynamic range (HDR) in order to improve performance.

[0009] One approach to achieving a high dynamic range is to use a Lateral Overflow Integration Capacitor (LOFIC) configuration (see, for example, Patent Document 1). LOFIC pixels have the basic configuration described above, plus an accumulation capacitor and an accumulation transistor, which store the supersaturated charge overflowing from the photodiode in the accumulation capacitor instead of discarding it during the same exposure time.

[0010] This LOFIC pixel can have two types of conversion gain: one due to the floating diffusion capacitance Cfd1 (high gain side: proportional to 1 / Cfd1), and another due to the LOFIC capacitance Clofic, which is the floating diffusion capacitance Cfd1 plus the storage capacitor C2 (low gain side: proportional to 1 / (Cfd1+Clofic)).

[0011] LOFIC is used to realize high dynamic range image sensors, utilizing low conversion gain (LCG) signals and high conversion gain (HCG) signals respectively to achieve large full-well capacitance and low dark noise.

[0012] Furthermore, in LOFIC, in LCG mode, the storage capacitance CS is large, and the Vdrop due to charge injection and input clock feedthrough is small, resulting in a large signal amplitude and desirable attenuation of the pixel output signal. Furthermore, in LOFIC, in HCG mode, the storage capacitance Cfd is small and Vdrop is large, resulting in a small signal amplitude and requiring a gain of 1 or more. [Prior art documents] [Patent Documents]

[0013] [Patent Document 1] Japanese Patent Publication No. 2005-328493 [Patent Document 2] Japanese Patent Publication No. 2020-115603 [Patent Document 3] Japanese Patent Publication No. 2023-001516 [Overview of the project] [Problems that the invention aims to solve]

[0014] However, in LOFIC, both high-conversion-gain (HCG) and low-conversion-gain (LCG) signals are converted digitally and stored in SRAM, resulting in high power consumption and a large footprint. Therefore, LOFIC image sensors require low-power, small-area analog-to-digital converters (ADCs).

[0015] For example, Patent Document 2 proposes a specific circuit configuration for a pixel signal processing unit in the readout circuit of a solid-state imaging device, which, although not targeting LOFIC, can eliminate the noise gap at the connection point between low-conversion-gain data and high-conversion-gain data, suppress increases in power consumption and circuit area, and achieve a high dynamic range.

[0016] Incidentally, in CMOS image sensors with a LOFIC structure, a dual readout circuit is required because the signal directions of the high conversion gain (HCG) signal and the low conversion gain (LCG) signal, i.e., the level transition directions, are opposite to each other. However, while the pixel signal processing unit in the readout circuit described in Patent Document 2 above can read both HCG and LCG signals generated from single-exposure HDR (SEHDR) pixels whose signal directions are the same, it is difficult to apply it directly to CMOS image sensors with a LOFIC structure.

[0017] Furthermore, in order to realize a dual readout circuit applicable to CMOS image sensors with an LOFIC structure, a readout circuit is needed that can process both LCG and HCG signals with minimal circuit overhead and achieve low power consumption, in order to reduce chip costs.

[0018] In light of these circumstances, for example, Patent Document 3 proposes a CMOS image sensor (solid-state imaging device) that is capable of reading out signals with different conversion gains and signal directions, while also suppressing increases in power consumption and circuit area, achieving a high dynamic range, and ultimately achieving high image quality.

[0019] In a CMOS image sensor, as described above, a column parallel circuit is often used. In this column parallel circuit, in order to mount many column circuits in a small area, a MOS capacitor having a large unit capacitance is recommended. However, the capacitance of a MOS capacitor depends on voltage, and in a normal CMOS process, non-linearity of a column amplifier (column amplifier) occurs. For example, the above-described LOFIC readout circuit has non-linear input / output characteristics in the amplifier. Therefore, in order to give the circuit linear input / output characteristics, it is necessary to use a linear capacitor by an additional process that is costly.

[0020] The circuit described in Patent Document 3 above can read both the HCG signal and the LCG signal generated from the LOFIC pixel. However, since this circuit uses a MOS capacitor without an additional process for cost reduction, it still shows non-linear input / output characteristics. Therefore, in the circuit described in Patent Document 3 above, it is difficult to sufficiently realize suppression of an increase in power consumption, an increase in circuit area, reduction of chip cost, a high dynamic range, and high image quality, and it is difficult to provide an AD conversion unit with a small circuit area and low power consumption for high dynamic range imaging.

[0021] The present invention can read signals having different conversion gains and different signal directions from each other, can improve linearity of input / output characteristics, can suppress an increase in power consumption and an increase in circuit area, can reduce chip cost, and can sufficiently realize a high dynamic range and thus high image quality, and an object thereof is to provide a solid-state imaging device, a driving method of the solid-state imaging device, and an electronic device that can provide an AD conversion unit with a small circuit area and low power consumption for high dynamic range imaging.

Means for Solving the Problem

[0022] A solid-state imaging device according to a first aspect of the present invention includes a readout pixel that performs photoelectric conversion and reads out as a pixel signal a first conversion gain signal and a second conversion gain signal, the first and second conversion gain signals having opposite signal directions corresponding to at least two conversion gains; and a pixel signal processing unit that processes the pixel signal read out from the readout pixel, wherein the pixel signal processing unit includes an analog-to-digital (AD) conversion unit capable of performing analog-to-digital (AD) conversion processing to convert the first conversion gain signal and the second conversion gain signal of the input pixel signal from an analog signal to a digital signal; and a memory unit capable of storing the digital signal converted by the AD conversion unit, wherein the AD conversion unit determines which of the first conversion gain signal and the second conversion gain signal is required for image generation, and selects information to be stored in the memory unit based on the determination information.

[0023] A second aspect of the present invention is a method for manufacturing a solid-state imaging device, comprising: a readout pixel that performs photoelectric conversion and reads out as a pixel signal a first conversion gain signal and a second conversion gain signal whose signal directions are opposite to those of at least two conversion gains; a pixel signal processing unit that processes the pixel signal read out from the readout pixel, wherein the pixel signal processing unit includes an AD conversion unit capable of performing analog-to-digital (AD) conversion processing to convert the first conversion gain signal and the second conversion gain signal of the input pixel signal from an analog signal to a digital signal; and a memory unit capable of storing the digital signal converted by the AD conversion unit, wherein the AD conversion unit determines which of the first conversion gain signal and the second conversion gain signal is required for image generation, and selects information to be stored in the memory unit based on the determination information.

[0024] An electronic device according to a third aspect of the present invention comprises a solid-state imaging device and an optical system for forming an image of a subject on the solid-state imaging device, wherein the solid-state imaging device includes a readout pixel capable of performing photoelectric conversion and reading out a first conversion gain signal and a second conversion gain signal as pixel signals, wherein the signal directions corresponding to at least two conversion gains are in opposite directions, and a pixel signal processing unit for processing the pixel signals read out from the readout pixel, wherein the pixel signal processing unit includes an analog-to-digital (AD) conversion unit capable of performing analog-to-digital (AD) conversion processing to convert the first conversion gain signal and the second conversion gain signal of the input pixel signal from an analog signal to a digital signal, and a memory unit capable of storing the digital signal converted by the AD conversion unit, wherein the AD conversion unit determines which of the first conversion gain signal and the second conversion gain signal is required for image generation, and selects information to be stored in the memory unit based on the determination information. [Effects of the Invention]

[0025] According to the present invention, it is possible to read out signals with different conversion gains and different signal directions, improve the linearity of input / output characteristics, suppress increases in power consumption and circuit area, reduce chip costs, and moreover, fully realize high dynamic range and, consequently, high image quality. This makes it possible to provide an AD conversion unit with a small circuit area and low power consumption for high dynamic range imaging. [Brief explanation of the drawing]

[0026] [Figure 1] This is a block diagram showing an example configuration of a solid-state imaging device according to the first embodiment of the present invention. [Figure 2] This is a circuit diagram showing an example of the configuration of a readout pixel in a solid-state imaging device according to the first embodiment of the present invention. [Figure 3] This is a timing chart showing an example of the readout sequence of a readout pixel in a solid-state imaging device according to the first embodiment of the present invention. [Figure 4]This is a circuit diagram showing an example of the configuration of a pixel signal processing unit according to the first embodiment of the present invention. [Figure 5] This timing chart shows an example of a readout sequence including signal determination and memory access processing for readout pixels and pixel signal processing units in a solid-state imaging device according to the first embodiment of the present invention. [Figure 6] This is a circuit diagram showing an example of the configuration of a key part in which a sample-and-hold circuit is connected to a comparator that forms the key part of the pixel signal processing unit according to the second embodiment of the present invention. [Figure 7] This is a circuit diagram showing an example configuration of a pixel signal processing unit according to a third embodiment of the present invention. [Figure 8] This is a circuit diagram showing an example of the configuration of the logic circuit section in the pixel signal processing unit according to the fourth embodiment of the present invention. [Figure 9] This figure shows an input / output correspondence table mainly for the logic circuit section of the pixel signal processing unit according to the fourth embodiment of the present invention. [Figure 10] This is a timing chart showing an example of the readout sequence of a readout pixel and a pixel signal processing unit in a solid-state imaging device according to a fourth embodiment of the present invention. [Figure 11] This figure shows the operation sequence and potential transitions for illustrating the operation in the readout process of the HCG signal and LCG signal in the conversion gain readout mode of a solid-state imaging device according to a fifth embodiment of the present invention. [Figure 12] This figure shows the optical response characteristics in the readout process in which the MCG signal is added to the HCG signal and LCG signal in the conversion gain readout mode of the solid-state imaging device according to the sixth embodiment of the present invention. [Figure 13] This is a circuit diagram showing an example of the configuration of the logic circuit section in the pixel signal processing unit according to the seventh embodiment of the present invention. [Figure 14] This is a timing chart showing an example of the readout sequence of a readout pixel and a pixel signal processing unit in a solid-state imaging device according to the seventh embodiment of the present invention. [Figure 15]This figure shows the optical response characteristics in the readout process of the HCG signal or MCG signal and the LCG signal in the conversion gain readout mode of a solid-state imaging device according to the eighth embodiment of the present invention. [Figure 16] This is a circuit diagram showing an example configuration of a pixel signal processing unit according to the ninth embodiment of the present invention. [Figure 17] This is a circuit diagram showing an example configuration of a pixel signal processing unit according to the tenth embodiment of the present invention. [Figure 18] This is a circuit diagram showing an example configuration of a pixel signal processing unit according to the 11th embodiment of the present invention. [Figure 19] This figure shows the optical response characteristics in the readout process of the HCG signal, MCG signal, and LCG signal in the conversion gain readout mode of a solid-state imaging device according to the twelfth embodiment of the present invention. [Figure 20] This figure shows the optical response characteristics in the readout process in which the MCG signal is added to the HCG signal and LCG signal in the conversion gain readout mode of the solid-state imaging device according to the 13th embodiment of the present invention. [Figure 21] This figure shows an example of the configuration of an electronic device to which a solid-state imaging device according to an embodiment of the present invention is applied. [Modes for carrying out the invention]

[0027] The embodiments of the present invention will be described below with reference to the drawings.

[0028] (First embodiment) Figure 1 is a block diagram showing an example configuration of a solid-state imaging device according to the first embodiment of the present invention. Figure 2 is a circuit diagram showing an example of the configuration of a readout pixel in a solid-state imaging device according to the first embodiment of the present invention. Figures 3(A) to 3(E) are timing charts showing an example of the readout sequence of a readout pixel in a solid-state imaging device according to the first embodiment of the present invention.

[0029] In this embodiment, the solid-state imaging device 10 is configured, for example, by a CMOS image sensor.

[0030] As shown in Figure 1, the solid-state imaging device 10 mainly comprises a pixel unit 20 as an imaging unit, a vertical scanning circuit (row scanning circuit) 30, a readout circuit (column readout circuit) 40 including a pixel signal processing unit 400, a horizontal scanning circuit (column scanning circuit) 50, and a timing control circuit 60. Of these components, for example, the vertical scanning circuit 30, the readout circuit 40, the horizontal scanning circuit 50, and the timing control circuit 60 constitute the pixel signal readout unit 70.

[0031] This solid-state imaging device 10 includes a readout pixel 200 that performs photoelectric conversion and can read out a first conversion gain signal and a second conversion gain signal, the first and second of which have opposite signal directions corresponding to at least two conversion gains, as pixel signals, and a pixel signal processing unit 400 that processes the pixel signals read out from the readout pixel 200. The pixel signal processing unit 400 includes an AD conversion unit 430 capable of performing analog-to-digital (AD) conversion processing to convert the first conversion gain signal and the second conversion gain signal of the input pixel signal from an analog signal to a digital signal, and a multiple-bit memory (SRAM) unit 440 capable of storing the digital signal converted by the AD conversion unit 430. The AD conversion unit 430 determines which of the first conversion gain signal and the second conversion gain signal is required for image generation, and selects information to be stored in the memory unit 440 based on the determination information.

[0032] The solid-state imaging device 10 according to this first embodiment is configured to provide an ADC (analog-to-digital converter) for high dynamic range imaging that has a small circuit area and low power consumption. In the solid-state imaging device 10 according to this first embodiment, the ADC (AD conversion unit) has a function to determine whether a first conversion gain signal (e.g., high conversion gain: HCG) or a second conversion gain signal (e.g., low conversion gain: LCG) is required for image generation. Furthermore, in the solid-state imaging device 10 according to this first embodiment, when the ADC (AD conversion unit) selects HCG for image generation, the ADC enters standby mode, and the LOFIC is configured to save power consumed while reading out the LCG signal from the pixel. Furthermore, the SRAM within the ADC (AD conversion unit) holds either the HCG signal or the LCG signal necessary for image generation, and its bit size is reduced by approximately half, thereby enabling a reduction in circuit area.

[0033] In this first embodiment, the readout pixels 200 arranged in a matrix in the pixel section 20 basically have the configuration shown in Figure 2. In other words, the readout pixel 200 is composed of a floating diffusion layer (FD) 11 that holds the transferred charge in order to read it out as a voltage signal, a photodiode PD 11 as a photoelectric conversion element that accumulates charge according to the amount of incident light during the exposure period PEXP, a transfer transistor TG 11-Tr as a transfer element that is kept in a non-conductive state during the exposure period PEXP and in a conductive state during the transfer period to transfer the charge accumulated in the photodiode PD 11 as a photoelectric conversion element to the floating diffusion layer FD 11, and a reset transistor RST 11-Tr as a reset element that can perform a reset process to discharge the accumulated charge of the floating diffusion layer FD 11.

[0034] Furthermore, the readout pixel 200 is configured to include a storage capacitor CS11, which is a storage capacitance element capable of accumulating overflow charge spilling from the photodiode PD11, which is a photoelectric conversion element, and a storage transistor SG11-Tr, which is a storage connection element that selectively connects the floating diffusion FD11 and the storage capacitor CS11 as a storage capacitance element.

[0035] Furthermore, the readout pixel 200 has an overflow path OVFP that allows the charge overflowing from the photodiode PD11, which acts as a photoelectric conversion element, and overflowing into the floating diffusion FD11 through the transfer transistor TG11-Tr, to overflow in the direction of the formation region of the storage capacitor CS11, which acts as a storage capacitance element. A storage capacitor CS11 is connected between the storage node NDS11 formed in a predetermined region of the overflow path OVFP and the reference potential VSS, a storage transistor SG11-Tr is connected between the storage node NDS11 and the floating diffusion FD11, and a reset transistor RST11-Tr is connected between the power supply potential VAAPIX and the storage node NDS11. Furthermore, the readout pixel 200 is configured to include a source follower transistor SF11-Tr, which acts as a source follower element that outputs a voltage signal converted by the floating diffusion FD11, and a selection transistor SEL11-Tr, which acts as a selection element.

[0036] The readout pixel 200 according to this first embodiment can switch the conversion gain between a first conversion gain determined by the first capacitance (e.g., high conversion gain: HCG) or a second conversion gain determined by the second capacitance (e.g., low conversion gain: LCG) by selectively connecting the floating diffusion FD11 and the storage capacitor CS11 as a storage capacitance element through the storage transistor SG11-Tr as a storage connection element under the control of the readout unit 70, thereby changing the capacitance of the floating diffusion FD11 to a first capacitance or a second capacitance.

[0037] Thus, the solid-state imaging device 10 is configured to perform, under the control of the readout unit 70, a first conversion gain mode readout, in which the pixel signal is read out with a first conversion gain (high conversion gain: HCG) corresponding to the first capacitance, and a second conversion gain mode readout, in which the pixel signal is read out with a second conversion gain (low conversion gain: LCG) corresponding to the second capacitance (different from the first capacitance), during a specified dual conversion gain readout mode period, as shown in Figure 3.

[0038] The readout pixel 200 is equipped with a structure called a lateral overflow integration capacitor (LOFIC), and under the control of the readout unit 70, it operates in a double sampling readout mode (LOFIC mode) using a second conversion gain related to the stored charge and overflow charge of the photodiode PD11, which is a photoelectric conversion element, under high-illumination conditions.

[0039] In this first embodiment, the readout pixel 200 performs dual conversion gain signal readout, which reads out the pixel signal with a first conversion gain (e.g., high conversion gain: HCG) corresponding to a first capacitance, and a second conversion gain signal readout, which reads out the pixel signal with a second conversion gain (e.g., low conversion gain: LCG) corresponding to a second capacitance (different from the first capacitance). In this first embodiment, as shown in Figure 3, the readout process for the readout pixel 200 is as follows: first, in the first conversion gain signal readout mode, the first readout reset signal HCGRST is read out, and then the first readout luminance signal HCGSIG is read out. Next, in the second conversion gain signal readout mode, the second readout luminance signal LCGSIG is read out, followed by the second readout reset signal LCGRST.

[0040] Thus, the first conversion gain signal (HCGRST, HCGSIG) and the second conversion gain signal (LCGSIG, LCGRST) read out from the readout pixel 200 as pixel signals PIXOUT are formed as signals with opposite signal directions (level transition directions).

[0041] (Specific circuit configuration of pixel 200) Here, we will explain the specific circuit configuration of the readout pixel 200 in Figure 2. This section describes an example configuration of a readout pixel 200 with an LOFIC structure.

[0042] The pixel section 20 consists of readout pixels 200, each containing a photodiode (photoelectric conversion element) and an in-pixel amplifier, arranged in a two-dimensional matrix with N rows and M columns.

[0043] As shown in Figure 2, for example, the readout pixel 200 is composed of a photodiode PD11 as a photoelectric conversion element, a transfer transistor TG11-Tr as a transfer element, a reset transistor RST11-Tr as a reset element, a source follower transistor SF11-Tr as a source follower element, a selection transistor SEL11-Tr as a selection element, a storage transistor SG11-Tr as a storage connection element, a storage capacitor CS11 as a storage capacitance element, a floating diffusion FD11, and a storage node NDS11 connected to the storage capacitor CS11.

[0044] Furthermore, in the readout pixel 200, the capacitive CFD of the floating diffusion FD11 is formed to have a very small capacitance for low noise. The capacitance CS1 of the storage capacitor CS11 is set to a very large capacitance (electrostatic capacitance) for high FWC (Full Well Capacity). The capacitance CS1 of the storage capacitor CS11 is greater than the capacitance CFD of the floating diffusion capacitor FD11. Furthermore, the capacitive CFD of the floating diffusion capacitor FD11 is mainly used for high conversion gain, while the capacitance CS1 of the storage capacitor CS11 is also used for low conversion gain.

[0045] The photodiode PD11 generates and stores a signal charge (in this case, electrons) in an amount corresponding to the amount of incident light. The following explanation assumes that the signal charge is an electron and each transistor is an n-type transistor; however, it is also acceptable for the signal charge to be a hole or for each transistor to be a p-type transistor.

[0046] In each readout pixel 200, an embedded photodiode (PPD) is used as the photodiode (PD). Because interface states exist on the substrate surface where photodiodes (PDs) are formed due to defects such as dangling bonds, a large amount of electric charge (dark current) is generated by thermal energy, which may prevent the correct signal from being read. In embedded photodiodes (PPDs), the charge storage portion of the photodiode (PD) is embedded within the substrate, which reduces the interference of dark current with the signal.

[0047] The transfer transistor TG11-Tr is connected between the photodiode PD11 and the floating diffusion FD11 and is controlled via the control signal TG. The transfer transistor TG11-Tr is selected to conduct when the control signal TG is at a high level (H), and transfers the charge (electrons) that has been photoelectrically converted by the photodiode PD11 and stored in the storage node to the floating diffusion FD11.

[0048] In the example shown in Figure 2, the reset transistor RST11-Tr is connected between the power supply potential VAAPIX and the storage node NDS11 and is controlled via the control signal RST. The reset transistor RST11-Tr is selected to conduct when the control signal RST is at a high level, and when the storage transistor SG11-Tr is held in the conduction state, it resets the floating diffusion FD11 (and storage capacitor CS11) to the power supply potential VAAPIX.

[0049] Furthermore, in this first embodiment, the reset transistor RST11-Tr, the storage transistor SG11-Tr, and the transfer transistor TG11-Tr are kept in a conductive state, thereby resetting the floating diffusion FD11 and the photodiode PD11. Furthermore, in this first embodiment, the reset transistor RST11-Tr and the storage transistor SG11-Tr are kept in a conductive state, and the floating diffusion FD11 and the storage capacitor CS11 are reset.

[0050] The storage transistor SG11-Tr is connected between the floating diffusion FD11 (and reset transistor RST11-Tr) and the storage capacitor CS11 via the storage node NDS11. The storage transistor SG11-Tr is controlled by a control signal SG applied to its gate via a control line. The storage transistor SG11-Tr is selected to conduct when the control signal SG is at a high level, connecting the floating diffusion transistor FD11 (and the reset transistor RST11-Tr) and the storage capacitor CS11. In this first embodiment, as described above, the reset transistor RST11-Tr and the storage transistor SG11-Tr are kept in a conductive state, and the floating diffusion FD11 and the storage capacitor CS11 are reset.

[0051] In this first embodiment, the overflow path OVFP is formed as a path that can transfer the overflow charge of the photodiode PD11 to the storage capacitor CS11 via the floating diffusion FD11, storage transistor SG11-Tr, and storage node NDS11, as shown in Figure 2 (solid arrow), and is also formed as a path that can transfer the overflow charge of the storage capacitor CS11 to the power supply potential VAAPIX via the storage node NDS11 and reset transistor RST11-Tr (dashed arrow).

[0052] The source follower transistor SF11-Tr and the selector transistor SEL11-Tr are connected in series between the power supply potential VAAPIX and the vertical signal line LSGN11. A floating diffusion transistor FD11 is connected to the gate of the source follower transistor SF11-Tr, and the selector transistor SEL11-Tr is controlled by a control signal SEL applied to its gate via a control line. The selection transistor SEL11-Tr is selected and becomes conductive during the selection period when the control signal SEL is at a high level. As a result, the source follower transistor SF11-Tr outputs the read voltage signals (VRST1, VSIG1) of the column output, which have been converted into voltage signals by the floating diffusion transistor FD11, to the vertical signal line LSGN11.

[0053] The pixel section 20 has N rows x M columns of readout pixels 200, so there are N control lines and M vertical signal lines. In Figure 1, each control line is represented as a single row scan control line.

[0054] The vertical scanning circuit 30 drives pixels in the shutter row and readout row through row scanning control lines in accordance with the control of the timing control circuit 60. Furthermore, the vertical scanning circuit 30 outputs row selection signals for the row addresses of the read row for reading signals and the shutter row for resetting the charge accumulated in the photodiode PD11, according to the address signal.

[0055] The readout circuit 40 includes a pixel signal processing unit 400 as a plurality of column signal processing circuits (not shown) arranged to correspond to each column output of the pixel unit 20, and may be configured to enable column parallel processing with the plurality of column signal processing circuits. In the readout circuit 40, the pixel signal processing unit 400 has the function of inverting one of the conversion gain signals, specifically the first conversion gain signal, which is formed as a signal with the signal direction, in other words, the level transition direction, and read out from the readout pixel 200 as a pixel signal PIXOUT, specifically the first conversion gain signal. Furthermore, the pixel signal processing unit 400 has an analog-to-digital (AD) conversion function that converts the first conversion gain signal and the second conversion gain signal from analog signals to digital signals after aligning the signal direction (level transition direction). A detailed example of the specific circuit configuration of the pixel signal processing unit will be described later.

[0056] The horizontal scanning circuit 50 scans the signals processed by the multiple pixel signal processing units 400 of the readout circuit 40, transfers them horizontally, and outputs them to a signal processing circuit (not shown).

[0057] The timing control circuit 60 generates timing signals necessary for signal processing of the pixel unit 20, vertical scanning circuit 30, readout circuit 40, horizontal scanning circuit 50, etc.

[0058] When the dual conversion gain readout mode MDCG is specified, the readout unit 70 performs the first conversion gain reset readout process HCGRRD, the first conversion gain readout process HCGSRD, the second conversion gain readout process LCGSRD, and the second conversion gain reset readout process LCGRRD.

[0059] In this first embodiment, after starting the exposure period PEXP, the readout unit 70 performs readout processing of the dual conversion gain readout mode MDCG as readout mode processing.

[0060] For example, as shown in Figure 2, the readout unit 70 holds the reset transistor RST11-Tr, the storage transistor SG11-Tr, and the transfer transistor TG11-Tr in a conductive state for a predetermined period of time to reset the photodiode PD11, the floating diffusion FD11, and the storage capacitor CS11 to perform shutter processing, and then deconducts the transfer transistor TG11-Tr to start the exposure period PEXP. Then, after starting the exposure period PEXP, the readout unit 70 sequentially performs the following as dual conversion gain readout mode MDCG processing: first conversion gain reset readout process HCGRRD, first conversion gain readout process HCGSRD, second conversion gain readout process LCGSRD, and second conversion gain reset readout process LCGRRD.

[0061] The above describes the configuration and functions of each part of the solid-state imaging device 10. Next, the configuration of the pixel signal processing unit 400, which is the column processing system of the readout unit 70 according to this first embodiment, and related readout processes will be described in detail.

[0062] Figure 4 is a circuit diagram showing an example of the configuration of a pixel signal processing unit according to the first embodiment of the present invention.

[0063] As shown in Figure 4, the pixel signal processing unit 400, which can amplify and perform AD conversion on multiple pixel signals read from the readout pixel 200, is configured to include a signal input unit 410, a reference voltage supply unit 420, an AD conversion unit 430, a memory unit 440, a logic unit 450, and a flag unit 460.

[0064] The signal input unit 410 receives the first conversion gain signal (HCGRST, HCGSIG) and the second conversion gain signal (LCGSIG, LCGRST), which are read out from the readout pixel 200 as the pixel signal PIXOUT (VPIX) on the vertical signal line LSGN11, and supplies the input signal VADC to the AD conversion unit 430.

[0065] The reference voltage signal supply unit 420 supplies the AD conversion unit 430 with a reference voltage VDAC(VREF) for comparison with the input signal VADC in the comparator 431 of the AD conversion unit 430. The reference voltage VDAC is applied to the comparison process in the AD conversion unit 430, where the analog voltage signal VSL is compared with a ramp waveform or a fixed voltage reference voltage VREF, which is varied with a predetermined slope, and converted into a digital signal.

[0066] Thus, the AD conversion unit 430 has the function of converting the analog voltage signal VSL (actually the inverted signal VADC of the signal VSL) output by the readout pixel 200 into a digital signal by comparing it with a ramp waveform that has been changed with a predetermined slope or a reference voltage VREF that is a fixed voltage.

[0067] As shown in Figure 4, the AD conversion unit 430 is composed of a comparator (COMP) 431, an auto-zero switch (reset switch) 432, and a current transistor 433 as a current source.

[0068] Comparator 431 receives a voltage signal VSL (or VADC) output from the output buffer section of the readout pixel 200 to the signal line LSGN11 as the first input terminal (-), and a reference voltage VREF as the second input terminal (+). It performs a comparison process that compares the voltage signal VSL (VADC) with the reference voltage VREF and outputs a digitized comparison result signal SCMP.

[0069] The comparator 431 has the output terminal (or coupling capacitor C) of the signal input unit 410 connected to the inverting input terminal (-) which serves as the first input terminal. By AC coupling the output buffer section of the readout pixel 200 and the input section of the comparator 431 of the AD conversion unit 430, noise reduction is achieved, and the system is configured to achieve a high SNR in low light conditions.

[0070] Furthermore, the comparator 431 has a reset switch 432 connected between its output terminal and the inverting input terminal (-) which serves as the first input terminal.

[0071] Basically, in the AD conversion unit 430, from the output buffer section of the readout pixel 200 The analog signal (potential VSL) read out on signal line LSGN11 is compared by comparator 431 with a reference voltage VREF, for example, a ramp signal RAMP which is a linearly changing slope waveform with a certain slope. At this time, counters, such as those not shown, which are arranged in each column similar to the comparator 431, are operating, and the ramp signal RAMP, which has a ramp waveform, and the counter value change in a one-to-one correspondence, thereby converting the voltage signal VSL into a digital signal. Basically, the AD conversion unit 430 converts a change in the reference voltage VREF (for example, the ramp signal RAMP) into a change in time, and then converts that time into a digital value by counting it in a certain period (clock). Then, when the analog signal VSL and the ramp signal RAMP (reference voltage VREF) intersect, the output of the comparator 431 inverts, stopping the counter's input clock, or inputting the previously stopped clock back into the counter. The counter's value (data) at that time is then stored in the memory unit 440, completing the AD conversion.

[0072] The auto-zero switch (reset switch) 432 can be switched between a conductive state and a non-conductive state by the control signal AZ. The auto-zero switch 432 is kept in a conductive state by supplying, for example, a high level of control signal AZ during a predetermined start period of the first conversion gain signal readout mode, thereby initializing the comparator (amplifier) ​​431. The auto-zero switch 432 saves the offset voltage of the comparator (amplifier) ​​431.

[0073] In the pixel signal processing unit 400, the AD conversion unit 430 is connected to the memory unit 440, the logic unit 450, and the flag memory unit 460, which are the targets of drive control.

[0074] The memory section 440 is formed by a multi-bit (10-bit in this embodiment) SRAM 440, and the flag memory is formed by a 1-bit SRAM 460. The memory section 440 has its bit size reduced by about half in order to hold either the HCG signal (first conversion gain signal) or the LCG signal (second conversion gain signal) necessary for image generation.

[0075] Here, the readout process for the HCG signal (first conversion gain signal) and LCG signal (second conversion gain signal) readout from the readout pixel 200 will be explained, focusing on the signal determination and memory access processing in the AD conversion unit 430 of the pixel signal processing unit 400, in relation to Figure 5.

[0076] Figures 5(A) to 5(G) are timing charts showing an example of a readout sequence including signal determination and memory access processing of the readout pixel and pixel signal processing unit in a solid-state imaging device according to the first embodiment of the present invention. Figure 5(A) shows the analog readout signal VSL read from the readout pixel 200, Figure 5(B) shows the readout signal VADC input to the AD conversion unit 430, Figure 5(C) shows the control signal AZ of the auto-zero switch 432 (AZ-SW), Figure 5(D) shows an example of decision bit information, Figure 5(E) shows the flag signal (FLAG) when a signal is selected, Figure 5(F) shows the flag latch signal (FLAG_(HCG)) when the HCG signal is selected, and Figure 5(G) shows the flag latch signal (FLAG(LCG)) when the LCG signal is selected.

[0077] As described above, the readout pixel 200 according to this first embodiment can switch the conversion gain between a first conversion gain determined by the first capacitance (e.g., high conversion gain: HCG) or a second conversion gain determined by the second capacitance (e.g., low conversion gain: LCG) by selectively connecting the floating diffusion FD11 and the storage capacitor CS11 as a storage capacitance element through the storage transistor SG11-Tr as a storage connection element under the control of the readout unit 70, thereby changing the capacitance of the floating diffusion FD11 to a first capacitance or a second capacitance.

[0078] Thus, the solid-state imaging device 10 is configured to perform, under the control of the readout unit 70, a first conversion gain mode readout, in which the pixel signal is read out with a first conversion gain (high conversion gain: HCG) corresponding to the first capacitance, and a second conversion gain mode readout, in which the pixel signal is read out with a second conversion gain (low conversion gain: LCG) corresponding to the second capacitance (different from the first capacitance), during a specified dual conversion gain readout mode period, as shown in Figure 3.

[0079] The readout pixel 200 is equipped with a structure called a lateral overflow integration capacitor (LOFIC), and under the control of the readout unit 70, it operates in a double sampling readout mode (LOFIC mode) using a second conversion gain related to the stored charge and overflow charge of the photodiode PD11, which is a photoelectric conversion element, under high-illumination conditions.

[0080] In this first embodiment, the readout pixel 200 performs dual conversion gain signal readout, which reads out the pixel signal with a first conversion gain (e.g., high conversion gain: HCG) corresponding to a first capacitance, and a second conversion gain signal readout, which reads out the pixel signal with a second conversion gain (e.g., low conversion gain: LCG) corresponding to a second capacitance (different from the first capacitance). In this first embodiment, as shown in Figure 3, the readout process for the readout pixel 200 is as follows: first, in the first conversion gain signal readout mode, the first readout reset signal HCGRST is read out, and then the first readout luminance signal HCGSIG is read out. Next, in the second conversion gain signal readout mode, the second readout luminance signal LCGSIG is read out, followed by the second readout reset signal LCGRST.

[0081] Thus, the first conversion gain signal (HCGRST, HCGSIG) and the second conversion gain signal (LCGSIG, LCGRST) read out from the readout pixel 200 as pixel signals PIXOUT are formed as signals with opposite signal directions (level transition directions). The pixel signal PIXOUT read from the readout pixel 200 (first conversion gain signal (HCGRST, HCGSIG) and second conversion gain signal (LCGSIG, LCGRST)) is then led to the AD conversion unit 430 of the pixel signal processing unit 400, where predetermined processing is performed, mainly focusing on signal determination and memory access processing.

[0082] The AD conversion unit 430 according to this first embodiment determines which of the HCG signal (first conversion gain signal) and LCG signal (second conversion gain signal) is required for image generation, and selects information to be stored in the memory unit 440 based on the determination information. The AD conversion unit 430 enters standby mode when it selects whether to require either the HCG signal (first conversion gain signal) or the LCG signal (second conversion gain signal) for image generation. Furthermore, it is possible to save power that would otherwise be consumed during the readout of the LCG signal (second conversion gain signal) or HCG signal (first conversion gain signal) from the readout pixel 200.

[0083] The SRAM of the memory unit 440 connected to the AD conversion unit 430 has its bit size reduced by about half in order to hold either the HCG signal (first conversion gain signal) or the LCG signal (second conversion gain signal) necessary for image generation. This makes it possible to reduce the circuit area.

[0084] The AD conversion unit 430 uses a DAC to determine which of the HCG signal (first conversion gain signal) and LCG signal (second conversion gain signal) is required for image generation. Furthermore, as shown in Figure 5(D), this determination is made by a determination bit DCBT, in which the AD conversion of the LCG signal (second conversion gain signal) is performed following the AD conversion of the HCG signal (first conversion gain signal).

[0085] More specifically, in the AD conversion unit 430, first, AD conversion is performed on the HCG signal (first conversion gain signal), as in a normal ADC, and the converted digital signal is stored in the 10-bit (multiple-bit) SRAM 440.

[0086] Next, in the AD conversion unit 430, as shown in Figure 5(D), the DAC is set to the decision bit DCBT. Then, it is determined whether or not the LCG signal (second conversion gain signal) is necessary for image generation, and the determination result is stored in the flag SRAM 460.

[0087] Thirdly, the AD conversion unit 430 performs AD conversion on the LCG signal (second conversion gain signal) if necessary, and the converted digital signal is stored in the multi-bit (not limited to 10 bits) SRAM 440. On the other hand, in the AD conversion unit 430, if not needed, the comparator 431 is stopped, and the data stored in the multi-bit SRAM 440 is held as an HCG signal (first conversion gain signal).

[0088] After the AD conversion period described above is complete, the data (signals) stored in the memory section 440 of each readout pixel 200 are output from the output circuit 40 to a signal processing circuit (not shown), and a two-dimensional image is generated by predetermined signal processing.

[0089] As described above, the fixed imaging device 10 according to the first embodiment includes a readout pixel 200 that performs photoelectric conversion and can read out a first conversion gain signal and a second conversion gain signal, the signal directions of which are opposite to those of at least two conversion gains, as pixel signals, and a pixel signal processing unit 400 that processes the pixel signals read out from the readout pixel 200. The pixel signal processing unit 400 includes an AD conversion unit 430 that can perform AD conversion processing to convert the first conversion gain signal and the second conversion gain signal of the input pixel signal from an analog signal to a digital signal, and a multiple bit memory (SRAM) unit 440 that can store the digital signal converted by the AD conversion unit 430. The AD conversion unit 430 determines which of the first conversion gain signal and the second conversion gain signal is required for image generation, and selects information to be stored in the memory unit 440 based on the determination information. Furthermore, the solid-state imaging device 10 according to this first embodiment is configured to provide an ADC (analog-to-digital converter) for high dynamic range imaging that has a small circuit area and low power consumption. In the solid-state imaging device 10 according to this first embodiment, the ADC (AD conversion unit) has a function to determine whether a first conversion gain signal (e.g., high conversion gain: HCG) or a second conversion gain signal (e.g., low conversion gain: LCG) is required for image generation. Furthermore, in the solid-state imaging device 10 according to this first embodiment, when the ADC (AD conversion unit) selects HCG for image generation, the ADC enters standby mode, and the LOFIC is configured to save power consumed while reading out the LCG signal from the pixel. Furthermore, the SRAM within the ADC (AD conversion unit) holds either the HCG signal or the LCG signal necessary for image generation, and its bit size is reduced by approximately half, thereby enabling a reduction in circuit area.

[0090] Therefore, according to the solid-state imaging device 10 of this first embodiment, it is possible to read out signals with different conversion gains and different signal directions from each other, as well as to improve the linearity of the input / output characteristics, suppress the increase in power consumption and circuit area, reduce chip costs, and moreover, fully realize high dynamic range and, consequently, high image quality. This makes it possible to provide an AD conversion unit with a small circuit area and low power consumption for high dynamic range imaging.

[0091] (Second embodiment) Figure 6 is a circuit diagram showing an example of the configuration of a key part in which a sample-and-hold circuit is connected to a comparator that forms the key part of the pixel signal processing unit according to the second embodiment of the present invention.

[0092] The differences between the pixel signal processing unit 400A in this second embodiment and the pixel signal processing unit 400 in the first embodiment are as follows:

[0093] In the pixel signal processing unit 400 of the first embodiment, the sample-and-hold circuit 4311 is not connected to the comparator 431 which forms the main part of the pixel signal processing unit 400.

[0094] In contrast, in the pixel signal processing unit 400A of this second embodiment, a sample-and-hold circuit (SH circuit 4311) is connected to a comparator 431 that forms the main part of the pixel signal processing unit 400A.

[0095] The sample-and-hold circuit 4311 in Figure 6 comprises a sample-and-hold switch M1, a capacitor C1, a tail switch MIstop for the column ADC, and a bias transistor M2.

[0096] Thus, according to the second embodiment, since the sample-and-hold circuit 4311 is connected to the comparator 431 which forms the main part of the pixel signal processing unit 400A, there is an advantage that interference noise can be reduced even if the ADC of the adjacent row stops during LCG conversion.

[0097] (Third embodiment) Figure 7 is a circuit diagram showing an example of the configuration of a pixel signal processing unit according to a third embodiment of the present invention.

[0098] The differences between the pixel signal processing unit 400B in this third embodiment and the pixel signal processing unit 400A in the second embodiment are as follows:

[0099] In the pixel signal processing unit 400A of the second embodiment, a sample-and-hold circuit is connected to the comparator 431 which forms the main part of the pixel signal processing unit 400A, so that interference noise can be reduced even if the ADC of the adjacent row stops during LCG conversion.

[0100] In contrast, in the pixel signal processing unit 400B, which has no sample-and-hold circuit and thus consumes more power but is small in area and free from interference noise, the sample-and-hold circuit 4311 is not connected to the comparator 431 that forms the core of the pixel signal processing unit 400B. Furthermore, in the pixel signal processing unit 400B of this third embodiment, the switching between the operating state and non-operating state of the comparator 431, which forms the main part of the pixel signal processing unit 400B, can be controlled by adjusting the gate voltage level of the bias transistor M2.

[0101] Thus, according to the third embodiment, since the sample-and-hold circuit 4311 is connected to the comparator 431 which forms the main part of the pixel signal processing unit 400B, there is an advantage that interference noise can be reduced even if the ADC of the adjacent row stops during LCG conversion.

[0102] In other words, according to the third embodiment, since the sample-and-hold circuit 4311 is connected to the comparator 431 which forms the main part of the pixel signal processing unit 400, interference noise can be reduced even if the ADC of the adjacent row stops during LCG conversion.

[0103] Furthermore, in the solid-state imaging device 10B of this third embodiment, interference noise is low due to the small area. Furthermore, the comparator 431 is controlled to not stop even when the LCG signal is not needed for image generation. Furthermore, in this third embodiment, compared to the second embodiment, the switch M1 and capacitor C1 that form the sample-and-hold circuit 4311 can be eliminated, making it possible to further reduce the circuit area. (Fourth embodiment) Figure 8 is a circuit diagram showing an example of the configuration of the logic circuit section in the pixel signal processing unit according to the fourth embodiment of the present invention. Figure 9 is a diagram showing the input / output correspondence table, mainly for the logic circuit section, of the pixel signal processing unit according to the fourth embodiment of the present invention. Figures 10(A) to (F) are timing charts showing an example of the readout sequence of a readout pixel and a pixel signal processing unit in a solid-state imaging device according to a fourth embodiment of the present invention.

[0104] Figure 10(A) shows the analog readout signal VADC read from the readout pixel 200, Figure 10(B) shows the bias hold signal input to the AD conversion unit 430, Figure 10(C) shows the latch control signal LATCH, Figure 10(D) shows the latch and ADC control signals LATCHVDAC, Figure 10(E) shows the determination result, and Figure 10(F) shows the clock.

[0105] The differences between the pixel signal processing unit 400C in this fourth embodiment and the pixel signal processing unit 400A in the second embodiment are as follows: In the pixel signal processing unit 400A of the second embodiment, the AD conversion unit 430 is configured to include a first logic circuit 451 for controlling the bias switch of the comparator 431 and a second logic circuit 452 for controlling access to the multi-bit SRAM 440.

[0106] In contrast, the pixel signal processing unit 400C of this fourth embodiment has the following additional configuration in addition to the configuration of the pixel signal processing unit 400A of the second embodiment. In other words, in the pixel signal processing unit 400C of the fourth embodiment, the AD conversion unit 430 is configured to include a first logic circuit 451 for controlling the bias switch of the comparator 431 and a second logic circuit 452 for controlling access to the multi-bit SRAM 440, and at least a portion of the first logic circuit 451 and the second logic circuit 452 are shared.

[0107] (Fifth embodiment) In this fifth embodiment, a 4T-DCG (Dual Conversion Gain) method for small pixels consisting of 4 transistor pixels is employed. 4-transistor pixels are in high demand as low-cost standard dynamic range (SDR) image sensors, and this fifth embodiment enables the realization of a low-cost SDR image sensor.

[0108] Furthermore, the circuit options for solid-state imaging devices described above, or later, can be used with 4T-DCG.

[0109] (Sixth embodiment) Figure 12 shows the optical response characteristics in the readout process in which the MCG signal is added to the HCG signal and LCG signal in the conversion gain readout mode of the solid-state imaging device according to the sixth embodiment of the present invention.

[0110] In the pixel signal processing unit 400E of this sixth embodiment, the AD conversion unit 430E performs input signal determination processing. Specifically, the AD conversion unit 430E processes the MCG (Middle Conversion Gain) signal in addition to the HCG signal and LCG signal in order to achieve a three-stage determination.

[0111] According to this sixth embodiment, the following effects can be obtained by adding a judgment process for the MCG signal. These effects will be explained in relation to Figure 12. In Figure 12, CHCG represents the photo-response linear characteristics of the HCG signal, CMCG represents the photo-response linear characteristics of the MCG signal, and CLCG represents the photo-response linear characteristics of the LCG signal.

[0112] In other words, according to this sixth embodiment, the voltage at the switching point from HCG increases by approximately 20 times, and the SNR is improved. Examples of the points that constitute these conditions are shown below (see Figure 12). P1; ADC input window 0.8V, P2; HCG to MCG switching point 0.085V, P3; Switching point from MCG to LCG, P4; HCG to LCG switching point 0.0043V, (No MCG)

[0113] (Seventh Embodiment) Figure 13 is a circuit diagram showing an example of the configuration of the logic circuit section in the pixel signal processing unit according to the seventh embodiment of the present invention. Figures 14(A) to (H) are timing charts showing an example of the readout sequence of a readout pixel and a pixel signal processing unit in a solid-state imaging device according to the seventh embodiment of the present invention.

[0114] Figure 14(A) shows the analog readout signal VADC read from the readout pixel 200, Figure 14(B) shows the bias hold signal input to the AD conversion unit 430, Figure 14(C) shows the latch control signal LATCH, Figure 14(D) shows the latch and ADC control signals LATCHVDAC, Figure 14(E) shows the determination result, Figure 14(F) shows the clock, Figure 14(G) shows the determination result, and Figure 14(H) shows the clock.

[0115] The differences between the pixel signal processing unit 400G of this seventh embodiment and the pixel signal processing unit 400A of the second embodiment are as follows. In the pixel signal processing unit 400A of the second embodiment, the AD conversion unit 430 is configured to include a first logic circuit 451 for controlling the bias switch of the comparator 431 and a second logic circuit 452 for controlling access to the multi-bit SRAM 440.

[0116] In contrast, the pixel signal processing unit 400G of this seventh embodiment has the following additional configuration in addition to the configuration of the pixel signal processing unit 400A of the second embodiment. In other words, in the pixel signal processing unit 400G of the seventh embodiment, the AD conversion unit 430 is configured to include a first logic circuit 451 for controlling the bias switch of the comparator 431 and a second logic circuit 452 for controlling access to the multi-bit SRAM 440, and at least a portion of the first logic circuit 451 and the second logic circuit 452 are shared.

[0117] In this seventh embodiment, similar to the sixth embodiment, one NAND gate NA1 and one NAND gate NA2 are added to each of the first logic circuit 451 and the second logic circuit 452 to realize a three-stage determination as a flexible determination mode. Additionally, a 1-bit SRAM has been added to store the MCG (Multi-Critical Gauge) judgment result.

[0118] Setting the clock signal ΦCK_M_ADC to low puts the ADC into a two-step decision mode, which has the advantage of shortening the AD conversion time.

[0119] (Eighth embodiment) Figure 15 shows the optical response characteristics in the readout process in which the MCG signal is added to the HCG signal and LCG signal in the conversion gain readout mode of the solid-state imaging device according to the eighth embodiment of the present invention.

[0120] In the pixel signal processing unit 400H of this eighth embodiment, the AD conversion unit 430H performs input signal determination processing. Specifically, the AD conversion unit 430H processes the MCG (Middle Conversion Gain) signal in addition to the HCG signal and LCG signal in order to achieve a three-stage determination.

[0121] According to this eighth embodiment, the following effects can be obtained by adding a judgment process for the MCG signal. These effects will be explained in relation to Figure 15. In Figure 15, CHCG represents the linear optical response characteristics of the HCG signal, CMCG represents the linear optical response characteristics of the MCG signal, and CLCG represents the linear optical response characteristics of the LCG signal.

[0122] According to this eighth embodiment, in order to avoid misjudgment of bright signals, LCG judgment is activated even when an HCG signal is selected in MCG judgment. This is because the saturation of the HCG and MCG signals is dropped in response to bright signals.

[0123] (Ninth embodiment) Figure 16 is a circuit diagram showing an example of the configuration of a pixel signal processing unit according to the ninth embodiment of the present invention.

[0124] In this ninth embodiment, the pixel signal processing unit 400H employs the standby technology of the double sampling (DS) circuit 410.

[0125] In the pixel signal processing unit 400H of the ninth embodiment, when the MCG flag is low, the DS circuit enters standby mode during MCG conversion. When the LCG flag is low, the DS circuit enters standby mode during LCG conversion.

[0126] According to the ninth embodiment, power consumption can be reduced.

[0127] (Tenth embodiment) Figure 17 is a circuit diagram showing an example of the configuration of a pixel signal processing unit according to the 10th embodiment of the present invention.

[0128] In this tenth embodiment, the pixel signal processing unit 400I employs a technique that stops the pixel current source after signal determination.

[0129] In the pixel signal processing unit 400I of the tenth embodiment, when the MCG flag is low, the DS circuit enters standby mode during MCG conversion. When the LCG flag is low, the DS circuit enters standby mode during LCG conversion.

[0130] According to the tenth embodiment, if the MCG flag is low, the pixel current source is turned off during MCG conversion. If the LCG flag is low, the pixel current source is turned off during LCG conversion. According to the tenth embodiment, power consumption can be reduced.

[0131] (11th embodiment) Figure 18 is a circuit diagram showing an example of the configuration of a pixel signal processing unit according to the 11th embodiment of the present invention.

[0132] The pixel signal processing unit 400J of this eleventh embodiment employs sample-and-hold (SH) circuit technology, which samples and holds the signal before reading it out. The SH circuit samples and holds the HCG reset level, HCG signal level, LCG reset level, and LCG signal level in four capacitors, respectively. After sampling and holding the signal, the LCG signal is read out to determine if it is LCG. If the LCG flag is High, LCG conversion is performed. Otherwise, the HCG signal is read out and converted to digital.

[0133] According to this 11th embodiment, power consumption can be reduced. Furthermore, according to this 11th embodiment, the AD conversion time can be shortened.

[0134] (12th embodiment) Figure 19 shows the optical response characteristics in the readout process of the HCG signal, MCG signal, and LCG signal in the conversion gain readout mode of a solid-state imaging device according to a twelfth embodiment of the present invention.

[0135] In the pixel signal processing unit 400K of this twelfth embodiment, HCG signal clipping technology is applied. To avoid a decrease in the HCG signal in response to bright signals, the HCG signal is clipped by a clipping circuit. The HCG signal is used for determination. If the HCG flag is high, the HCG signal is converted. Otherwise, the LCG signal is converted.

[0136] According to this twelfth embodiment, power consumption can be reduced. Furthermore, according to this twelfth embodiment, it is possible to shorten the AD conversion time.

[0137] (13th embodiment) Figure 20 shows the optical response characteristics in the readout process in which the MCG signal is added to the HCG signal and LCG signal in the conversion gain readout mode of the solid-state imaging device according to the 13th embodiment of the present invention.

[0138] In the pixel signal processing unit 400L of this 13th embodiment, a three-stage determination technique (using MCG signal clipping) is applied. The MCG signal is used to determine whether it is LCG or HCG. If the MCG flag is high, the MCG signal is converted. Otherwise, the ADC converts either the HCG signal or the LCG signal.

[0139] According to this 13th embodiment, power consumption can be reduced. Furthermore, according to this 13th embodiment, it is possible to shorten the AD conversion time.

[0140] The solid-state imaging devices 10, 10A to 10L described above can be applied as imaging devices to electronic devices such as digital cameras, video cameras, mobile devices, surveillance cameras, and medical endoscope cameras.

[0141] Figure 21 shows an example of the configuration of an electronic device equipped with a camera system to which a solid-state imaging device according to an embodiment of the present invention is applied.

[0142] As shown in Figure 21, the electronic device 300 has a CMOS image sensor 310 to which the solid-state imaging devices 10, 10A to 10L according to this embodiment can be applied. Furthermore, the electronic device 300 has an optical system (lens, etc.) 320 that guides incident light into the pixel area of ​​the CMOS image sensor 310 (to form an image of the subject). The electronic device 300 has a signal processing circuit (PRC) 330 that processes the output signal of the CMOS image sensor 310.

[0143] The signal processing circuit 330 performs predetermined signal processing on the output signal of the CMOS image sensor 310. The image signal processed by the signal processing circuit 330 can be displayed as a video on a monitor such as a liquid crystal display, output to a printer, or directly recorded on a recording medium such as a memory card, among other possibilities.

[0144] As described above, by incorporating the aforementioned solid-state imaging devices 10, 10A to 10L as the CMOS image sensor 310, it becomes possible to provide a high-performance, compact, and low-cost camera system. Furthermore, it can be used in applications where camera installation requirements have constraints such as mounting size, number of connectable cables, cable length, and installation height, such as surveillance cameras and medical endoscope cameras. [Explanation of Symbols]

[0145] 10, 10A~10L... Solid-state imaging device, 20... Pixel section, 200, 200A~200L... Readout pixels, PD11... Photodiode, FD11... Floating diffusion, TG11-Tr... Transfer transistor, RST11-Tr... Reset transistor, SF11-Tr... Source follower transistor, SG11-Tr... Accumulation transistor, CS11... Accumulation capacitor, 30... Vertical scanning circuit, 40... Readout circuit 400, 400A~400L...Pixel signal processing unit, 410...Signal input unit, 420...Reference voltage supply unit, 430...AD conversion unit, 431...Comparator, 440...Memory unit, 450...Logic unit, 460...Flag memory unit, 50...Horizontal scanning circuit, 60...Timing control circuit, 70...Readout unit, 300...Electronic equipment, 310...CMOS image sensor, 320...Optical system, 330...Signal processing circuit (PRC).

Claims

1. A readout pixel that performs photoelectric conversion and can read out a first conversion gain signal and a second conversion gain signal, the first and second conversion gain signals, as pixel signals, where the signal directions corresponding to at least two conversion gains are in opposite directions. Includes a pixel signal processing unit that processes the pixel signal read out from the readout pixel, The aforementioned pixel signal processing unit, An AD conversion unit capable of performing analog-to-digital (AD) conversion processing to convert the first conversion gain signal and the second conversion gain signal of the input pixel signal from an analog signal to a digital signal, A memory unit capable of storing the digital signal converted by the AD conversion unit, Includes, The aforementioned AD conversion unit is Determine which of the first and second conversion gain signals is required for image generation. Based on the determination information, select the information to be stored in the memory unit. Solid-state imaging device.

2. The aforementioned AD conversion unit is When selecting whether to require the first or second conversion gain signal for image generation, the system enters standby mode to conserve power that would otherwise be consumed during the reading of the second or first conversion gain signal from the readout pixel. The solid-state imaging apparatus according to claim 1.

3. The memory unit has a bit size reduced to about half in order to hold either the first conversion gain signal or the second conversion gain signal necessary for image generation. The solid-state imaging apparatus according to claim 2.

4. The aforementioned AD conversion unit is Determine which of the first and second conversion gain signals is required for image generation, and The determination is made by a determination bit which performs AD conversion of the second conversion gain signal following AD conversion of the first conversion gain signal. The solid-state imaging apparatus according to claim 1.

5. The aforementioned AD conversion unit is As usual, A / D conversion is performed on the first conversion gain signal, and the converted digital signal is stored in a multi-bit RAM. The solid-state imaging apparatus according to claim 4.

6. The aforementioned AD conversion unit is The DAC is set as the decision bit to determine whether the second conversion gain signal is necessary for image generation. The result of the judgment is stored in the flag RAM. The solid-state imaging apparatus according to claim 5.

7. The AD conversion unit is, If necessary, A / D conversion is performed on the second conversion gain signal, and the converted digital signal is stored in a multi-bit RAM. The solid-state imaging apparatus according to claim 6.

8. The AD conversion unit is, Includes a comparator, If not necessary, the comparator is stopped and the data stored in the multi-bit RAM is held as the first conversion gain signal. The solid-state imaging apparatus according to claim 7.

9. At least a portion of the comparator within the AD conversion unit can be connected to a sample-and-hold circuit. The solid-state imaging apparatus according to claim 8.

10. The aforementioned AD conversion unit is The comparator is kept in a non-stop state even when the second conversion gain signal is not needed for image generation. The solid-state imaging apparatus according to claim 8.

11. The aforementioned AD conversion unit is A first logic circuit for controlling the bias switch of the comparator, It includes a second logic circuit that controls access to the multi-bit RAM, The first logic circuit and the second logic circuit share at least a portion of their components. The solid-state imaging apparatus according to claim 8.

12. The aforementioned readout pixel is Dual conversion gain signal readout is performed, which involves reading out the pixel signal with a first conversion gain corresponding to a first capacitance, and reading out the pixel signal with a second conversion gain corresponding to a second capacitance different from the first capacitance. The solid-state imaging apparatus according to claim 8.

13. The aforementioned AD conversion unit is In addition to the first conversion gain signal and the second conversion gain signal, an intermediate conversion gain (MCG) signal is processed. The solid-state imaging apparatus according to claim 8.

14. The aforementioned AD conversion unit is In addition to the first conversion gain determination and the second conversion gain determination, in order to enable intermediate conversion gain (MCG) determination, A NAND (Non-Endoscopic Dynamic Logic) circuit is connected to the output stage of each of the first and second logic circuits. The solid-state imaging apparatus according to claim 13.

15. The aforementioned AD conversion unit is Includes a 1-bit RAM for storing the intermediate conversion gain determination result. The solid-state imaging apparatus according to claim 14.

16. The aforementioned AD conversion unit is If the intermediate conversion gain determination instruction signal, which instructs the intermediate conversion gain determination process, is received in an inactive state, From the three-step determination mode that performs the intermediate conversion gain determination process, as well as the first conversion gain determination process and the second conversion gain determination process The system transitions to a two-step determination mode, which performs a first conversion gain determination process and a second conversion gain determination process. The solid-state imaging apparatus according to claim 13.

17. The aforementioned AD conversion unit is To avoid misjudging bright signals, the second conversion gain signal determination is set to active even if the first conversion gain signal is selected in the intermediate conversion gain determination. The solid-state imaging apparatus according to claim 13.

18. The aforementioned AD conversion unit is A double sampling (DS) circuit is connected to the input stage of the readout pixels of the aforementioned comparator. The aforementioned DS circuit is If the intermediate conversion gain signal determination flag is inactive, the system is set to standby mode during intermediate conversion gain signal conversion. If the second conversion gain signal determination flag is inactive, the system is set to standby mode during the second conversion gain signal conversion. The solid-state imaging apparatus according to claim 8.

19. The aforementioned AD conversion unit is If the aforementioned intermediate conversion gain signal determination flag is inactive, the pixel bias circuit is turned off during the intermediate conversion gain signal conversion. If the second conversion gain signal determination flag is inactive, the pixel bias circuit is turned off during the second conversion gain signal conversion. The solid-state imaging apparatus according to claim 18.

20. The aforementioned AD conversion unit is Before pixel readout, the reset level and signal level of the first conversion gain signal, and the reset level and signal level of the second conversion gain signal are sampled and held by predetermined capacitors. After sampling and holding, the second conversion gain signal is read out and it is determined whether or not it is the second conversion gain signal conversion. The judgment result is set as the second conversion gain signal conversion flag. When the second conversion gain signal flag is at an active level, Perform the second conversion gain signal conversion, If the second conversion gain signal flag is at an inactive level, The first conversion gain signal is read out and converted to digital. The solid-state imaging apparatus according to claim 8.

21. The aforementioned AD conversion unit is Includes clipping circuit, In order to avoid a decrease in the first conversion gain signal for bright signals, the first conversion gain signal is clipped by the clipping circuit. A decision is made using the first conversion gain signal. If the first conversion gain signal flag indicates that it is active, the first conversion gain signal is converted. If the first conversion gain signal flag indicates inactive, the second conversion gain signal is converted. The solid-state imaging apparatus according to claim 13.

22. The aforementioned AD conversion unit is It is possible to perform a three-stage judgment using MCG signal clipping. In making the decision, First, the MCG signal is used to determine whether it is LCG or HCG. If the MCG flag is active, the MCG signal is converted. Otherwise, convert either the MCG signal or the LCG signal. The solid-state imaging apparatus according to claim 21.

23. A readout pixel that performs photoelectric conversion and can read out a first conversion gain signal and a second conversion gain signal, the first and second conversion gain signals, as pixel signals, where the signal directions corresponding to at least two conversion gains are in opposite directions. Includes a pixel signal processing unit that processes the pixel signal read out from the readout pixel, The aforementioned pixel signal processing unit, An AD conversion unit capable of performing analog-to-digital (AD) conversion processing to convert the first conversion gain signal and the second conversion gain signal of the input pixel signal from an analog signal to a digital signal, A memory unit capable of storing the digital signal converted by the AD conversion unit, A method for driving a solid-state imaging device, including, In the aforementioned AD conversion unit, Determine which of the first and second conversion gain signals is required for image generation. Based on the determination information, select the information to be stored in the memory unit. A method for driving a solid-state imaging device.

24. Solid-state imaging device, The solid-state imaging device has an optical system for forming an image of a subject, The solid-state imaging device is A readout pixel that performs photoelectric conversion and can read out a first conversion gain signal and a second conversion gain signal, the first and second conversion gain signals, as pixel signals, where the signal directions corresponding to at least two conversion gains are in opposite directions. Includes a pixel signal processing unit that processes the pixel signal read out from the readout pixel, The aforementioned pixel signal processing unit, An AD conversion unit capable of performing analog-to-digital (AD) conversion processing to convert the first conversion gain signal and the second conversion gain signal of the input pixel signal from an analog signal to a digital signal, A memory unit capable of storing the digital signal converted by the AD conversion unit, Includes, The aforementioned AD conversion unit is Determine which of the first and second conversion gain signals is required for image generation. Based on the determination information, select the information to be stored in the memory unit. electronic equipment.

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