Memory device
The memory device addresses the challenge of high interconnection density by using a back-side interconnection structure, enabling more components or a smaller footprint through relaxed design rules.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- POWERCHIP SEMICON MFG CORP
- Filing Date
- 2026-01-20
- Publication Date
- 2026-05-12
AI Technical Summary
The increasing density of interconnections in electronic devices due to shrinking sizes and the limitations of extreme ultraviolet lithography in achieving narrow line widths necessitate alternative methods to maintain component density and reduce wiring density.
A memory device design that incorporates a third interconnection structure on the back side of the substrate, utilizing both front and back wiring layers for electrical connections, reducing surface wiring density and allowing for relaxed design rules.
Enables the inclusion of more components in a given horizontal area or reduction of the horizontal area while maintaining component count by reducing surface wiring density and allowing for narrower interconnections.
Smart Images
Figure 2026076996000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor device, and more particularly to a memory device.
Background Art
[0002] The size of electronic devices continues to shrink, and user requirements for the performance of electronic devices continue to increase. Those skilled in the art are striving to include more components in electronic devices while maintaining the existing horizontal area, or to maintain the number of existing components while having the smallest horizontal area. However, in either of the above situations, the density of interconnections (especially the density of interconnections closest to the components) increases significantly, so a thinner line width is required.
[0003] In the current manufacturing process, extreme ultraviolet light (EUV) with a short exposure wavelength is widely used as the light source of an exposure machine, and it is possible to realize interconnections with a thin line width by narrowing the wavelength of the exposure light source. However, the lithography process using EUV is expensive and energy-consuming, and in the case where the size of electronic devices continues to shrink, the lithography process using EUV currently cannot satisfy the desired size. Therefore, those skilled in the art continue to search for methods other than narrowing the wavelength of the exposure light source.
Summary of the Invention
Problems to be Solved by the Invention
[0004] The present invention provides a memory device in which a third interconnection structure is arranged, including a second wiring layer located on the back side of the substrate, and the first and second elements include not only a first electrical connection path through the first wiring layer on the front side of the substrate, but also a second electrical connection path through the second wiring layer on the back side of the substrate. In other words, since some of the wiring in the wiring area on the surface of the wafer is moved to the back side of the wafer, the density of interconnections formed on the surface of the wafer can be greatly reduced. Therefore, the memory device can include more components while maintaining the existing horizontal area, and the design rules of the memory device can also be relaxed, meaning that selective design of narrower interconnection widths becomes possible. [Means for solving the problem]
[0005] One embodiment of the present invention provides a memory device comprising a substrate, a first interconnection structure, first and second elements, a second interconnection structure, and a third interconnection structure. The substrate includes a first surface and a second surface facing each other. The first interconnection structure is disposed on the first surface of the substrate. The first and second elements are disposed within the substrate and / or the first interconnection structure, where the first interconnection structure includes a plurality of first wiring layers disposed closest to the first and second elements. The second interconnection structure is disposed on the first interconnection structure. The third interconnection structure is disposed on the second surface of the substrate and includes a plurality of second wiring layers disposed closest to the first and second elements. Each of the first and second elements includes a first electrical connection path through the first wiring layer and a second electrical connection path through the second wiring layer.
[0006] In one embodiment of the present invention, the substrate includes a cell region and a peripheral region adjacent to the cell region, and at least one of the first element and the second element is arranged in the peripheral region and is electrically connected to the memory array of the cell region via a first electrical connection path and / or a second electrical connection path.
[0007] In one embodiment of the present invention, at least one of the first element and the second element includes a sense amplifier or a word line driver.
[0008] In one embodiment of the present invention, the first element is connected to the second element via a first electrical connection path and / or a second electrical connection path.
[0009] In one embodiment of the present invention, the third interconnection structure includes a first via that penetrates the substrate and contacts the first element or the second element.
[0010] In one embodiment of the present invention, the third interconnection structure includes a second via that penetrates the substrate and the first interconnection structure and contacts the first wiring layer.
[0011] One embodiment of the present invention provides a memory device comprising a first wafer and a second wafer stacked on the first wafer. The first wafer comprises a first substrate, a first front-side interconnect structure, a plurality of first elements, a second front-side interconnect structure, and a first back-side interconnect structure. The first substrate includes a front surface and a back surface that face each other. The first front-side interconnect structure is located on the front surface of the first substrate. The first elements are located on the first substrate and / or within the first front-side interconnect structure, where the first front-side interconnect structure includes a plurality of first wiring layers located closest to the first elements. The second front-side interconnect structure is located on the first front-side interconnect structure. The first back-side interconnect structure is located on the back surface of the first substrate and includes a plurality of second wiring layers located closest to the first elements. Each first element includes a first front-side electrical connection path through a first wiring layer and a first back-side electrical connection path through a second wiring layer. The second wafer includes a second substrate, a third front-side interconnect structure, a plurality of second elements, a fourth front-side interconnect structure, and a second back-side electrical connection path. The second substrate is arranged on the second front-side interconnect structure and includes a front surface and a back surface facing each other. The third front-side interconnect structure is arranged on the front surface of the second substrate. The second elements are arranged on the second substrate and / or within the third front-side interconnect structure, where the third front-side interconnect structure includes a plurality of third wiring layers arranged closest to the second elements. The fourth front-side interconnect structure is arranged on the third front-side interconnect structure. The second back-side interconnect structure is located on the back surface of the second substrate and includes a plurality of fourth wiring layers positioned closest to the second element. Each second element includes a second front-side electrical connection path through the third wiring layer and a second back-side electrical connection path through the fourth wiring layer. The second front-side interconnect structure includes rewiring layers connecting the second back-side electrical connection paths.
[0012] In one embodiment of the present invention, the redistribution layer is connected to the first front-side electrical connection path.
[0013] In one embodiment of the present invention, the first back-side interconnection structure and the second back-side interconnection structure each include a first via that penetrates the first substrate and the second substrate, respectively, and contacts the first element and the second element, respectively.
[0014] In one embodiment of the present invention, each first back-side interconnection structure and the second back-side interconnection structure includes a second via, the second via of the first back-side interconnection structure penetrates the first substrate and the first front-side interconnection structure and contacts the first wiring layer, and the second via of the second back-side interconnection structure penetrates the second substrate and the third front-side interconnection structure and contacts the third wiring layer.
[0015] In one embodiment of the present invention, the second front-side interconnection structure includes a front-side pad that is in direct contact with the fourth wiring layer.
[0016] In one embodiment of the present invention, the second wafer includes a through via that penetrates a third front-side interconnect structure, a second substrate, and a second back-side interconnect structure, and contacts one of the fourth wiring layers. [Effects of the Invention]
[0017] Based on the above, in the above memory device, since the third interconnection structure including the second wiring layer is located on the back side of the substrate, the first and second elements not only include a first electrical connection path (through the first wiring layer) on the front side of the substrate, but also a second electrical connection path (through the second wiring layer) on the back side of the substrate. In other words, since some of the wiring that was originally located in the wiring area on the front side of the wafer is moved to the back side of the wafer, the density of interconnections formed on the surface of the wafer can be greatly reduced. In this way, if the memory device maintains the existing horizontal area, the memory device can realize a design with more components by using relaxed design rules (for example, a design including high-density, narrow-linewidth interconnections is optional but not required).
[0018] To make the above content easier to understand, several embodiments will be described in detail below with reference to the drawings.
Brief Description of the Drawings
[0019] The accompanying drawings are included to provide a further understanding of the present invention, are incorporated herein, and constitute a part hereof. The drawings show exemplary embodiments of the present invention and, together with the description, serve to explain the principles of the present invention. [Figure 1] It is a schematic cross-sectional view showing a memory device according to an embodiment of the present invention. [Figure 2] It is a schematic cross-sectional view showing a memory device of another embodiment of the present invention. [Figure 3] It is a schematic cross-sectional view showing a wafer 10a shown in FIG. 2 according to an embodiment of the present invention. [Figure 4] It is a schematic cross-sectional view showing a wafer 10b shown in FIG. 2 according to an embodiment of the present invention. [Figure 5] It is a schematic cross-sectional view showing a wafer 10c shown in FIG. 2 according to an embodiment of the present invention.
Modes for Carrying Out the Invention
[0020] In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, it will be apparent that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown schematically in order to simplify the drawings.
[0021] Hereinafter, the present invention will be described more comprehensively with reference to the drawings of the embodiments. However, the present invention is not limited to the embodiments described in the present invention and can also be implemented in different embodiments. The thicknesses of the layers and regions in the drawings are enlarged for clarity. In the following embodiments, the same or similar parts are denoted by the same reference numerals, and the repeated description thereof is omitted.
[0022] When an element is "above" or "connected to" another element, it means that it may be directly on or connected to the other element, or there may be intervening elements. When an element is "directly above" or "directly connected to" another element, it means that there are no intervening elements. As used herein, "connection" may refer to both physical and / or electrical connections, and "electrical connection" or "coupling" may refer to the presence of other elements between two elements. As used herein, "electrical connection" may refer to a concept that includes physical connections (e.g., wired connections) and physical disconnections (e.g., wireless connections).
[0023] As used herein, "about," "approximately," or "substantially" includes the recited value and average values within the range of acceptable deviations that can be determined by one of ordinary skill in the art. Considering the specific amount of error associated with a measurement (i.e., the limitations of the measurement system), the meaning of "about" can refer to values within, for example, one or more standard deviations of a value, or within ±30%, ±20%, ±10%, ±5% of the value. Further, as used herein, "about," "approximately," or "substantially" can be based on optical properties, etching properties, or other properties to select a more acceptable range of deviations or standard deviation, and it is not necessary to apply one standard deviation to all subjects.
[0024] The terms used herein are used solely for the purpose of describing exemplary embodiments and are not used to limit the present invention. In this case, unless otherwise specified, the singular form also includes the plural form.
[0025] FIG. 1 is a schematic cross-sectional view showing a memory device according to an embodiment of the present invention.
[0026] Referring to Figure 1, the memory device includes a wafer 10 and a carrier substrate 20 supporting the wafer 10. The wafer 10 includes a substrate 100, a first interconnection structure FS1, a first element D1 and a second element D2, a second interconnection structure FS2, and a third interconnection structure BS. The carrier substrate 20 may include a base substrate 200 and a bonding layer 210 formed on the base substrate 200. The base substrate 200 may include a material suitable for a wafer substrate, such as silicon. The bonding layer 210 may include a material suitable for an adhesive layer. The memory device may include dynamic random access memory (DRAM).
[0027] The substrate 100 includes a first surface S1 and a second surface S2 that face each other. The substrate 100 may include a semiconductor substrate or an SOI (Silicon on Insulator) substrate. The semiconductor material in the semiconductor substrate or SOI substrate may include elemental semiconductors, alloy semiconductors, or compound semiconductors. For example, elemental semiconductors may include Si or Ge. Alloy semiconductors may include SiGe, SiGeC, etc. Compound semiconductors may include SiC, III-V semiconductor materials, or II-VI semiconductor materials. III-V semiconductor materials may include GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, GaNP, GaPas, AlNP, AlNAs, AlPAs, InNP, InNAs, InPAs, GaAlNP, GaAlNAs, GaAlPAs, GaInNP, GaInNAs, GaInPAs, InAlNP, InAlNAs, or InAlPAs. The II-VI semiconductor materials may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, or HgZnSTe. The semiconductor material can be doped with a dopant of a first conductivity type, or with a dopant of a second conductivity type complementary to the first conductivity type. For example, the first conductivity type may be n-type, and the second conductivity type may be p-type.
[0028] The first interconnection structure FS1 is disposed on the first surface S1 of the substrate 100. The first element D1 and the second element D2 are disposed on the substrate 100 and / or within the first interconnection structure FS1. For example, at least one of the first element D1 and the second element D2 may include a well (not shown) formed in the substrate 100 and / or a structure (not shown) formed on the substrate 100 (i.e., formed within the first interconnection structure FS1). In some embodiments, at least one of the first element D1 and the second element D2 may include a sense amplifier or a word line driver.
[0029] The first interconnection structure FS1 includes a plurality of first wiring layers 1Wf arranged in the closest proximity to the first element D1 and the second element D2. The first wiring layers 1Wf may contain a conductive material such as a metal or a metal alloy. The metal and metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof. In some embodiments, the first interconnection structure FS1 may include a dielectric layer IL0 formed on a first surface S1 of the substrate 100, in which the first wiring layers 1Wf are formed, and conductive contacts 1C formed within the dielectric layer IL0, which electrically connect the first element D1 and the second element D2 to the first wiring layers 1Wf. The dielectric layer IL0 may contain a dielectric material such as an oxide (e.g., silicon oxide) or a nitride (e.g., silicon nitride). The conductive contacts 1C may contain a conductive material such as a metal or a metal alloy. The metals and metal alloys may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof.
[0030] The second interconnection structure FS2 is placed on the first interconnection structure FS1. The second interconnection structure FS2 is electrically connected to the first interconnection structure FS1. In some embodiments, the second interconnection structure FS2 is placed between the first interconnection structure FS1 and the bonding layer 210 of the carrier substrate 20. That is, in some embodiments, after the first interconnection structure FS1, the first element D1 and the second element D2, and the second interconnection structure FS2 of the wafer 10 are formed, the wafer 10 can be turned over and placed on the carrier substrate 20. Then, after the back side of the wafer 10 is subjected to a thinning process, the third interconnection structure BS is formed on the second surface S2 of the thinned substrate 100.
[0031] In some embodiments, the second interconnection structure FS2 may include a dielectric layer 110 and wiring 120 formed within the dielectric layer 110. The dielectric layer 110 may include a single dielectric layer or multiple dielectric layers, but is not limited thereto. The dielectric layer 110 may include a dielectric material such as an oxide (e.g., silicon oxide) or a nitride (e.g., silicon nitride). The interconnection 120 may include a single wiring layer or multiple wiring layers or rewiring layers and vias connecting the wiring layers or rewiring layers. The interconnection 120 may include a conductive material such as a metal or a metal alloy. The metal and metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof.
[0032] The third interconnection structure BS is arranged on the second surface S2 of the substrate 100 and includes a plurality of second wiring layers 1Wb positioned closest to the first element D1 and the second element D2, with each first element D1 and second element D2 including a first electrical connection path through the first wiring layer 1Wf and a second electrical connection path through the second wiring layer 1Wb. In other words, by moving some of the wiring that was originally located in the wiring area on the front side of the wafer 10 to the back side of the wafer 10, the density of interconnections formed on the front side of the wafer 10 (e.g., the density of the first wiring layer 1Wf) can be significantly reduced. In this way, if the storage device maintains the existing horizontal area, the storage device can achieve a design with more components by using relaxed design rules, or if the storage device maintains the existing number of components, the storage device can achieve a design with a smaller horizontal area by using relaxed design rules. Furthermore, since the wiring layers closest to the first element D1 and the second element D2 have higher density and narrower line widths, moving some of the wiring layers closest to the first element D1 and the second element D2 from the front side of the wafer 10 to the back side of the wafer 10 can significantly relax the design rules.
[0033] In some embodiments, when some wiring layers are moved to the back side of wafer 10, the first element D1 can be connected to the second element D2 via a first electrical connection path (e.g., via the path of the first wiring layer 1Wf) and / or via a second electrical connection path (e.g., via the path of the second wiring layer 1Wb). In some embodiments, the substrate 100 may include a cell region and a peripheral region adjacent to the cell region, and at least one of the first element D1 and the second element D2 may be located in the peripheral region and be electrically connected to a memory array (not shown) in the cell region via a first electrical connection path (e.g., via the path passing through the first wiring layer 1Wf) and / or via a second electrical connection path (e.g., via the second wiring layer 1Wb).
[0034] The third interconnection structure BS may include a dielectric layer 130 formed on the second surface S2 of the substrate 100, and vias (e.g., a first via TSV1 and a second via TSV2) that electrically connect the second wiring layer 1Wb to the first element D1 and / or the second element D2. For example, in some embodiments, the third interconnection structure BS may include a first via TSV1 that penetrates the dielectric layer 130 and the substrate 100 and contacts the first element D1. In some embodiments, the third interconnection structure BS may include a second via TSV2 that penetrates the dielectric layer 130, the substrate 100, and the first interconnection structure FS1 and contacts the first wiring layer 1Wf. The dielectric layer 130 may include a dielectric material such as an oxide (e.g., silicon oxide) or a nitride (e.g., silicon nitride). The first via TSV1 and / or the second via TSV2 may contain a conductive material such as a metal, a metal alloy, a metal nitride, a metal silicide, or a combination thereof. In some embodiments, the metals and metal alloys may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof. The metal nitrides may be, for example, TiN, WN, TaN, TaSiN, TiSiN, WSiN, or a combination thereof. The metal silicides may include tungsten silicide, titanium silicide, cobalt silicide, zirconium silicide, platinum silicide, molybdenum silicide, copper silicide, nickel silicide, or a combination thereof.
[0035] The third interconnection structure BS may include a dielectric layer 140 formed on the dielectric layer 130 and covering the second wiring layer 1Wb, and an interconnection 150 formed within the dielectric layer 140. The dielectric layer 140 may include a single dielectric layer or multiple dielectric layers, but the present invention is not limited thereto. The dielectric layer 140 may include a dielectric material such as an oxide (e.g., silicon oxide) or a nitride (e.g., silicon nitride). The interconnection 150 may include a single wiring layer or multiple wiring layers or rewiring layers, and vias connecting the wiring layers or rewiring layers. The interconnection 150 may include a conductive material such as a metal or a metal alloy. The metal and metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof.
[0036] The memory device may include an underbump metallization (UBM) layer 160 formed on a third interconnection structure BS, and an electrical connection metal 170 formed on the UBM layer 160. In some embodiments, the wafer 10 may be physically and / or electrically connected to an external device via the UBM layer 160 and the electrical connection metal 170. The UBM layer 160 can be formed by a known metallization method using a known conductive material such as a metal. The electrical connection metal 170 may include a low-melting-point metal such as solder (e.g., Sn-Al-Cu). The electrical connection metal 170 may have a single-layer or multi-layer structure. For example, a multi-layer structure may include copper pillars and solder, and a single-layer structure may include tin-silver solder or copper. The number, spacing, configuration, etc., of the electrical connection metals 170 are not limited.
[0037] Figure 2 is a schematic cross-sectional view showing a storage device according to another embodiment of the present invention. Figure 3 is a schematic cross-sectional view showing wafer 10a shown in Figure 2 according to one embodiment of the present invention. Figure 4 is a schematic cross-sectional view showing wafer 10b shown in Figure 2 according to one embodiment of the present invention. Figure 5 is a schematic cross-sectional view showing wafer 10c shown in Figure 2 according to one embodiment of the present invention. The wafer stack 10' shown in Figure 2 includes a first wafer 10a, a second wafer 10b, and a third wafer 10c. Here, the first wafer 10a, the second wafer 10b, and the third wafer 10c are substantially the same as wafer 10 shown in Figure 1, so identical or similar components are indicated by the same or similar reference numerals and are not described below.
[0038] Referring to Figure 2, the memory device includes a wafer stack 10' and a carrier wafer 20' that supports the wafer stack 10'. The wafer stack 10' includes a first wafer 10a and a second wafer 10b stacked on the first wafer 10a. The memory device may include dynamic random access memory (DRAM).
[0039] Referring to Figures 2 and 3, the first wafer 10a includes a first substrate 100, a first front-side interconnection structure FS1, a plurality of first elements (e.g., D1 and D2 shown in Figure 3), a second front-side interconnection structure FS2, and a first back-side interconnection structure BS1. The first substrate 100 includes a front surface S1 and a back surface S2 that face each other. The first front-side interconnection structure FS1 is located on the front surface S1 of the first substrate 100. The first elements are located on the first substrate 100 and / or within the first front-side interconnection structure FS1. Here, the first front-side interconnection structure FS1 includes a first wiring layer 1Wf1 located closest to the first elements. The second front-side interconnection structure FS2 is located on the first front-side interconnection structure FS1. The first back-side interconnection structure BS1 is arranged on the back surface S2 of the first substrate 100 and includes a plurality of second wiring layers 1Wb1 arranged in closest proximity to the first element. Each first element includes a first front-side electrical connection path through the first wiring layer 1Wf1 and a first back-side electrical connection path through the second wiring layer 1Wb1.
[0040] Referring to Figures 2 and 4, the second wafer 10b includes a second substrate 100, a third front-side interconnection structure FS1, a plurality of second elements (e.g., D1 and D2 shown in Figure 4), a fourth front-side interconnection structure FS2, and a second back-side interconnection structure BS2. The second substrate 100 is placed on the second front-side interconnection structure FS2 and includes a front surface S1 and a back surface S2 facing each other. The third front-side interconnection structure FS1 is placed on the front surface S1 of the second substrate 100. The second elements are placed in the second substrate 100 and / or the third front-side interconnection structure FS1, where the third front-side interconnection structure FS1 includes a plurality of third wiring layers 1Wf2 placed closest to the second elements. The fourth front-side interconnection structure FS2 is placed on the third front-side interconnection structure FS1. The second back-side interconnection structure BS2 is arranged on the back surface S2 of the second substrate 100 and includes a plurality of fourth wiring layers 1Wb2 arranged in the closest proximity to the second element. Each second element includes a second front-side electrical connection path through a third wiring layer 1Wf2 and a second back-side electrical connection path through the fourth wiring layer 1Wb2.
[0041] Referring to Figures 2 to 4, the second front-side interconnection structure FS2 includes a redistribution layer RDL2 that connects to a second back-side electrical connection path (via the path of the fourth wiring layer 1Wb2). Thus, a first element of the first wafer 10a (e.g., D1 or D2 in Figure 3) can be connected to the redistribution layer RDL2 via the first front-side electrical connection path (e.g., via the path of the first wiring layer 1Wf1), and a second element of the second wafer 10b (e.g., D1 or D2 in Figure 4) can be connected to the redistribution layer RDL2 via the second back-side electrical connection path (e.g., via the path of the fourth wiring layer 1Wb2). Thus, the wafer stack 10' can achieve a design with more components by using relaxed design rules, or the wafer stack 10' can achieve a design in a smaller horizontal area while maintaining the number of existing components by using relaxed design rules. The redistribution layer RDL2 may contain a conductive material such as a metal or a metal alloy. The metal and metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof.
[0042] In some embodiments, as shown in Figures 3 and 4, the first back-side interconnect structure BS1 and the second back-side interconnect structure BS2 may include a first via TSV1 that penetrates the first substrate 100 of the first wafer 10a and the second substrate of the second wafer 10b, respectively, and contacts the first element of the first wafer 10a and the second element of the second wafer 10b, respectively.
[0043] In some embodiments, as shown in Figures 3 and 4, the first rear interconnect structure BS1 and the second rear interconnect structure BS2 may each include a second via TSV2. The second via TSV2 of the first rear interconnect structure BS1 penetrates the first front interconnect structure FS1 of the first substrate 100 and the first wafer 10a and contacts the first wiring layer 1Wf1, and the second via TSV2 of the second rear interconnect structure BS2 penetrates the third front interconnect structure FS1 of the second substrate 100 and the second wafer 10b and contacts the first wiring layer 1Wf1 and the third wiring layer 1Wf2.
[0044] In some embodiments, as shown in Figure 3, the second front-side interconnect structure FS2 may include a front-side pad 122 that is in direct contact with the fourth wiring layer 1Wb2. That is, the first wafer 10a and the second wafer 10b can be joined by hybrid bonding. For example, the front-side pad 122 of the first wafer 10a is in direct contact with the fourth wiring layer 1Wb2 of the second wafer 10b (i.e., metal-to-metal bonding), and the dielectric layer 110 of the first wafer 10a shown in Figure 3 is in direct contact with the dielectric layer 130 of the second wafer 10b shown in Figure 4 (i.e., dielectric-to-dielectric bonding).
[0045] In some embodiments, as shown in Figure 4, the second wafer 10b includes a through-via TSV3 that penetrates the third front-side interconnect structure FS1, the second substrate 100, and the second back-side interconnect structure BS2, and the through-via TSV3 contacts one of the fourth wiring layers 1Wb2. In some embodiments, the through-via TSV3 electrically connects one of the fourth wiring layers 1Wb2 to a wiring layer 2Wf formed in the fourth front-side interconnect structure FS2. That is, the second back-side interconnect structure BS2 may not be connected to the wiring layer 2Wf of the fourth front-side interconnect structure FS2 via the third front-side interconnect structure FS1, but rather to the wiring layer 2Wf of the fourth front-side interconnect structure FS2 via the through-via TSV3. In some embodiments, the through-via TSV3 shown in Figure 3 or 4 can be considered a central through-via (TSV-middle) because it is formed after the first or second element is formed.
[0046] As shown in Figure 2, the carrier wafer 20' may include a front-end process structure FEOL and a back-end process structure BEOL formed on the front-end process structure FEOL.
[0047] The front-end process structure FEOL may include a base substrate 200, a plurality of elements 202, and a device layer 204 on which the elements 202 are formed. The base substrate 200 may include a semiconductor substrate or an SOI substrate. In some embodiments, the base substrate 200 may contain the same or similar material as the substrate 100. The element 202 may include active and / or passive elements. The device layer 204 may include elements formed therein (e.g., element 202) and a dielectric layer covering the elements.
[0048] The back-end process structure BEOL may include a dielectric layer 212, interconnects 220 formed within the dielectric layer 212, a front-side pad 230, and a redistribution layer RDL1. In some embodiments, the redistribution layer RDL1 is connected to a first back-side electrical connection path of a first element of the first wafer 10a (e.g., D1 or D2 shown in Figure 3) (e.g., via the path of a second wiring layer 1Wb1). Thus, the first element of the first wafer 10a (e.g., D1 or D2 in Figure 3) can be connected to the redistribution layer RDL1 via a first back-side electrical connection path (e.g., via the path of a second wiring layer 1Wb1), and by using relaxed design rules, designs with more components can be realized, or, if the storage device maintains the number of existing components, the storage device can be designed in a smaller horizontal area by using relaxed design rules.
[0049] The dielectric layer 212 may comprise a single dielectric layer or multiple dielectric layers, but the present invention is not limited thereto. The dielectric layer 212 may comprise a dielectric material such as an oxide (e.g., silicon oxide) or a nitride (e.g., silicon nitride). The interconnect 220 may comprise a single wiring layer or multiple wiring layers or rewiring layers and vias connecting the wiring layers or rewiring layers. The interconnect 220 and / or rewiring layer RDL1 may comprise a conductive material such as a metal or a metal alloy. The metal and metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof.
[0050] The upper surface of the front pad 230 may be exposed to the surface of the back-end process structure BEOL facing the first wafer 10a. As a result, the carrier wafer 20' and the first wafer 10a can be bonded to each other by using hybrid bonding. For example, the front pad 230 of the carrier wafer 20' and the second wiring layer 1Wb1 of the first wafer 10a are in contact with each other (i.e., metal-to-metal bonding), and the dielectric layer 212 and the dielectric layer 130 are in contact with each other (i.e., dielectric-to-dielectric bonding).
[0051] In some embodiments, referring to Figures 2, 4, and 5, a third wafer 10c is stacked on a second wafer 10b. Here, the second front-side interconnection structure FS2 of the second wafer 10b includes a redistribution layer RDL3 connected to a back-side electrical connection path (e.g., a path through wiring layer 1Wb3) of the third wafer 10c. Therefore, elements of the second wafer 10b (e.g., D1 or D2 shown in Figure 4) may be connected to the redistribution layer RDL3 via a front-side electrical connection path (e.g., a path through wiring layer 1Wf2), and elements of the third wafer 10c (e.g., D1 or D2 shown in Figure 5) may be connected to the redistribution layer RDL3 via a back-side electrical connection path (e.g., a path through wiring layer 1Wb3), so that the wafer stack 10' can achieve a design with more components by using relaxed design rules, or, if the wafer stack 10 maintains the number of existing components, can achieve a design with a smaller horizontal area by using relaxed design rules. The redistribution layer RDL3 may contain a conductive material such as a metal or a metal alloy. The metals and metal alloys may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof.
[0052] As described above, in the memory device of the above embodiment, since the third interconnection structure including the second wiring layer is located on the back side of the substrate, the first and second elements not only include a first electrical connection path on the front side of the substrate (through the first wiring layer), but also a second electrical connection path on the back side of the substrate (through the second wiring layer). In other words, since some of the wiring that was originally located in the wiring region on the surface of the wafer moves to the back side of the wafer, the density of interconnections formed on the surface of the wafer can be greatly reduced. In this way, if the memory device maintains the existing horizontal area, the memory device can realize a design with more components by using relaxed design rules (for example, a design including high-density, narrow-linewidth interconnections is optional but not required).
[0053] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the present invention. In consideration of the foregoing, the present invention is intended to encompass modifications and variations, insofar as they remain within the scope of the claims and their equivalents. [Industrial applicability]
[0054] The storage device of the present invention can be applied to a three-dimensional (3D) storage device, a dynamic random access storage device, or a combination thereof. [Explanation of Symbols]
[0055] 10: Wafer 10': Wafer stack 10a: First wafer 10b: Second wafer 10c: Third wafer 20: Carrier substrate 20': Carrier wafer 100: Circuit board / First circuit board / Second circuit board 120, 150, 220: Interconnection 122, 230: Front pad 160: Underbump Metallization (UBM) Layer / UBM Layer 170: Electrical connection metal 200: Base board 202: Related 204: Device Layer 210: Bonding layer 1C: Conductive contact 1Wf, 1Wf1: First wiring layer 1Wb, 1Wb1: Second wiring layer 1Wf2: Third wiring layer 1Wb2: Fourth wiring layer 1Wf2, 1Wb3, 2Wf: wiring layer BS: Third interconnection structure BS1: First rear-side interconnection structure BS2: Second Rear Interconnection Structure D1: First element D2: Second element FS1: First interconnection structure / First front-side interconnection structure / Third front-side interconnection structure FS2: Second interconnection structure / Second front-side interconnection structure / Fourth front-side interconnection structure FEOL: Front-end process structure BEOL: Backend Process Structure IL0, 110, 130, 140, 212: Dielectric layers RDL1, RDL2, RDL3: Redistribution Layers S1: First surface / Front surface S2: Second surface / back surface TSV1: First Beer TSV2: The Second Beer TSV3: Through-Via
Claims
1. A substrate including a first surface and a second surface facing each other, A first interconnection structure disposed on the first surface of the substrate, Displaced within the substrate and / or the first interconnection structure, the first interconnection structure includes first and second elements, which include a plurality of first wiring layers positioned closest to the first and second elements, A second interconnection structure disposed on the first interconnection structure, A third interconnection structure comprising a plurality of second wiring layers disposed on the second surface of the substrate and positioned closest to the first and second elements, Equipped with, Each of the first and second elements includes a first electrical connection path through the first wiring layer and a second electrical connection path through the second wiring layer. storage device.
2. The substrate includes a cell region and a peripheral region adjacent to the cell region, and at least one of the first element and the second element is arranged in the peripheral region and is electrically connected to the memory array of the cell region via the first electrical connection path and / or the second electrical connection path. The storage device according to claim 1.
3. At least one of the first element and the second element includes a sense amplifier or a word line driver. The storage device according to claim 2.
4. The first element is connected to the second element via the first electrical connection path and / or the second electrical connection path. The storage device according to claim 3.
5. The third interconnection structure includes a first via that penetrates the substrate and contacts the first element or the second element. The storage device according to claim 1.
6. The third interconnection structure includes a second via that penetrates the substrate and the first interconnection structure and contacts the first wiring layer. The storage device according to claim 5.
7. A first substrate including a front surface and a back surface facing each other, A first front-side interconnection structure disposed on the front-side surface of the first substrate, A plurality of first elements disposed on the first substrate and / or the first front-side interconnection structure, wherein the first front-side interconnection structure includes a plurality of first wiring layers disposed closest to the first elements, A second front-side interconnection structure is arranged on the first front-side interconnection structure, A first back-side interconnection structure comprising a plurality of second wiring layers arranged on the back surface of the first substrate and positioned closest to the first element, Each of the first elements has a first front-side electrical connection path passing through the first wiring layer and a first back-side electrical connection path passing through the second wiring layer. A first wafer containing, The first wafer is stacked on top of the first wafer, A second substrate is arranged on the second front interconnection structure and includes a front surface and a back surface that face each other, A third front-side interconnection structure disposed on the front-side surface of the second substrate, A plurality of second elements disposed on the second substrate and / or the third front interconnect structure, wherein the third front interconnect structure includes a plurality of third wiring layers disposed closest to the second elements, A fourth front-side interconnection structure is arranged on the third front-side interconnection structure, A second back-side interconnection structure comprising a plurality of fourth wiring layers arranged on the back surface of the second substrate and positioned closest to the second element, A second wafer containing, Includes, Each of the aforementioned second elements includes a second front-side electrical connection path through the third wiring layer and a second back-side electrical connection path through the fourth wiring layer. The second front-side interconnection structure includes a rewiring layer connected to the second back-side electrical connection path. storage device.
8. The rewiring layer is connected to the first front-side electrical connection path. The storage device according to claim 7.
9. The first back-side interconnection structure and the second back-side interconnection structure each include a first via that penetrates the first substrate and the second substrate, respectively, and contacts the first element and the second element, respectively. The storage device according to claim 7.
10. Each of the first and second back-side interconnection structures includes a second via, the second via of the first back-side interconnection structure penetrating the first substrate and the first front-side interconnection structure and contacting the first wiring layer, and the second via of the second back-side interconnection structure penetrating the second substrate and the third front-side interconnection structure and contacting the third wiring layer. The storage device according to claim 9.
11. The second front-side interconnection structure includes a front-side pad that is in direct contact with the fourth wiring layer. The storage device according to claim 10.
12. The second wafer includes through vias that penetrate the third front interconnect structure, the second substrate, and the second back interconnect structure and contact one of the fourth wiring layers. The storage device according to claim 11.