Electrostatic chucks for panels and insulating panels

Abstract

This technology provides a way to securely hold insulating panels, such as glass substrates on which semiconductor chips are placed. [Solution] The electrostatic chuck 100 comprises a ceramic substrate 110 having an upper surface 111 which is the main surface on which the insulating panel 200 is placed, and a plurality of electrode pairs 120 embedded in the ceramic substrate 110. Each electrode pair 120 comprises two electrodes 122 and 124. The plurality of electrode pairs 120 are arranged to overlap with the semiconductor chip 220 in the vertical direction 5. The overlapping area of ​​the semiconductor chip 220 and electrode 122 is the same as the overlapping area of ​​the semiconductor chip 220 and electrode 124.

Description

Technical Field

[0001] The present invention relates to an electrostatic chuck for a panel and an insulating panel.

Background Art

[0002] Patent Document 1 discloses, as a technique for adsorbing and holding a glass substrate, forming an adsorption film on substantially the entire back surface of the glass substrate. The adsorption film is a film that generates dielectric polarization by applying an electric field or a film having conductivity. In Patent Document 1, it is disclosed that by forming an adsorption film on the back surface of the glass substrate, the glass substrate can be held by an electrostatic chuck incorporating a conventional bipolar electrode.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The technique for holding the glass substrate described in Patent Document 1 is premised on forming an adsorption film on the back surface of the glass substrate. There is a need for a technique for adsorbing the glass substrate without forming such an adsorption film.

[0005] In recent years, as a technique for packaging an entire wafer or panel together instead of the conventional packaging for each individual chip, techniques called WLP (Wafer level package) and PLP (Panel level package) have attracted attention. PLP is a method of panelizing by arranging a silicon chip (semiconductor chip) on an insulating panel such as a glass substrate or molding it with a sealing resin. Along with this, there is a need for a technique for reliably holding an insulating panel such as a glass substrate on which semiconductor chips are arranged.

[0006] This invention has been made in view of these circumstances, and aims to provide a technology for reliably holding an insulating panel, such as a glass substrate on which a semiconductor chip is arranged. [Means for solving the problem]

[0007] According to an aspect of the present invention, an electrostatic chuck for a panel used in an insulating panel comprising a plurality of semiconductor chips, A plate-shaped ceramic sintered body having a main surface on which the panel is placed, The ceramic sintered body is embedded in a plurality of electrode pairs, each electrode pair having an anode and a cathode, and comprises a plurality of electrode pairs. The plurality of electrode pairs are arranged such that each semiconductor chip overlaps with at least one electrode pair in the vertical direction perpendicular to the main surface. An electrostatic chuck for a panel is provided, characterized in that the sum of the areas of the anodes and the sum of the areas of the cathodes overlapping each semiconductor chip in the vertical direction are equal to each other. [Effects of the Invention]

[0008] According to the above configuration, each electrode pair is arranged so that the semiconductor chip and the electrode pair overlap in the vertical direction. Therefore, the Coulomb force acting between the overlapping electrode pairs and the semiconductor chip ensures reliable electrostatic adsorption of the insulating panel. Furthermore, for each semiconductor chip, the overlapping area between the semiconductor chip and the anode is the same as the overlapping area between the semiconductor chip and the cathode. As a result, during the process in which the Coulomb force is acting, the potential of each semiconductor chip stabilizes at an intermediate potential between the anode and cathode, thus stabilizing and homogenizing the process. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a schematic diagram illustrating a portion of the insulating panel 200. [Figure 2]Figure 2 is a schematic diagram illustrating the state in which the insulating panel 200 is placed on the electrostatic chuck 100. [Figure 3] This is a schematic diagram illustrating the electrodes 122 and 124 that constitute the electrode pair 120. [Figure 4] Figure 4 is a schematic diagram illustrating the state in which an insulating panel 200, which includes a semiconductor chip 220 exposed on the lower surface 212 of a substrate 210, is placed on an electrostatic chuck 100. [Figure 5] Figure 5 is a schematic diagram illustrating the state in which an insulating panel 200, equipped with a semiconductor chip 220 whose upper surface area 221 is larger than the lower surface area 222, is placed on an electrostatic chuck 100. [Figure 6] (a) is a schematic diagram illustrating an example in which one semiconductor chip 220 overlaps with two electrode pairs 120 in the vertical direction 5, (b) and (c) are schematic diagrams illustrating an example in which a portion of an electrode pair 120 is located between two adjacent semiconductor chips 220, and (d) is a schematic diagram illustrating an example in which a portion of electrodes 122 and 124 constituting an electrode pair 120 overlaps with one semiconductor chip 220 in the vertical direction 5. [Modes for carrying out the invention]

[0010] The electrostatic chuck 100 and insulating panel 200 according to this embodiment will be described with reference to Figures 1 and 2. Figure 1 is a schematic diagram illustrating the insulating panel 200, and Figure 2 is a schematic diagram illustrating the state in which the insulating panel 200 is placed on the electrostatic chuck 100. Note that in Figure 2, some of the multiple electrode pairs 120 described later are shown.

[0011] The electrostatic chuck 100 according to this embodiment is used to hold the insulating panel 200. In the following description, the vertical direction 5 is defined based on the state in which the insulating panel 200 is placed on the electrostatic chuck 100 (the state in Figure 2). As shown in Figure 1, the insulating panel 200 according to this embodiment mainly comprises a substrate 210 and a plurality of semiconductor chips 220. Although 24 semiconductor chips 220 are shown in Figure 1, the number of semiconductor chips 220 is not limited to 24.

[0012] <Insulating Panel 200> As shown in Figure 1, the insulating panel 200 comprises a base material 210, which is a rectangular plate-shaped member, and a plurality of semiconductor chips 220 arranged on the upper surface 211 of the base material 210. The base material 210 is an example of an insulating member of the present invention. The base material 210 is formed of an insulating material. As the base material 210, for example, a glass substrate made of glass, a resin substrate made of resin, a printed circuit board, etc., can be used. In this embodiment, the base material 210 of the insulating panel 200 has a rectangular plate shape with a length of 457 mm and a width of 610 mm, and a thickness T1 (length in the vertical direction 5) of 1.2 mm. The size, shape, and thickness of the base material 210 can be made as appropriate. For example, the base material 210 can be made into a square shape with a length of 600 mm and a width of 600 mm. The thickness T1 of the base material 210 is preferably 0.7 mm to 2 mm. If the thickness T1 of the substrate 210 becomes too thick, the distance between the bottom surface 212 of the substrate 210 and the semiconductor chip 220 becomes too large, resulting in a decrease in the Coulomb force. The distance between the bottom surface 212 of the substrate 210 and the semiconductor chip 220 is preferably 0 to 1.3 mm, and more preferably 0 to 0.5 mm. This is because the Coulomb force can be exerted even with a smaller voltage applied between the electrode pairs 120.

[0013] Multiple semiconductor chips 220 are arranged in a grid pattern at predetermined intervals G on the upper surface 211 of the substrate 210, forming multiple rows and multiple columns. In this embodiment, each semiconductor chip 220 has a square shape with sides of 10 mm. The thickness T2 of each semiconductor chip 220 is 0.7 mm. The size and shape of each semiconductor chip 220 can be adjusted as appropriate. The number and arrangement of the semiconductor chips 220 can also be adjusted as appropriate.

[0014] Each semiconductor chip 220 is embedded in the substrate 210 such that the upper surface 221 of each semiconductor chip 220 and the upper surface 210 of the substrate 210 are on the same plane. In this embodiment, the thickness T1 of the substrate 210 is greater than the thickness T2 of each semiconductor chip 220 (T1 > T2). Therefore, the upper surface 221 of each semiconductor chip 220 is exposed on the upper surface 211 of the substrate 210, but the lower surface 222 of the semiconductor chip 220 is not exposed on the lower surface 212 of the substrate 210.

[0015] <Electrostatic Chuck 100> As shown in Figure 2, the ceramic substrate 110 is a substantially rectangular plate-shaped member and has two main surfaces (upper surface 111 and lower surface 112) facing each other in the vertical direction 5. The insulating panel 200 to be held is placed on the upper surface 111 of the ceramic substrate 110. In this embodiment, the length (thickness) of the ceramic substrate 110 in the vertical direction 5 is 20 mm. The thickness of the ceramic substrate 110 can be, for example, 5 mm to 50 mm. Furthermore, the ceramic substrate 110 can be made to an appropriate size to match the size of the insulating panel 200. For example, if the size of the insulating panel 200 is 600 mm in length and 600 mm in width, the size of the ceramic substrate 110 can also be made to match 600 mm in length and 600 mm in width. In this embodiment, the ceramic substrate 110 is formed from an alumina (Al2O3) ceramic sintered body. For example, the Al2O3 content can be 80% or more.

[0016] As shown in FIG. 2, electrode pairs 120 for electrostatic adsorption are embedded in the ceramic substrate 110. Although only six are shown in FIG. 2, in the present embodiment, the number of electrode pairs 120 is a plurality of six or more (the same as the number of semiconductor chips 220). Each electrode pair 120 is disposed at a position overlapping the semiconductor chip 220 in the vertical direction 5 when the insulating panel 200 is placed on the electrostatic chuck 100. Each electrode pair 120 has an electrode 122 and an electrode 124. For each semiconductor chip 220, the area where the semiconductor chip 220 overlaps the electrode 122 is the same as the area where the semiconductor chip 220 overlaps the electrode 124. The electrode pair 120 can be embedded at a position 0.1 mm to 2.0 mm below the upper surface 111 of the ceramic substrate 110. That is, the thickness of the ceramic insulating layer from the upper surface 111 of the ceramic substrate 110 to the electrode pair 120 can be 0.1 mm or more and 2.0 mm or less.

[0017] The electrodes 122 and 124 constituting the electrode pair 120 for electrostatic adsorption can be formed of a printed electrode, a mesh woven with metal wires, a foil, or a plate material. The printed electrode is a metal material with a thickness of 10 μm or more, the foil is a metal material with a thickness of less than 0.1 mm, and the plate material is a metal material with a thickness of 0.1 mm or more. As the metal material for forming the electrodes 122 and 124 constituting the electrode pair 120, for example, a heat-resistant metal (high melting point metal) such as tungsten (W) or molybdenum (Mo) can be used. In this case, the purity of tungsten and molybdenum is preferably 99% or more. Also, an alloy containing molybdenum and / or tungsten can be used as the metal material for forming the electrodes 122 and 124 constituting the electrode pair 120. The electrodes 122 and 124 constituting the electrode pair 120 can have an appropriate shape as long as the total area where they overlap the semiconductor chip 220 in the vertical direction 5 is the same for each other, as will be described later.

[0018] As shown in FIG. 3, each electrode pair 120 is arranged such that two rectangular electrodes 122 and 124 face each other with a predetermined interval therebetween. For the plurality of electrode pairs 120, the electrodes 122 are electrically conductive with each other, and the electrodes 124 are also electrically conductive with each other. By applying a predetermined voltage (for example, ±500V to ±5000V) between the electrode 122 and the electrode 124 of each electrode pair 120, the insulating panel 200 can be electrostatically adsorbed. In this embodiment, the ceramic substrate 110 and the plurality of electrode pairs 120 constitute an electrostatic chuck.

[0019] <Operation and Effect of Embodiment> In the above embodiment, the electrostatic chuck 100 is a panel electrostatic chuck used for an insulating panel 200 including a plurality of semiconductor chips 220. The electrostatic chuck 100 includes a ceramic substrate 110 having an upper surface 111 which is a main surface for placing the insulating panel 200, and a plurality of electrode pairs 120 embedded in the ceramic substrate 110. Each electrode pair 120 includes two electrodes 122 and 124. The plurality of electrode pairs 120 are arranged so as to overlap with the semiconductor chips 220 in the vertical direction 5. Generally, it is difficult for an electrostatic chuck to electrostatically adsorb an insulating substrate. However, in the electrostatic chuck 100 of this embodiment, since each electrode pair 120 is arranged such that the semiconductor chip 220 and the electrode pair 120 overlap in the vertical direction 5, the insulating panel 200 can be electrostatically adsorbed by the Coulomb force acting between the electrode pair 120 and the semiconductor chip 220 that overlap each other in the vertical direction 5. Further, for each semiconductor chip 220, the area where the semiconductor chip 220 and the electrode 122 overlap is the same as the area where the semiconductor chip 220 and the electrode 124 overlap. Thereby, a Coulomb force can be surely generated between the electrode pair 120 and the semiconductor chip 220, and the base material 210 of the insulating panel 200 can be stably electrostatically adsorbed. Also, during the process in which the Coulomb force is acting, the potential of each semiconductor chip stabilizes at the intermediate potential between the anode and the cathode, and the process is stabilized and homogenized.

[0020] <Modification> The embodiments described above are merely illustrative and can be modified as appropriate. For example, the ceramic substrate 110 does not necessarily have to be made of Al2O3 ceramics. For example, the ceramic substrate 110 can be made of a ceramic sintered body mainly composed of AlN, silicon nitride, etc.

[0021] In the above embodiment, in the insulating panel 200, the upper surfaces 221 of each semiconductor chip 220 were exposed on the upper surface 211 of the substrate 210, but the lower surfaces 222 of the semiconductor chips 220 were not exposed on the lower surface 212 of the substrate 210. However, as shown in Figure 4, the upper surfaces 221 of each semiconductor chip 220 may be exposed on the upper surface 211 of the substrate 210, and the lower surfaces 222 of the semiconductor chips 220 may be exposed on the lower surface 212 of the substrate 210. In the case of such a panel configuration, the distance between the lower surface 222 of the semiconductor chip 220 and the electrode pair 120 becomes shorter compared to the case where the lower surface 222 of the semiconductor chip 220 is not exposed on the lower surface 212 of the substrate 210. This makes it possible to increase the Coulomb force between the electrode pair 120 and the semiconductor chip 220, and to reliably electrostatically attract the substrate 210 of the insulating panel 200.

[0022] Furthermore, as shown in Figure 5, the area of ​​the upper surface 221 of the semiconductor chip 220 may be larger than the area of ​​the lower surface 222. In the case of such a panel configuration, even if the semiconductor chip 220 is pulled downward toward the electrostatic chuck 100 by electrostatic attraction, it is possible to suppress the semiconductor chip 220 from detaching from the substrate 210 and falling downward.

[0023] In the above embodiment, as shown in Figure 2, the electrode pairs 120 were arranged such that one semiconductor chip 220 and one electrode pair 120 overlapped in the vertical direction 5. However, the present invention is not limited to such an embodiment, and the electrode pairs 120 may be arranged such that one semiconductor chip 220 overlaps with multiple electrode pairs 120 in the vertical direction 5. For example, as shown in Figure 6(a), the electrode pairs 120 may be arranged such that one semiconductor chip 220 overlaps with two electrode pairs 120 in the vertical direction 5. Also, in the above embodiment, no electrode pairs 120 were arranged between two adjacent semiconductor chips 220. However, the present invention is not limited to such an embodiment, and as shown in Figures 6(b) and 6(c), a portion of the electrode pairs 120 may be arranged between two adjacent semiconductor chips 220. In either case, for each semiconductor chip 220, the sum of the overlapping areas between the semiconductor chip 220 and the electrode 122 is equal to the sum of the overlapping areas between the semiconductor chip 220 and the electrode 124. This ensures that a Coulomb force is reliably generated between the electrode pair 120 and the semiconductor chip 220, allowing for stable electrostatic adsorption of the substrate 210 of the insulating panel 200. Furthermore, during the process in which the Coulomb force is acting, the potential of each semiconductor chip stabilizes at an intermediate potential between the anode and cathode, stabilizing and homogenizing the process.

[0024] In the above embodiment, the electrode pair 120 was arranged such that the entire electrodes 122 and 124 constituting the electrode pair 120 overlapped with one semiconductor chip 220 in the vertical direction 5. However, the present invention is not limited to such an embodiment, and as shown in Figure 6(d), the electrode pair 120 may be arranged such that only a portion of the electrodes 122 and 124 constituting the electrode pair 120 overlaps with one semiconductor chip 220 in the vertical direction 5. In this case as well, since the sum of the overlapping areas of the semiconductor chip 220 and electrode 122 is the same as the sum of the overlapping areas of the semiconductor chip 220 and electrode 124, a Coulomb force can be reliably generated between the electrode pair 120 and the semiconductor chip 220, and the substrate 210 of the insulating panel 200 can be stably electrostatically attracted. Furthermore, during the process in which the Coulomb force is acting, the potential of each semiconductor chip stabilizes at an intermediate potential between the anode and cathode, stabilizing and homogenizing the process.

[0025] Although embodiments and modified versions of the invention have been described above, the technical scope of the present invention is not limited to the scope described above. It will be obvious to those skilled in the art that various modifications or improvements can be made to the above embodiments. It is also clear from the claims that such modified or improved forms may be included in the technical scope of the present invention. [Explanation of Symbols]

[0026] 100 electrostatic chucks 110 Ceramic substrate 120 electrode pairs 122, 124 electrode 200 Insulating Panels 210 Base material 220 semiconductor chips

Claims

1. An electrostatic chuck for panels used in insulating panels equipped with multiple semiconductor chips, A plate-shaped ceramic sintered body having a main surface on which the panel is placed, The ceramic sintered body is embedded in a plurality of electrode pairs, each electrode pair having an anode and a cathode, and comprises a plurality of electrode pairs. The plurality of electrode pairs are arranged such that each semiconductor chip overlaps with at least one electrode pair in the vertical direction perpendicular to the main surface. An electrostatic chuck for a panel, characterized in that the sum of the areas of the anodes and the sum of the areas of the cathodes overlapping each semiconductor chip in the vertical direction are equal to each other.

2. A plate-shaped insulating member having a first main surface and a second main surface facing the first main surface, The insulating member comprises a plurality of semiconductor chips arranged to be dispersed on the first main surface of the insulating member, An insulating panel characterized in that the plurality of semiconductor chips are exposed to the first main surface and the second main surface.

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