Multilayer ceramic electronic components

Abstract

To provide multilayer ceramic electronic components with excellent lifespan characteristics. [Solution] Multiple dielectric layers stacked along the first axis, A plurality of internal electrode layers are disposed between adjacent dielectric layers along the first axis, It has an intermediate region disposed between the dielectric layer and the internal electrode layer, The dielectric layer is of the general formula ABO 3-α It is represented as (0≦α≦1) and contains a compound having a perovskite-type structure, The aforementioned internal electrode layer contains a base metal element as its main component, The aforementioned intermediate region contains copper and copper oxide, in a multilayer ceramic electronic component.

Description

[Technical Field]

[0001] This disclosure relates to multilayer ceramic electronic components. [Background technology]

[0002] Multilayer ceramic electronic components have a structure in which dielectric layers and internal electrode layers are alternately stacked. Examples of multilayer ceramic electronic components include multilayer ceramic capacitors (MLCCs).

[0003] Multilayer ceramic capacitors, a type of multilayer ceramic electronic component, can store electricity and conduct high frequencies, and are therefore used in various electronic devices for purposes such as voltage stabilization and noise reduction. Multilayer ceramic electronic components are particularly used in communication devices such as smartphones.

[0004] Since multilayer ceramic electronic components are rarely replaced after being installed in electronic devices, they are required to have excellent lifespan characteristics. For this reason, research into multilayer ceramic electronic components with improved lifespan characteristics has been conducted for some time.

[0005] For example, Patent Document 1 discloses a ceramic electronic component comprising a laminated chip in which a plurality of dielectric layers mainly composed of ceramic and a plurality of internal electrode layers are stacked, wherein the internal electrode layers contain Ni, Sn, and Au, and a concentration gradient is formed in the thickness direction of the dielectric layer such that the concentration of Au and the concentration of Sn gradually decrease from the interface portion with the internal electrode layer toward the interior. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2023-158176 [Overview of the project] [Problems that the invention aims to solve]

[0007] However, the ceramic electronic components disclosed in Patent Document 1 require relatively expensive materials such as gold, so there was a need for novel multilayer ceramic electronic components with superior lifespan characteristics and a different material composition from conventional multilayer ceramic electronic components.

[0008] The purpose of this disclosure is to provide multilayer ceramic electronic components with excellent lifespan characteristics. [Means for solving the problem]

[0009] The multilayer ceramic electronic components disclosed herein are Multiple dielectric layers stacked along the first axis, A plurality of internal electrode layers are disposed between adjacent dielectric layers along the first axis, It has an intermediate region disposed between the dielectric layer and the internal electrode layer, The dielectric layer is of the general formula ABO 3-α It is represented as (0≦α≦1) and contains a compound having a perovskite-type structure, The aforementioned internal electrode layer contains a base metal element as its main component, The aforementioned intermediate region contains copper and copper oxide. [Effects of the Invention]

[0010] According to this disclosure, it is possible to provide multilayer ceramic electronic components with excellent lifespan characteristics. [Brief explanation of the drawing]

[0011] [Figure 1] Figure 1 is a partial cross-sectional perspective view illustrating a multilayer ceramic capacitor according to one aspect of the present disclosure. [Figure 2] Figure 2 is a cross-sectional view illustrating an example of a multilayer ceramic capacitor according to one aspect of the present disclosure. [Figure 3]FIG. 3 is a cross-sectional view illustrating a multilayer ceramic capacitor according to one aspect of the present disclosure. [Figure 4] FIG. 4 is a cross-sectional view illustrating details of a dielectric body according to one aspect of the present disclosure. [Figure 5] FIG. 5 is an enlarged schematic view of region D in FIG. 4. [Figure 6] FIG. 6 is a flowchart of a method for manufacturing a multilayer ceramic capacitor according to one aspect of the present disclosure. [Figure 7] FIG. 7 is a diagram illustrating a method for manufacturing a multilayer ceramic capacitor according to one aspect of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto. In the present specification and drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to omit redundant descriptions. In the drawings, an X-axis, a Y-axis, and a Z-axis that are orthogonal to each other are shown as appropriate. The X-axis, Y-axis, and Z-axis define a fixed coordinate system fixed to a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component. The X-axis, Y-axis, and Z-axis can correspond to the length, width, and height of the multilayer ceramic capacitor when the outer shape of the multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component, is substantially rectangular parallelepiped. Hereinafter, the multilayer ceramic electronic component of the present embodiment will be described using a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component.

[0013] [Multilayer Ceramic Electronic Component] (1) Structure of Multilayer Ceramic Electronic Component Figure 1 is a partial cross-sectional perspective view illustrating a multilayer ceramic capacitor 100. Figures 2 and 3 are cross-sectional views illustrating a multilayer ceramic capacitor. Figure 2 is a cross-sectional view along line AA in Figure 1. Figure 3 is a cross-sectional view along line BB in Figure 1. As illustrated in Figures 1 to 3, the multilayer ceramic capacitor 100 comprises a body 10 having a substantially rectangular parallelepiped shape. In the body 10, two opposing surfaces are referred to as the top surface and the bottom surface, and the four surfaces connecting the top surface and the bottom surface are referred to as sides. Usually, the surface on the circuit board side when the multilayer ceramic capacitor is mounted on a circuit board is referred to as the bottom surface, but this is not limited to this. In the example of Figures 1 to 3, the body 10 has a first external electrode 20a and a second external electrode 20b provided on the two opposing sides, the first side 10a and the second side 10b (see Figure 2). The first external electrode 20a extends from the first side 10a to the four adjacent surfaces. The second external electrode 20b extends from the second side surface 10b to four adjacent surfaces. However, the first external electrode 20a and the second external electrode 20b are spaced apart from each other. The external electrodes may be provided on any surface of the base body 10, not limited to two opposing sides.

[0014] The stacking direction in which the dielectric layer 11 and the internal electrode layer 12 are stacked is the first axis. In Figures 1 to 3, the first axis, which is the stacking direction between the dielectric layer 11 and the internal electrode layer 12, is the Z axis, and is the direction in which each internal electrode layer faces the other.

[0015] The axis perpendicular to the first axis, which is the stacking direction, is the second axis. In Figures 1 to 3, the second axis, which is perpendicular to the first axis, which is the stacking direction, is the X-axis. The second axis runs along the length of the base body 10 and is the axis that runs along the direction in which the first side surface 10a and the second side surface 10b of the base body 10 face each other, and the direction in which the first external electrode 20a and the second external electrode 20b face each other.

[0016] The axis perpendicular to the first axis, which is the stacking direction, and perpendicular to the second axis is the third axis. The third axis is the axis along the width of the internal electrode layer 12. In Figures 1 to 3, the third axis, which is perpendicular to the first axis, which is the stacking direction, and perpendicular to the second axis, is the Y axis. The third axis is the axis along the direction in which the third side 10c and the fourth side 10d, which are two of the four sides of the base body 10 other than the first side 10a and the second side 10b, face each other (see Figure 3). The X axis, Y axis, and Z axis are orthogonal to each other.

[0017] The stacking direction is not limited to the Z direction, but can be any direction. For example, the first axis, which is the stacking direction, may be the X-axis in the X direction, or the Y-axis in the Y direction.

[0018] In this specification, while diagrams illustrating a specific embodiment may be used to describe a general embodiment, the coordinate system used in one embodiment is interpreted and applied in a general embodiment as a general coordinate system with the stacking direction as the first axis. For example, what is described as the X, Y, and Z axes in Figures 1 to 3, where the stacking direction coincides with the Z direction as a specific embodiment, can be interpreted and applied in a general embodiment as the second, third, and first axes.

[0019] The element 10 has a structure in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 are alternately stacked. The internal electrode layers 12 comprise a plurality of first internal electrode layers 12a and a plurality of second internal electrode layers 12b. The first internal electrode layers 12a and the second internal electrode layers 12b are alternately stacked. The edges of the first internal electrode layers 12a are led out to the surface of the element 10 on which the first external electrode 20a is provided, in the example of Figures 1 to 3, to the first side surface 10a. The edges of the second internal electrode layers 12b are led out to the surface of the element 10 on which the second external electrode 20b is provided, in the example of Figures 1 to 3, to the second side surface 10b. As a result, the first internal electrode layers 12a and the second internal electrode layers 12b are alternately conductive to the first external electrode 20a and the second external electrode 20b. Therefore, the multilayer ceramic capacitor 100 has a structure in which capacitor units are stacked. Furthermore, in the laminate of the dielectric layer 11 and the internal electrode layer 12, the internal electrode layer 12 is arranged as the outermost layer in the stacking direction, and the outer surfaces of the laminate in the stacking direction, in the examples of Figures 1 to 3, the top and bottom surfaces, are covered by a cover layer 13. The cover layer 13 mainly consists of a ceramic material. For example, the composition of the cover layer 13 may be the same as or different from that of the dielectric layer 11. Note that the configuration is not limited to that shown in Figures 1 to 3, as long as the first internal electrode layer 12a and the second internal electrode layer 12b are exposed in different regions of the surface of the laminate and conduct to different external electrodes. Different regions of the surface of the laminate may be the respective surface regions of opposing faces of the laminate, the respective surface regions of adjacent faces of the laminate, or different surface regions of the same face of the laminate. As long as the different external electrodes are spaced apart from each other, the first internal electrode layer 12a and the second internal electrode layer 12b may extend from the surface exposed to the surface region of the laminate to other surfaces.

[0020] As will be explained in more detail later, the base body 10 has multiple intermediate regions 40 (see Figure 4) between the dielectric layer 11 and the internal electrode layer 12. The intermediate regions 40 are not shown in Figures 1 to 3.

[0021] The size of the multilayer ceramic capacitor 100 is not particularly limited, but for example, it may be 0.25 mm in length, 0.125 mm in width, and 0.125 mm in height; 0.4 mm in length, 0.2 mm in width, and 0.2 mm in height; 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height; 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height; 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height; or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height. However, the sizes listed above for the multilayer ceramic capacitor 100 are merely examples, and the multilayer ceramic capacitor is not limited to the above sizes. The size of the multilayer ceramic capacitor 100 may be, for example, length > width ≥ height, width > length ≥ height, height > length ≥ width, or height > width ≥ length. For example, length represents the size in the X-axis direction, width represents the size in the Y-axis direction, and height represents the size in the Z-axis direction.

[0022] As described above, the multilayer ceramic capacitor 100 of this embodiment has a plurality of dielectric layers 11 stacked along the first axis, the Z-axis, and a plurality of internal electrode layers 12 each positioned between adjacent dielectric layers 11 along the first axis. Furthermore, the multilayer ceramic capacitor 100 of this embodiment has an intermediate region 40 positioned between the dielectric layers 11 and the internal electrode layers 12. The dielectric layers 11, internal electrode layers 12, and intermediate region 40 will be described below. (2) Regarding the dielectric layer The dielectric layer 11 is of the general formula ABO 3-α It is represented as (0≦α≦1) and contains compounds having a perovskite-type structure. (2-1) Components contained in the dielectric layer Compounds having a perovskite structure, in the case of a stoichiometric composition, have a value of 0 for α, which represents the amount deviating from the stoichiometric composition, and are represented by the general formula ABO3. Compounds having a perovskite structure represented by the above general formula may have α greater than 0 and less than or equal to 1. In other words, compounds having a perovskite structure represented by the above general formula may have more oxygen deficiencies than the stoichiometric composition.

[0023] As compounds having a perovskite structure, barium titanate (BaTiO3), calcium zirconate (CaZrO3), calcium titanate (CaTiO3), strontium titanate (SrTiO3), magnesium titanate (MgTiO3), Ba forming a perovskite structure 1-x-y Ca x Sr y Ti 1-z Zr z One or more selected from the like such as O3 (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1) can be used.

[0024] Ba 1-x-y Ca x Sr y Ti 1-z Zr z O3 includes barium strontium titanate, barium calcium titanate, barium zirconate, barium titanium zirconate, calcium titanium zirconate, barium calcium titanium zirconate, and the like. Note that the compound having a perovskite structure may contain oxygen deficiency in any material case.

[0025] Since the dielectric layer 11 is particularly excellent in dielectric properties, as a compound having a perovskite structure, it preferably contains barium titanate, may contain barium titanate as a main component, or may be composed only of barium titanate. Barium titanate has excellent dielectric properties such as an extremely high dielectric constant and a small dielectric loss. Therefore, by containing barium titanate in the dielectric layer 11 as a compound having a perovskite structure, the capacitance of the multilayer ceramic capacitor 100 can be increased. In this specification, "contained as a main component" means that it is contained the most in terms of the molar ratio among the contained components.

[0026] Also, in the dielectric layer 11, the compound having a perovskite structure may be contained as a main component. The dielectric layer 11 may contain, for example, 50 mol% or more of a compound having a perovskite structure, or may contain 90 mol% or more. (Additives) The dielectric layer 11 may also contain additives as optional components.

[0027] The additives that the dielectric layer 11 can contain are not particularly limited, but examples include oxides containing one or more elements selected from zirconium (Zr), magnesium (Mg), molybdenum (Mo), vanadium (V), chromium (Cr), and rare earth elements (scandium (Sc), cerium (Ce), neodymium (Nd), yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)), or oxides containing one or more elements selected from cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), and silicon (Si), or glass containing one or more elements selected from cobalt, nickel, lithium, boron, sodium, potassium, and silicon. (2-2) Regarding the thickness of the dielectric layer The thickness of the dielectric layer 11 is not particularly limited, but from the viewpoint of miniaturizing the multilayer ceramic capacitor 100 while increasing the number of layers to increase capacitance, it is preferably 1.0 μm or less, and more preferably 0.8 μm or less.

[0028] The minimum thickness of the dielectric layer 11 is not particularly limited, but from the viewpoint of improving productivity and yield, it can be set to a minimum of 2 to 4 times the average diameter of the dielectric material particles used. For example, if the average diameter of the dielectric material particles used is 0.1 μm, the minimum thickness of the dielectric layer 11 can be 0.2 μm or more and 0.4 μm or less, and the thickness of the dielectric layer 11 may be, for example, 0.2 μm or more, or 0.4 μm or more.

[0029] The particle size of dielectric material particles can be defined as the Heywood diameter (the diameter of a circle with an area equal to the area of ​​the dielectric material particle being evaluated) at the observed cross-section. The average diameter, which is the average value of the dielectric material particle sizes, can be defined as the arithmetic mean of the particle sizes of 50 to 200 arbitrarily selected dielectric material particles.

[0030] When evaluating the thickness of the dielectric layer 11, the evaluation is performed in a cross-section that includes the first axis, which is equal to the stacking direction. For example, it is preferable to evaluate in a cross-section that includes either the second axis set perpendicular to the stacking direction, or the third axis set perpendicular to both the stacking direction and the second axis, due to the ease of polishing and measurement. In the former case, the multilayer ceramic capacitor 100 is polished in the third axis direction, and in the latter case, in the second axis direction. Five layers are selected from the central part, the upper end, and the lower end of the exposed dielectric layer 11 in the first axis direction. If the number of dielectric layers 11 is even, six layers are selected from the central part. Then, for each selected dielectric layer, the thickness is measured at three locations: the central part, the left end, and the right end, and the average of the measured thicknesses is taken as the thickness of each dielectric layer 11. Furthermore, the average of the thicknesses of all selected and evaluated dielectric layers 11 can be taken as the thickness of the dielectric layer 11 in the multilayer ceramic capacitor 100.

[0031] In the examples shown in Figures 1 and 2, the first axis, which is the stacking direction, is the Z-axis direction. Therefore, the multilayer ceramic capacitor 100 is polished along the third axis, the Y-axis, to expose the XZ plane where the dielectric layer 11 and the internal electrode layer 12 are stacked.

[0032] In this case, five dielectric layers 11 located in the center along the first axis (Z axis) of the exposed XZ plane are selected, and five dielectric layers 11 each are selected at the upper and lower ends along the first axis (Z axis). If the number of dielectric layers 11 is even, six layers may be selected for the central part. In this case, the dielectric layers 11 to be selected are selected from within the capacitance section 14.

[0033] Then, for each of the selected dielectric layers 11, the thickness is measured at three points along the second axis, the X-axis, at distances of 1 / 4, 1 / 2, and 3 / 4 of the length of the dielectric layer 11 along the X-axis from the edge, and the average value of these measurements is taken as the thickness of the dielectric layer 11. The same procedure is used to measure the thickness of all the selected dielectric layers 11 and evaluate the average value to obtain the thickness of the dielectric layers 11 in the multilayer ceramic capacitor 100.

[0034] The thickness of the dielectric layer 11 and the thickness of the internal electrode layer 12, described later, are measured from cross-sectional observation images of the multilayer ceramic capacitor 100. Since the intermediate region 40 is not clearly visible externally, when measuring the thickness of the dielectric layer 11 and the internal electrode layer 12, the measurement is performed based on the boundary between the dielectric layer 11 and the internal electrode layer 12 that can be visually confirmed. Therefore, the thickness of the dielectric layer 11 and the thickness of the internal electrode layer 12, described later, also include the intermediate region 40. (3) Regarding the internal electrode layer (3-1) Components contained in the internal electrode layer As illustrated in Figure 2, the region where the first internal electrode layer 12a connected to the first external electrode 20a and the second internal electrode layer 12b connected to the second external electrode 20b face each other is a region in the multilayer ceramic capacitor 100 where capacitance is generated. Therefore, the region where capacitance is generated is referred to as the capacitance region 14. In other words, the capacitance region 14 is a region where adjacent internal electrode layers face each other across a dielectric layer 11 connected to different external electrodes.

[0035] The region where the first internal electrode layers 12a connected to the first external electrode 20a face each other in the stacking direction without passing through the second internal electrode layer 12b connected to the second external electrode 20b is referred to as the first end margin 15a. Similarly, the region where the second internal electrode layers 12b connected to the second external electrode 20b face each other in the stacking direction without passing through the first internal electrode layer 12a connected to the first external electrode 20a is referred to as the second end margin 15b. Each end margin is a region where internal electrode layers connected to the same external electrode face each other in the stacking direction without passing through internal electrode layers connected to different external electrodes. The first end margin 15a and the second end margin 15b are regions where internal electrode layers 12 with equal potential face each other and are regions where no substantial capacitance is generated.

[0036] The side margin 16 is a region located outside the capacitance portion 14 in the third axis perpendicular to the stacking direction and the second axis, and in the example of Figure 3, in the direction along the Y axis. That is, the side margin 16 is the outer region adjacent to the capacitance portion 14 when viewed from the stacking direction, and is the outer region adjacent to the capacitance portion 14 on the side from which the internal electrode layer 12 is not drawn out. The side margin 16 is also a region that does not generate capacitance. (base metal) The internal electrode layer 12 can contain base metal elements as its main component.

[0037] The internal electrode layer 12 may contain components used in the internal electrode layer of a multilayer ceramic capacitor. In particular, the internal electrode layer 12 may mainly consist of a base metal such as nickel (Ni), tin (Sn), or tungsten (W), or an alloy containing one or more selected from the group of base metals, that is, it may contain the largest amount in terms of molar volume.

[0038] Because it offers excellent electrical properties and reduces costs, the internal electrode layer 12 may contain nickel as a base metal element, or it may contain nickel as the main component.

[0039] The main component of the first internal electrode layer 12a and the main component of the second internal electrode layer 12b may be the same or different. For example, the main components of both the first internal electrode layer 12a and the second internal electrode layer 12b may be the same, namely nickel. (Copper, copper oxide) According to the inventors' research, the lifetime characteristics of the multilayer ceramic capacitor 100 can be improved by including copper and copper oxide in the intermediate region described later. The copper and copper oxide can be added to a metal conductive paste or the like for forming the internal electrode layer during manufacturing.

[0040] Therefore, the internal electrode layer 12 may contain one or more elements selected from copper and copper oxide. Furthermore, copper and copper oxide may form compounds with base metal elements contained in the internal electrode layer 12 and be contained within the internal electrode layer 12.

[0041] The proportion of copper and copper oxide contained in the internal electrode layer 12 is not particularly limited and can be added and contained to the extent that an intermediate region is formed. Details of the intermediate region 40 will be described later. (3-2) Regarding the thickness of the internal electrode layer The thickness of the internal electrode layer 12 is not particularly limited, but from the viewpoint of miniaturizing the multilayer ceramic capacitor 100 while increasing the number of layers to increase capacitance, it is preferably 0.8 μm or less, and more preferably 0.6 μm or less.

[0042] The minimum thickness of the internal electrode layer 12 is not particularly limited, but from the viewpoint of improving productivity and yield, it can be set to 0.4 μm or more when formed by printing a metal conductive paste using methods such as screen printing or gravure printing. For example, when formed by thin-film processes such as sputtering or vapor deposition, it can be set to a thinner thickness of 0.1 μm or more than that achieved by printing methods. When evaluating the thickness of the internal electrode layer 12, the evaluation is performed in a cross-section that includes a first axis equal to the stacking direction, similar to the evaluation of the thickness of the dielectric layer 11. For example, it is preferable to evaluate in a cross-section that further includes a second axis set perpendicular to the stacking direction, or a cross-section that further includes a third axis set perpendicular to both the stacking direction and the second axis, due to the ease of polishing and measurement.

[0043] The multilayer ceramic capacitor 100 is polished so that the above cross-section is visible, and five layers are selected from the central, upper, and lower ends of the exposed internal electrode layer 12 in the first axial direction. If the number of layers in the internal electrode layer 12 is even, six layers are selected from the central part. Then, the thickness of each selected internal electrode layer 12 is measured at three locations: the central part, the left end, and the right end, and the average of the measured thicknesses is taken as the thickness of each internal electrode layer 12. Furthermore, the average of the thicknesses of all the selected and evaluated internal electrode layers 12 can be taken as the thickness of the internal electrode layer 12 in the multilayer ceramic capacitor 100.

[0044] In the examples shown in Figures 1 and 2, the first axis, which is the stacking direction, is the Z-axis direction. Therefore, the multilayer ceramic capacitor 100 is polished along the Y-axis to expose the XZ plane where the dielectric layer 11 and the internal electrode layer 12 are stacked. In this case, from the XZ plane exposed by polishing, five internal electrode layers 12 located in the center along the first axis (Z-axis) are selected, and five internal electrode layers 12 located at the upper and lower ends along the first axis (Z-axis) are selected. If the number of internal electrode layers 12 is even, six layers may be selected in the central part. In this case, the selected internal electrode layers 12 are selected from within the capacitance section 14.

[0045] Then, for each selected internal electrode layer 12, the thickness is measured at three points along the second axis, the X-axis, at distances of 1 / 4, 1 / 2, and 3 / 4 of the length of the internal electrode layer 12 along the X-axis from the end, and the average value of these measurements is taken as the thickness of the internal electrode layer 12. By the same procedure, the thickness of all selected internal electrode layers 12 is measured, and the average value of the thicknesses of all selected and evaluated internal electrode layers 12 can be taken as the thickness of the internal electrode layers 12 in the evaluated multilayer ceramic capacitor 100. (4) Regarding the intermediate area Figure 4 shows a magnified view of a portion of the dielectric layer 11 and internal electrode layer 12 of the base body 10. Figure 4 is, for example, a magnified view of region C in Figure 3.

[0046] The multilayer ceramic capacitor 100 has an intermediate region 40 disposed between the dielectric layer 11 and the internal electrode layer 12. The intermediate region 40 may contain copper and copper oxide.

[0047] Figure 4 is a schematic diagram, and therefore the intermediate region 40 is shown as having a constant thickness and as a continuous layer, but it is not limited to this configuration. The intermediate region 40 may be discontinuous, for example, and its thickness may vary depending on the location.

[0048] The presence or absence of the intermediate region 40 can be confirmed using 3DAP (3-dimensional atom probe) analysis. Specifically, for example, a sample prepared to include the interface between the dielectric layer 11 and the internal electrode layer 12 can be subjected to line analysis using 3D AP analysis along the stacking direction of the dielectric layer 11 and the internal electrode layer 12. From the results of the line analysis, the region in which the relative concentration of base metal elements contained in the internal electrode layer 12 is 90 at% or more can be identified as the internal electrode layer 12. From the results of the line analysis, the region in which the relative concentration of base metal elements contained in the internal electrode layer 12 is 5 at% or less can be identified as the dielectric layer 11. From the results of the line analysis, the region in which the relative concentration of base metal elements contained in the internal electrode layer 12 is greater than 5 at% but less than 90 at% can be identified as a region that may be the intermediate region 40.

[0049] Furthermore, if it can be confirmed that copper and copper oxide are distributed within a region that could be an intermediate region 40 between the dielectric layer 11 and the internal electrode layer 12, then the region that could be an intermediate region 40 can be determined to be an intermediate region 40. In other words, it can be determined that it has an intermediate region 40. If at least one of copper and copper oxide is not distributed within the region that has been determined to be an intermediate region 40, then it is not determined to be an intermediate region 40, and it can be determined that it does not have an intermediate region 40.

[0050] The intermediate region 40 may contain copper and copper oxide. The copper is in its metallic state, i.e., elemental copper.

[0051] When the multilayer ceramic capacitor 100 is held under DC bias for a long period of time, oxygen vacancies that act as donors move to the negative electrode side, and the dielectric on the negative electrode side where oxygen vacancies have accumulated exhibits n-type electrical conductivity. At the same time, the oxygen vacancies disappear from the dielectric on the positive electrode side, which is located opposite the negative electrode. At this time, the acceptors that were added to reduce leakage current at the oxygen vacancies and that had been neutralized by bonding with the oxygen vacancies are activated, and the dielectric exhibits p-type electrical conductivity.

[0052] In the multilayer ceramic capacitor 100 of this embodiment, as described above, there is an intermediate region 40 between the dielectric layer 11 and the internal electrode layer 12, and the intermediate region 40 contains copper (Cu) and copper oxide (CuO). It is thought that the copper (Cu) contained in the intermediate region 40 acts as a barrier to n-type electrical conduction, and the copper oxide acts as a barrier to p-type electrical conduction. For this reason, in the multilayer ceramic capacitor 100 of this embodiment, it is possible to reduce the increase in leakage current even after applying voltage for a long period of time, and it is thought that failure of the multilayer ceramic capacitor 100 can be prevented. As a result, the multilayer ceramic capacitor of this embodiment can be made into a multilayer ceramic electronic component with excellent lifespan characteristics.

[0053] Since the multilayer ceramic capacitor 100 is typically used as a non-polarized capacitor, separating the positive and negative electrodes and adding copper and copper oxide to each would increase the burden on the user when mounting it in electronic devices.

[0054] In the multilayer ceramic capacitor of this embodiment, an intermediate region 40 is placed between the dielectric layer 11 and the internal electrode layer 12 without distinguishing between positive and negative electrodes, and the intermediate region 40 contains copper and copper oxide. Therefore, the multilayer ceramic capacitor 100 can be used without distinguishing between polarities during mounting, thereby preventing an increase in the burden on the user.

[0055] Furthermore, according to the inventors' research, it is believed that in the multilayer ceramic capacitor 100, the causes of degradation occur locally and simultaneously at multiple locations, leading to the progression of degradation.

[0056] In contrast, in the multilayer ceramic capacitor 100 of this embodiment, copper and copper oxide, which act as barriers to electrical conduction, are distributed within the intermediate region 40. Therefore, a barrier exists at the corresponding location for localized degradation, preventing the spread of degradation and, as a result, extending the lifespan of the multilayer ceramic capacitor and improving its lifespan characteristics. (4-1) About copper and copper oxide (Regarding distribution) The distribution of copper and copper oxide in the intermediate region 40 is not particularly limited. For example, copper and copper oxide may be mixed and distributed throughout the entire intermediate region 40, or at least a portion of the region may contain copper and region contain copper oxide independently without mixing.

[0057] Figure 5(A) shows a schematic diagram of a magnified view of region D, which is part of the intermediate region 40 in Figure 4. As shown in Figure 5(A), within the intermediate region 40, the region 51 containing copper and the region 52 containing copper oxide may exist independently of each other. In this case, since the region 51 containing copper and the region 52 containing copper oxide exist independently of each other, they can be said to be distributed in an island-like manner. In Figure 5(A), the region 51 containing copper and the region 52 containing copper oxide are shown as circles or ellipses, but they are not limited to these forms and can be any shape. In Figure 5(A), due to space limitations, only one selected region is labeled, but the same hatched shapes represent the region 51 containing copper or the region 52 containing copper oxide, respectively.

[0058] Within the intermediate region 40, the copper-containing region 51 and the copper oxide-containing region 52 exist independently of each other. This allows the copper-containing region 51 and the copper oxide-containing region 52 to function as barriers to n-type and p-type electrical conduction, respectively. Therefore, the lifetime characteristics of the multilayer ceramic capacitor in this embodiment can be particularly enhanced.

[0059] The size of each region is not particularly limited, but for example, the average value of the major axis L51 of the copper-containing region 51 and the average value of the major axis L52 of the copper oxide-containing region 52 may both be between 1 nm and 20 nm.

[0060] By setting the average value of the major axis L51 of the copper-containing region 51 and the average value of the major axis L52 of the copper oxide-containing region 52 to 1 nm or more, it can function as a particularly high barrier against electrical conductivity.

[0061] By setting the average value of the major axis L51 of the copper-containing region 51 and the average value of the major axis L52 of the copper oxide-containing region 52 to 20 nm or less, the copper-containing region 51 and the copper oxide-containing region 52 can be densely packed within the intermediate region 40. Therefore, the intermediate region 40 can be made into a barrier with particularly high performance against electrical conductivity.

[0062] The method for measuring the average length L51 of the copper-containing region 51 and the average length L52 of the copper oxide-containing region 52 is not particularly limited. For example, the length axes of two or more regions can be evaluated for each of the copper-containing region 51 and the copper oxide-containing region 52, which are contained within a region of at least 30 μm × 30 μm × 50 μm, after 3D atomic probe analysis. Then, for example, the average value of the length L51 of two or more regions measured for the copper-containing region 51 can be taken as the average length L51 of the copper-containing region 51. Similarly, for example, the average value of the length L52 of two or more regions measured for the copper oxide-containing region 52 can be taken as the average length L52 of the copper oxide-containing region 52. The upper limit of the number of regions measured when determining the average length of each region is not particularly limited, but for example, it can be 50 or less for each. The average length L51 of the copper-containing region 51 and the average length L52 of the copper oxide-containing region 52 may be the same or different.

[0063] The copper-containing region 51 and the copper oxide-containing region 52 may each be formed by particles, but they may also be formed by aggregates of multiple particles, for example.

[0064] Furthermore, the copper-containing region 51 and the copper oxide-containing region 52 may have a layered structure.

[0065] In other words, as shown in Figure 5(B), a copper-containing layer 51A, which is a copper-containing region 51, and a copper oxide-containing layer 52A, which is a copper oxide-containing region 52, can be stacked. In Figure 5(B), an example is shown where the intermediate region 40 has one copper-containing layer 51A and one copper oxide-containing layer 52A, but it is not limited to this form. The intermediate region 40 can also have multiple copper-containing layers 51A and multiple copper oxide-containing layers 52A.

[0066] Because the copper-containing region 51 and the copper oxide-containing region 52 have a layered structure, the intermediate region 40 can function as a uniform barrier to electrical conduction between the dielectric layer 11 and the internal electrode layer 12. Therefore, it is believed that the layered structure of the copper-containing region 51 and the copper oxide-containing region 52 can particularly improve the lifespan characteristics of the multilayer ceramic capacitor 100 of this embodiment.

[0067] The thickness T51A of the copper-containing layer 51A and the thickness T52A of the copper oxide-containing layer 52A are not particularly limited. For example, the thickness T51A of the copper-containing layer 51A may be between 1 nm and 10 nm. Similarly, the thickness T52A of the copper oxide-containing layer 52A may be between 1 nm and 10 nm.

[0068] By setting the thickness T51A of the copper-containing layer 51A and the thickness T52A of the copper oxide-containing layer 52A to 1 nm or more, they can function as particularly high barriers against electrical conductivity.

[0069] By setting the thickness T51A of the copper-containing layer 51A and the thickness T52A of the copper oxide-containing layer 52A to 10 nm or less, the intermediate region 40 can be made into a barrier with particularly high performance against electrical conductivity.

[0070] The method for measuring the thickness T51A of the copper-containing layer 51A and the thickness T52A of the copper oxide-containing layer 52A is not particularly limited.

[0071] The thickness T51A of the copper-containing layer 51A and the thickness T52A of the copper oxide-containing layer 52A can be measured, for example, using three-dimensional atomic probe analysis. Specifically, for a sample prepared to include the interface between the dielectric layer 11 and the internal electrode layer 12, line analysis can be performed using three-dimensional atomic probe analysis along the stacking direction of the dielectric layer 11 and the internal electrode layer 12.

[0072] Then, based on the line analysis results, the thickness in the stacking direction of the region where copper is distributed within the region identified as the intermediate region 40 can be measured at two or more non-overlapping points, and the average value can be taken as the thickness T51A of the copper-containing layer 51A.

[0073] Furthermore, based on the line analysis results, the thickness in the stacking direction of the region where copper oxide is distributed within the region identified as the intermediate region 40 can be measured at two or more non-overlapping points, and the average value can be taken as the thickness T52A of the layer 52A containing copper oxide.

[0074] The method for identifying the intermediate region 40 can be carried out using the same procedure as the method for determining the presence or absence of the intermediate region 40, and has already been explained, so the explanation will be omitted. Furthermore, the stacking direction mentioned above refers to the stacking direction between the dielectric layer 11 and the internal electrode layer 12.

[0075] Furthermore, the fact that the copper-containing region 51 and the copper oxide-containing region 52 have a layered shape means that, for example, line analysis using the above-mentioned three-dimensional atomic probe analysis can be performed at multiple adjacent, non-overlapping locations, for example The determination can be made by conducting the test at three or more locations.

[0076] The arrangement of the copper-containing layer 51A and the copper oxide-containing layer 52A is not particularly limited, but for example, the copper-containing layer 51A and the copper oxide-containing layer 52A may be arranged in order from a position close to the internal electrode layer 12. The distribution of the copper-containing layer 51A and the copper oxide-containing layer 52A may be determined, for example, by three-dimensional atomic probe analysis, but is not limited to this form. For example, it may be confirmed by elemental mapping using energy-dispersive X-ray (EDX) analysis with a transmission electron microscope (TEM) or scanning transmission electron microscope (SEM).

[0077] TEM stands for transmission electron microscope, and SEM stands for Scanning Transmission Electron Microscope. EDX stands for energy dispersive X-ray spectroscopy.

[0078] TEM / SEM-EDX evaluation can be performed in a cross-section that includes a first axis equal to the stacking direction. For example, evaluation in a cross-section that further includes a second axis set perpendicular to the stacking direction, or a cross-section that further includes a third axis set perpendicular to both the stacking direction and the second axis, is preferable due to the ease of polishing and measurement. In the example shown in Figures 1 and 2, the first axis, which is the stacking direction, is the Z-axis direction, so the multilayer ceramic capacitor 100 is polished along the Y-axis, which is the third axis, to expose the XZ plane where the dielectric layer 11 and the internal electrode layer 12 are stacked. Then, by performing TEM / STEM-EDX analysis on a sample thinned to a thickness of about 0.1 μm, the distribution of the copper-containing layer 51A and the copper oxide-containing layer 52A within the intermediate region 40 can be confirmed. The distribution of the base metal-copper alloy layers below may also be identified using the same method. (Regarding concentration) The ratio of copper to copper oxide concentrations contained in the intermediate region 40 is not particularly limited.

[0079] For example, the ratio of the copper concentration to the copper oxide concentration in the intermediate region 40 may be 100% or more and 200% or less.

[0080] By setting the ratio of copper concentration to copper oxide concentration in the intermediate region 40 to 100% or more and 200% or less, the intermediate region 40 can function as a well-balanced barrier against n-type and p-type electrical conduction, thereby particularly improving the lifespan characteristics of the multilayer ceramic capacitor 100.

[0081] The method for measuring the ratio of copper concentration to copper oxide concentration in the intermediate region 40 is not particularly limited. Within the intermediate region 40, for example, the concentration of copper and the concentration of copper oxide can be evaluated in a region of at least 30 μm × 30 μm × 10 μm where three-dimensional atomic probe analysis has been performed. Both the concentration of copper and the concentration of copper oxide can be determined in at%. Then, the ratio of the concentration of copper to the determined concentration of copper oxide can be calculated. The ratio of the concentration of copper to the concentration of copper oxide can be calculated using the following formula, where the concentration of copper oxide is CuO and the concentration of copper is Cu.

[0082] (Ratio of copper concentration to copper oxide concentration) = Cu / CuO × 100 (4-2) Base metal-copper alloys The intermediate region 40 may also contain components other than copper and copper oxide. For example, copper or copper oxide may react with the base metal contained in the internal electrode layer 12 to form a base metal-copper alloy, and the intermediate region 40 may also contain a base metal-copper alloy.

[0083] As previously mentioned, nickel may be used as the base metal, so the intermediate region 40 may contain, for example, a nickel-copper alloy (Ni-Cu alloy) as a base metal-copper alloy.

[0084] The inclusion of a base metal-copper alloy in the intermediate region 40 reduces the penetration of hydrogen into the dielectric layer 11, thereby improving the moisture resistance of the multilayer ceramic capacitor.

[0085] For example, in Figure 5(A), a region containing a base metal-copper alloy may be included independently within the intermediate region 40, separate from the copper-containing region 51 and the copper oxide-containing region 52. Alternatively, the region containing the base metal-copper alloy may be mixed and distributed within one or more regions selected from the copper-containing region 51 and the copper oxide-containing region 52.

[0086] For example, as shown in Figure 5(C), the intermediate region 40 can also have a structure in which a layer 53 containing a base metal-copper alloy, a layer 51A containing copper, and a layer 52A containing copper oxide are stacked.

[0087] The arrangement of each layer is not particularly limited, but for example, a layer 53 containing a base metal-copper alloy, a layer 51A containing copper, and a layer 52A containing copper oxide may be arranged in order from a position close to the internal electrode layer 12.

[0088] [Manufacturing method for multilayer ceramic capacitors] Next, the manufacturing method of the multilayer ceramic capacitor 100 will be described. Figure 6 is a flowchart 60 illustrating the manufacturing method of the multilayer ceramic capacitor 100. Figure 7 is a diagram illustrating the manufacturing method of the multilayer ceramic capacitor 100. (1) Raw material powder preparation process (S1) In the raw material powder preparation process, first, dielectric material for forming the dielectric layer 11 is prepared. The A-site element and B-site element contained in the dielectric layer 11 are usually ABO 3-α The dielectric layer 11 is contained in the form of a sintered body of particles with (0≦α≦1). For example, barium titanate is a tetragonal compound having a perovskite-type structure and exhibits a high dielectric constant. Barium titanate can generally be obtained by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. Various methods have been conventionally known for synthesizing the main component ceramic of the dielectric layer 11, such as the solid-phase method, the sol-gel method, and the hydrothermal method. In this embodiment, any of these can be employed.

[0089] In the raw material powder preparation process, predetermined additive compounds can be added to the obtained ceramic raw material powder depending on the purpose. Examples of additive compounds include oxides containing one or more elements selected from zirconium (Zr), magnesium (Mg), molybdenum (Mo), vanadium (V), chromium (Cr), and rare earth elements (scandium (Sc), cerium (Ce), neodymium (Nd), yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)), or oxides containing one or more elements selected from cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), and silicon (Si), or glasses containing one or more elements selected from cobalt, nickel, lithium, boron, sodium, potassium, and silicon.

[0090] For example, ceramic materials can be prepared by wet-mixing ceramic raw material powder with additives containing manganese or compounds containing additive compounds, followed by drying and pulverization. For example, the ceramic material obtained as described above may be subjected to pulverization as needed to adjust the particle size, or the particle size may be adjusted by combining this with a classification process. A dielectric material can be obtained through the above steps. (2) Dielectric green sheet formation process (S2) In the dielectric green sheet formation process, the raw material powder obtained in the raw material powder preparation process can be wet-mixed with a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer. Alternatively, the binder may be added at the same time as mixing the ceramic raw material powder in the raw material powder preparation process (S1), and then wet-mixed.

[0091] In the dielectric green sheet formation process, the obtained slurry can be used to coat a substrate using, for example, a die coater method or a doctor blade method, and then dried to form a dielectric green sheet. The substrate is, for example, polyethylene terephthalate (PET) film. A diagram illustrating the dielectric green sheet formation process has been omitted.

[0092] Therefore, the dielectric green sheet formation process (S2) is based on the general formula ABO 3-α A dielectric green sheet containing a dielectric with a perovskite structure represented by (0 ≤ α ≤ 1) can be formed. (3) Internal electrode layer formation process (S3) The first internal electrode layer 12a and the second internal electrode layer 12b may be primarily composed of one or more base metals selected from nickel (Ni), tin (Sn), tungsten (W), and alloys containing these metals. In addition to the above main components, the internal electrode layer 12 may also contain copper or copper oxide.

[0093] The main component of the first internal electrode layer 12a and the main component of the second internal electrode layer 12b may be the same or different. For example, the main components of both the first internal electrode layer 12a and the second internal electrode layer 12b may be the same, namely nickel.

[0094] The metal conductive paste for forming the precursors of the first internal electrode layer 12a and the second internal electrode layer 12b can be prepared by kneading a selected main component, copper, copper oxide, an organic binder, and a solvent. Copper may be added in elemental form. Copper oxide may also be added in copper oxide form.

[0095] In the internal electrode layer formation process, as illustrated in Figure 7(A), a metal conductive paste for forming the internal electrode layer, containing an organic binder, can be printed onto the surface of the dielectric green sheet 71 by screen printing, gravure printing, or the like. Examples of organic binders include ethyl cellulose (EC) and polyvinyl butyral (PVB) resin. This arranges a first internal electrode layer pattern 72a for the first internal electrode layer 12a or a second internal electrode layer pattern 72b for the second internal electrode layer 12b on the surface of the dielectric green sheet 71. Various auxiliary agents, such as dispersants, and ceramic particles as co-materials can also be added to the metal conductive paste. The main component of the ceramic particles is not particularly limited, but it is preferable that it be the same as the main ceramic component of the dielectric layer 11. When ceramic particles are added as co-materials, they can be added during the mixing of the metal conductive paste. The method for forming the internal electrode layer is not limited to printing; plating, vacuum deposition, sputtering, and CVD methods may also be used.

[0096] Alternatively, a dielectric pattern paste for the reverse pattern layer can be obtained by adding a binder such as ethyl cellulose and an organic solvent such as terpineol to the dielectric pattern material obtained in the raw material powder preparation process and kneading it in a roll mill. Then, as illustrated in Figure 7(A), the dielectric pattern 73 may be placed on the dielectric green sheet 71 by printing the dielectric pattern paste in the peripheral area where the internal electrode layer pattern is not printed, thereby filling the step difference with the internal electrode layer pattern. The dielectric green sheet 71 with the internal electrode layer pattern and dielectric pattern 73 printed on it is referred to as a laminated unit.

[0097] (4) Lamination process (S4) In the lamination process, as illustrated in Figure 7(B), the lamination units can be stacked such that the internal electrode layers and dielectric layers are staggered, and the edges of the internal electrode layers are alternately exposed on both ends of the dielectric layer in the longitudinal direction, alternately leading out to a pair of external electrodes. Specifically, a dielectric green sheet 71 printed with a first internal electrode layer pattern 72a and a dielectric pattern 73 is stacked in sequence with a dielectric green sheet 71 printed with a second internal electrode layer pattern 72b and a dielectric pattern 73. For example, the number of layers in the lamination unit can be 100 to 500. (5) Crimping process (S5) In the heat-sealing process, a predetermined number of cover sheets, for example, 2 to 10 layers, can be heat-sealed to the top and bottom of the laminated body in which the laminated units are stacked. (6) Singulation process (S6) In the individualization process, the crimped body is separated into individual pieces, and a laminate of individual pieces can be obtained. Existing methods such as dicing with a dicer or laser cutting can be used as appropriate for individualization. (7) Firing process (S7) In the firing process, the individual laminated pieces can be degreased and then fired. The degreasing and firing processes may be performed consecutively or separately. The conditions for degreasing and firing are not particularly limited. For example, degreasing may be performed in a nitrogen atmosphere at a temperature between 250°C and 500°C.

[0098] For firing, for example, if the oxygen partial pressure is 10 -12 atm over 10 -8 The firing may be carried out in a weakly oxidizing atmosphere or a reducing atmosphere with a temperature range of 1100°C to 1350°C, below atm, for 5 minutes to 10 hours. The oxygen partial pressure is preferably 10 -12 atm over 10 -10 It may also be set to atm or less.

[0099] When a reducing atmosphere is used, one or more reducing gases selected from hydrogen and carbon monoxide can be used. The reducing gas may also be an inert gas, such as nitrogen, or a mixed gas with a noble gas. Examples of noble gases include helium and argon. By using a weakly oxidizing atmosphere or a reducing atmosphere, especially a strongly reducing atmosphere, during calcination, an intermediate region containing copper and copper oxide can be formed.

[0100] The firing temperature range may preferably be 1150°C to 1350°C. The firing time may preferably be 5 minutes to less than 15 minutes.

[0101] In the manufacturing of multilayer ceramic capacitors, a re-oxidation treatment may be performed in a nitrogen atmosphere at a temperature of 600°C to 1000°C after firing. However, in the manufacturing method of the multilayer ceramic capacitor of this embodiment, it is preferable to omit, or not perform, the above re-oxidation treatment. (8) External electrode formation process (S8) In the external electrode formation process, a metal conductive paste for forming the external electrode layer, containing a base metal such as nickel as a main component, a metal such as copper, and an organic binder, can be formed by screen printing, dipping, etc., and then baked. The method of forming the external electrode is not limited to printing or dipping; plating, vacuum deposition, sputtering, or CVD methods may also be used. Alternatively, a conductive resin paste may be formed by screen printing, dipping, etc., and the resin may be cured. If necessary, layers of copper, nickel, or tin may be formed by plating or other treatments. This allows for the formation of the first external electrode 20a and the second external electrode 20b. Through the above process, a multilayer ceramic capacitor 100 can be manufactured.

[0102] The above process is merely an example, and the manufacturing method of the multilayer ceramic capacitor of this embodiment is not limited to the above configuration. For example, the base layer for the external electrodes can be provided on the surface of the fragmented laminate, and the external electrodes can be formed by firing the ceramic simultaneously with the firing of the base layer for the external electrodes. In this case, in the external electrode formation process after firing, the external electrodes are completed by forming layers of copper, nickel, or tin on top of this base layer through a plating process.

[0103] [Other embodiments] Although embodiments have been described in detail above, this disclosure is not limited to any particular embodiment, and various modifications and changes are possible within the scope of the claims.

[0104] For example, although the above embodiment is applied to a multilayer ceramic capacitor with two terminal electrodes, it may also be applied to a multilayer ceramic capacitor with three or more terminals. [Examples]

[0105] The present invention will be described with specific examples below, but it is not limited to these examples.

[0106] The present invention will be described with specific examples below, but it is not limited to these examples. (1) Evaluation method (1-1) Three-dimensional atomic probe analysis For 3D atomic probe analysis, needle-shaped samples with a tip diameter of 50 nm to 100 nm, including the vicinity of the interface between the dielectric layer 11 and the internal electrode layer 12, were fabricated using FIB based on the multilayer ceramic capacitors prepared in each example and comparative example. Then, a high electric field was applied to the tip of the needle-shaped sample, and a laser pulse was added to ionize the sample surface. 3D atomic probe analysis was then performed by analyzing the atomic distribution using a secondary detector.

[0107] A LEAP5000XS (AMETEK) was used as the 3D atomic probe analyzer. The wavelength of the laser pulse applied to the needle-shaped sample was set to 355 nm.

[0108] The presence or absence of the intermediate region 40 was determined by the following procedure.

[0109] Line analysis was performed on the fabricated needle-shaped samples using three-dimensional atomic probe analysis along the stacking direction of the dielectric layer 11 and the internal electrode layer 12. From the results of the line analysis, the region in which the relative concentration of base metal elements contained in the internal electrode layer 12 was 90 at% or more was defined as the internal electrode layer 12. The region in which the relative concentration of base metal elements contained in the internal electrode layer 12 was 5 at% or less was defined as the dielectric layer 11. Furthermore, the region in the internal electrode layer 12 where the relative concentration of base metal elements was greater than 5 at% but less than 90 at% was defined as the region that could become the intermediate region 40.

[0110] Based on the line analysis results, if it was confirmed that copper and copper oxide were distributed within a region that could be an intermediate region 40 between the dielectric layer 11 and the internal electrode layer 12, the region was determined to be an intermediate region 40. If at least one of copper and copper oxide was not distributed within the region that was determined to be an intermediate region 40, it was not determined to be an intermediate region 40, and it was determined that there was no intermediate region 40.

[0111] The relative concentrations of each element were calculated so that the sum of the elements detected by 3D atomic probe analysis—Ba, Ti, O, Cu, and Ni—was 100 at%. (1-2) Accelerated life testing For each example and comparative example, 50 samples of multilayer ceramic capacitors were prepared. Accelerated lifetime testing (HALT) was then performed on each of the selected samples. In the HALT test, a voltage of 10V was applied to each of the 50 samples manufactured under the same conditions in a 125°C constant temperature chamber, and the time until insulation degradation was measured.

[0112] During the evaluation, insulation resistance was measured, and if the insulation resistance value fell below 1 MΩ, it was determined that insulation degradation had occurred.

[0113] The average time until insulation degradation was obtained for the 50 samples evaluated, and this was used to determine the time until insulation degradation, or lifespan, for each example and comparative example sample.

[0114] The evaluation results are shown in the "Lifespan" column of Table 1. A higher number indicates better lifespan characteristics.

[0115] If the estimated lifespan was 500 minutes or more, the lifespan was judged as ○. If the estimated lifespan was less than 500 minutes, the lifespan was judged as ×.

[0116] If the lifespan assessment is "○", it can be said that it is a multilayer ceramic capacitor with excellent lifespan characteristics. (2) Conditions for preparing the sample [Example 1] (2-1) Raw material powder preparation process A multilayer ceramic capacitor was manufactured according to the flowchart 60 shown in Figure 6.

[0117] Specifically, a slurry was first obtained by wet-mixing barium titanate powder, polyvinyl butyral (PVB) resin, a solvent, a plasticizer, and glass powder containing SiO2 as a sintering aid. (2-2) Dielectric Green Sheet Formation Process The obtained slurry was coated onto a base film, and the slurry coated onto the base film was dried to obtain a dielectric green sheet. (2-3) Internal electrode layer formation process Next, copper powder and copper oxide powder were added to nickel powder, the main metal element, and mixed to prepare a mixed powder. Ethyl cellulose (EC) or polyvinyl butyral (PVB) resin as a binder, along with a solvent and a plasticizer, were added to the prepared mixed powder and wet-mixed to obtain a metal conductive paste for forming the internal electrode layer. Then, the metal conductive paste was printed onto a portion of the surface of a dielectric green sheet to form an internal electrode layer pattern on each dielectric green sheet containing nickel, copper, and copper oxide as the main base metal elements.

[0118] A laminated unit was fabricated by the dielectric green sheet formation process and the internal electrode layer formation process described above. The obtained laminated unit comprises a dielectric green sheet and an internal electrode layer pattern formed on the surface of the dielectric green sheet. (2-4) Lamination process Next, 500 stacking units were stacked to form a laminate. (2-5) Crimping process, individual piece formation process Then, after the laminate was compressed, it was separated into individual pieces to obtain chip-shaped green laminates. (2-6) Firing process Next, this chip-shaped green laminate was degreased in a nitrogen atmosphere at 500°C.

[0119] After degreasing, a metal conductive paste containing nickel-based metal fillers, a binder, and a solvent was applied to the green laminate from both ends to each side as a base layer, and then dried. Subsequently, the green laminate with the base layer for the external electrodes was placed in a firing furnace and fired.

[0120] During the firing process, the oxygen partial pressure is 1.0 × 10⁻⁶. -10 The material was heated to 1300°C for 10 seconds under a reducing atmosphere, which is a mixture of hydrogen and nitrogen at an atm temperature. During the heating process, the supply rate of the green laminate and the oxygen partial pressure were adjusted to prevent abrupt changes in the firing atmosphere due to gases generated from the green laminate and to prevent cracks from forming in the fired product. (2-7) External electrode formation process A first external electrode 20a and a second external electrode 20b were formed on the laminated body after firing by plating.

[0121] The resulting multilayer ceramic capacitor had a chip shape of 1.0 mm × 0.5 mm × 0.5 mm, a dielectric layer 11 thickness of 0.8 μm, an internal electrode layer 12 thickness of 0.6 μm, and 500 layers. The thicknesses of the dielectric layer 11 and the internal electrode layer 12 were evaluated using the procedure already described.

[0122] The obtained multilayer ceramic capacitors were evaluated as described above. The evaluation results are shown in Table 1. [Comparative Example 1] A multilayer ceramic capacitor was fabricated and evaluated using the same procedure as in Example 1, except that copper powder and copper oxide powder were not added or mixed to the Ni powder, which is the main metal element, during the internal electrode layer formation process. The evaluation results are shown in Table 1. [Comparative Example 2] In the internal electrode layer formation process, copper powder was added and mixed with Ni powder, the main component metal element, but copper oxide powder was not added or mixed. Except for the above, a multilayer ceramic capacitor was fabricated and evaluated using the same procedure as in Example 1. The evaluation results are shown in Table 1. [Comparative Example 3] In the internal electrode layer formation process, copper oxide powder was added and mixed with Ni powder, the main component metal element, but copper powder was not added or mixed. Except for the above, a multilayer ceramic capacitor was fabricated and evaluated using the same procedure as in Example 1. The evaluation results are shown in Table 1.

[0123] [Table 1] According to Table 1, in Example 1, which has an intermediate region 40 disposed between the dielectric layer 11 and the internal electrode layer 12, and in which the intermediate region 40 contains copper and copper oxide, it was confirmed that the lifetime characteristics were higher compared to Comparative Examples 1 to 3, which do not have the intermediate region 40.

[0124] In Comparative Examples 2 and 3, although regions containing either copper or copper oxide were identified between the dielectric layer 11 and the internal electrode layer 12, neither copper nor copper oxide could be found within these regions.

[0125] In Comparative Examples 2 and 3, as described above, regions containing either copper or copper oxide were confirmed between the dielectric layer 11 and the internal electrode layer 12, but it was confirmed that the lifetime characteristics were inferior compared to Example 1.

[0126] The aspects of this disclosure are, for example, as follows:

[0127] <1> Multiple dielectric layers stacked along the first axis, A plurality of internal electrode layers are disposed between adjacent dielectric layers along the first axis, It has an intermediate region disposed between the dielectric layer and the internal electrode layer, The dielectric layer is of the general formula ABO 3-α It is represented as (0≦α≦1) and contains a compound having a perovskite-type structure, The aforementioned internal electrode layer contains a base metal element as its main component, The aforementioned intermediate region contains copper and copper oxide, in a multilayer ceramic electronic component.

[0128] <2> Within the aforementioned intermediate region, the region containing copper and the region containing copper oxide exist independently of each other. <1> Multilayer ceramic electronic components as described above.

[0129] <3> The average value of the major axis of the region containing copper and the average value of the major axis of the region containing copper oxide are both between 1 nm and 20 nm. <2> Multilayer ceramic electronic components as described above.

[0130] <4> The region containing copper and the region containing copper oxide have a layered shape. <2> Multilayer ceramic electronic components as described above.

[0131] <5> In the aforementioned intermediate region, the ratio of the concentration of copper to the concentration of copper oxide is 100% or more and 200% or less. <1> from <4> A multilayer ceramic electronic component as described in any of the following.

[0132] <6> The internal electrode layer contains nickel as the base metal element. <1> from <5> A multilayer ceramic electronic component as described in any of the following.

[0133] <7> The dielectric layer contains barium titanate as the compound having the perovskite-type structure. <1> from <6> A multilayer ceramic electronic component as described in any of the following. [Explanation of Symbols]

[0134] 100 Multilayer Ceramic Capacitors 10 Base Body 10a First side 10b Second side 11 Dielectric layer 12 Internal electrode layer 12a 1st internal electrode layer 12b Second internal electrode layer 13. Cover layer 14 Capacity part 15a First end margin 15b Second End Margin 16 Side margins 20a 1st external electrode 20b 2nd external electrode C area D area 40 Intermediate area 51 Copper-containing regions 52 Regions containing copper oxide L51 Longest diameter L52 Longest diameter 51A Copper-containing layer 52A Layer containing copper oxide T51A Thickness T52A Thickness 53 Base metal-copper alloy layer 60 Flowcharts S1 Raw material powder preparation process S2 Dielectric Green Sheet Formation Process S3 Internal electrode layer formation process S4 Lamination process S5 Crimping process S6 singulation process S7 Firing Process S8 External electrode formation process 71 Dielectric Green Sheet 72a First internal electrode layer pattern 72b Second internal electrode layer pattern

Claims

1. Multiple dielectric layers stacked along the first axis, A plurality of internal electrode layers are disposed between adjacent dielectric layers along the first axis, It has an intermediate region disposed between the dielectric layer and the internal electrode layer, The dielectric layer is of the general formula ABO ３－α It is represented as (0 ≤ α ≤ 1) and contains a compound having a perovskite-type structure, The aforementioned internal electrode layer contains a base metal element as its main component, The aforementioned intermediate region contains copper and copper oxide, in a multilayer ceramic electronic component.

2. The multilayer ceramic electronic component according to claim 1, wherein within the intermediate region, the region containing copper and the region containing copper oxide exist independently of each other.

3. The multilayer ceramic electronic component according to claim 2, wherein the average value of the major axis of the copper-containing region and the average value of the major axis of the copper oxide-containing region are 1 nm or more and 20 nm or less.

4. The multilayer ceramic electronic component according to claim 2, wherein the region containing copper and the region containing copper oxide have a layered shape.

5. The multilayer ceramic electronic component according to any one of claims 1 to 4, wherein the ratio of the concentration of copper to the concentration of copper oxide in the intermediate region is 100% or more and 200% or less.

6. The multilayer ceramic electronic component according to any one of claims 1 to 4, wherein the internal electrode layer contains nickel as the base metal element.

7. The multilayer ceramic electronic component according to any one of claims 1 to 4, wherein the dielectric layer contains barium titanate as the compound having the perovskite-type structure.

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