Multilayer electronic components

Abstract

This invention provides a multilayer electronic component with improved reliability in wire bonding to external electrodes. [Solution] The laminated electronic component 1 comprises a laminate 2 and external electrodes 3 arranged on the third surface F3 and the fourth surface F4 of the laminate 2, respectively. The external electrodes 3 comprise a Ni plating layer 3b1 and an Au plating layer 3b2 arranged on the Ni plating layer 3b1. A void exists between the Ni plating layer 3b1 and the Au plating layer 3b2, and the void presence rate is 0.05% or less.

Description

Technical Field

[0001] The present invention relates to a multilayer electronic component.

Background Art

[0002] Multilayer electronic components are often mounted on a substrate by solder or the like. However, multilayer electronic components may be adversely affected by the flux contained in the solder. For this reason, multilayer electronic components may be mounted by wire bonding (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, when a multilayer electronic component is mounted by wire bonding via an external electrode, the wire attached by wire bonding may come off from the external electrode.

[0005] Therefore, an object of the present invention is to provide a multilayer electronic component with improved connectivity between an external electrode and a wire.

Means for Solving the Problems

[0006] To solve the above problems, one aspect of the present invention provides a laminated electronic component comprising: a laminate having a first surface and a second surface facing each other in the stacking direction; a third surface and a fourth surface facing each other in a first direction intersecting the stacking direction; and a fifth surface and a sixth surface facing each other in a second direction intersecting the stacking direction and the first direction; and external electrodes disposed on the third surface and the fourth surface of the laminate, wherein the external electrodes comprise a Ni plating layer and an Au plating layer disposed on the Ni plating layer, and a void exists between the Ni plating layer and the Au plating layer, with the void presence rate being 0.05% or less.

[0007] Furthermore, in order to solve the above problems, one aspect of the present invention provides a laminated electronic component comprising: a laminate having a first surface and a second surface opposite to each other in the height direction, a third surface and a fourth surface opposite to each other in a first direction intersecting the height direction, and a fifth surface and a sixth surface opposite to each other in a second direction intersecting the height direction and the first direction; and external electrodes disposed on the third surface and the fourth surface of the laminate, respectively, wherein the external electrodes are disposed on the first surface, the second surface, the fifth surface and the sixth surface following the third surface or the fourth surface, and the external electrode disposed on the first surface comprises a Ni plating layer and an Au plating layer disposed on the Ni plating layer, wherein a void exists between the Ni plating layer and the Au plating layer, and the void presence rate is 0.05% or less. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a multilayer electronic component in which the reliability of wire bonding to external electrodes is improved during wire bonding. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic perspective view of the multilayer ceramic capacitor 1 of this embodiment. [Figure 2]Figure 1 shows a cross-sectional view of the multilayer ceramic capacitor 1 along line II, as well as a diagram showing the capacitor mounted on the substrate 100 and wire-bonded. [Figure 3] Figure 3 shows an image of the Ni plating layer after binarization. [Figure 4] This is a flowchart illustrating the manufacturing method of the multilayer ceramic capacitor 1. [Figure 5] This is a diagram illustrating the wire bonding method. [Figure 6] This table shows the results of the evaluation of the peeling of the Au plating layer of multilayer ceramic capacitor 1. [Figure 7] This is a schematic perspective view of a multilayer ceramic capacitor 1A of another embodiment. [Figure 8] Figure 7 shows a cross-sectional view of the multilayer ceramic capacitor 1A along the line II-II, as well as a diagram showing the capacitor mounted on the substrate 100 and wire-bonded. [Modes for carrying out the invention]

[0010] Hereinafter, a multilayer ceramic capacitor 1 will be described as one embodiment of the multilayer electronic component of the present invention. Figure 1 is a schematic perspective view of the multilayer ceramic capacitor 1. Figure 2 is a cross-sectional view of the multilayer ceramic capacitor 1 of Figure 1 along line II, and a diagram showing the state in which it is mounted on a substrate 100 and wire-bonded.

[0011] (Multilayer ceramic capacitor 1) The multilayer ceramic capacitor 1 comprises a laminate 2 and a pair of external electrodes 3 provided on the third surface F3 and the fourth surface F4, which are two opposing surfaces of the laminate 2.

[0012] In the following description, as terms representing the orientation of the multilayer ceramic capacitor 1, the direction in which the dielectric layer 14 and the internal electrode layer 15 are laminated is defined as the lamination direction T. In the multilayer ceramic capacitor 1, the direction intersecting the lamination direction T and in which a pair of external electrodes 3 are provided is defined as the first direction L. The direction intersecting both the first direction L and the lamination direction T is defined as the second direction W. In the embodiment, the lamination direction T, the first direction L, and the second direction W are orthogonal to each other.

[0013] As shown in FIG. 2, the second external electrode 32 on the fourth surface F4 side of the multilayer ceramic capacitor 1 is attached to the first land 101 provided on one surface of the substrate 100 via the conductive adhesive 102.

[0014] (Multilayer body 2) The multilayer body 2 has an inner layer portion 11 and two outer layer portions 12 arranged so as to sandwich the inner layer portion 11 from both sides in the lamination direction T. The inner layer portion 11 includes a plurality of sets of dielectric layers 14 and internal electrode layers 15.

[0015] In this specification, among the six outer surfaces of the multilayer body 2 shown in FIG. 1, a pair of outer surfaces facing each other in the lamination direction T are defined as the first surface F1 and the second surface F2, a pair of outer surfaces facing each other in the first direction L are defined as the third surface F3 and the fourth surface F4, and a pair of outer surfaces facing each other in the second direction W are defined as the fifth surface F5 and the sixth surface F6 for explanation. Note that the surface of the multilayer body 2 may be roughened.

[0016] Among the first surface F1, the second surface F2, the third surface F3, the fourth surface F4, the fifth surface F5, and the sixth surface F6, a portion where two surfaces intersect is called an edge line portion, and a portion where three surfaces intersect is called a corner portion. It is preferable that R is provided at the edge line portion and the corner portion, and by providing R, chipping can be prevented. When R is provided at the edge line portion and the corner portion, the surfaces excluding the corner portion and the edge line portion may be flat.

[0017] (Inner layer portion 11) The inner layer portion 11 has a first internal electrode layer 151 with one end exposed on the third surface F3, a second internal electrode layer 152 with one end exposed on the fourth surface F4, and a dielectric layer 14 laminated alternately with the first internal electrode layer 151 and the second internal electrode layer 152.

[0018] The dielectric layer 14 has a first region covering one end in the first direction L that is not exposed on the third surface F3 or the fourth surface F4 among the first internal electrode layer 151 and the second internal electrode layer 152, and a second region covering at least a part of one surface in the lamination direction T of the first internal electrode layer 151 and the second internal electrode layer 152. That is, the first region means between the first internal electrode layer 151 and the fourth surface F4 and between the second internal electrode layer 152 and the third surface F3. The second region covers at least a part of the surface on the first surface F1 side of the first internal electrode layer 151 and the second internal electrode layer 152.

[0019] It is preferable that the dielectric component most contained in the first region and the dielectric component most contained in the second region are of the same kind. The dielectric component is composed of, for example, but not limited to, components such as Ba, Ti, Ca, Zr, Sr, etc. For example, when a large amount of CaTiO3 or CaZrO3 is contained as the dielectric component, it is possible to make it difficult for dielectric breakdown to occur between the end portion in the first direction L of the first internal electrode layer 151 and the second external electrode 32, and between the first internal electrode layer 151 and the second internal electrode layer 152. Also, without being limited to this, SrTiO3, etc. can be used as the main component.

[0020] Also, the second region is preferably formed of a material with a high dielectric constant, such as BaTiO3, etc., in order to increase the capacitance of the multilayer ceramic capacitor 1.

[0021] The internal electrode layer 15 has a facing region where the first internal electrode layer 151 and the second internal electrode layer 152 face each other, and a lead-out region led out from the facing region onto the third surface F3 and the fourth surface F4. Also, the width of the internal electrode layer 15 may change toward one end of the exposed internal electrode.

[0022] The components of the first internal electrode layer 151 and the second internal electrode layer 152 can be made of suitable conductive materials such as metals like Ni, Cu, Ag, Pd, Au, and Sn, or alloys containing at least one of these metals, such as Ag-Pd alloys, but are not limited to these. Furthermore, by including a Sn layer at the interface between the first internal electrode layer 151 and the second internal electrode layer 152 and the dielectric layer 14, electric field concentration at the interface can be mitigated, leading to improved high-temperature load reliability. In this case, Sn can be sufficiently effective even if it is included in only one of the internal electrode layers 15, either the first internal electrode layer 151 or the second internal electrode layer 152.

[0023] When the region between the first internal electrode layer 151 and the fifth surface F5, and the region between the second internal electrode layer 152 and the fifth surface F5 are defined as the fifth surface side region, and the region between the first internal electrode layer 151 and the sixth surface F6, and the region between the second internal electrode layer 152 and the sixth surface F6 are defined as the sixth surface side region, Si segregation may be present in the fifth and sixth surface side regions located on both sides of the second direction W of these internal electrode layers 15. This can improve the flexural strength of the multilayer ceramic capacitor 1.

[0024] (Outer layer part 12) The outer layer 12 comprises a first outer layer 121 and a second outer layer 122. The first outer layer 121 and the second outer layer 122 are each formed of an insulating material. When the outer layer 12 is formed of the same dielectric material as the first and second regions of the dielectric layer 14, each outer layer 12 may consist of multiple outer dielectric layers or a single outer dielectric layer. It is also possible to form the dielectric layer 14 and the outer layer 12 with different components. For example, the dielectric layer 14 may have a higher dielectric constant than the outer layer 12, and the outer layer 12 may be made of a component with good moisture resistance, weather resistance, and strength resistance. The outer layer 12 may also be formed of a DLC film or of different insulating materials such as insulating resin.

[0025] (External electrode 3) The external electrode 3 includes a first external electrode 31 positioned on a third surface F3 and a second external electrode 32 positioned on a fourth surface F4. Preferably, the external electrode 3 is positioned to wrap around to the first surface F1, the second surface F2, the fifth surface F5, and the sixth surface F6. The first external electrode 31 and the second external electrode 32 each have a base electrode layer 3a and a plating layer 3b.

[0026] (Base electrode layer 3a) In this embodiment 1, the base electrode layer 3a contains a metal component and a glass component. Preferably, the base electrode layer 3a has Cu as its main component. However, the base electrode layer 3a may also contain other metal components and glass components in addition to Cu. Examples of glass components include oxides of Ba, Sr, Si, Ca, Zn, Al, or B. Examples of other metal components may include Mg, Cr, Sr, Al, Na, Fe, etc.

[0027] As a modification example 1, the base electrode layer 3a may contain a metal component and a dielectric component of the same type as the dielectric layer 14. This makes it possible to form the laminate 2 and the base electrode layer 3a by simultaneous firing.

[0028] As a second modification, the base electrode layer 3a may contain a conductive component and a resin component. This allows for the suppression of crack formation through the stress-relaxing effect of the resin.

[0029] As a third modification, the base electrode layer 3a may be formed by a plating layer containing 99% or more by volume of metal components. In this case, the plating layer is directly connected to the internal electrode layer 15.

[0030] (Plating layer 3b) In the embodiment, the plating layer 3b, which is positioned outside the base electrode layer 3a, is preferably composed of at least two layers, and has an Au plating layer 3b2 on its outermost surface. In the embodiment, for example, it includes a Ni plating layer 3b1 and an Au plating layer 3b2 from the base electrode layer 3a side. Placing the Au plating layer 3b2 on the outermost surface can improve the Au wire bonding properties.

[0031] The plating layer 3b preferably does not contain glass. The metal content per unit volume of the plating layer 3b is preferably 99% by volume or more.

[0032] Furthermore, the thickness of the Ni plating layer 3b1 can preferably be between 0.8 μm and 6.0 μm. Also, the thickness of the Au plating layer 3b2 can preferably be between 0.3 μm and 1.1 μm.

[0033] The dimensions of the multilayer ceramic capacitor 1 including the external electrodes 3 are not particularly limited. For example, the dimensions of the multilayer ceramic capacitor 1 including the external electrodes 3 can be 0.40 ± 0.02 mm in the first direction L, 0.20 ± 0.02 mm in the second direction W, and 0.20 ± 0.02 mm in the stacking direction T.

[0034] (Voids in the plating layer) In the multilayer ceramic capacitor 1 of this embodiment, a void exists between the Ni plating layer 3b1 and the Au plating layer 3b2 placed on the Ni plating layer 3b1. The void is formed in the voids formed in the Ni plating layer 3b1. A void refers to a part of the Ni plating layer 3b1 where Ni plating has not been formed, or a part where Ni plating has been formed but the Ni plating is thinner than in other parts and is observed as a depression.

[0035] (Voids and gaps) The voids are formed when the Au plating layer 3b2 covers the voids in the Ni plating layer 3b1. In other words, the voids in the Ni plating layer 3b1 become the voids between the Ni plating layer 3b1 and the Au plating layer 3b2.

[0036] Viewing the plating layer 3b from a direction approximately perpendicular to its surface is called a plan view. In a plan view, the shape of the voids corresponds to the shape of the voids that form them. In other words, the shape and size of the voids observed in the plating layer 3b in a plan view are the same as the shape and size of the voids observed in the Ni plating layer 3b1 after the Au plating layer 3b2 has been removed.

[0037] (Void abundance) In the multilayer ceramic capacitor 1 of this embodiment, the void content is 0.10% or less. Preferably, it is 0.05% or less. More preferably, the void content is 0.01% or more and 0.05% or less.

[0038] By reducing the void ratio to 0.05% or less, the connectivity between external electrodes can be improved. On the other hand, if the void ratio exceeds 0.05%, the reliability of wire bonding to the external electrodes cannot be improved. In areas where voids exist, the connection of wire bonding to the external electrodes tends to be unstable. This is because, in areas where voids exist, sufficient force may not be applied to the wire during bonding to connect it to the external electrode. Furthermore, in areas where voids exist, the Au plating layer 3b2 may peel off.

[0039] Furthermore, by ensuring that the void content is 0.01% or higher, the moisture resistance of the multilayer ceramic capacitor 1 can be improved. Ensuring that the void content is 0.01% or higher means that the number of voids in the Ni plating layer 3b1 is not reduced to zero, but rather some voids are present. The presence of voids increases the bonding area between the Ni plating layer 3b1 and the Au plating layer 3b2. This increases the sealing performance between the Ni plating layer 3b1 and the Au plating layer 3b2. As a result, the moisture resistance of the multilayer ceramic capacitor 1 can be improved.

[0040] This section explains how to determine the void ratio. The void ratio can be determined by image processing. First, the Au plating layer 3b2 is removed from the plating layer 3b, exposing the Ni plating layer 3b1. Next, the surface of the exposed Ni plating layer 3b1 is observed using a FE-SEM (Field Emission Scanning Electron Microscope).

[0041] The observation conditions will be a magnification of 10,000x, an acceleration voltage of 10kV, and detection of secondary electrons generated from the sample. This will allow us to obtain an SEM image of the surface of the Ni plating layer 3b1.

[0042] Next, the SEM images are processed. First, as a preprocessing step, noise is removed from the images as needed. Noise removal can be done using filtering functions included in image processing software, for example.

[0043] Next, a binarization process is performed. Specifically, the difference in brightness between the void areas and the Ni-plated areas is binarized. The threshold for white and black is set to 50%. In other words, for example, if there are 256 gray levels, the threshold will be set to 128 gray levels.

[0044] Figure 3 shows an image of the Ni plating layer after binarization. Figure 3 is a diagram illustrating the image after binarization. Note that Figure 3 is not an image of the Ni plating layer after binarization in this embodiment, but merely an illustrative diagram. In Figure 3, the white areas WH represent the Ni plating. In Figure 3, the black areas BK represent the voids.

[0045] The probability of voids being present in the binarized image is calculated using the following formula. Void abundance (%) = (Area of ​​void portion (black portion BK)) / (Total area (white portion WH + black portion BK)) × 100 The area in an image can be calculated from the number of pixels in the SEM image.

[0046] (Equivalent diameter of the void) Next, the equivalent circular diameter of the void will be described. In the multilayer ceramic capacitor 1 of this embodiment, the equivalent circular diameter of the void can preferably be 1.0 μm or less.

[0047] By reducing the equivalent circular diameter of the void to 1.0 μm or less, the reliability of wire bonding to the external electrode can be further improved. When the size of the void exceeds 1.0 μm in equivalent circular diameter, the reliability of wire bonding to the external electrode tends to decrease, regardless of the shape of the void in plan view. This is because, as the continuous area of ​​the void increases, the Au plating layer 3b2 becomes more likely to peel off from the Ni plating layer 3b1 in that area, and consequently, the wire becomes more likely to peel off from the external electrode.

[0048] This section explains how to determine the equivalent diameter of a void. The void's abundance can be determined by image processing. Specifically, a line is created from the scale bar of the SEM image. Then, the diameter of the center of one void is measured. The number of measurements (n) is set to three. The average diameter of the three measurement results is then taken as the equivalent diameter.

[0049] (Size of each void) Next, the size of each void will be described. In the multilayer ceramic capacitor 1 of this embodiment, the size of each void is preferably 1.0 μm. 2 The following applies:

[0050] The size of each void is 1.0 μm. 2 The reliability of wire bonding to external electrodes can be further improved by the following: Void size of 1.0 μm 2 If the size exceeds 1.0 μm, the reliability of wire bonding to the external electrode tends to decrease. 2 In areas with gaps exceeding this value, the Au plating layer 3b2 becomes more likely to peel off from the Ni plating layer 3b1, and consequently, the wire becomes more likely to peel off from the external electrode.

[0051] The area described above is obtained for each void contained in the SEM image, and the average area is calculated. The calculated average area is taken as the area per void. The size of the SEM image used when calculating the area per void can be, for example, the size of 1387 pixels.

[0052] (Method for manufacturing a multilayer ceramic capacitor 1) Next, the manufacturing method of the multilayer ceramic capacitor 1 of this embodiment will be described. Figure 4 is a flowchart illustrating the manufacturing method of the multilayer ceramic capacitor 1.

[0053] (Laminated block manufacturing process S1) A dielectric sheet for the dielectric layer 14 and a conductive paste for the internal electrode layer 15 are prepared. The dielectric sheet and the conductive paste for the internal electrode layer 15 contain a binder and a solvent. The binder and solvent may be known substances.

[0054] A conductive paste for the internal electrode layer 15 is printed on the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern for the first internal electrode layer 151 formed on it, and a dielectric sheet with the pattern for the second internal electrode layer 152 formed on it.

[0055] A predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the first outer layer portion 121 on the first surface F1 side. On top of this, a dielectric sheet with the pattern of the first internal electrode layer 151 printed on it and a dielectric sheet with the pattern of the second internal electrode layer 152 printed on it are layered in sequence to form the inner layer portion 11. On top of this inner layer portion 11, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the second outer layer portion 122 on the second surface F2 side. This creates a laminated sheet. Then, the created laminated sheet is pressed in the stacking direction T by means of a hydrostatic press or the like to create a laminated block.

[0056] (Laminated block cutting process S2) The laminated block is cut to a predetermined size, thereby producing laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other methods.

[0057] (Firing process S3) The laminated chips are fired to produce the laminated body 2. The firing temperature depends on the materials of the dielectric layer 14 and the internal electrode layer 15, but is preferably between 900°C and 1400°C. Alternatively, firing may not be performed at this stage, and the laminated chips may be fired together with the base electrode layer 3a during the base electrode formation process S4 described later.

[0058] (Substrate formation process S4) A conductive paste, which will serve as the base electrode layer 3a, is applied to the third surface F3 and the fourth surface F4 of the laminate 2. In this embodiment, the conductive paste containing glass components and metal is applied by a method such as dipping.

[0059] Subsequently, a baking process is performed to form the base electrode layer 3a. The temperature during this baking process is preferably between 700°C and 900°C. This baking process sinters the conductive paste.

[0060] (Plating layer formation process S5) In this embodiment, the plating layer 3b includes, in order from the underlayer electrode layer 3a side, a Ni plating layer 3b1 and an Au plating layer 3b2. The Ni plating layer 3b1 and the Au plating layer 3b2 are formed, for example, by electroplating using a barrel plating method.

[0061] (Control of voids in the Ni plating layer) An example of a method for controlling voids formed in the Ni plating layer 3b1 is described below. The voids between the Ni plating layer 3b1 and the Au plating layer 3b2 can be controlled by the immersion time in the plating bath and the current density when forming the Au plating layer 3b2. For example, the Au plating layer 3b2 is formed by combining electroless plating and electroplating. In this case, the electroless plating time is set to 1 minute or more and 2 minutes or less, and the current value is set to 4.7A as the Dk value (cathode current density value). This makes it possible to reduce the void presence to 0.10% or less, or 0.05% or less.

[0062] By the above manufacturing method, a multilayer ceramic capacitor 1 is manufactured in which the void ratio, the equivalent circular diameter of the voids, and the size of each void are within a predetermined range.

[0063] (Wire bonding process) As shown in Figure 2, in the multilayer ceramic capacitor 1 of the embodiment manufactured in this way, for example, the second external electrode 32 on the fourth surface F4 side is bonded to a first land 101 provided on one surface of the substrate 100 via a conductive adhesive 102.

[0064] One end of wire 202 is connected to the first external electrode 31 on the third surface F3 side of the multilayer ceramic capacitor 1. The other end of wire 202 is connected, for example, to a second land 103 on the substrate 100 other than the first land 101 to which the multilayer ceramic capacitor 1 is bonded.

[0065] (Wire bonding method) Figure 5 illustrates a wire bonding method. Wire bonding is performed using a bonding apparatus equipped with a capillary 200 having an inner bore 201 (only the capillary 200 portion is shown, the whole apparatus is not shown). A wire 202 is inserted into the inner bore 201 of the capillary 200, and the wire 202 can be fed out from the tip of the capillary 200.

[0066] In this embodiment, the wire 202 is made of gold, and the outermost surface of the external electrode 3 of the multilayer ceramic capacitor 1 is an Au plating layer 3b2, so the bonding between the wire 202 and the external electrode 3 is good.

[0067] The bonding apparatus first uses an image processing mechanism to detect the position of the external electrodes 3 of the multilayer ceramic capacitor 1, and then uses a moving mechanism to move the capillary 200 onto the external electrodes 3 of the multilayer ceramic capacitor 1.

[0068] When detecting the position of the external electrodes 3 of the multilayer ceramic capacitor 1 using an image processing mechanism, first, light is shone onto the entire substrate 100 on which the multilayer ceramic capacitor 1 is mounted, and the position of the external electrodes 3 of the multilayer ceramic capacitor 1 is recognized as an image based on the reflected light from the external electrodes 3.

[0069] Next, the capillary 200 is moved above the external electrode 3, and the tip of the wire 202 is melted by discharge or the like to form a ball. Then, the capillary 200 is moved downward, and as shown in Figure 5(a), the ball at the tip of the wire 202 is pressed against the external electrode 3 of the multilayer ceramic capacitor 1, and one end of the wire 202 is connected to the external electrode 3 of the multilayer ceramic capacitor 1 by applying ultrasound or the like.

[0070] After connecting one end of the wire 202 to the external electrode 3 of the multilayer ceramic capacitor 1, as shown in Figure 5(b), the wire 202 is fed out from the inner hole 201 of the capillary 200 and moved to the second land 103. The wire 202 is then pressed against the second land 103 and bonded to it while applying ultrasonic vibration, and then the wire 202 is cut. This connects the external electrode 3 of the multilayer ceramic capacitor 1 to the second land 103 on the substrate 100 side.

[0071] (Implementation structure) As described above, the structure in which the multilayer ceramic capacitor 1 is mounted on the substrate 100 is called the mounting structure. The mounting structure of this embodiment can be expressed as follows. In other words, the mounting structure includes a multilayer ceramic capacitor 1 and a substrate 100. The multilayer ceramic capacitor 1 includes a laminated body 2 and an external electrode 31. The laminate 2 has a first surface F1 and a second surface F2 that are opposite to the stacking direction T, A third surface F3 and a fourth surface F4 opposite to the first direction L which intersects the stacking direction T, It has a fifth surface F5 and a sixth surface F6 that are opposite to the stacking direction T and a second direction W that intersects the first direction L. The external electrodes 31 are arranged on the third surface F3 and the fourth surface F4 of the laminate 2, respectively. The external electrode 31 comprises a Ni plating layer 3b1 and an Au plating layer 3b2 disposed on the Ni plating layer 3b1, with a void existing between the Ni plating layer 3b1 and the Au plating layer 3b2. The void content is less than 0.05%. Furthermore, the multilayer ceramic capacitor 1 has a dimension in the stacking direction T that is longer than the dimension in the first direction L.

[0072] Furthermore, the second external electrode 32, which is the external electrode 31 of the fourth surface F4 of the laminate 2, is bonded to the first land 101 provided on one surface of the substrate 100 via a conductive adhesive 102. Furthermore, one end of the wire 202 is connected to the first external electrode 31, which is the external electrode 31 on the third surface F3 side of the multilayer ceramic capacitor 1. On the other hand, the other end of the wire 202 is connected to the second land 103, which is a land on the substrate 100 other than the first land 101 to which the multilayer ceramic capacitor 1 is bonded.

[0073] (Evaluation of peeling of the Au plating layer) The peeling evaluation of the Au plating layer 3b2 of the multilayer ceramic capacitor 1 of this embodiment will be described. Figure 6 is a table showing the evaluation results of the void presence rate and the peeling rate of the Au plating layer.

[0074] This section describes the evaluation method for the peeling rate of the Au plating layer. The sizes of the multilayer ceramic capacitors used in the evaluation are as follows. Dimension of the first direction L: 0.4 mm Dimension of the second direction W: 0.2 mm Dimension in stacking direction T: 0.2 mm

[0075] Prepare 100 multilayer ceramic capacitors each for Example 1, Example 2, Comparative Example 1, and Comparative Example 2, each with a different void ratio between the Ni plating layer and the Au plating layer.

[0076] One hundred multilayer ceramic capacitors of each embodiment and comparative example are arranged and fixed to the substrate. The means of fixing are not particularly limited. The means of fixing should be such that the multilayer ceramic capacitors do not detach from the substrate during the Au plating peeling test using tape, which will be described later. An example of a fixing method is fixing with adhesive.

[0077] Next, adhesive tape is applied to each of the 100 multilayer ceramic capacitors that are arranged and fixed on the substrate. The adhesive tape is applied so as to cover the Au plated layer. The adhesive tape is 3M product, part number T5625, yellow, or an adhesive tape with equivalent adhesive strength.

[0078] After applying the adhesive tape, peel it off in one swift motion. After removing the tape, check under a microscope to see if the Au plating layer has been removed.

[0079] As shown in Figure 6, in Example 1, where the void content was 0.01%, and in Example 2, where the void content was 0.05%, the peeling rate of the Au plating layer was suppressed, at 0.00% and 3.00%, respectively. In other words, the reliability of wire bonding to the external electrode was improved.

[0080] In contrast, in Comparative Example 1, where the void content was 0.41%, and Comparative Example 2, where the void content was 16.9%, a significant amount of peeling of the Au plating layer was observed, with peeling rates of 34.0% and 45.0%, respectively. In other words, the reliability of wire bonding performed on the external electrode was low.

[0081] As shown in Figure 6, it was confirmed that reducing the void content to 0.05% or less suppressed peeling of the Au plating layer and improved the reliability of wire bonding.

[0082] (Multilayer ceramic capacitor according to other embodiments) Another embodiment of the multilayer ceramic capacitor 1A will be described with reference to Figures 7 and 8. Figure 7 is a schematic perspective view of the multilayer ceramic capacitor 1A of another embodiment. Figure 8 is a cross-sectional view of the multilayer ceramic capacitor 1A of Figure 7 along the line II-II, and shows the capacitor mounted on the substrate 100 and wire-bonded.

[0083] In the multilayer ceramic capacitor 1 described earlier with reference to Figures 1 and 2, the capacitor is bonded to a first land 101 provided on one surface of the substrate 100, for example, by a conductive adhesive 102, and the second external electrode 32 on the fourth surface F4 side is bonded to the first land 101 via the conductive adhesive 102. However, the multilayer ceramic capacitor 1 is not limited to this.

[0084] As shown in Figures 7 and 8, in the multilayer ceramic capacitor 1A of the other embodiment, the dimension in the stacking direction T is shorter than the first direction L in which external electrodes 3 are formed at both ends as shown.

[0085] Furthermore, as shown in Figure 7, the external electrodes 3 of the multilayer ceramic capacitor 1A in the other embodiment wrap around the first surface F1, the second surface F2, the fifth surface F5, and the sixth surface F6 for a longer distance than those of the multilayer ceramic capacitor 1 in the above-described embodiment.

[0086] In other configurations, the multilayer ceramic capacitor 1A is the same as the multilayer ceramic capacitor 1 in the above-described embodiment, so the description of the similar parts will be omitted. That is, the external electrodes 31 and 32 of the multilayer ceramic capacitor 1A in this other embodiment include a base electrode layer and a plating layer, and the void content is 0.10% or less, preferably 0.05% or less.

[0087] As shown in Figure 8, the second surface F2 of the multilayer ceramic capacitor 1A in another embodiment is bonded to a first land 101 provided on one surface of the substrate 100, for example, by epoxy resin 105. The wire 202 extends from both sides of the external electrode 31 and external electrode 32, which extend toward the first surface F1.

[0088] In the multilayer ceramic capacitor 1A of the other embodiment, as with the multilayer ceramic capacitor 1 of the embodiment, the reliability of wire bonding to the external electrodes can be improved during wire bonding.

[0089] (Implementation structure) The mounting structure of the multilayer ceramic capacitor 1A in other embodiments can be expressed as follows. In other words, the mounting structure includes a multilayer ceramic capacitor 1A and a substrate 100. The multilayer ceramic capacitor 1A includes a laminated body 2 and an external electrode 31. The laminate 2 has a first surface F1 and a second surface F2 that are opposite to each other in the height direction TA, The third surface F3 and the fourth surface F4 are opposite to the horizontal direction TB which intersects the height direction TA, It has a fifth surface F5 and a sixth surface F6 that are opposite to the width direction TC, which intersects the height direction T and the lateral direction TB. The external electrodes 31 are arranged on the third surface F3 and the fourth surface F4 of the laminate 2, respectively. The external electrodes are further arranged on the first surface F1, second surface F2, fifth surface F5 and sixth surface F6, following the third surface F3 or fourth surface F4, 31. The external electrode 31 comprises a Ni plating layer 3b1 and an Au plating layer 3b2 disposed on the Ni plating layer 3b1, with a void existing between the Ni plating layer 3b1 and the Au plating layer 3b2. The void content is less than 0.05%. Furthermore, the multilayer ceramic capacitor 1A has a height dimension TA that is shorter than the width dimension TB.

[0090] Here, the height direction TA is the direction along the plane perpendicular to the plane when the multilayer ceramic capacitor 1A is placed on a plane such as a substrate 100. The lateral direction TB is the direction in which the external electrodes 31 and 32 face each other in the multilayer ceramic capacitor 1A. Figure 7 shows the height direction TA, lateral direction TB, and width direction TC when the multilayer ceramic capacitor 1A is placed on the YZ plane in a Cartesian coordinate system.

[0091] In Figure 8, the height direction TA and the stacking direction T are parallel. However, depending on how the multilayer ceramic capacitor 1A is mounted, the height direction TA and the width direction W may also be parallel.

[0092] The second surface F2 of the multilayer ceramic capacitor 1A is bonded to a first land 101 provided on one surface of the substrate 100 with a resin such as epoxy resin 105. The wire 202 extends from both sides of the external electrode 31 and external electrode 32, which extend toward the first surface F1. Specifically, one end of each wire 202 extends from an external electrode 31 that extends from the third surface F3 towards the first surface F1, and from an external electrode 32 that extends from the fourth surface F4 towards the first surface F1. The other end of each wire 202 is connected to a different land provided on one surface of the substrate 100.

[0093] Although embodiments of the present invention have been described above, the present invention is not limited to the embodiments described above, and various modifications and variations are possible as follows. [Explanation of symbols]

[0094] 1. Multilayer ceramic capacitor (multilayer electronic component) 1A Multilayer ceramic capacitor (multilayer electronic component) of another embodiment 2 Laminate 3 External electrode 3a Base electrode layer 3b Plating layer 3b1 Ni plating layer 3b2 Au plating layer 11 Inner layer 12 Outer layer 14 Dielectric layer 15 Internal electrode layer 31 First external electrode 32 Second external electrode 100 circuit boards 101 The First Land 102 Conductive adhesive 103 The Second Land 105 Epoxy resin 121 First outer layer 122 Second outer layer 151 First internal electrode layer 152 Second internal electrode layer 200 capillaries 201 Internal bore 202 wire

Claims

1. A first surface and a second surface facing each other in the stacking direction, A third surface and a fourth surface that are opposite to the first direction intersecting the stacking direction, A laminate having a fifth surface and a sixth surface opposite to the stacking direction and a second direction intersecting the first direction, The laminate comprises external electrodes disposed on the third surface and the fourth surface, respectively. The aforementioned external electrode is Ni plating layer and An Au plating layer is placed on the Ni plating layer, Equipped with, A void exists between the Ni plating layer and the Au plating layer. A multilayer electronic component in which the presence rate of the aforementioned voids is 0.05% or less.

2. A first surface and a second surface that are opposite each other in the height direction, A third surface and a fourth surface opposite to the first direction intersecting the height direction, A laminate having a fifth surface and a sixth surface opposite to the height direction and a second direction intersecting the first direction, The laminate comprises external electrodes disposed on the third surface and the fourth surface, respectively. The external electrodes are arranged on the first, second, fifth, and sixth surfaces, following the third or fourth surface. The external electrode arranged on the first surface is Ni plating layer and An Au plating layer is placed on the Ni plating layer, Equipped with, A void exists between the Ni plating layer and the Au plating layer. A multilayer electronic component in which the presence rate of the aforementioned voids is 0.05% or less.

3. The laminated electronic component according to claim 1 or 2, wherein the equivalent circular diameter of the void is 1.0 μm or less.

4. The size of each of the aforementioned voids is 1.0 μm. ２ The stacked electronic component according to claim 1 or 2, which is as follows:

5. The stacked electronic component according to any one of claims 1 to 4, wherein the thickness of the Au plating layer is 0.3 μm or more and 1.1 μm or less.

6. The stacked electronic component according to claim 1, wherein the dimension in the stacking direction is longer than the dimension in the first direction.

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