Indication device

Abstract

The objective is to provide a low-voltage driven display device that suppresses a decrease in brightness or contrast. [Solution] The display device includes an array substrate containing pixel electrodes and a planarization film having an opening in a region overlapping with the pixel electrodes; a counter substrate facing and spaced apart from the array substrate and containing a common electrode facing the pixel electrodes; and a liquid crystal layer between the array substrate and the counter substrate. The pixel electrodes are positioned in a region overlapping with the opening, and a first spacer is positioned in the region overlapping with the opening to reduce the distance between the pixel electrodes and the common electrodes.

Description

Technical Field

[0001] The present invention relates to a display device.

Background Art

[0002] As liquid crystal display devices, there are known a transmissive display that displays an image by transmitting the light of a backlight disposed on the back surface of a liquid crystal panel, a reflective display that displays an image by reflecting external light with pixel electrodes, and a transflective display that has characteristics of both the transmissive type and the reflective type. These liquid crystal display devices are used as displays for electronic devices such as personal computers and smartphones, and have a configuration in which the background cannot be seen through the screen.

[0003] On the other hand, a display device that allows the background to be seen through while displaying an image has been developed. For example, a display device is disclosed in which a display area is configured by polymer-dispersed liquid crystal (PDLC) disposed between a pair of light-transmissive substrates, and a planarization film is removed to improve the transparency of pixels (see Patent Document 1).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, since the thickness of the planarization film is large, removing the planarization film increases the cell gap in the pixels, and a sufficient voltage is not applied to the PDLC, resulting in problems such as a decrease in luminance and contrast. In addition, in order to apply a sufficient voltage to the PDLC, it is necessary to apply a high voltage to drive the display device.

[0006] One of the objectives of the present invention is to provide a low-voltage driven display device that suppresses a decrease in brightness or contrast. [Means for solving the problem]

[0007] A display device according to one embodiment of the present invention includes an array substrate including pixel electrodes and a planarization film having an opening in a region overlapping with the pixel electrodes; a counter substrate arranged opposite and at a distance from the array substrate and including a common electrode facing the pixel electrodes; and a liquid crystal layer between the array substrate and the counter substrate, wherein the pixel electrodes are arranged corresponding to the openings, and a first spacer is arranged corresponding to the region where the openings are provided to narrow the distance between the pixel electrodes and the common electrodes. [Brief explanation of the drawing]

[0008] [Figure 1] This is a perspective view illustrating the overview of a display device according to one embodiment of the present invention. [Figure 2] This is a schematic cross-sectional view showing the structure corresponding to the area between A1 and A2 of the display device shown in Figure 1. [Figure 3] This is a plan view illustrating the configuration of a display device according to one embodiment of the present invention. [Figure 4] This is a plan view of pixels in a display device according to one embodiment of the present invention. [Figure 5] This is a cross-sectional view of a pixel in a display device according to one embodiment of the present invention. [Figure 6] This is a cross-sectional view of a pixel in a display device according to one embodiment of the present invention. [Figure 7] This is a cross-sectional view of a pixel in a display device according to one embodiment of the present invention.

[0009] The embodiments of the present invention will be described below with reference to the drawings, etc. However, the present invention can be implemented in various forms without departing from its gist, and is not to be interpreted as being limited to the embodiments described below. Furthermore, in order to clarify the explanation with respect to the drawings, the width, thickness, shape, etc. of each part may be schematically represented compared to the actual embodiment, but these schematic figures are just examples and do not limit the interpretation of the present invention. In addition, in this specification and each figure, the same or similar reference numerals are used for elements that have been described with respect to previously shown figures, and redundant explanations may be omitted. In this specification, etc., ordinal numbers are assigned for convenience to distinguish parts, parts, etc., and do not indicate priority or order.

[0010] In this invention, when multiple films are formed by processing a single film, these multiple films may have different functions and roles. However, these multiple films originate from a film formed as the same layer in the same process, and have the same layer structure and the same material. Therefore, these multiple films are defined as existing in the same layer. Furthermore, when multiple films are formed by processing a single film, they may be described separately as -1, -2, etc. in this specification.

[0011] In this specification, expressions such as "above" and "below" describe the relative positional relationship between the structure of interest and other structures. In this specification, in a side view, the direction from the array substrate described later toward the pixel electrodes is defined as "above," and the opposite direction is defined as "below." In this specification and the claims, when describing a manner in which one structure is placed on top of another structure, unless otherwise specified, the expression "above" includes both cases where one structure is placed directly above another structure so as to be in contact with it, and cases where another structure is placed above another structure via yet another structure.

[0012] (First Embodiment) A display device 10 according to one embodiment of the present invention will be described with reference to Figures 1 to 5.

[0013] <Overview of the display device> Figure 1 shows a perspective view of a display device 10 according to one embodiment of the present invention. The display device 10 includes a display panel 102 which includes an array substrate 150, a counter substrate 152, a liquid crystal layer (not shown) between the array substrate 150 and the counter substrate 152, a gate drive circuit 28, a source drive circuit 38, a light source 104, and a first transparent substrate 151A and a second transparent substrate 151B which sandwich the display panel 102. In the following description with reference to Figure 1, one direction of the plane in the display panel 102 is referred to as the D1 direction, the direction perpendicular to the D1 direction is referred to as the D2 direction, and the direction perpendicular to the D1-D2 plane is referred to as the D3 direction.

[0014] The array substrate 150 and the opposing substrate 152 are light-transmitting. Preferably, the array substrate 150 and the opposing substrate 152 are transparent to visible light. The opposing substrate 152 is positioned in the D3 direction so as to face the array substrate 150. The array substrate 150 and the opposing substrate 152 are bonded together by a sealing material 154 while facing each other with a gap between them. A liquid crystal layer (not shown) is provided in the gap between the array substrate 150 and the opposing substrate 152.

[0015] The display panel 102 has a display area 12 and a peripheral area 14 outside the display area 12. Multiple pixels PIX are arranged in the row direction and column direction in the display area 12. Here, the row direction refers to the direction parallel to the D1 direction, and the column direction refers to the direction parallel to the D2 direction. In the display area 12, m pixels are arranged in the row direction and n pixels are arranged in the column direction. The values ​​of m and n are set appropriately according to the vertical display resolution and the horizontal display resolution. Gate wiring (also called scan signal lines) is arranged in the D1 direction in the display area 12, and source wiring (also called data signal lines) is arranged in the D2 direction.

[0016] A gate drive circuit 28 and a source drive circuit 38 are provided in the peripheral region 14 of the array substrate 150. Figure 1 shows an embodiment in which the gate drive circuit 28 and the source drive circuit 38 are provided as integrated circuits (ICs) and mounted on the array substrate 150 using the COG (Chip on Glass) method. The gate drive circuit 28 and the source drive circuit 38 are not limited to the embodiment shown, and may be mounted using the COF (Chip on Film) method, or may be formed by thin-film transistors (TFTs) on the array substrate 150.

[0017] The peripheral region 14 is provided with a gate wiring region 32, a common wiring region 22, and a source wiring region 42. The gate wiring region 32 is a region where a pattern is formed by wiring connecting the gate drive circuit 28 and the gate wiring GL provided in the display region 12. The common wiring region 22 is a region where a pattern is formed by common wiring. Circuit-wise, the common wiring region 22 is used as wiring to apply a common voltage to the common electrode 218 (see Figure 5) provided on the opposing substrate 152. The source wiring region 42 is a region where a pattern is formed by wiring connecting the source drive circuit 38 and the source wiring SL provided in the display region 12.

[0018] The light source 104 has a structure along the D1 direction. The light source 104 is composed of, for example, light emitting diodes (LEDs) arranged along the D1 direction. There is no limitation on the detailed structure of the light source 104. In addition to the light emitting diodes arranged in the D1 direction, optical members such as a reflector, a diffuser plate, and a lens may be included. The light source 104 and the light emission control circuit 110 for controlling the light source 104 may be provided as separate members independent of the display panel 102. Also, the light emission timing of the light source 104 may be controlled by the light emission control circuit 110 that synchronizes with the gate drive circuit 28 and the source drive circuit 38. The light emission control circuit 110 for controlling the light source 104 may be provided as a separate member in the same manner as the light source 104 separately from the display panel 102, may be mounted on the array substrate 150 as an individual component, or may be incorporated in the gate drive circuit 28 or the source drive circuit 38.

[0019] The first transparent substrate 151A and the second transparent substrate 151B are provided so as to sandwich the display area 12 and the peripheral area 14. The first transparent substrate 151A and the second transparent substrate 151B have a function as a protective member of the display panel 102. Also, as described with reference to FIG. 2, the first transparent substrate 151A and the second transparent substrate 151B have a function as a light guide plate for introducing the light emitted from the light source 104 into the display panel 102.

[0020] FIG. 2 shows a cross-sectional structure of the display device 10 corresponding to the between A1 - A2 shown in FIG. 1. As shown in FIG. 2, the first transparent substrate 151A is provided on the array substrate 150 side of the display panel 102, and the second transparent substrate 151B is provided on the counter substrate 152 side. The first transparent substrate 151A and the second transparent substrate 151B are made of a glass substrate or a plastic substrate. It is preferable that the first transparent substrate 151A and the second transparent substrate 151B have a refractive index equivalent to that of the array substrate 150 and the counter substrate 152. The array substrate 150 and the first transparent substrate 151A, and the counter substrate 152 and the second transparent substrate 151B are adhered with a transparent adhesive not shown.

[0021] The display panel 102 is arranged such that the array substrate 150 and the counter substrate 152 face each other, and a liquid crystal layer 210 is provided therebetween. The array substrate 150 is larger than the counter substrate 152 and has a size such that a part of the peripheral region 14 is exposed from the counter substrate 152. A drive circuit (source drive circuit 38 in FIG. 2) is mounted on the array substrate 150. Also, a flexible printed circuit 34 is attached to the peripheral edge of the array substrate 150.

[0022] The light source 104 is arranged adjacent to one side surface of either the first transparent substrate 151A or the second transparent substrate 151B. FIG. 2 shows a configuration in which the light source 104 is arranged along one side surface of the second transparent substrate 151B. Also, FIG. 2 shows a configuration in which the light source 104 is attached to the array substrate 150, but the present invention is not limited to the configuration in which the light source 104 is arranged, and the attachment structure is not limited as long as the attachment position can be fixed. The light source 104 may be supported by, for example, a housing surrounding the display panel 102.

[0023] As shown in FIG. 2, the light source 104 is arranged along the first side surface 15C of the second transparent substrate 151B. As shown in FIG. 2, the light source 104 irradiates the light L to the first side surface 15C of the second transparent substrate 151B. Since the light source 104 emits the light L toward the first side surface 15C, it may be called a side light source. The first side surface 15C of the second transparent substrate 151B facing the light source 104 serves as a light incident surface.

[0024] As schematically shown in FIG. 2, the light L incident from the first side surface 15C of the second transparent substrate 151B propagates in a direction (D2 direction) away from the first side surface 15C while being reflected by the second plane 15B of the second transparent substrate 151B and the first plane 15A of the first transparent substrate 151A. When the light L travels from the medium with a large refractive index to the medium with a small refractive index when the light L goes to the outside from the first plane 15A of the first transparent substrate 151A and the second plane 15B of the second transparent substrate 151B. At this time, if the incident angle of the light L incident on the first plane 15A and the second plane 15B is larger than the critical angle, total reflection occurs, and the light is guided in the D2 direction while being reflected by the first plane 15A and the second plane 15B.

[0025] The liquid crystal layer 210 is formed of polymer-dispersed liquid crystal. The liquid crystal layer 210, formed of polymer-dispersed liquid crystal, is controlled to have a scattering state and a non-scattering state for each pixel PIX (see Figure 1). As shown in Figure 2, when light L propagates while reflecting off the first plane 15A and the second plane 15B, if there is a pixel in the liquid crystal layer 210 that is in a scattering state, at least a portion of the light is scattered, and the incident angle of the scattered light becomes smaller than the critical angle, causing the scattered light LA ​​and LB to be emitted to the outside from the first plane 15A and the second plane 15B, respectively, and the emitted scattered light LA ​​and LB are observed by the observer. In the display panel 102, the areas other than those from which the scattered light LA ​​and LB are emitted are substantially transparent because the array substrate 150 and the opposing substrate 152, as well as the first transparent substrate 151A and the second transparent substrate 151B, are light-transmitting (transparent to visible light), and the liquid crystal layer 210 is in a non-scattering state, allowing the observer to see the back side through the display panel 102.

[0026] Figure 3 is a plan view illustrating the configuration of the array substrate 150 of a display device 10 according to one embodiment of the present invention. As shown in Figure 3, the array substrate 150 includes a display area 12 and a peripheral area 14.

[0027] The display area 12 has multiple pixels PIX arranged in a matrix. Each of the multiple pixels PIX has multiple transistors and liquid crystal elements.

[0028] The peripheral region 14 is provided so as to surround the display region 12. The peripheral region 14 refers to the area on the array substrate 150 from the display region 12 to the edge of the array substrate 150. In other words, the peripheral region 14 refers to the area on the array substrate 150 other than the area on which the display region 12 is provided (i.e., the area outside the display region 12).

[0029] In addition to the gate drive circuit 28 and source drive circuit 38, the peripheral region 14 is provided with a gate wiring region 32, a source wiring region 42, common wiring 16, common wiring 18, terminal section 26, terminal section 36, flexible printed circuit 24, flexible printed circuit 34, and various test circuits. Terminal sections 26 and 36 are arranged along one side of the array substrate 150.

[0030] A flexible printed circuit board 24 is connected to the terminal section 26. The flexible printed circuit board 24 supplies various signals to the gate drive circuit 28, common wiring 16, common wiring 18, ESD protection circuit 59, and QD pad 56. The gate drive circuit 28 is connected to multiple gate wirings GL, and each of the multiple gate wirings GL is electrically connected to each of the multiple pixels PIX in the display area 12. In Figure 3, the area where multiple gate wirings GL are provided is represented as the gate wiring area 32, and the detailed arrangement of the multiple gate wirings GL is not shown. The number of gate wirings GL connected to the two gate drive circuits 28 corresponds to the number of rows of pixels PIX in the display area 12. In Figure 3, the gate wiring area 32 is shown to be spaced apart from the display area 12, but in reality, the gate wirings GL and pixels PIX are electrically connected.

[0031] A flexible printed circuit 34 is connected to the terminal section 36. The flexible printed circuit 34 supplies a video signal to the source drive circuit 38. The source drive circuit 38 is connected to a plurality of source wirings SL, and each of the plurality of source wirings SL is electrically connected to each of the plurality of pixels PIX in the display area 12. In Figure 3, the area where the plurality of source wirings SL are provided is represented as the source wiring area 42, and the detailed arrangement of the plurality of source wirings SL is not shown. The number of source wirings SL connected to the eight source drive circuits 38 corresponds to at least three times the number of rows of pixels PIX in the display area 12. In this embodiment, the case where the number of source wirings SL is four times the number of rows of pixels PIX in the display area 12 will be described. Note that in Figure 3, the source wiring area 42 is shown to be provided separately from the display area 12, but in reality, the source wirings SL and pixels PIX are electrically connected.

[0032] Between the gate wiring area 32 and the display area 12, a common wiring 18, an ESD protection circuit 46, a gate inspection circuit 48, and an inspection line 54 are provided. Between the source wiring area 42 and the display area 12, a common wiring 18, an ESD protection circuit 46, a source inspection circuit 52, and an inspection line 54 are provided. The inspection line 54 is connected to the ESD protection circuit 58 and the QD pad 56. The common wiring 18 is also connected to the ESD protection circuit 59.

[0033] The common wiring 16 is provided so as to surround the peripheral region 14 on the array substrate 150, and signals are supplied from the two flexible printed circuits 24. The common wiring 16 is also electrically connected to the mesh-like common wiring region 22.

[0034] The display device 10 is not limited to high-speed drive panels such as the transparent displays shown in Figures 1 and 2. The display device 10 can be applied to large, high-definition panels used in non-transparent display devices.

[0035] <Pixel configuration> Figure 4 is a plan view illustrating the pixels (PIX) of a display device 10 according to one embodiment of the present invention. Figure 4 shows only some of the components included in the array substrate 150 and the opposing substrate 152.

[0036] The array substrate 150 includes scan signal lines 202, data signal lines SL, transistors Tr (or switching elements), planarization film 207, pixel electrodes 216, and spacers SP1. The opposing substrate 152 includes a light-shielding layer 219, common electrodes 218, and spacers SP2. The scan signal lines 202 include a plurality of scan signal lines 202, each of which extends in the D1 direction. Each of the plurality of scan signal lines 202 is located in a wiring region extending in the D1 direction. The data signal lines SL include a plurality of data signal lines SL, each of which extends in the D2 direction. Each of the plurality of data signal lines SL intersects with each of the plurality of scan signal lines 202. Here, a pixel PIX as used herein corresponds to a region defined by two adjacent scan signal lines 202 and two adjacent plurality of data signal lines SL. The transistor Tr is positioned at the intersection of the scan signal line 202 and the data signal line SL. The transistor Tr may also be positioned in the respective wiring regions of the scan signal line 202 and the data signal line SL. The transistor Tr positioned at the intersection of the scan signal line 202 and the data signal line SL is provided corresponding to each pixel PIX.

[0037] The planarization film 207 is placed over the wiring region where the scan signal line 202, data signal line SL, and transistor Tr are located. The planarization film 207 can cover the scan signal line 202, data signal line SL, and transistor Tr. The planarization film 207 may have regions that do not overlap with a portion of the transistor Tr. The planarization film 207 has an aperture OP1 corresponding to each pixel PIX.

[0038] Pixel electrodes 216 are provided for each pixel PIX. The pixel electrodes 216 are positioned in a region that overlaps with the aperture OP1 of the planarization film 207. The outer ends of the pixel electrodes 216 are positioned to surround the aperture OP1. Each pixel electrode 216 corresponds to a specific pixel PIX. The pixel electrodes 216 are electrically connected to the transistor Tr provided for each pixel PIX.

[0039] The light-shielding layer 219 is arranged in a grid pattern to cover the scan signal line 202 and the data signal line SL. The light-shielding layer 219 is positioned to overlap with the scan signal line 202, the data signal line SL, and the transistor Tr. In Figure 4, the light-shielding layer 219 provided on the opposing substrate 152 is shown by a dotted line. The light-shielding layer 219 has an aperture OP2 corresponding to each pixel PIX. The aperture OP2 is positioned to be surrounded by the aperture OP1 of the planarization film 207. The common electrode 218 is sized to extend across the entire display area 12.

[0040] Spacer SP1 is provided for each pixel PIX. Spacer SP1 is positioned in the region overlapping with the opening OP1 of the planarization film 207. Spacer SP1 is positioned in the region overlapping with the opening OP2 of the light-shielding layer 219. Spacer SP1 is positioned so as to be surrounded by the opening OP1 of the planarization film 207. Spacer SP1 may also be positioned so as to surround the opening OP2 of the light-shielding layer 219. As shown in Figure 4, in a plan view, spacer SP1 may be smaller than the opening OP1 of the planarization film 207 and larger than the opening OP2 of the light-shielding layer 219. Spacer SP1 is formed along the opening OP1 of the planarization film 207. In Figure 4, a rectangular spacer SP1 is formed along the opening OP1, which has a rectangular outer circumference, but spacer SP1 only needs to be shaped along the outer circumference of the opening OP1 and is not limited to a rectangle.

[0041] Spacer SP2 is positioned so as to overlap with the planarization film 207. In Figure 4, spacer SP2 provided on the opposing substrate 152 is shown by a dotted line. Spacer SP2 is preferably positioned at the intersection of the scan signal line 202 and the data signal line SL. Spacer SP2 is positioned in a regular manner with respect to the intersections of pixels PIX arranged in a matrix. For example, multiple spacer SP2 may be positioned every other row and every other column of pixels PIX. In other words, spacer SP2 does not need to be placed at intersections adjacent to intersections where spacer SP2 is placed.

[0042] Next, with reference to Figure 5, the cross-sectional structure of the display device 10 according to one embodiment of the present invention will be described. Figure 5 is a cross-sectional view of a pixel PIX in the display device according to one embodiment of the present invention.

[0043] As shown in Figure 5, a scanning signal line 202, an insulating film 203, an insulating film 205, a conductive layer 208, a planarization film 207, a conductive layer 212, a conductive layer 214, an insulating film 209, and a pixel electrode 216 can be provided on the array substrate 150. The insulating films 203 and 205 can function as gate insulating films of the transistor Tr. The conductive layer 208 can function as a gate electrode of the transistor Tr. In addition to the insulating films 203, 205, and 208, the transistor Tr may also be provided with conductive layers that function as source electrodes and drain electrodes (not shown), and oxide semiconductor layers that function as semiconductor layers. The transistor Tr can be a bottom-gate driven, top-gate driven, or dual-gate driven transistor.

[0044] A planarization film 207 is provided on the conductive layer 208 and the insulating film 205. The planarization film 207 is provided to alleviate the irregularities of the various wirings that constitute the transistor Tr. When the display device 10 is applied to a transparent display, the aperture OP1 of the pixel PIX is formed by removing the planarization film 207. This makes it possible to suppress light absorption by the planarization film 207 at the aperture OP1. The thickness or height of the planarization film 207 can be 1.5 to 3.0 μm when it is formed from a material such as resin, as will be described later.

[0045] A conductive layer 212 is provided on the planarization film 207. A conductive layer 214 is provided on the conductive layer 212. The conductive layers 212 and 214 function as capacitive wiring. An insulating film 209 is provided on the conductive layers 212 and 214. A pixel electrode 216 is provided on the insulating film 209. The pixel electrode 216 is positioned in the opening OP1, extending from the upper surface of the planarization film 207 along the tapered portion from the upper surface of the spacer SP1. The pixel electrode 216 is connected to a conductive layer that functions as the drain electrode of a transistor (not shown) through openings provided in the insulating film 205 and the insulating film 209.

[0046] A counter substrate 152 is provided, facing and spaced apart from the array substrate 150. The counter substrate 152 is provided with a light-shielding layer 219, a spacer SP1, a common electrode 218, and a spacer SP2. The light-shielding layer 219 functions as a black matrix. In Figure 5, the light-shielding layer 219 is provided in the region overlapping with the scanning signal line 202. The light-shielding layer 219 may be formed of a metal film and, by being provided in contact with the common electrode 218, which is formed of a transparent conductive film, functions as an auxiliary electrode. A liquid crystal layer 210 is provided between the array substrate 150 and the counter substrate 152 and is sealed with a sealing material 154 (see Figure 1).

[0047] A spacer SP2 is further provided between the array substrate 150 and the opposing substrate 152, and the spacer SP2 can maintain a constant distance d2 between the array substrate 150 and the opposing substrate 152. The spacer SP2 can be connected to both the array substrate 150 and the opposing substrate 152. In Figure 5, the spacer SP2 is provided on the opposing substrate 152 and is connected to both the array substrate 150 and the opposing substrate 152.

[0048] Spacer SP2 protrudes from the opposing substrate 152 toward the array substrate 150. The protruding height d2 (spacing d2) of spacer SP2 can be smaller than the protruding height d1 (spacing d1) of spacer SP1, which will be described later, toward the array substrate 150 from the opposing substrate 152. However, the protruding height d1 of spacer SP1 is determined by the size of the spacing d3 between the pixel electrode 216 and the common electrode in the aperture OP1, which will be described later. Specifically, it is adjusted so that the spacing d3 is 1.0 to 2.5 μm, so it may be larger than the protruding height d2 of spacer SP2. The protruding height d2 of spacer SP2 can be adjusted by the thickness or height of the planarization film 207 so that the spacing d3 is the above distance. Alternatively, the reverse is also possible; the thickness or height of the planarization film 207 can be adjusted by the protruding height d2 of spacer SP2 so that the spacing d3 is the above distance. Note that when spacer SP2 is formed using resin as described later, the height d2 can be 1.0 to 3.0 μm.

[0049] The common electrode 218 is positioned opposite the pixel electrode 216. In this way, the pixel electrode 216, the liquid crystal layer 210, and the common electrode 218 constitute the liquid crystal element LE.

[0050] In the region overlapping with the aperture OP1, a spacer SP1 is provided between the array substrate 150 and the opposing substrate 152. In Figure 5, the spacer SP1 is provided between the opposing substrate 152 and the common electrode 218. By positioning the spacer SP1 in the region overlapping with the aperture OP1, the thickness d3 of the liquid crystal layer 210 can be defined. In other words, the spacer SP1 can narrow the distance d3 between the pixel electrode 216 and the common electrode 218.

[0051] Spacer SP1 is connected to either the array substrate 150 or the opposing substrate 152. In Figure 5, spacer SP1 is connected to the opposing substrate 152. Spacer SP1 protrudes inward toward the opening OP1 of the planarization film 207. In Figure 5, spacer SP1 protrudes inward toward the opening OP1 of the planarization film 207 from the opposing substrate 152. This protrusion pushes the common electrode 218 on spacer SP1 toward the array substrate 150. As the common electrode 218 is pushed toward the array substrate 150, the distance d3 between the pixel electrode 216 and the common electrode 218 is narrowed compared to when spacer SP1 is not provided between the array substrate 150 and the opposing substrate 152. Spacer SP1 has the function of narrowing the distance d3 between the pixel electrode 216 and the common electrode 218. In other words, spacer SP1 has the function of thinning the thickness (d3) of the liquid crystal layer 210 in the pixel PIX.

[0052] The protruding height d1 of spacer SP1 is preferably adjusted so that the distance d3 between the pixel electrode 216 and the common electrode 218 is 1.0 to 2.5 μm. The height d1 of spacer SP1 can be greater than or less than the protruding height d2 of spacer SP2, depending on the distance d3. For example, in Figure 5, if the height d2 of spacer SP2 is 1000 nm and the sum of the distance d1 and the distance d3 is about 3.0 μm, then it is preferable that the distance d3 is 2.5 μm or less and the height d1 of spacer SP1 is 0.5 μm or more. Therefore, there are cases where the height d1 of spacer SP1 is smaller than the height d2 of spacer SP2.

[0053] As described above, the height d1 of spacer SP1 is preferably 0.5 to 5.0 μm when the height d2 of spacer SP2 is 1.0 to 3.0 μm and the height of the planarization film 207 is 1.5 to 3.0 μm.

[0054] Preferably, the taper of the spacer SP1 follows the shape of the taper of the planarization film 207 in cross-sectional view. The thicker the spacer SP1, the closer the tapered portion of the spacer SP1 gets to the tapered portion of the planarization film 207. When the tapered portion of the spacer SP1 and the tapered portion of the planarization film 207 get close, there is a possibility that the pixel electrode 216 and the common electrode 218 will short-circuit. By making the taper of the spacer SP1 follow the shape of the taper of the planarization film 207 and setting the spacing d1 to the length described above, the spacing d2 between the pixel electrode 216 and the common electrode 218 can be reduced without short-circuiting the pixel electrode 216 and the common electrode 218.

[0055] Figure 5 shows an example where a single-layer structure is used for the spacer SP1, but a laminated structure may also be used, for example, a structure in which multiple layers made of different materials are laminated together.

[0056] <Materials of each component of the display device 10> As the array substrate 150 and the opposing substrate 152, rigid substrates that are translucent and not flexible, such as glass substrates, quartz substrates, and sapphire substrates, can be used. On the other hand, if the array substrate 150 and the opposing substrate 152 need to be flexible, flexible substrates containing resin and having flexibility, such as polyimide substrates, acrylic substrates, siloxane substrates, or fluororesin substrates, can be used as the array substrate 150 and the opposing substrate 152. Impurities may be introduced into the above resins to improve the heat resistance of the array substrate 150 and the opposing substrate 152. Furthermore, when the display device 10 is applied to a transparent display or a large high-definition display, it is preferable to use glass substrates as the array substrate 150 and the opposing substrate 152. In addition, the first transparent substrate 151A and the second transparent substrate 151B are provided to protect the array substrate 150 and the opposing substrate 152. For this reason, it is preferable to use, for example, a translucent glass substrate or a plastic substrate.

[0057] Common metallic materials can be used for the scanning signal line 202, conductive layer 206, conductive layer 208, and conductive layer 214. Examples of these materials include aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), and alloys or compounds thereof. The above materials may be used as single layers or in laminated layers. For example, an Al\Ti laminated structure can be used for the scanning signal line 202. For example, a TiN\Ti\Al\Ti\TiN laminated structure can be used for the conductive layer 206. For example, Mo can be used for the conductive layer 208. A Mo\Al laminated structure can be used as the conductive layer.

[0058] A general insulating material can be used as the gate insulating film 203, insulating film 205, and insulating film 209. For example, inorganic insulating layers such as silicon oxide (SiOx), silicon oxide nitride (SiOxNy), silicon nitride (SiNx), silicon oxide nitride (SiNxOy), aluminum oxide (AlOx), aluminum oxide nitride (AlOxNy), aluminum oxide nitride (AlNxOy), and aluminum nitride (AlNx) can be used as the gate insulating film 203, insulating film 205, and insulating film 209. An insulating layer with few defects can be used as one of these insulating layers.

[0059] As the planarization film 207, organic insulating materials such as polyimide resin, acrylic resin, epoxy resin, silicone resin, fluororesin, or siloxane resin can be used. Furthermore, the above organic insulating materials may also be used as the gate insulating film 203, insulating film 205, and insulating film 209. The above materials may be used as single layers or in laminated layers as the above components. For example, a laminated structure of silicon nitride and silicon oxide can be used as the gate insulating film 203. For example, a laminated structure of silicon oxide and silicon nitride can be used as the insulating film 205. Also, silicon nitride can be used as the insulating film 209.

[0060] The above-mentioned SiOxNy and AlOxNy are silicon and aluminum compounds, respectively, that contain nitrogen (N) in a smaller proportion (x>y) than oxygen (O). Similarly, SiNxOy and AlNxOy are silicon and aluminum compounds, respectively, that contain oxygen in a smaller proportion (x>y) than nitrogen.

[0061] As the oxide semiconductor layer, a metal oxide having semiconductor properties can be used. The oxide semiconductor layer is translucent. For example, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) can be used. In particular, an oxide semiconductor having a composition ratio of In:Ga:Zn:O = 1:1:1:4 can be used. However, the oxide semiconductor containing In, Ga, Zn, and O used in this embodiment is not limited to the above composition, and oxide semiconductors with different compositions can also be used. For example, the ratio of In may be increased to improve mobility. Also, the ratio of Ga may be increased to increase the band gap and reduce the effect of light irradiation.

[0062] In this embodiment, an example using an oxide semiconductor layer as the semiconductor layer has been described, but an amorphous silicon or polysilicon semiconductor layer may also be used.

[0063] A mixture of indium oxide and tin oxide (ITO) and a mixture of indium oxide and zinc oxide (IZO) can be used as the conductive layer 212, the pixel electrode 216, and the common electrode 218. Other materials may be used as the transparent conductive layer. The light-shielding layer 219 used for the black matrix BM can be formed from a black resin or metal material. The black matrix BM is formed in contact with the common electrode 218 (see Figure 5). By forming the black matrix BM from a metal material relative to the common electrode 218 which is formed from a transparent conductive film, it can function as an auxiliary electrode to reduce resistance loss. As the metal material for forming the black matrix BM, it is preferable to use chromium, molybdenum, titanium, etc., which have a relatively low reflectivity compared to aluminum.

[0064] When the display device 10 is applied to a transparent display, it is preferable to use a polymer-dispersed liquid crystal as the liquid crystal layer 210. The polymer-dispersed liquid crystal includes bulk and fine particles. The orientation of the fine particles changes in the bulk according to the potential difference between the pixel electrode 216 and the common electrode 218. By individually controlling the potential of the pixel electrode 216 for each pixel PIX, at least the degree of light transmission and dispersion is controlled for each pixel PIX. The degree of scattering of the liquid crystal layer (fine particles) is controlled according to the voltage of each pixel electrode 216 and the voltage of the common electrode 218. For example, the liquid crystal layer may use a polymer-dispersed liquid crystal such that the degree of scattering increases as the voltage between the voltage of each pixel PIX and the common electrode 218 increases, or it may use a polymer-dispersed liquid crystal such that the degree of scattering increases as the voltage between the voltage of each pixel electrode 216 and the common electrode 218 decreases.

[0065] In the liquid crystal layer 210, the ordinary refractive indices of the bulk and fine particles are equal to each other. When no voltage is applied between the pixel electrode 216 and the common electrode 218, the refractive index difference between the bulk and fine particles is zero in all directions. The liquid crystal layer 210 is in a non-scattering state and does not scatter the light emitted from the light source. The light emitted from the light source propagates away from the light source 104 (light-emitting part) while being reflected by the first main surface of the array substrate 150 and the first main surface of the opposing substrate 152. When the liquid crystal layer 210 is in a non-scattering state and does not scatter the light L emitted from the light source, the background of the opposing substrate 152 is visible from the array substrate 150, and the background of the array substrate 150 is visible from the opposing substrate 152.

[0066] Between the pixel electrode 216 to which a voltage is applied and the common electrode 218, the optical axis of the microparticle is tilted by the electric field generated between the pixel electrode 216 and the common electrode 218. Since the bulk optical axis does not change due to the electric field, the orientation of the bulk optical axis and the optical axis of the microparticle are different from each other. In a pixel PIX where the voltage is applied to the pixel electrode 216, light emitted from the light source is scattered. As described above, a portion of the scattered light emitted from the light source is radiated outward from the first main surface of the array substrate 150 or the first main surface of the opposing substrate 152 and is observed by the observer.

[0067] In pixels PIX where no voltage is applied to the pixel electrode 216, the background on the first main surface side of the opposing substrate 152 is visible from the first main surface of the array substrate 150, and the background on the first main surface side of the array substrate 150 is visible from the first main surface of the opposing substrate 152. When a video signal is input to the display device 10 of this embodiment, a voltage is applied to the pixel electrode 216 of the pixel PIX on which the image is displayed, and the image based on the video signal is visible together with the background. In this way, when the polymer-dispersed liquid crystal is in a scattering state, an image is displayed in the display area.

[0068] Spacer SP1 is transparent to visible light. Preferably, the transmittance of spacer SP1 is higher than that of the planarization film 207. Spacer SP1 can be made of a so-called transparent organic or inorganic insulating material that absorbs little visible light. When a laminated structure is used for spacer SP1, each of the laminated layers may be made of an organic or inorganic insulating material. As a transparent organic insulating material, for example, a negative-type photosensitive resin can be used. As a transparent inorganic insulating material, for example, ITO, SiNx, SiOx, etc., can be used.

[0069] Spacer SP2 can use resin-based spacers such as commonly used photospacers (PS) and column spacers (CS).

[0070] As described above, in the display device 10, by providing a spacer SP1 in the region overlapping with the aperture OP1 of the planarization film 207, the distance d3 between the pixel electrode 216 and the common electrode 218 is narrowed, and the electric field strength between the pixel electrode 216 and the common electrode 218 can be strengthened. By strengthening the electric field strength between the pixel electrode 216 and the common electrode 218, a sufficient voltage is applied to the liquid crystal layer, improving the brightness and contrast ratio of the display device 10 when displaying white, and enabling low-voltage driving.

[0071] (Second Embodiment) Referring to Figure 6, a display device 20 according to one embodiment of the present invention will be described. Figure 6 is an end view showing the display device 20 according to one embodiment of the present invention. Note that the description of components that are the same as or similar to those of the display device 10 shown in Figure 5 may be omitted.

[0072] Spacer SP2 is placed between the opposing substrate 152 and the common electrode 218. Spacer SP2 is formed in the same layer as spacer SP1. Spacer SP2 is transparent to visible light.

[0073] The common electrode 218 is positioned to cover the spacer SP2. The common electrode 218 is positioned to cover the top and side surfaces of the spacer SP2. Note that the common electrode 218 positioned on the top surface of the spacer SP2 refers to the common electrode 218 between the spacer SP2 and the planarization film 207. In Figure 6, the common electrode 218 covers the top and side surfaces of the spacer SP2, but it may be formed so as not to cover the top surface of the spacer SP2 in order to improve connectivity or adhesion between the spacer SP2 and the array substrate 150.

[0074] In the display device 20, forming the spacer SP2 in the same layer as the spacer SP1 simplifies the manufacturing process of the display device 20 and reduces manufacturing costs. Furthermore, by providing the spacer SP1 in the region overlapping with the opening OP1 of the planarization film 207, the gap d3 between the pixel electrode 216 and the common electrode 218 is narrowed, and the electric field strength between the pixel electrode 216 and the common electrode 218 can be strengthened. The strengthened electric field strength between the pixel electrode 216 and the common electrode 218 ensures that a sufficient voltage is applied to the liquid crystal layer 210, improving the brightness and contrast ratio of the display device 20 when displaying white. In addition, the strengthened electric field strength between the pixel electrode 216 and the common electrode 218 eliminates the need to apply a high voltage to the liquid crystal layer 210, enabling low-voltage driving.

[0075] (Third embodiment) Referring to Figure 7, a display device 30 according to one embodiment of the present invention will be described. Figure 7 is an end view showing the display device 30 according to one embodiment of the present invention. Note that the description of components that are the same as or similar to those of the display devices shown in Figures 5 and 6 may be omitted.

[0076] Spacer SP2 is placed between the array substrate 150 and the pixel electrode 216. Spacer SP1 can cover the bottom surface OP1-1 of the opening OP1 of the planarization film 207 and at least a portion of the side surface OP1-2 of the opening OP1. Spacer SP1 is provided so as to fill the opening OP1. It is preferable that spacer SP1 sufficiently fills the opening OP1 to the extent that it is flush with the upper surface of the planarization film 207. It is preferable that the upper surface of spacer SP1 and the upper surface of the planarization film 207 are flat. By providing the pixel electrode 216 on such spacer SP1, the distance d3 between the pixel electrode 216 and the common electrode can be reduced.

[0077] The planarization film 207 is transparent to visible light and is formed using a material that has a low refractive index at the surface where the planarization film 207 and the spacer SP1 are in contact. The planarization film 207 is made of a resin material and is therefore transparent, but it absorbs light in the visible light band. On the other hand, the spacer SP1 is also made of a resin material, but it is preferable to use a resin material that has higher transparency than the resin material that forms the planarization film 207.

[0078] As explained above, in the display device 30, the spacer SP1 is provided in the opening OP1 of the planarized film 207, which narrows the gap d2 between the pixel electrode 216 and the common electrode 218, thereby strengthening the electric field strength between the pixel electrode 216 and the common electrode 218. This increased electric field strength ensures that a sufficient voltage is applied to the liquid crystal layer, improving the brightness and contrast ratio of the display device 20 when displaying white. Furthermore, the increased electric field strength between the pixel electrode 216 and the common electrode 218 eliminates the need to apply a high voltage to the liquid crystal layer, enabling low-voltage driving. By employing a process of filling only the opening OP1 with resin material, processes such as patterning become unnecessary. This simplifies the manufacturing process of the display device 30, reducing manufacturing costs.

[0079] While preferred embodiments have been described above, this disclosure is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various modifications are possible without departing from the spirit of this disclosure. Any modifications made without departing from the spirit of this disclosure will naturally fall within the technical scope of this disclosure. [Explanation of Symbols]

[0080] 10: Display device, 12: Display area, 14: Peripheral area, 15A: First plane, 15B: Second plane, 15C: First side, 16: Common wiring, 18: Common wiring, 20: Display device, 22: Common wiring area, 24: Flexible printed circuit, 26: Terminal section, 28: Gate drive circuit, 30: Display device, 32: Gate wiring area, 34: Flexible printed circuit, 36: Terminal section, 38: Source drive circuit, 42: Source wiring area, 46: Protection circuit, 48: Gate inspection circuit, 52: Source inspection circuit, 54 : Inspection line, 56: Pad, 58: Protection circuit, 59: Protection circuit, 102: Display panel, 104: Light source, 110: Light emission control circuit, 150: Array substrate, 151A: First transparent substrate, 151B: Second transparent substrate, 152: Opposing substrate, 154: Encapsulation material, 202: Scanning signal line, 203: Insulating film, 205: Insulating film, 206: Conductive layer, 207: Planarization film, 208: Conductive layer, 209: Insulating film, 210: Liquid crystal layer, 212: Conductive layer, 214: Conductive layer, 216: Pixel electrode, 218: Common electrode, 219: Light shielding layer

Claims

1. An array substrate including a pixel electrode and a planarization film having an opening in a region overlapping with the pixel electrode, A counter substrate is positioned opposite and at a distance from the array substrate, and includes a common electrode facing the pixel electrode, The liquid crystal layer between the array substrate and the opposing substrate, It has, The pixel electrode is arranged in a region that overlaps with the aperture. A display device in which a first spacer is arranged in a region overlapping with the aforementioned opening to narrow the distance between the pixel electrode and the common electrode.

2. The display device according to claim 1, wherein the first spacer is provided between the opposing substrate and the common electrode.

3. The array substrate further comprises a second spacer that maintains a constant distance between the array substrate and the opposing substrate. The second spacer is positioned between the opposing substrate and the common electrode. The display device according to claim 2.

4. The first spacer is provided in the opening, The display device according to claim 1, wherein the pixel electrode is provided along the upper surface of the planarization film and the upper surface of the first spacer.

5. The display device according to claim 1, wherein the first spacer is transparent to visible light.

6. The display device according to claim 1, wherein the first spacer protrudes toward the inside of the opening.

7. The array substrate includes scan signal lines, data signal lines, and transistors. The planarization film covers the scan signal line, the data signal line, and the transistor. The display device according to claim 1, wherein the pixel electrode is electrically connected to the transistor.

8. The array substrate further comprises a second spacer that maintains a constant distance between the array substrate and the opposing substrate. The display device according to claim 1, wherein the protruding height of the first spacer is greater than the protruding height of the second spacer.

9. The first spacer is connected to one of the array substrate and the opposing substrate, The display device according to claim 8, wherein the second spacer is connected to both the array substrate and the opposing substrate.

10. The display device according to claim 1, wherein the first spacer is disposed between the array substrate and the pixel electrode.

11. The display device according to claim 10, wherein the first spacer covers the bottom surface of the opening and at least a portion of the side surface of the opening.

12. The display device according to claim 10, wherein the planarization film is transparent to visible light.

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