Inverter load simulation device

Abstract

This invention provides an inverter load simulation device capable of producing a sinusoidal waveform output with suppressed distortion even at high switching frequencies. [Solution] The inverter load simulation device 1 includes switching circuits 13, 23, 33 which are bridge circuits composed of a plurality of switching elements SW1 to SW4, a drive control unit 51 which controls the driving of the plurality of switching elements SW1 to SW4 in the switching circuit 13, a filter 40 which converts the voltage output from the switching circuit 13 into a sinusoidal voltage, isolated DC / DC 11, 21, 31 which supply a DC voltage to the switching circuits 13, 23, 33 and which can change the DC voltage, and a DC voltage adjustment unit 52 which changes the DC voltage output by the isolated DC / DC 11, 21, 31 according to the voltage Vo output to the inverter P under test.

Description

Technical Field

[0001] The present invention relates to an inverter load simulation device that simulates a load on a test inverter.

Background Art

[0002] An inverter load simulation device that simulates a load on a test inverter is known. As such an inverter load simulation device, for example, Patent Document 1 discloses an inverter load simulation device that stably controls an output voltage and an output current while simulating a load so that a test inverter operates in a three-phase balanced state.

[0003] In the inverter load simulation device of Patent Document 1, a load inverter is connected to the test inverter and functions as a simulated load. By controlling the amplitude and phase of the output current of the load inverter, the test inverter can be tested in a state equivalent to that in which a motor is connected to the test inverter.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] By the way, in an inverter load simulation device such as that of Patent Document 1, a clean sine wave output that is less likely to affect the evaluation of a test body inverter, which is the test inverter, is required, and miniaturization of the entire device is also required.

[0006] To achieve the clean sinusoidal output described above, one possible configuration is to equip the inverter load simulation device with a filter that removes harmonic components from the output voltage to obtain a sinusoidal output. Furthermore, in order to miniaturize the entire device, one possible configuration is to increase the switching frequency of the switching elements used in the inverter load simulation device to reduce the size of the filter.

[0007] However, as mentioned above, increasing the switching frequency increases the effect of the dead time, which is the time when a pair of electrically connected switching elements are turned off to prevent short circuits. This results in distortion of the sinusoidal waveform output from the inverter load simulation device.

[0008] Therefore, there is a need for an inverter load simulation device that suppresses output distortion due to dead time even at high switching frequencies. In other words, there is a need for an inverter load simulation device that can achieve a sinusoidal waveform output with suppressed distortion even at high switching frequencies.

[0009] The objective of this invention is to realize an inverter load simulation device that can achieve a sinusoidal waveform output with suppressed distortion even at high switching frequencies. [Means for solving the problem]

[0010] An inverter load simulation device according to one embodiment of the present invention simulates a load on an inverter under test. The inverter load simulation device includes a switching circuit which is a bridge circuit composed of a plurality of switching elements; a drive control unit which controls the driving of the plurality of switching elements in the switching circuit; a filter which converts the voltage output from the switching circuit into a sinusoidal voltage; a variable DC voltage power supply unit which supplies a DC voltage to the switching circuit and can change the DC voltage; and a DC voltage adjustment unit which increases or decreases the DC voltage output by the variable DC voltage power supply unit in accordance with the increase or decrease of the output voltage output to the inverter under test (first configuration).

[0011] The distortion of the sinusoidal waveform output due to dead time is determined by the DC voltage, which is the input voltage to the switching circuit of the inverter load simulation device, the duration of the dead time, and the switching period. Therefore, when the output voltage of the inverter load simulation device is low, the on time in the waveform of the voltage output from the switching circuit becomes shorter, and the effect of the dead time becomes larger.

[0012] In contrast, as described above, by changing the DC voltage, which is the input voltage to the switching circuit, according to the output voltage output from the inverter load simulation device to the inverter under test, the effect of the dead time on the waveform of the voltage output from the switching circuit can be suppressed.

[0013] Therefore, it is possible to realize an inverter load simulation device that can achieve a sinusoidal waveform output with suppressed distortion even at high switching frequencies.

[0014] In the first configuration, when the output voltage to the inverter under test decreases, the DC voltage adjustment unit reduces the DC voltage, and the drive control unit generates a drive signal and outputs it to the switching circuit such that the on-time of the drive signal output for drive control to the plurality of switching elements is longer than the on-time of the drive signal when the output voltage is reduced by shortening the on-time without reducing the DC voltage (second configuration).

[0015] In the above configuration, when the DC voltage output by the variable DC voltage power supply is reduced in response to a decrease in the output voltage to the inverter under test, the on-time of the drive signals output to multiple switching elements is increased. This makes it possible to maintain the output voltage to the inverter under test while reducing the effect of dead time on the waveform of the voltage output from the switching circuit.

[0016] Therefore, it is possible to realize an inverter load simulation device that can achieve a sinusoidal waveform output with suppressed distortion even at high switching frequencies.

[0017] In the first or second configuration described above, the filter has an inductor component and a capacitor component. The drive control unit generates a drive signal for driving and controlling the plurality of switching elements so as to cancel out harmonic components included in the output voltage of the inverter under test (third configuration).

[0018] This allows for the drive and control of multiple switching elements to cancel out harmonic components in the output voltage of the inverter under test. Therefore, it is possible to realize an inverter load simulation device that can achieve a sinusoidal waveform output with suppressed distortion even at high switching frequencies.

[0019] In the third configuration described above, the drive control unit generates a drive signal for driving and controlling the plurality of switching elements without considering harmonic components included in the output voltage to the inverter under test, when the on / off period in the drive signal is greater than or equal to a predetermined value (fourth configuration).

[0020] When the on / off period of the drive signal for multiple switching elements exceeds a predetermined value, the rate of change per unit time of the output voltage for the inverter under test becomes large. Therefore, compared to the case where the period is low, the effect of distortion on the voltage becomes smaller, and time delay becomes noticeable when distortion correction control such as in the third configuration is performed. Thus, when the period exceeds a predetermined value, distortion correction control such as in the third configuration is not performed, thereby achieving a sinusoidal waveform output with suppressed distortion.

[0021] Therefore, it is possible to realize an inverter load simulation device that can produce a sinusoidal waveform output with suppressed distortion from low frequencies to high frequencies.

[0022] In the third configuration, the drive control unit adds the current value of the current flowing through the test inverter to the current command when generating the drive signal (fifth configuration).

[0023] When the capacitor current flowing through the capacitor component included in the filter fluctuates, distortion occurs in the waveform of the voltage output to the test inverter. Therefore, by suppressing the fluctuation of the capacitor current, the distortion of the voltage waveform can be suppressed.

[0024] As described above, by adding the current flowing through the test inverter to the current command when generating the drive signal, it is possible to suppress the capacitor current from flowing through the test inverter. Thereby, the fluctuation of the capacitor current due to the current flowing through the test inverter can be suppressed, and the distortion of the voltage waveform can be suppressed.

[0025] Therefore, it is possible to realize an inverter load simulation device capable of realizing an output of a sinusoidal waveform with suppressed distortion.

Effects of the Invention

[0026] An inverter load simulation device according to an embodiment of the present invention includes a switching circuit that is a bridge circuit composed of a plurality of switching elements, a drive control unit that controls the driving of the plurality of switching elements in the switching circuit, a filter that converts the voltage output from the switching circuit into a sinusoidal voltage, a variable DC voltage power supply unit that supplies a DC voltage to the switching circuit and can change the DC voltage, and a DC voltage adjustment unit that changes the DC voltage output from the variable DC voltage power supply unit according to the voltage output to the test inverter.

[0027] As described above, it is possible to reduce the influence of dead time on the waveform of the voltage output from the switching circuit. Therefore, it is possible to realize an inverter load simulation device capable of realizing an output of a sinusoidal waveform with suppressed distortion even at a high switching frequency.

Brief Description of the Drawings

[0028] [Figure 1] Figure 1 is a diagram showing the schematic configuration of the inverter load simulation device according to Embodiment 1, using functional blocks. [Figure 2] Figure 2 is a functional block diagram showing the detailed configuration of the drive control unit and the DC voltage adjustment unit. [Figure 3] Figure 3 shows an example of a drive signal for one of the switching elements in a switching circuit. [Figure 4] Figure 4 shows an example of the output voltage waveform output from the inverter load simulation device to the inverter under test. [Figure 5] Figure 5 is a diagram showing the schematic configuration of the drive control unit of the inverter load simulation device according to Embodiment 2, using functional blocks. [Figure 6] Figure 6 shows a schematic configuration of the filter. [Modes for carrying out the invention]

[0029] Embodiments of the present invention will be described in detail below with reference to the drawings. The same or corresponding parts in the drawings are denoted by the same reference numerals, and their descriptions will not be repeated.

[0030] [Embodiment 1] Figure 1 is a diagram showing the schematic configuration of an inverter load simulation device 1 according to Embodiment 1 of the present invention, using functional blocks. This inverter load simulation device 1 simulates the load on the inverter P under test. Specifically, the inverter load simulation device 1 converts a DC voltage to an AC voltage by driving a switching circuit, and outputs a voltage to the inverter P under test that simulates the load on the inverter P under test in response to the driving of the inverter P under test. The load is, for example, a motor. The load may be something other than a motor, as long as it is an object driven by the inverter under test.

[0031] The inverter load simulation device 1 of this embodiment is configured to output three-phase AC voltages so as to be driven as a load for a three-phase inverter P under test. That is, the inverter load simulation device 1 has three power conversion units 10, 20, and 30 that output AC voltages for each phase.

[0032] The inverter load simulation device 1 comprises three power conversion units 10, 20, and 30, a filter 40, and a control unit 50. Power conversion unit 10 comprises an isolated DC / DC converter 11, a capacitor 12, and a switching circuit 13. Similarly, power conversion unit 20 comprises an isolated DC / DC converter 21, a capacitor 22, and a switching circuit 23. Power conversion unit 30 comprises an isolated DC / DC converter 31, a capacitor 32, and a switching circuit 33.

[0033] In other words, the inverter load simulation device 1 includes isolated DC / DC 11, 21, 31 (variable DC voltage power supply units), capacitors 12, 22, 32, switching circuits 13, 23, 33, a filter 40, and a control unit 50. The power conversion units 10, 20, 30 for each phase have a similar configuration. Therefore, in the following, only the power conversion unit 10 will be described, and the descriptions of the power conversion units 20 and 30 will be omitted.

[0034] The isolated DC / DC converter 11 converts the DC voltage of a power supply (not shown) to a predetermined DC voltage Vdc while electrically isolating the input and output sides. The isolated DC / DC converter 11 can change the output voltage using a voltage adjustment signal output from the DC voltage adjustment unit 52 of the control unit 50, which will be described later. The isolated DC / DC converter 11 has, for example, a plurality of switching elements (not shown) to change the output voltage. The plurality of switching elements are driven by the voltage adjustment signal. The configuration of the isolated DC / DC converter 11 is the same as that of a conventional configuration, so a detailed explanation is omitted.

[0035] Capacitor 12 is electrically connected to the output side of the isolated DC / DC converter 11. Capacitor 12 can stabilize the voltage supplied from the isolated DC / DC converter 11 to the switching circuit 13.

[0036] The switching circuit 13 converts the DC voltage Vdc output from the isolated DC / DC converter 11 into an AC voltage and outputs it, simulating the load in response to the drive of the inverter P under test. The switching circuit 13 has multiple switching elements SW1 to SW4. In this embodiment, the switching circuit 13 has four switching elements SW1 to SW4. The other switching circuits 23 and 33 also each have four switching elements SW1 to SW4.

[0037] Switching elements SW1 and SW2 are electrically connected in series. Switching elements SW3 and SW4 are electrically connected in series. Switching elements SW1 and SW2, and switching elements SW3 and SW4, which are electrically connected in series, are electrically connected in parallel. The midpoints of switching elements SW1 and SW2 are electrically connected to the inverter P under test via a filter 40, which will be described later. The midpoints of switching elements SW3 and SW4 are electrically connected to the midpoints of pairs of switching elements in other power conversion units 20 and 30.

[0038] Thus, the multiple switching elements SW1 to SW4 in the switching circuit 13 constitute an H-bridge circuit. In other words, the switching circuit 13 is a bridge circuit composed of multiple switching elements SW1 to SW4. The multiple switching elements SW1 to SW4 in the switching circuit 13 are driven and controlled by the drive control unit 51 of the control unit 50, which will be described later.

[0039] The filter 40 converts the AC voltage output from the switching circuit 13 into a sinusoidal voltage. The filter 40 has, for example, an inductor component and a capacitor component. The sinusoidal voltage output from the filter 40 is output to the inverter P under test. The configuration of the filter 40 is the same as that of conventional configurations, so a detailed explanation is omitted.

[0040] The control unit 50 controls the driving of the switching circuit 13 and the isolated DC / DC converter 11. Specifically, the control unit 50 includes a drive control unit 51 and a DC voltage adjustment unit 52.

[0041] The drive control unit 51 controls the driving of the switching elements SW1 to SW4 of the switching circuits 13, 23, and 33 in the power conversion units 10, 20, and 30 of each phase. Specifically, the drive control unit 51 generates a drive signal that controls the driving of each switching element so that it outputs an AC voltage from the switching circuits 13, 23, and 33, and outputs it to each switching element.

[0042] The DC voltage adjustment unit 52 controls the driving of the isolated DC / DC converters 11, 21, and 31 in the power conversion units 10, 20, and 30 of each phase. The DC voltage adjustment unit 52 generates and outputs the voltage adjustment signal according to the voltage output from the isolated DC / DC converters 11, 21, and 31 and the output voltage Vo of the inverter load simulation device 1.

[0043] Figure 2 is a functional block diagram showing the detailed configuration of the drive control unit 51 and the DC voltage adjustment unit 52. The drive control unit 51 includes a load simulation voltage command generation unit 61, a voltage 3-phase 2-phase conversion unit 62, a current 3-phase 2-phase conversion unit 63, a 2-phase 3-phase conversion unit 64, a voltage controller 65, and a PWM signal generation unit 66.

[0044] The voltage 3-phase 2-phase conversion unit 62 converts the 3-phase output voltages Vuv, Vvw, Vwu to the inverter P under test into 2-phase voltages Vd, Vq. The current 3-phase 2-phase conversion unit 63 converts the 3-phase currents Iu, Iv, Iw flowing through the inverter P under test into 2-phase currents Id, Iq. The configurations of the voltage 3-phase 2-phase conversion unit 62 and the current 3-phase 2-phase conversion unit 63 are the same as in conventional configurations, so a detailed explanation is omitted. In the following, the output voltage Vo will also be represented as the 3-phase output voltages Vuv, Vvw, Vwu. Also, the 3-phase currents Iu, Iv, Iw will be represented as current Io in Figure 1.

[0045] The load simulation voltage command generation unit 61 generates load simulation voltage commands (Vd command, Vq command) based on the two-phase currents Id and Iq converted by the three-phase to two-phase current conversion unit 63. The voltage commands (Vd command, Vq command) generated by the load simulation voltage command generation unit 61 are input to the voltage controller 65 after the two-phase voltages Vd and Vq converted by the three-phase to two-phase voltage conversion unit 62 are subtracted from them. Meanwhile, the voltage commands (Vd command, Vq command) are input to the output voltage calculation unit 71 of the DC voltage adjustment unit 52, which will be described later. The configuration of the load simulation voltage command generation unit 61 is the same as the conventional configuration, so a detailed explanation is omitted.

[0046] The voltage commands (Vd command, Vq command) input to the voltage controller 65 are input to the two-phase to three-phase conversion unit 64 and converted into three-phase voltage commands. Subsequently, the PWM signal generation unit 66 uses the three-phase voltage commands to generate drive signals for the switching elements SW1 to SW4 of the switching circuits 13, 23, and 33. The configurations of the two-phase to three-phase conversion unit 64, the voltage controller 65, and the PWM signal generation unit 66 are the same as in conventional configurations, so a detailed explanation is omitted.

[0047] This allows the three-phase output voltages Vuv, Vvw, Vwu and the three-phase currents Iu, Iv, Iw flowing through the inverter P to be used to generate drive signals for the switching elements SW1 to SW4 of the switching circuits 13, 23, and 33. Therefore, the drive control unit 51 can drive and control the switching elements SW1 to SW4 of the switching circuits 13, 23, and 33.

[0048] The DC voltage adjustment unit 52 includes an output voltage calculation unit 71, an isolated DC / DC voltage command generation unit 72, a voltage controller 73, and a PWM signal generation unit 74.

[0049] The output voltage calculation unit 71 uses the voltage commands (Vd command, Vq command) output from the load simulation voltage command generation unit 61 of the drive control unit 51 to calculate the output voltage Vo for the inverter P under test. Specifically, the output voltage calculation unit 71 calculates √(Vd 2 +Vq 2The output voltage Vo is calculated using the formula.

[0050] The isolated DC / DC voltage command generation unit 72 generates voltage commands for the isolated DC / DC 11, 21, and 31 using the output voltage Vo. The generated voltage commands are then added to the voltages output from the isolated DC / DC 11, 21, and 31 (isolated DC / DC output voltages in Figure 2) and input to the voltage controller 73. The PWM signal generation unit 74 uses the voltage commands input to the voltage controller 73 to generate and output a drive signal (voltage adjustment signal) for driving and controlling a switching element (not shown) that adjusts the voltages output from the isolated DC / DC 11, 21, and 31.

[0051] The configurations of the isolated DC / DC voltage command generation unit 72, the voltage controller 73, and the PWM signal generation unit 74 are the same as in the conventional configuration, so a detailed explanation is omitted.

[0052] With the above configuration, the DC voltage adjustment unit 52 can generate and output a voltage adjustment signal that adjusts the voltage output to the switching circuits 13, 23, and 33 in the voltage conversion units 10, 20, and 30 of each phase, according to the voltage output from the isolated DC / DC converters 11, 21, and 31 and the output voltage Vo of the inverter load simulation device 1.

[0053] Incidentally, in switching circuits 13, 23, and 33 having the configuration described above, a dead time is required in which both of the electrically series-connected switching elements (in this embodiment, switching elements SW1, SW2 and switching elements SW3, SW4) are in the off state. Such a dead time affects the distortion of the voltage waveform output from switching circuits 13, 23, and 33. In particular, the effect of the dead time is significant when the on time of the switching elements is short.

[0054] In this case, if Dvo (hereinafter referred to as voltage distortion rate) is the ratio of the dead time to the output voltage Vo, it can be expressed by the following equation (1). Dvo = Vdc / Vo × (Td / Tc) (1) Here, Td is the dead time, and Tc is the switching period. Therefore, Td / Tc is a constant value. Consequently, by increasing or decreasing the DC voltage Vdc according to the output voltage Vo, the voltage distortion rate Dvo with respect to the output voltage Vo can be suppressed.

[0055] Therefore, in the inverter load simulation device 1 of this embodiment, the DC voltage adjustment unit 52 reduces the voltage output from the isolated DC / DC 11, 21, 31 to the switching circuits 13, 23, 33 when the output voltage Vo decreases. This allows the desired output voltage Vo to be obtained without shortening the on-time. Thus, distortion of the voltage waveform output from the switching circuits 13, 23, 33 due to the effects of the dead time can be suppressed.

[0056] The DC voltage adjustment unit 52, when the output voltage Vo decreases, lowers the DC voltage Vdc output from the isolated DC / DC 11, 21, 31 to the switching circuits 13, 23, 33 to a level lower than the DC voltage Vdc before the output voltage Vo decreased. When lowering the DC voltage Vdc, the DC voltage adjustment unit 52 determines an acceptable voltage distortion rate Dvo based on the required specifications, and lowers the DC voltage Vdc according to the output voltage Vo so that the voltage distortion rate Dvo is less than or equal to that rate. When the output voltage Vo decreases, the DC voltage adjustment unit 52 may lower the voltage output from the isolated DC / DC 11, 21, 31 to the switching circuits 13, 23, 33 by a predetermined percentage, or it may lower it to a voltage equivalent to the output voltage Vo.

[0057] When the DC voltage adjustment unit 52 reduces the DC voltage Vdc output from the isolated DC / DC 11, 21, 31 to the switching circuits 13, 23, 33 as described above, the drive control unit 51 generates the drive signal and outputs it to the switching circuits 13, 23, 33 such that the on-time of the drive signal output for drive control to the multiple switching elements SW1 to SW4 is longer than the on-time of the drive signal when the output voltage Vo is reduced by shortening the on-time without reducing the DC voltage Vdc.

[0058] Figure 3 shows an example of a drive signal for one of the switching elements SW1 to SW4 in the switching circuit 13. Figure 3(a) is an example of the drive signal when the voltage Vdc=x output from the isolated DC / DC 11,21,31 to the switching circuits 13,23,33 is and the output voltage Vo has not yet decreased. Figure 3(b) is an example of the drive signal when Vdc=x and the output voltage Vo has decreased. Figure 3(c) is an example of the drive signal when Vdc=x / 5 and the output voltage Vo has decreased.

[0059] Figure 4 shows an example of the waveform of the output voltage Vo output from the inverter load simulation device 1 to the inverter P under test. Figure 4(a) shows an example of the waveform of the output voltage Vo when the drive signal shown in Figure 3(b) is input to the switching element. Figure 4(b) shows an example of the waveform of the output voltage Vo when the drive signal shown in Figure 3(c) is input to the switching element. Note that Figure 4 shows the voltage waveforms for two phases (solid line, dashed line).

[0060] In the case shown in Figure 3(a), the effect of the dead time on the duration that the switching element is ON is not very large. However, as the output voltage Vo decreases, as shown in Figure 3(b), the duration that the switching element is ON becomes shorter, and the effect of the dead time becomes larger. As a result, as shown in Figure 4(a), distortion occurs in the waveform of the output voltage Vo from the inverter load simulation device 1 to the test inverter P.

[0061] In contrast, as shown in Figure 3(c), by lowering Vdc in accordance with the decrease in output voltage Vo, the effect of dead time on the period during which the switching element is ON can be reduced to the same extent as in the case of Figure 3(a). Therefore, as shown in Figure 4(b), distortion occurring in the waveform of the output voltage Vo can be suppressed.

[0062] Furthermore, it is preferable that the DC voltage adjustment unit 52 reduces the voltage output from the isolated DC / DC converters 11, 21, 31 to the switching circuits 13, 23, 33 to an extent that suppresses distortion of the voltage waveform output from the switching circuits 13, 23, 33 when the output voltage Vo decreases.

[0063] The inverter load simulation device 1 according to this embodiment simulates the load on the inverter P under test. The inverter load simulation device 1 includes switching circuits 13, 23, and 33, which are bridge circuits composed of a plurality of switching elements SW1 to SW4; a drive control unit 51 that controls the driving of the plurality of switching elements SW1 to SW4 in the switching circuit 13; a filter 40 that converts the voltage output from the switching circuit 13 into a sinusoidal voltage; isolated DC / DC converters 11, 21, and 31 that supply a DC voltage Vdc to the switching circuits 13, 23, and 33 and can change the DC voltage Vdc; and a DC voltage adjustment unit 52 that changes the DC voltage Vdc output by the isolated DC / DC converters 11, 21, and 31 according to the voltage Vo output to the inverter P under test.

[0064] As described above, by changing the DC voltage Vdc, which is the input voltage to the switching circuits 13, 23, and 33, in accordance with the voltage Vo output from the inverter load simulation device 1 to the inverter P under test, the effect of dead time on the waveform of the voltage output from the switching circuits 13, 23, and 33 can be suppressed.

[0065] Therefore, an inverter load simulation device 1 can be realized that can produce a sinusoidal waveform output with suppressed distortion even at high switching frequencies.

[0066] Furthermore, in this embodiment, when the output voltage Vo for the inverter P under test decreases, the DC voltage adjustment unit 52 reduces the DC voltage Vdc. The drive control unit 51 generates the drive signal and outputs it to the switching circuits 13, 23, and 33 such that the on-time of the drive signal output for drive control to the plurality of switching elements SW1 to SW4 is longer than the on-time of the drive signal when the output voltage is reduced by shortening the on-time without reducing the DC voltage Vdc.

[0067] This allows the DC voltage Vdc output by isolated DC / DC converters 11, 21, and 31 to be reduced in accordance with the decrease in the voltage Vo output to the inverter P under test. By increasing the on-time of the drive signals output to multiple switching elements SW1 to SW4, the voltage output to the inverter P under test can be maintained while minimizing the effect of dead time on the output voltage waveform from switching circuits 13, 23, and 33.

[0068] [Embodiment 2] Figure 5 is a diagram showing the schematic configuration of the drive control unit 151 of the inverter load simulation device 101 (see Figure 6) according to Embodiment 2, using functional blocks. The inverter load simulation device 101 of this embodiment differs from the inverter load simulation device 1 of Embodiment 1 in that the drive control unit 151 performs distortion correction control and corrects the voltage command according to the current flowing through the inverter P under test. In the following, components similar to those in Embodiment 1 are denoted by the same reference numerals and their descriptions are omitted, and only the parts that differ from Embodiment 1 will be described.

[0069] Figure 6 shows a schematic configuration of filter 40. As shown in Figure 6, filter 40 includes inductor components 41 and 42 and a capacitor component 43. That is, filter 40 is an LCL filter that does not include a resistive component. In filter 40, inductor components 41 and 42 are electrically connected in series. In addition, in filter 40, the capacitor component 43 connects the midpoint of inductor components 41 and 42 to a reference potential line that electrically connects the inverter load simulation device 101 (ILS in Figure 6) and the inverter P under test. Note that filter 40 of Embodiment 1 may have a similar configuration, or it may have a different configuration.

[0070] The drive control unit 151 receives the capacitor voltage Vc in the capacitor component 43 of the filter 40, as well as the ILS current I_ILS output from the inverter load simulation device 101 and the inverter current I_INV flowing through the inverter P under test. In Figure 5, the capacitor voltage Vc is represented by the three phase voltages Vcu, Vcv, and Vcw, the ILS current I_ILS is represented by the three phase currents Iu_ILS, Iv_ILS, and Iw_ILS, and the inverter current I_INV is represented by the three phase currents Iu, Iv, and Iw.

[0071] As shown in Figure 5, the drive control unit 151 includes a load simulation voltage command generation unit 61, a voltage 3-phase 2-phase conversion unit 62, a current 3-phase 2-phase conversion unit 63, a 2-phase 3-phase conversion unit 64, a voltage controller 65, a current controller 165, a PWM signal generation unit 66, a distortion correction unit 167, and a distortion gain selection unit 168.

[0072] The load simulation voltage command generation unit 61 generates voltage commands for the Vd command and Vq command using the two-phase inverter currents Id_INV and Iq_INV converted from the three-phase inverter currents Iu, Iv, and Iw by the three-phase current two-phase conversion unit 63. The Vd command and Vq command are output to a DC voltage adjustment unit (not shown), similar to Embodiment 1.

[0073] The Vd and Vq commands are input to the voltage controller 65 after the 2-phase capacitor voltages Vd_c and Vq_c, which are converted from the 3-phase capacitor voltages Vcu, Vcv, and Vcw by the 3-phase to 2-phase voltage conversion unit 62, are subtracted. The voltage controller 65 changes the output current command so that the voltage command becomes the capacitor voltage.

[0074] The current command is input to the current controller 165 after the two-phase inverter currents Id_INV and Iq_INV are added together and the two-phase ILS currents Id_ILS and Iq_ILS, which are converted from the three-phase ILS currents Iu_ILS, Iv_ILS, and Iw_ILS by the three-phase to two-phase current conversion unit 63, are subtracted. The current controller 165 changes the output voltage command so that the current command becomes the ILS current.

[0075] As described above, by adding the inverter currents Id_INV and Iq_INV to the current command, the current I_INV flowing through the inverter P under test can be output from the inverter load simulation device 101. This suppresses the flow of current through the capacitor component 43 of the filter 40. Therefore, the occurrence of distortion in the voltage waveform of the inverter P under test can be suppressed.

[0076] The voltage command output from the current controller 165 is input to the distortion correction unit 167, and after the distortion correction value Δ output from the distortion correction unit 167 is subtracted, it is converted into a three-phase voltage command by the two-phase to three-phase conversion unit 64 and input to the PWM signal generation unit 66.

[0077] The distortion correction unit 167 uses the voltage command output from the current controller 165, the two-phase capacitor voltages Vd_c and Vq_c, and the two-phase ILS currents Id_ILS and Iq_ILS to calculate the distortion correction value Δ by the following equation (2). The distortion correction value Δ is the harmonic component (noise generated by the switching operation of switching elements, etc.) included in the voltage output to the inverter P under test.

number

[0078] The distortion correction value Δ calculated by the distortion correction unit 167 is input to the distortion gain selection unit 168. The distortion gain selection unit 168 selects a multiplier of 1 when the switching frequency of the switching elements SW1 to SW4 of the switching circuits 13, 23, and 33 is low, and selects a multiplier of 0 when the switching frequency is high. The distortion gain selection unit 168 multiplies the input distortion correction value Δ by the selected multiplier and subtracts it from the voltage command output from the current controller 165.

[0079] Thus, in this embodiment, when the switching frequency is low, the inverter load simulation device 101 corrects the voltage command with a distortion correction value Δ. As a result, the inverter load simulation device 101 can output a voltage from which the distortion correction value Δ has been removed. On the other hand, when the switching frequency is high, the inverter load simulation device 101 does not correct the voltage command with a distortion correction value Δ. That is, when the on / off period of the drive signal for the switching elements SW1 to SW4 of the switching circuits 13, 23, 33 is greater than or equal to a predetermined value, the drive control unit 151 generates the drive signal without considering the harmonic components (distortion correction value Δ) included in the voltage output to the inverter P under test.

[0080] When the switching frequency is high, the output time of the low voltage with high distortion is shortened, so the distortion itself becomes smaller, and the distortion correction control described above becomes unnecessary. Furthermore, if distortion correction control is performed, the time delay becomes noticeable and worsens the distortion. As a result, problems such as differences in the peak value of the output voltage waveform occur. In contrast, by not performing distortion correction control when the switching frequency is high, as described above, a voltage waveform with less distortion can be obtained.

[0081] Furthermore, a high switching frequency refers to a frequency range where the on / off period of the drive signal for the switching elements SW1 to SW4 of the switching circuits 13, 23, and 33 is greater than or equal to a predetermined value, and where performing the distortion correction control described above would worsen the distortion. Conversely, a low switching frequency refers to a frequency range where the on / off period of the drive signal for the switching elements SW1 to SW4 of the switching circuits 13, 23, and 33 is lower than a predetermined value, and where performing the distortion correction control described above would improve the distortion.

[0082] In this embodiment, the filter 40 has inductor components 41, 42 and a capacitor component 43. The drive control unit 151 generates drive signals to drive and control a plurality of switching elements SW1 to SW4 so as to cancel harmonic components contained in the output voltage Vo of the inverter P under test.

[0083] This allows multiple switching elements to be driven and controlled in a way that cancels out harmonic components contained in the output voltage Vo of the inverter under test. Therefore, an inverter load simulation device 101 can be realized that can produce a sinusoidal waveform output with suppressed distortion even at high switching frequencies.

[0084] Furthermore, in this embodiment, if the on / off period in the drive signal is greater than or equal to a predetermined value, the drive control unit 151 generates a drive signal for driving and controlling a plurality of switching elements SW1 to SW4 without considering the harmonic components included in the output voltage Vo for the inverter P under test.

[0085] When the on / off period of the drive signals for multiple switching elements SW1 to SW4 exceeds a predetermined value, the rate of change per unit time of the voltage output to the inverter P under test becomes large. Therefore, compared to the case where the period is low, the effect of distortion on the output voltage Vo becomes smaller, and time delay becomes noticeable when distortion correction control is performed. Thus, by not performing distortion correction control when the period exceeds a predetermined value, a sinusoidal waveform output with suppressed distortion can be achieved.

[0086] Therefore, an inverter load simulation device 101 can be realized that can produce a sinusoidal waveform output with suppressed distortion from low frequencies to high frequencies.

[0087] Furthermore, in this embodiment, the drive control unit 151 adds the current value of the current flowing through the inverter P under test to the current command used to generate the drive signal.

[0088] When the capacitor current flowing through the capacitor component 43 included in the filter 40 fluctuates, distortion occurs in the waveform of the output voltage Vo for the inverter P under test. Therefore, by suppressing the fluctuation of the capacitor current, the distortion of the output voltage Vo waveform can be suppressed.

[0089] As described above, by adding the current value of the current flowing through the inverter P under test to the current command used to generate the drive signal, the flow of the capacitor current through the inverter P under test can be suppressed. This suppresses fluctuations in the capacitor current caused by the current flowing through the inverter P under test, and suppresses distortion of the output voltage Vo waveform.

[0090] (Other embodiments) Although embodiments of the present invention have been described above, the embodiments described above are merely examples for carrying out the present invention. Therefore, the invention is not limited to the embodiments described above, and it is possible to carry out the invention by appropriately modifying the embodiments described above without departing from the spirit of the invention.

[0091] In each of the above embodiments, the inverter load simulation device 1,101 outputs a three-phase AC voltage. However, the inverter load simulation device may be configured to output a single-phase or multi-phase AC voltage.

[0092] In each of the above embodiments, the DC voltage adjustment unit 52 may continuously change the DC voltage output from the isolated DC / DC 11, 21, and 31 according to the output voltage Vo, or it may change it in steps.

[0093] In the above embodiment 1, the operation of the DC voltage adjustment unit 52 when the output voltage Vo of the inverter load simulation device 1 decreases was described. However, the DC voltage adjustment unit 52 may also increase the DC voltage output from the isolated DC / DC 11, 21, 31 in accordance with the increase in the output voltage Vo of the inverter load simulation device 1.

[0094] Furthermore, in the first embodiment described above, an example was given in which the DC voltage Vdc is changed to 1 / 5 when the output voltage Vo of the inverter load simulation device 1 decreases. However, this is just one example, and the DC voltage Vdc may be changed to other values.

[0095] In Embodiment 2, the Vd command and Vq command generated by the load simulation voltage command generation unit 61 are output to a DC voltage adjustment unit (not shown). However, the Vd command and Vq command do not necessarily have to be output to the DC voltage adjustment unit. In other words, in Embodiment 2, the DC voltage output from the isolated DC / DC converter does not need to be changed according to the output voltage of the inverter load simulation device, as in Embodiment 1.

[0096] In the above embodiment 2, the drive control unit 151 performs strain correction control using the ILS current I_ILS. However, the drive control unit may also perform strain correction control using a current command generated within the drive control unit. [Industrial applicability]

[0097] This invention can be used in an inverter load simulation device that simulates the load on an inverter under test. [Explanation of Symbols]

[0098] 1.101 Inverter Load Simulation Device 10, 20, 30 Power conversion section 11, 21, 31 Isolated DC / DC (Variable DC Voltage Power Supply) 12, 22, 32 Capacitors 13, 23, 33 Switching Circuits 40 filters 41, 42 Inductor components 43 Capacitor components 50 Control Unit 51, 151 Drive control unit 52 DC Voltage Regulating Section 61 Load simulation voltage command generation unit 62 Voltage 3-phase 2-phase conversion unit 63 Current 3-phase 2-phase conversion unit 64 Two-phase to three-phase conversion unit 65, 73 Voltage Controllers 66, 74 PWM signal generation section 71 Output Voltage Calculation Section 72 Isolated DC / DC Voltage Command Generation Unit 165 Current Controller 167 Distortion Correction Section 168 Distortion Gain Selection Section P Inverter under test SW1~SW4 Switching elements Vo Output Voltage Vc Capacitor voltage Vdc DC voltage Iu, Iv, Iw: Three-phase currents flowing through the inverter under test. Id, Iq: Two-phase currents flowing through the inverter under test. I_ILS ILS current Id_ILS, Iq_ILS: Two-phase ILS currents Iu_ILS, Iv_ILS, Iw_ILS 3-phase ILS current Id_INV, Iq_INV: Two-phase inverter currents Iu, Iv, Iw 3-phase inverter current Vd_c, Vq_c are the two-phase capacitor voltages. Vcu, Vcv, Vcw: 32-phase capacitor voltages L1, L2 Inductance

Claims

1. An inverter load simulation device that simulates the load on an inverter under test, A switching circuit is a bridge circuit composed of multiple switching elements, A drive control unit that controls the driving of the plurality of switching elements in the switching circuit, A filter that converts the voltage output from the switching circuit into a sinusoidal voltage, A variable DC voltage power supply unit that supplies a DC voltage to the switching circuit and can change the DC voltage, A DC voltage adjustment unit that increases or decreases the DC voltage output by the variable DC voltage power supply unit in accordance with the increase or decrease in the output voltage output to the inverter under test, Having, Inverter load simulation device.

2. In the inverter load simulation device according to claim 1, When the output voltage to the inverter under test decreases, The DC voltage adjustment unit reduces the DC voltage, The drive control unit generates the drive signal and outputs it to the switching circuit such that the on-time of the drive signal output for drive control to the plurality of switching elements is longer than the on-time of the drive signal when the output voltage is reduced by shortening the on-time without reducing the DC voltage. Inverter load simulation device.

3. In the inverter load simulation device according to claim 1 or 2, The filter has an inductor component and a capacitor component. The drive control unit generates a drive signal for controlling the driving of the plurality of switching elements so as to cancel the harmonic components included in the output voltage of the inverter under test. Inverter load simulation device.

4. In the inverter load simulation device according to claim 3, The drive control unit generates a drive signal for controlling the multiple switching elements without considering harmonic components included in the output voltage of the inverter under test, if the on / off period in the drive signal is greater than or equal to a predetermined value. Inverter load simulation device.

5. In the inverter load simulation device according to claim 3, The drive control unit adds the current value of the current flowing through the inverter under test to the current command used to generate the drive signal. Inverter load simulation device.

Images