Communication module

Abstract

We provide a communication module that allows for a reduction in circuit size. [Solution] The communication module 10 is connected to the main device 201 and includes an amplification control device 101 that receives a main signal from the main device, which includes a command signal, an address signal that specifies the address of at least one register of the antenna switch 102 and the band select switch 103, and a write data signal that is recorded in the register corresponding to the address, and interprets the command signal. The communication module 10 includes an antenna switch 102 and a band select switch 103 that are connected to the amplification control device 101 through a first signal line through which a clock signal is transmitted and a second signal line through which a data signal is transmitted.

Description

Technical Field

[0001] The present invention relates to a communication module.

Background Art

[0002] In a semiconductor device, data may be transmitted and received between a plurality of devices by serial communication. In serial communication, a device includes a main device (master device) and a sub-device (slave device) connected to the main device. By the main device transmitting a signal to the sub-device, for example, writing of data to the sub-device is performed. The sub-device may interpret a command included in the signal from the main device and execute processing according to the command.

[0003] The circuit for command interpretation has a large circuit scale. Therefore, when a circuit for command interpretation is provided in each sub-device, the overall circuit scale also becomes large. Further, Patent Document 1 describes a configuration in which, instead of providing a circuit for command interpretation in each sub-device, an interface circuit for interpreting a signal from the main device is provided separately from the sub-devices.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the configuration described in Patent Document 1, the interface circuit is connected to the sub-device to which data is to be transmitted via a clock bus, a data bus, and an enable bus that sends an enable signal. In the configuration described in Patent Document 1, the interface circuit selects one of several sub-devices via the enable bus and transmits data to it. In this case, since an enable bus is provided for each sub-device, an area is required for the wiring of the enable bus, which increases the overall circuit size.

[0006] This invention has been made in view of these circumstances, and aims to provide a communication module that can reduce the size of the circuit. [Means for solving the problem]

[0007] A communication module according to one aspect of the present invention comprises a first sub-device connected to a main device, and at least one second sub-device that is not connected to the main device but is connected to the first sub-device through a first signal line on which a clock signal is transmitted and a second signal line on which a data signal is transmitted. The first subdevice receives a main signal from the main device, interprets the command signal, and generates a write instruction signal after receiving the command signal and while receiving the main signal if it writes information based on the data signal to one of the at least one second subdevice based on the interpretation result of the command signal, and supplies the write instruction signal through the first signal line or the second signal line, and the data signal through the second signal line, to each of the at least one second subdevice after receiving the command signal and while receiving the main signal. Each of the at least one second subdevice determines whether the register corresponding to the address indicated by the address signal is contained within at least one second subdevice, and if the register is contained within at least one second subdevice and a write instruction signal is supplied from the first subdevice, it writes the write data signal to the register.

[0008] A communication module according to another aspect of the present invention comprises: a first subdevice connected to a main device, which receives a main signal from the main device including a command signal and a device ID signal indicating a device ID that identifies the device, interprets the command signal, and is assigned first device ID information; a second subdevice connected to the first subdevice via a first signal line through which a clock signal is transmitted and a second signal line through which a data signal is transmitted, and is assigned second device ID information; and a third subdevice connected to the first subdevice via a third signal line through which a clock signal is transmitted and a fourth signal line through which a data signal is transmitted, and is assigned third device ID information. In the communication module, the first subdevice determines whether the device ID signal included in the main signal matches the first device ID information held by the first subdevice, and whether the device ID signal included in the main signal matches the second device ID information or the third device ID information held by the first subdevice. If the device ID signal included in the main signal matches the second device ID information held by the first subdevice, it generates a first subdevice control signal indicating data writing or reading to the second subdevice based on the interpretation result of the command signal, and supplies the first subdevice control signal to the second subdevice. If the device ID signal included in the main signal matches the third device ID information held by the first subdevice, it generates a second subdevice control signal indicating data writing or reading to the third subdevice based on the interpretation result of the command signal, and supplies the second subdevice control signal to the third subdevice. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide a communication module that can reduce the circuit size. [Brief explanation of the drawing]

[0010] [Figure 1] This figure shows an example of a circuit including a communication module according to the first embodiment. [Figure 2] This figure shows the configuration of the amplification control device in the communication module according to the first embodiment. [Figure 3] This diagram shows the configuration of subdevices in the communication module according to the first embodiment. [Figure 4] This is an example of the main signal and data signal according to the first embodiment. [Figure 5] This is another example of the main signal and data signal according to the first embodiment. [Figure 6] This is another example of the main signal and data signal according to the first embodiment. [Figure 7]Another example of the main signal and the data signal according to the first embodiment. [Figure 8] Another example of the main signal and the data signal according to the first embodiment. [Figure 9] It is a figure which shows another example of the structure of the sub - device in the communication module which concerns on 1st Embodiment. [Figure 10] It is a figure which shows another example of the structure of the sub - device in the communication module which concerns on 1st Embodiment. [Figure 11] It is a figure which shows an example of the circuit containing the communication module which concerns on 1st Embodiment. [Figure 12] It is a figure which shows the structure of the amplification control device in the communication module which concerns on 2nd Embodiment. [Figure 13] It is a figure which shows the structure of the sub - device in the communication module which concerns on 2nd Embodiment. [Figure 14] [[ID=2i]]It is an example of the signal which the amplification control device which concerns on 2nd Embodiment transmits and receives, and the signal which the sub - device transmits and receives. [Figure 15] It is another example of the signal which the amplification control device which concerns on 2nd Embodiment transmits and receives, and the signal which the sub - device transmits and receives. [Figure 16] It is a figure which shows an example of the circuit containing the communication module which concerns on 3rd Embodiment. [Figure 17] It is a flowchart which shows the process by the amplification control device in the communication module which concerns on 3rd Embodiment.

Modes for Carrying Out the Invention

[0011] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same elements are denoted by the same reference numerals, and redundant explanations are omitted as much as possible.

[0012] (First Embodiment) The first embodiment will be described. FIG. 1 shows an example of a circuit including a communication module 10, a main device 201, and analog circuits 301a, 301b, 301c according to the present embodiment.

[0013] The communication module 10 is a sub-device whose data communication is controlled by the main device 201.

[0014] The communication module 10 includes an amplification control device 101, an antenna switch 102, and a band select switch 103. The amplification control device 101 is an amplification control device that controls a power amplification circuit. The antenna switch 102 is an antenna switch that selects a signal amplified by the power amplification circuit and transmitted / received through an antenna. The band select switch 103 is a band select switch that selects the wavelength of a signal transmitted / received through an antenna. In the example of FIG. 1, the antenna switch 102 and the band select switch 103 are illustrated as sub-devices. However, the number of sub-devices may be more than two or may be one. Also, the functions of the devices connected to the main device 201 are not limited to power amplification, antenna control, and wavelength selection, and devices having other functions may be connected.

[0015] The amplification control device 101 is connected to the antenna switch 102 and the band select switch 103 respectively through two wirings, a clock signal line 104 and a data signal line 105. The amplification control device 101 and the antenna switch 102 and the band select switch 103 perform two-way communication by transmitting and receiving data through a two-wire bus. Note that the communication module 10 may follow the I2C method or may follow other communication methods.

[0016] The main device 201 transmits a main signal to the amplification control device 101 to rewrite the information stored in the registers of the antenna switch 102 or the band select switch 103. The main signal includes a command signal, an address signal specifying the address of at least one register of the antenna switch 102 or the band select switch 103, and a write data signal to be recorded in the register corresponding to the address. The main device 201 also transmits a clock signal to the amplification control device 101.

[0017] The command signal is information indicating the type of write based on the main signal. The command signal indicates the write format, such as a format that writes to at least one register in a device, a format that writes to one register in a device, or a format that writes to one register in a device while masking the bit value. The address signal is information that identifies each of the registers of the antenna switch 102 or the band select switch 103. The address signal is, for example, 5-bit or 8-bit data. The write data signal is the data to be written to the register, and its number of bits is, for example, 8 bits.

[0018] Analog circuit 301a is connected to the register of the amplification control device 101 and performs control, for example, bias control for power amplification, based on the information stored in the register of the amplification control device 101. Analog circuit 301b is connected to the register of the antenna switch 102 and performs, for example, switching between transmitting and receiving signals through the antenna, based on the information stored in the register of the antenna switch 102. Analog circuit 301c is connected to the register of the band select switch 103 and selects the wavelength of the signal transmitted and received through the antenna, based on the information stored in the register of the band select switch 103. In this embodiment, the amplification control device 101, the antenna switch 102, and the band select switch 103 are described as different devices, but the amplification control device 101, the antenna switch 102, and the band select switch 103 all have the common function of controlling analog circuits based on the information written to their respective registers.

[0019] Each part of the amplification control device 101 will be described with reference to Figure 2. The amplification control device 101 includes a data receiving unit 1011, a command start determination unit 1012, a data signal generation unit 1013, a clock enable signal generation unit 1014, a data transmission unit 1015, and a register unit 1016.

[0020] The data receiving unit 1011 receives the clock signal and main signal from the main device 201 and performs processing to interpret the main signal. For example, the data receiving unit 1011 generates command identification information to identify a command based on the information indicated by the command signal included in the main signal. The data receiving unit 1011 transmits the command identification information to the data signal generation unit 1013 and the clock enable signal generation unit 1014, which will be described later.

[0021] The data receiving unit 1011 transmits the address signal and the write data signal included in the main signal to the data signal generation unit 1013. The data receiving unit 1011 also generates bit position information indicating the position where command identification information is to be added, and transmits this information to the data signal generation unit 1013 and the clock enable signal generation unit 1014. In addition to information on the position where command identification information is to be added, the bit position information may also include information indicating the start and end positions of signals in the data signal, such as the start position of the address signal and the start position of the write data signal.

[0022] The command start determination unit 1012 determines, based on the clock signal and the main signal, whether or not the transmission of a command signal from the main device 201 to the amplification control device 101 has started. When the supply of a command signal starts, the command start determination unit 1012 transmits a command detection signal to the data transmission unit 1015. The command start determination unit 1012 also transmits a reset signal to the data signal generation unit 1013.

[0023] The data signal generation unit 1013 generates data signals to be transmitted to the antenna switch 102 and the band select switch 103 based on the command identification information, bit position information, address signal, and write data signal from the data reception unit 1011. The data signal generation unit 1013 transmits the data signals to the data transmission unit 1015.

[0024] The clock enable signal generation unit 1014 generates a clock enable signal based on command identification information and bit position information. The clock enable signal is a signal to start transmitting a data signal from the amplification control device 101 to the antenna switch 102. The clock enable signal generation unit 1014 generates a clock enable signal when the timing determined based on the bit position information indicates the time to start transmitting a data signal to the antenna switch 102 and the band select switch 103, and transmits it to the data transmission unit 1015.

[0025] When a command detection signal is input and a clock enable signal is supplied from the clock enable signal generation unit 1014, the data transmission unit 1015 transmits the data signal from the data signal generation unit 1013 to the antenna switch 102 and the band select switch 103 together with the clock signal supplied to the data transmission unit 1015. The data transmission unit 1015 transmits the clock signal through the clock signal line 104 and the data signal through the data signal line 105.

[0026] The register section 1016 is a rewritable memory area that includes registers. The register section 1016 also controls writing to each register based on signals from the data receiving section 1011. The register section 1016 is connected to the analog circuit 301a.

[0027] The communication module 10 performs parallel operation, communicating signals within the communication module 10 in parallel with receiving the main signal. The amplification control device 101 generates data signals to be sent to the antenna switch 102 and band select switch 103, and transmits the data signals to the antenna switch 102 and band select switch 103, in parallel with the processing of interpreting the main signal from the main device 201. This makes the processing more efficient compared to, for example, storing the signals to be written to the antenna switch 102 and band select switch 103 in the amplification control device 101, and then reading the information stored in the amplification control device 101 and transmitting it to the antenna switch 102 and band select switch 103.

[0028] The antenna switch 102 will be described with reference to Figure 3. Other sub-devices, including the band select switch 103, have a similar configuration for data communication equipment. The antenna switch 102 includes a data receiving unit 1021, a command start determination unit 1022, and a register unit 1023.

[0029] The data receiving unit 1021 receives the address signal and the write data signal included in the data signal.

[0030] The command start determination unit 1022 determines, based on the clock signal and the main signal, whether or not the transmission of a data signal from the amplification control device 101 to the antenna switch 102 has started. When the supply of a data signal is started, the command start determination unit 1012 sends a reset signal to the data receiving unit 1021.

[0031] The register section 1023 is a rewritable memory area that includes registers 10231, 10232, 10233, and 10234. The register section 1023 also controls writing to each register based on signals from the data reception section 1021. Each of the registers 10231, 10232, 10233, and 10234 has a unique address. In addition, each register of the band select switch 103 has an address that is different from or the same as the addresses of registers 10231, 10232, 10233, and 10234. The register section 1023 is connected to the analog circuit 301b.

[0032] Referring to Figure 4, an example of data signal generation by the amplification control device 101 and interpretation of the data signal by the antenna switch 102 will be explained. Figure 4 shows an example of the main signal and data signal when data is written to one register by a command that writes to at least one register in a certain device.

[0033] The main signals include the start signal, command signal, address signal, write data signal, and end signal in that order.

[0034] When the data receiving unit 1011 receives the main signal from the main device 201, the data receiving unit 1011 interprets the command signal. If the command signal is a command indicating that writes to at least one register in a certain device, the data signal generation unit 1013 generates information in which identification information B1 is added to the beginning of the address signal based on the address signal, command identification information, and bit position information. Identification information B1 is 1 bit of information; if the bit value is 0, it indicates that the address length is 5 bits, and if the bit value is 1, it indicates that the address length is 8 bits. The data transmission unit 1015 records the identification information B1 at the position corresponding to the beginning clock of the address signal in the main signal and transmits a data signal with the address signal shifted by 1 clock.

[0035] Next, the data signal generation unit 1013 generates information in which identification information B2 is added to the beginning of the write data signal following the address signal. Identification information B2 is 1 bit of information; if the bit value is 0, it indicates that the content of the following signal is a write data signal, and if the bit value is 1, it indicates that the content of the following signal is a mask signal that specifies bits not to be written. The data transmission unit 1015 uses the data signal corresponding to the beginning clock of the write data signal in the main signal as identification information B2, and transmits a data signal that is shifted by 1 clock. In addition, the data signal also includes parity bits at the beginning and end, and information indicating the actual write data is recorded in the bits sandwiched between the parity bits.

[0036] In the example shown in Figure 4, there is one write data signal included in the main signal. Therefore, the data signal generation unit 1013 generates the data signal by adding identification information B3 to the parity bit at the end of the write data signal. Identification information B3 is a single bit of information, and if the bit value is 0, it indicates that writing to the register based on the write data will not be performed. In this case, the register in the antenna switch 102 will not be rewritten. Also, if the bit value of identification information B3 is 1, identification information B3 indicates that writing to the register based on the write data will be performed. A signal with a bit of identification information B3 of 1 functions as a write instruction signal that indicates writing information based on the data signal to the register of the subdevice. Note that, for example, if there is an error in the write data signal, the data signal generation unit 1013 sets the bit value of identification information B3 to 0 to prevent writing.

[0037] In the communication module 10, each sub-device, such as the antenna switch 102 and the band select switch 103, receives the address signal included in the data signal received by the data receiving unit 1021.

[0038] The data receiving unit transmits a write enable signal to the register unit 1023 based on the identification information contained in the data signal. The register unit 1023 determines whether the interpreted address information is contained in its own register unit 1023 and corresponds to an address such as register 10231. If the address information corresponds to an address in its own register and the bit value of identification information B3 is 1, the register unit 1023 writes the write data signal to the corresponding register. Even if the bit value of identification information B3 is 1, if the interpreted address information does not correspond to an address in its own register, the register unit 1023 does not write to register 10231 or the like based on the write data signal.

[0039] This allows the final write operation to be determined based on whether the different addresses in each register match, even when a common data signal is sent from the amplification control device 101 to multiple sub-devices. This enables the registers of each sub-device to be rewritten appropriately.

[0040] Referring to Figure 5, another example of data signal generation by the amplification control device 101 and interpretation of the data signal by the antenna switch 102 will be explained. Figure 5 shows an example of the main signal and data signal when data is written to two registers by a command indicating that at least one register in a certain device should be written to.

[0041] The main signals include, in this order: start signal, command signal, address signal, first write data signal, second write data signal, and end signal.

[0042] The data transmission unit 1015 generates information in which identification information B1 is set to 0 and added to the beginning of the address signal. The data signal generation unit 1013 generates information in which identification information B2 is added to the beginning of the first write data signal following the address signal.

[0043] Next, the data signal generation unit 1013 generates information in which identification information B4 is appended to the end of the first write data signal following the first write data signal. In the example in Figure 5, identification information B4 is 1 bit of information, and similar to identification information B3, if the bit value is 0, it indicates that no write will be performed to the register based on the write data, and if the bit value is 1, it indicates that a write will be performed to the register based on the write data.

[0044] Finally, the data signal generation unit 1013 generates a data signal such that identification information B3 is added to the end of the write data signal.

[0045] In the example shown in Figure 5, the antenna switch 102 interprets the address information contained in the data signal received by the data receiving unit 1021. Here, we will explain the case where the address signal points to the register of the antenna switch 102 itself.

[0046] The data receiving unit 1021 receives the identification information B2 and the first write data signal following the address signal. Since the bit value of identification information B2 is 0, it determines that the subsequent data is write data. Next, the data receiving unit 1021 receives the identification information B4 and the second write data signal following the first data signal. Since the bit value of identification information B4 is 1, the data receiving unit 1021 determines that it may write the first write data to the register. Finally, the data receiving unit 1021 receives the identification information B3 following the second write data signal. Since the bit value of identification information B3 is 1, the data receiving unit 1021 determines that it may write the second write data to the register. At this time, the data receiving unit 1021 increments the address indicated by the first address information and writes the second write data to the subsequent register.

[0047] Referring to Figure 6, another example of data signal generation by the amplification control device 101 and interpretation of the data signal by the antenna switch 102 will be explained. Figure 4 shows an example of the main signal and data signal when data is written to one register in a device using a command that indicates writing the bit value to one register while masking it.

[0048] The main signals include, in this order, a start signal, a command signal, an address signal, a mask signal, a write data signal, and an end signal.

[0049] The data transmission unit 1015 generates information in which identification information B1 is set to 0 and added to the beginning of the address signal. Following the address signal, the data signal generation unit 1013 generates information in which identification information B2 is added to the beginning of the first write data signal. At this time, the data signal generation unit 1013 sets the bit of identification information B2 to 1 because the command indicates that the bit value will be written to one register in a certain device while masking the bit value.

[0050] Next, the data signal generation unit 1013 generates information in which identification information B5 is added to the beginning of the write data signal following the mask signal. In the example in Figure 5, identification information B5 is 1 bit of information, and similar to identification information B2, if the bit value is 0, it indicates that the content of the following signal is a write data signal, and if the bit value is 1, it indicates that the content of the following signal is a mask signal indicating the bit to be masked.

[0051] Finally, the data signal generation unit 1013 generates a data signal such that identification information B3 is added to the end of the write data signal.

[0052] In the example shown in Figure 6, the antenna switch 102 interprets the address information contained in the data signal received by the data receiving unit 1021.

[0053] The data receiving unit 1021 receives the identification information B2 and the mask signal that follows the address signal. Since the bit value of the identification information B2 is 1, it is determined that the subsequent signal is a mask signal.

[0054] Next, the data receiving unit 1021 receives the write data signal following the identification information B5 and the mask signal. Since the bit value of identification information B5 is 0, the data receiving unit 1021 determines that the content of the signal is write data. Finally, the data receiving unit 1021 receives the identification information B3 following the write data signal. Since the bit value of identification information B3 is 1, the data receiving unit 1021 determines that it is OK to write the write data to the register. At this time, the data receiving unit 1021 writes the write data to the register corresponding to the address indicated by the initial address information without rewriting the bit indicated by the mask signal.

[0055] In the examples shown in Figures 4 to 6, the data signal generation unit 1013 adds identification information B3 to the end of the data signal, enabling the antenna switch 102 to determine whether or not to write. However, the data signal generation unit 1013 does not necessarily need to include identification information B3 in the data signal. The communication module 10 may, for example, cause the antenna switch 102 to determine whether or not to write based on the presence or absence of a clock signal transmitted by the data transmission unit 1015.

[0056] An example of this case is shown in Figure 7. In the example in Figure 7, the main signal is the same as in Figure 4. However, the data signal generation unit 1013 differs from the example in Figure 4 in that it does not add identification information B3 to the end of the data signal.

[0057] In the example shown in Figure 7, when the amplification control device 101 allows the antenna switch 102 to write data, the data transmission unit 1015 transmits a clock signal C1 to the antenna switch 102 following the write data signal. The antenna switch 102 determines that data writing is possible when the data reception unit 1011 receives the clock signal C1 following the write data signal. The clock signal C1 functions as a write instruction signal indicating that information based on the data signal should be written to the register of the subdevice.

[0058] The example in Figure 8 shows a case where data is not written due to an error in the write data signal or other reasons. In this case, the data transmission unit 1015 does not transmit a clock signal to the antenna switch 102 following the write data signal. The antenna switch 102 does not write the data because the data reception unit 1011 does not receive a clock signal following the write data signal.

[0059] In this way, the communication module 10 determines whether or not data can be written to the antenna switch 102, etc., based on the clock signal or identification information from the amplification control device 101.

[0060] Figure 9 shows an example of another configuration of the antenna switch 102. The antenna switch 102A, which has a data receiving unit 1021A, can also be configured not to perform processing corresponding to a command that indicates writing while masking bit values.

[0061] Figure 10 shows an example of another configuration of the antenna switch 102. The antenna switch 102B, which has a data receiving unit 1021B, further includes a write clock generation unit 1024, which converts a write enable signal based on a data signal and controls writing to the register unit 1023 based on a clock signal, as described in Figures 7 and 8.

[0062] (Second Embodiment) A second embodiment will now be described. In the second and subsequent embodiments, the differences from the first embodiment will be mainly described, and the explanation of matters common to the first embodiment will be omitted. Figure 11 shows an example of a circuit including the communication module 110, the main device 201, and the analog circuits 301a, 301b, and 301c according to the second embodiment. The communication module 110 according to the second embodiment differs from the communication module 10 according to the first embodiment in that it allows reading from the register of the amplification control device 1101A, or the antenna switch 1102 or the band select switch 1103.

[0063] The communication module 110 is a sub-device whose data communication is controlled by the main device 201.

[0064] The communication module 110 includes an amplification control device 1101, an antenna switch 1102, and a band select switch 1103. For example, the amplification control device 1101 is an amplification control device that controls a power amplification circuit, the antenna switch 1102 is a switch that selects the signal amplified by the power amplification circuit and transmitted and received through the antenna, and the band select switch 1103 is a switch that selects the wavelength of the signal transmitted and received through the antenna. In the example in Figure 11, two sub-devices are shown as examples, but the number of sub-devices may be more than two, or it may be just one. The amplification control device 1101 has an analog circuit 301a, and the antenna switch 1102 and the band select switch 1103 each have analog circuits 301b and 301c, respectively. The functions of the analog circuits 301a, 301b, and 301c are the same as those of the analog circuits described in the first embodiment.

[0065] The amplification control device 1101 is connected to the antenna switch 1102 and the band select switch 1103, respectively, through two wires: a clock signal line 1104 and a data signal line 1105. The amplification control device 1101 and the antenna switch 1102 and the band select switch 1103 communicate bidirectionally, as in the first embodiment.

[0066] The amplification control device 1101 has a write mode in which it writes information to its own register or to the register of the antenna switch 1102 or the band select switch 1103, and a read mode in which it reads information from the register of the amplification control device 1101 or the register of the antenna switch 1102 or the band select switch 1103. The antenna switch 1102 and the band select switch 1103 have a write mode in which information is written to their own register and a read mode in which information is read from their own register. The write mode or read mode of the amplification control device 1101, the antenna switch 1102, and the band select switch 1103 can be switched based on a signal from the main device 201.

[0067] The main device 201 sends a main signal containing a command signal instructing the amplification control device 1101 to rewrite the information stored in the registers of the antenna switch 1102 or the band select switch 1103. Alternatively, the main device 201 sends a main signal containing a command signal instructing the amplification control device 1101 to read the information stored in the registers of the antenna switch 1102 or the band select switch 1103.

[0068] The main signal includes a command signal and an address signal that specifies the address of at least one register, each of the antenna switch 1102 and the band select switch 1103.

[0069] The command signal includes information instructing a write to the registers of the antenna switch 1102 or the band select switch 1103, or information instructing a readout of information stored in the registers of the antenna switch 1102 or the band select switch 1103. If the command signal includes information instructing a write to the registers of the antenna switch 1102 or the band select switch 1103, the command signal includes information indicating the type of write based on the main signal. In the case of a write, the command signal, as in the first embodiment, includes information indicating the write format, such as a format in which a write is performed to at least one register in a device, a format in which a write is performed to one register in a device, or a format in which a bit value is masked while writing to one register in a device.

[0070] When performing a write operation, the main device 201 sends a main signal to the amplification control device 1101 that includes a command signal containing information instructing the antenna switch 1102 or band select switch 1103 to write to its register, an address signal, and a write data signal to be recorded in the register.

[0071] When performing a read operation, the main device 201 sends a main signal to the amplification control device 1101 that includes a command signal containing information instructing the reading of information stored in the registers of the antenna switch 1102 or the band select switch 1103, and an address signal. The main device 201 also sends a clock signal to the amplification control device 1101.

[0072] The main device 201 may also write to and read from the registers of the amplification control device 1101, and may send a main signal to the amplification control device 1101 indicating a write or read operation.

[0073] The address signal is information that identifies the registers of either the antenna switch 1102 or the band select switch 1103. The address signal is, for example, 5-bit or 8-bit data.

[0074] Each part of the amplification control device 1101 will be described with reference to Figure 12. In addition to the command start determination unit 1012, data signal generation unit 1013, clock enable signal generation unit 1014, and register unit 1016 described in the first embodiment, the amplification control device 1101 also includes a data transmission / reception unit 1201, input / output buffer units 1202 and 1203, a mode control unit 1204, an input / output control circuit 1205, and a selection circuit 1206. In Figure 12, the transmission path of the signal corresponding to the information read from the amplification control device 1101, the antenna switch 1102, or the band select switch 1103 is shown by a dashed line.

[0075] The data transmission / reception unit 1201 receives the clock signal and main signal from the main device 201 and performs processing to interpret the main signal. For example, the data transmission / reception unit 1201 generates command identification information to identify a command based on the information indicated by the command signal included in the main signal. The data transmission / reception unit 1201 transmits the command identification information to the data signal generation unit 1013 and the clock enable signal generation unit 1014. The data transmission / reception unit 1201 also controls the antenna switch 1102 or band select switch 1103 to receive information read from the antenna switch 1102 or band select switch 1103 as a read signal and transmit it to the main device 201. The read signal may be transmitted to the main device 201 as a signal indicating that information stored in the register unit 1016 of the amplification control device 1101 has been read.

[0076] The input / output buffer section 1202 is a circuit that allows signals to pass through during communication between the amplification control device 1101 and the main device 201. The input / output buffer section 1203 is a circuit that allows signals to pass through during communication between the amplification control device 1101 and the antenna switch 1102 and the band select switch 1103.

[0077] The mode control unit 1204 is a circuit that controls the write mode or read mode of the amplification control device 1101. The main device 201 transmits a signal to the amplification control device 1101 to control the write mode or read mode of the amplification control device 1101. The data transmission / reception unit 1201 transmits a mode control signal to the mode control unit 1204 to set the write mode or read mode of the amplification control device 1101 based on the input from the main device 201. The mode control signal also includes information to set the read mode for reading information from the antenna switch 1102 or the band select switch 1103, or for reading information stored in the amplification control device 1101 itself.

[0078] The mode control unit 1204 stores information corresponding to the mode control signal. The information stored in the mode control unit 1204 is referenced by the input / output control circuit 1205 and the selection circuit 1206.

[0079] The input / output control circuit 1205 refers to the information stored in the mode control unit 1204 and determines whether the amplification control device 1101 is in write mode or read mode. Depending on the write mode and read mode setting, the input / output control circuit 1205 sends signals to the input / output buffer units 1202 and 1203 to control the transmission and reception of signals by the input / output buffer units 1202 and 1203.

[0080] In write mode, the input / output control circuit 1205 controls the input / output buffer unit 1202 to transmit the write data signal included in the main signal to the data transmission / reception unit 1201. Also in write mode, the input / output control circuit 1205 controls the input / output buffer unit 1203 to transmit a data signal or read instruction signal to the antenna switch 1102 and the band select switch 1103.

[0081] Furthermore, in read mode, the input / output control circuit 1205 controls the input / output buffer unit 1202 so that it transmits the read signal from the antenna switch 1102, the band select switch 1103, or the amplification control device 1101 to the main device 201 via the amplification control device 101. Also, in read mode, the input / output control circuit 1205 controls the input / output buffer unit 1203 so that it transmits the read signal from the antenna switch 1102 or the band select switch 1103 to the selection circuit 1206.

[0082] The selection circuit 1206 receives signals read from the antenna switch 1102 or the band select switch 1103, or signals of information stored in the amplification control device 1101 read from the register unit 1016 by the data transmission / reception unit 1201. The selection circuit 1206 refers to the information stored in the mode control unit 1204 and determines whether the amplification control device 1101 is in write mode or read mode. If the amplification control device 1101 is in read mode, the selection circuit 1206 determines whether the information to be read is from the antenna switch 1102 or the band select switch 1103, or from information stored in the amplification control device 1101 itself. Depending on the determination result, the selection circuit 1206 transmits the information from the antenna switch 1102 or the band select switch 1103, or the information stored in the amplification control device 1101, to the input / output buffer unit 1202.

[0083] The operation of the amplification control device 1101 in write mode will now be described. The operation of the amplification control device 1101 in write mode is the same as the operation of the amplification control device 101 in the first embodiment. The data transmission / reception unit 1201 transmits the address signal and the write data signal included in the main signal to the data signal generation unit 1013, and the command start determination unit 1012 determines whether or not the transmission of the command signal has started. The data signal generation unit 1013 generates a data signal based on the command identification information, bit position information, address signal, and write data signal from the data reception unit 1011, and transmits the data signal to the data transmission unit 1015. The clock enable signal generation unit 1014 generates a clock enable signal based on the command identification information and bit position information and transmits it to the data transmission unit 1015. When a command detection signal is input and a clock enable signal is supplied from the clock enable signal generation unit 1014, the data transmission unit 1015 transmits the data signal from the data signal generation unit 1013 to the antenna switch 1102 or the band select switch 1103 together with the clock signal supplied to the data transmission unit 1015. The communication module 110, similar to the communication module 10 in the first embodiment, performs parallel operation, communicating signals within the communication module 110 in parallel with receiving the main signal. The amplification control device 101 generates data signals to be transmitted to the antenna switch 102 and the band select switch 103 and transmits the data signals to the antenna switch 102 and the band select switch 103 in parallel with the processing of interpreting the main signal from the main device 201.

[0084] The operation of the amplification control device 1101 in readout mode will be described below. Here, it is assumed that, prior to readout by the amplification control device 1101, the antenna switch 1102 and the band select switch 1103 are also pre-set to readout mode in addition to the amplification control device 1101.

[0085] The data transmission / reception unit 1201 receives a main signal from the main device 201 that includes an address signal and a read command signal instructing the reading of data from the antenna switch 1102 or the band select switch 1103.

[0086] The data transmission / reception unit 1201 transmits the address signal included in the main signal to the data signal generation unit 1013. The data reception unit 1011 generates command identification information indicating a readout from the antenna switch 1102 or the band select switch 1103, and bit position information indicating the position where the command identification information is added, and transmits these to the data signal generation unit 1013 and the clock enable signal generation unit 1014. In addition to the information on the position where the command identification information is added, the bit position information may also include information indicating the start and end positions of signals in the data signal, such as the start position of the address signal and the start position of the readout signal.

[0087] The data signal generation unit 1013 generates read instruction signals to be transmitted to the antenna switch 102 and the band select switch 103 based on command identification information, bit position information, and address signals from the data reception unit 1011. The data signal generation unit 1013 transmits the read instruction signals to the data transmission unit 1015.

[0088] When a command detection signal is input and a clock enable signal is supplied from the clock enable signal generation unit 1014, the data transmission unit 1015 transmits a read instruction signal from the data signal generation unit 1013 to the antenna switch 1102 and the band select switch 1103 along with the clock signal supplied to the data transmission unit 1015. The data transmission unit 1015 transmits the clock signal through the clock signal line 104 and the read instruction signal through the data signal line 105. This instructs the reading of data from the antenna switch 1102 and the band select switch 1103.

[0089] The antenna switch 1102 will be described with reference to Figure 13. Other sub-devices, including the band select switch 1103, also have a similar configuration for data communication. In addition to the command start determination unit 1022 and register unit 1023 described in the first embodiment, the antenna switch 1102 includes a data transmission / reception unit 1301, an input / output buffer unit 1302, a mode control unit 1303, an input / output control circuit 1304, and a register selection circuit 1305.

[0090] In write mode, the data transmission / reception unit 1301 receives the address signal and the write data signal included in the data signal from the amplification control device 1101. In read mode, the data transmission / reception unit 1301 receives a read instruction signal from the amplification control device 1101.

[0091] The input / output buffer section 1302 is a circuit that allows signals to pass through during communication between the amplification control device 1101 and the antenna switch 1102.

[0092] The mode control unit 1303 is a circuit that controls the write mode or read mode of the antenna switch 1102. The main device 201 transmits a signal to the antenna switch 1102 via the amplification control device 1101 to control the write mode or read mode of the antenna switch 1102. The data transmission / reception unit 1301 transmits a mode control signal to the mode control unit 1303 that sets the write mode or read mode of the antenna switch 1102 based on the input from the main device 201 via the amplification control device 1101.

[0093] The mode control unit 1303 stores information corresponding to the mode control signal. The information stored in the mode control unit 1303 is referenced by the input / output control circuit 1304.

[0094] The input / output control circuit 1304 refers to the information stored in the mode control unit 1303 and determines whether the amplification control device 1101 is in write mode or read mode. Depending on the write mode and read mode setting, the input / output control circuit 1304 sends a signal to the input / output buffer unit 1302 to control the transmission and reception of signals by the input / output buffer unit 1302.

[0095] In write mode, the input / output control circuit 1304 controls the input / output buffer unit 1302 to transmit the write data signal included in the data signal to the data transmission / reception unit 1301.

[0096] In addition, in read mode, the input / output control circuit 1304 controls the input / output buffer unit 1302 to transmit the read signal from the antenna switch 1102 to the amplification control device 101.

[0097] The register selection circuit 1305 selects a register in the register section 1023 of the antenna switch 1102 based on the address of each register in the register section 1023 included in the read instruction signal. The information read from the selected register is transmitted as a read signal to the amplification control device 1101 via the data transmission / reception unit 1301.

[0098] The operation of the antenna switch 1102 in write mode will now be described. The operation of the antenna switch 1102 in write mode is the same as the operation of the antenna switch 102 in the first embodiment. The data transmission / reception unit 1301 receives data signals from the amplification control device 1101. The command start determination unit 1022 determines, based on the clock signal and the data signal, whether or not the amplification control device 1101 has started transmitting data signals to the antenna switch 1102. When the supply of data signals starts, the command start determination unit 1022 sends a reset signal to the data transmission / reception unit 1301. The register unit 1023 controls writing to each register based on signals from the data transmission / reception unit 1301.

[0099] The operation of the antenna switch 1102 in read mode will be described below. Here, it is assumed that the antenna switch 1102 is pre-set to read mode. Note that read mode is a mode for verifying whether the data stored in the antenna switch 1102 in write mode has been correctly written, and therefore can also be called test mode. Test mode is set exclusively for the antenna switch 1102 and the band select switch 1103. In other words, if the antenna switch 1102 is in read mode, the band select switch 1103 is not set to read mode. The data transmission / reception unit 1301 receives a read instruction signal from the amplification control device 1101. Based on the address included in the read instruction signal, the data transmission / reception unit 1301 reads the information stored in the antenna switch 1102. Specifically, the antenna switch 1102 determines whether the register corresponding to the address indicated by the address signal is included in the antenna switch 1102, and if the register is included in the antenna switch 1102 and a read instruction signal is supplied from the amplification control device 1101, it reads the information stored in the register from the register.

[0100] Referring to Figure 14, the signals in the amplification control device 1101 and the antenna switch 1102 in readout mode will be described. Figure 14 shows an example of the signals from a command to read from one register of the antenna switch 1102.

[0101] The main signal received by the amplification control device 1101 includes a start signal, a command signal, a byte count signal, and an address signal. Following the main signal, the amplification control device 1101 outputs a read signal to the main device 201, and the read operation is completed with an end signal. Here, the byte count signal indicates the number of bytes of data to be read. The byte count signal is 4 bits of information and sets the number of bytes from 1 to 16. In the example in Figure 14, the byte count signal indicates that data of length 1 byte is to be read.

[0102] When the data transmission / reception unit 1201 receives a main signal from the main device 201, the data transmission / reception unit 1201 interprets a command signal. If the command signal is a command indicating to read from at least one register of the antenna switch 1102, the data signal generation unit 1013 generates information in which identification information B6 is prepended to the byte count signal, based on the address signal, command identification information, and bit position information.

[0103] Identification information B6 is a single bit of information, and a bit value of 0 indicates that data reading is instructed. The data transmission unit 1015 records identification information B6 at the position corresponding to the first clock of the byte count signal in the main signal and transmits a data signal with the byte count signal shifted by one clock. The antenna switch 1102 reads the signal when the antenna switch 1102 is set to read mode (test mode) and identification information B6 instructs data reading.

[0104] Next, the data signal generation unit 1013 generates information in which identification information B1 is added to the beginning of the address signal. Identification information B1 is 1 bit of information; a bit value of 0 indicates that the address length is 5 bits, and a bit value of 1 indicates that the address length is 8 bits. The data transmission unit 1015 records the identification information B1 at the position corresponding to the beginning clock of the address signal in the main signal and transmits a data signal in which the address signal is shifted by 1 clock. At this time, the address signal in the main signal includes parity bits P at the beginning and end, and the bits sandwiched between the parity bits P contain information indicating the actual address.

[0105] In the example shown in Figure 14, the number of bytes specified by the byte count signal is 1. Therefore, a read signal of 1 byte is read from the antenna switch 1102. The read signal is transmitted from the data transmission / reception unit 1301 of the antenna switch 1102 to the amplification control device 1101, and output to the main device 201 through the data transmission / reception unit 1201 of the amplification control device 1101.

[0106] Referring to Figure 15, another example of signals in the amplification control device 1101 and the antenna switch 1102 in readout mode is described. Figure 15 shows an example of signals from a command to read from two registers of the antenna switch 1102.

[0107] The main signal received by the amplification control device 1101 includes a start signal, a command signal, a byte count signal, and an address signal. Following the main signal, the amplification control device 1101 outputs multiple read signals to the main device 201, and the read operation is completed with an end signal. In the example in Figure 15, the byte count signal indicates that data of length 2 bytes is being read.

[0108] If the command signal is a command indicating that the antenna switch 1102 should read from multiple registers, the data signal generation unit 1013 generates information in which identification information B6 is added to the beginning of the byte count signal, based on the address signal, command identification information, and bit position information. The antenna switch 1102 reads the signal when the antenna switch 1102 is set to read mode (test mode) and identification information B6 instructs to read data. Subsequently, the data signal generation unit 1013 generates information in which identification information B1 is added to the beginning of the address signal. In the example in Figure 15, the number of bytes specified by the byte count signal is 2. Therefore, a read signal of 2 bytes is read from the antenna switch 1102.

[0109] In the communication module 110 according to the second embodiment, similar to the communication module 10 described in the first embodiment, the circuit for command interpretation can be provided only in the amplification control device 1101. The antenna switch 1102 and the band select switch 1103 only need to have a circuit for address interpretation, so the circuit size of the antenna switch 1102 and the band select switch 1103 can be reduced. This reduces the overall circuit size of the communication module 10.

[0110] Furthermore, in the communication module 110 according to the second embodiment, in addition to writing information to the sub-device in the communication module 10 described in the first embodiment, it is also possible to directly read information from the sub-device. Here, directly reading information means, for example, reading the information itself stored in the register of the antenna switch 1102. If information is not read directly from the antenna switch 1102, the following procedure is required. First, when writing information to the antenna switch 1102, a copy of the information to be written is stored in the amplification control device 1101. Next, the information stored in the amplification control device 1101 is read as the information stored in the antenna switch 1102, thereby substituting for reading the information from the antenna switch 1102. In this procedure, it is not possible to confirm whether the information has actually been correctly written to the antenna switch 1102. For example, a write error may occur due to the state of the signal path between the amplification control device 1101 and the antenna switch 1102. On the other hand, since the communication module 110 can directly read information from the sub-device, the write status can be properly confirmed during product evaluation and shipping tests.

[0111] (Third embodiment) A third embodiment will now be described. Figure 16 shows an example of a circuit including a communication module 160, a main device 201, and analog circuits 301a, 301b, and 301c according to the third embodiment. The communication module 160 is a sub-device whose data communication is controlled by the main device 201.

[0112] The communication module 160 includes an amplification control device 1601, an antenna switch 1602, and a band select switch 1603.

[0113] The amplification control device 1601 is connected to the antenna switch 1602 via a clock signal line 1604 and a data signal line 1605. The amplification control device 1601 is connected to the band select switch 1103 via a clock signal line 1606 and a data signal line 16057. The communication module 160 differs from the communication module 10 according to the first embodiment in that the amplification control device 1601 is connected to each of the antenna switches 1602 and 1603 via separate paths.

[0114] The amplification control device 1601, the antenna switch 1602, and the band select switch 1603 communicate bidirectionally, similar to the communication module 10 described in the first embodiment and the communication module 110 described in the second embodiment, and read and write information.

[0115] In the communication module 160, device ID information that identifies each of the amplification control device 1601, antenna switch 1602, and band select switch 1603 is assigned as a slave address. In addition, the amplification control device 1601 stores the device ID information of each sub-device connected to it.

[0116] In the communication module 160, a main signal is transmitted to the amplification control device 1601, which includes a command signal indicating an operation such as writing or reading, and a device ID signal indicating a device ID for identifying the device from the main device 201. Based on the device ID signal, the amplification control device 1601 transmits and receives signals to the antenna switch 1602 and the band select switch 1603.

[0117] Referring to Figure 17, the processing in the amplification control device 1601 will be described. In step S1701, the amplification control device 1601 receives the main signal from the main device 201.

[0118] In step S1702, the amplification control device 1601 determines whether the device ID signal included in the main signal matches the device ID information of the amplification control device 1601 itself.

[0119] If a positive determination is made in step S1702, in step S1703, the amplification control device 1601 performs a write or read operation on itself.

[0120] If a negative determination is made in step S1702, in step S1704, the amplification control device 1601 determines whether the device ID signal included in the main signal matches the device ID information assigned to the antenna switch 1602 or the band select switch 1603.

[0121] If a positive determination is made in step S1704, in step S1705, the amplification control device 1601 generates a subdevice control signal indicating a write or read operation to the subdevice identified by the device ID information. Here, the subdevice control signal is a signal for writing or reading the information described in the first and second embodiments.

[0122] In step S1706, the amplification control device 1601 transmits a clock signal and a subdevice control signal to the subdevice identified by the device ID information.

[0123] If a negative determination is made in step S1704, in step S1707, the amplification control device 1601 stops receiving the main signal from the main device 201.

[0124] In the communication module 160, the amplification control device 1601 transmits and receives signals to the antenna switch 1602 or band select switch 1603 based on the device identification signal. Therefore, it is not necessary to provide a circuit for interpreting the main signal in the antenna switch 1602 and the band select switch 1603. The antenna switch 1602 and the band select switch 1603 only need to have a circuit for address interpretation, so the circuit size of the antenna switch 1602 and the band select switch 1603 can be reduced. This reduces the overall circuit size of the communication module 10. Furthermore, in the communication modules 10 and 110 in the first and second embodiments, the amplification control device and each sub-device were identified by a common address, but in the communication module 160, the amplification control device and each sub-device can be identified by different addresses, and information can be written to or read from them.

[0125] The embodiment has been described above. The communication module 10 according to the first embodiment includes an amplification control device 101 connected to a main device 201, and at least one second subdevice that is not connected to the main device 201 but is connected to the first subdevice through a first signal line on which a clock signal is transmitted and a second signal line on which a data signal is transmitted. The amplification control device 101 receives a main signal from the main device 201, which includes a command signal, an address signal specifying the address of at least one register having at least one second subdevice, and a write data signal to be recorded in the register corresponding to the address, the address signal being a signal following the command signal and the write data signal being a signal following the address signal, interprets the command signal, and based on the interpretation result of the command signal, generates a write instruction signal after receiving the command signal and while receiving the main signal if information based on the data signal is to be written to either the antenna switch 102 or the band select switch 103, and supplies the write instruction signal through the first signal line or the second signal line, and the data signal through the second signal line, respectively, after receiving the command signal and while receiving the main signal.

[0126] In the communication module 10, the antenna switch 102 and the band select switch 103 determine whether the register corresponding to the address indicated by the address signal is included in the antenna switch 102 or the band select switch 103. If the register is included in the antenna switch 102 or the band select switch 103 and a write instruction signal is supplied from the amplification control device 101, the write data signal is written to the register.

[0127] In the communication module 10, the amplification control device 101, in parallel with receiving the main signal, generates a write instruction signal when writing information based on a data signal to either the antenna switch 102 or the band select switch 103 based on the interpretation result of the command signal, generates a data signal based on an address signal and a write data signal, which is supplied to each of the antenna switch 102 and the band select switch 103 based on the interpretation result of the command signal, and supplies the write instruction signal to each of the antenna switch 102 and the band select switch 103 through the clock signal line 104 or the data signal line 105, and the data signal through the data signal line 105. Each of the antenna switch 102 and the band select switch 103 determines whether the register corresponding to the address indicated by the address signal is included in at least one sub-device, and if the register is included in at least one sub-device and a write instruction signal is supplied from the amplification control device 101, it writes the write data signal to the register.

[0128] In the communication module 10, the large-scale command interpretation circuit can be provided only in the amplification control device 101. The antenna switch 102 and band select switch 103 only need to have the circuit for address interpretation, so the circuit size of the antenna switch 102 and band select switch 103 can be reduced. This reduces the overall circuit size of the communication module 10. In addition, the communication module 10 generates data signals to be transmitted to the antenna switch 102 and band select switch 103 and transmits data signals to the antenna switch 102 and band select switch 103 in parallel with receiving the main signal. This makes the communication processing more efficient.

[0129] In the above embodiment, the amplification control device 101 generates a data signal that includes identification information based on the type of write of a write data signal to at least one register, the write instruction signal is included at the end of the data signal as identification information, and the antenna switch 102 and the band select switch 103 may each write the write data signal to the register based on the identification information.

[0130] As a result, the antenna switch 102 and the band select switch 103 do not require a circuit to interpret commands, thus reducing the circuit size of the communication module 10. Furthermore, the antenna switch 102 and the band select switch 103 do not require a circuit to determine whether data can be written, thus reducing the circuit size of the communication module 10.

[0131] In the above embodiment, the identification information may be information indicating the data length of the data signal. In the above embodiment, the identification information may be information indicating the type of data contained in the data signal.

[0132] In the above embodiment, the type of write includes a write type that indicates that a portion of the write data signal is written to the register without rewriting a predetermined bit in the register, the identification information indicates whether the type of data included in the data signal is a write data signal or a mask signal indicating a predetermined bit that cannot be rewritten, and each of the antenna switch 102 and the band select switch may write a portion of the write data signal to at least one register based on the write data signal and the mask signal. This makes it possible to write data while masking a predetermined bit.

[0133] In the above embodiment, the write type includes a write type indicating that a first write data signal is written to the first register of the antenna switch 102 and the band select switch 103, and a second write data signal is written to the second register of at least one subdevice. Identification information is included at the end of each of the first and second write data signals. The antenna switch 102 and the band select switch 103 may each write the first write data signal to the first register and the second write data signal to the second register based on the identification information. This allows information to be written to multiple registers consecutively. Furthermore, it becomes possible to generate data signals based on the main signal while maintaining the data width.

[0134] In the communication module 110 according to the second embodiment, the main signal includes a command signal that instructs to read information from at least one register of the antenna switch 102 or the band select switch 103. The amplification control device 1101 generates a read instruction signal based on the address signal when reading information stored in at least one register from the antenna switch 102 or the band select switch 103, based on the interpretation result of the command signal. The read instruction signal is supplied to the antenna switch 102 and the band select switch 103, respectively, through the clock signal line 1104 or the data signal line 1105. The device receives the read signal read from the register of the antenna switch 102 or the band select switch 103 and transmits the read signal to the main device 201.

[0135] In the communication module 110, the antenna switch 102 and the band select switch 103 determine whether the register corresponding to the address indicated by the address signal is included in the antenna switch 102 or the band select switch 103. If the register is included in the antenna switch 102 or the band select switch 103 and a read instruction signal is supplied from the amplification control device, the information stored in the register is read from the register.

[0136] In the communication module 110, similar to the communication module 10, the antenna switch 1102 and the band select switch 1103 only need to have circuits for address interpretation, thus reducing the circuit size of the antenna switch 1102 and the band select switch 1103, and thus reducing the overall circuit size of the communication module 110. Furthermore, in the communication module 110, it becomes possible to directly read information from the antenna switch 1102 and the band select switch 1103, making it possible to properly check the write status of the antenna switch 1102 and the band select switch 1103 during product evaluation and shipping tests.

[0137] In the above embodiment, the amplification control device 1101 may generate a read instruction signal that includes identification information based on the type of readout from at least one register, and receive a readout signal read from the antenna switch 102 or band select switch 103 based on the identification information. In the above embodiment, the identification information may also be information indicating the data length of the readout signal.

[0138] This makes it possible to set the read type to output a signal in the same format as that used by a device for checking the write status, for example, improving convenience when checking the write status.

[0139] In the above embodiment, the main signal includes a command signal indicating that the antenna switch 102 and the band select switch 103 should be set to write mode or read mode. The amplification control device 1101 generates a mode setting signal based on the interpretation result of the command signal, which sets the antenna switch 102 and the band select switch 103 to write mode or read mode. The mode setting signal is supplied to the antenna switch 102 and the band select switch 103, respectively, through the clock signal line 1104 or the data signal line 1105. The device may also receive a read signal read from the register of either the antenna switch 102 or the band select switch 103, which is set to read mode and has been supplied with a read instruction signal. This enables writing and reading to the sub-devices.

[0140] In the above embodiment, the write instruction signal may be a clock signal generated following the data signal. Also in the above embodiment, the amplification control devices 101 and 1101 may decide not to write the write data signal to either the antenna switch 102 or the band select switch 103 if an error exists in the main signal.

[0141] This eliminates the need for error detection by the antenna switch 102, etc., and reduces the circuit size of the antenna switch 102, etc. As a result, the overall circuit size of the communication modules 10 and 110 can be reduced.

[0142] The communication module 160 according to the third embodiment includes: an amplification control device 1601 connected to the main device 201, which receives a main signal from the main device 201 including a command signal and a device ID signal indicating a device ID that identifies the device, interprets the command signal, and is assigned first device ID information; an antenna switch 1602 connected to the amplification control device 1601 through a first signal line through which a clock signal is transmitted and a second signal line through which a data signal is transmitted, and is assigned second device ID information; and a band select switch 1603 connected to the amplification control device 1601 through a third signal line through which a clock signal is transmitted and a fourth signal line through which a data signal is transmitted, and is assigned third device ID information.

[0143] In the communication module, the amplification control device 1601 determines whether the device ID signal included in the main signal matches the first device ID information possessed by the amplification control device 1601, and whether the device ID signal included in the main signal matches the second device ID information or third device ID information possessed by the amplification control device 1601. If the device ID signal included in the main signal matches the second device ID information possessed by the amplification control device 1601, it generates a first sub-device control signal to the antenna switch 1602 indicating data writing or reading based on the interpretation result of the command signal, and supplies the first sub-device control signal to the antenna switch 1602. If the device ID signal included in the main signal matches the third device ID information possessed by the amplification control device 1601, it generates a second sub-device control signal to the band select switch 1603 indicating data writing or reading based on the interpretation result of the command signal, and supplies the second sub-device control signal to the band select switch 1603.

[0144] This eliminates the need for circuits to interpret the main signal in the antenna switch 1602 and the band select switch 1603. Since the antenna switch 1602 and the band select switch 1603 only need to have circuits for address interpretation, the circuit size of the antenna switch 1602 and the band select switch 1603 can be reduced, and the overall circuit size of the communication module 10 can be reduced. In addition, the communication module 160 can identify the amplification control device and each sub-device with different addresses and write or read information, thus improving the convenience of writing or reading.

[0145] The embodiments described above are provided to facilitate understanding of the present invention and are not intended to limit its interpretation. The present invention can be modified or improved without departing from its spirit, and equivalents thereof are also included. That is, any design modifications made to each embodiment by those skilled in the art are also included within the scope of the present invention, as long as they retain the features of the present invention. For example, the elements and their arrangement and conditions in each embodiment are not limited to those exemplified and can be modified as appropriate. Furthermore, each embodiment is illustrative, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible, and these are also included within the scope of the present invention as long as they retain the features of the present invention.

[0146] <1> The first sub-device is connected to the main device, The system includes at least one second subdevice that is not connected to the main device but is connected to the first subdevice through a first signal line on which a clock signal is transmitted and a second signal line on which a data signal is transmitted, The aforementioned first subdevice is The main signal is received from the main device and includes a command signal, an address signal specifying the address of at least one register having at least one second subdevice, and a write data signal to be recorded in the register corresponding to the address, wherein the address signal is a signal following the command signal, and the write data signal is a signal following the address signal. Interpreting the aforementioned command signal, When writing information based on the data signal to one of the at least one second sub-device based on the interpretation result of the command signal, a write instruction signal is generated after the reception of the command signal and while the main signal is being received. Based on the interpretation result of the command signal, the data signal is supplied to each of the at least one second subdevice and is generated based on the address signal and the write data signal after the reception of the command signal and while the reception of the main signal. The write instruction signal is supplied to each of the at least one second sub-device via the first signal line or the second signal line, and the data signal is supplied via the second signal line, after the command signal is received and while the main signal is received. Each of the at least one second subdevice is, Determine whether the register corresponding to the address indicated by the address signal is included in the at least one second subdevice. A communication module that writes the write data signal to the register when the register is included in the at least one second subdevice and the write instruction signal is supplied from the first subdevice. <2> <1> A communication module as described above, The aforementioned first subdevice is A data signal is generated which includes identification information based on the type of write of the write data signal to the at least one register, and the write instruction signal is included at the end of the data signal as the identification information. Each of the at least one second subdevice is a communication module that writes the write data signal to the register based on the identification information. <3> <1> A communication module as described above, The aforementioned identification information is information indicating the data length of the data signal, in a communication module. <4> <2> A communication module as described above, The aforementioned identification information is information indicating the type of data included in the data signal, in a communication module. <5> <4> A communication module as described above, The type of write includes a type of write that does not rewrite a predetermined bit of the register and writes a portion of the write data signal to the register. The identification information indicates whether the type of data included in the data signal is the write data signal or a mask signal indicating the predetermined bits that cannot be rewritten. Each of the at least one second subdevice is a communication module that writes a portion of the write data signal to the at least one register based on the write data signal and the mask signal. <6> <4> or <5> A communication module as described above, The write type includes a write type that indicates writing a first write data signal to a first register of at least one second subdevice and writing a second write data signal to a second register of at least one second subdevice. The identification information is included at the end of the first write data signal and the second write data signal, Each of the at least one second subdevice is a communication module that, based on the identification information, writes the first write data signal to the first register and the second write data signal to the second register. <7> <1> from <6> A communication module as described in any of the following: The aforementioned write instruction signal is the clock signal generated following the data signal, in a communication module. <8> <1> from <7> A communication module as described in any of the following: The main signal includes the command signal which instructs to read information from the at least one register of the at least one second subdevice. The aforementioned first subdevice is When reading information stored in the at least one register from the at least one second subdevice based on the interpretation result of the command signal, a read instruction signal based on the address signal is generated. The read instruction signal is supplied to each of the at least one second sub-device through the first signal line or the second signal line. The read signal read from the register of one of the at least one second subdevice is received. A communication module that transmits the read signal to the main device. <9> <8> A communication module as described above, The aforementioned first subdevice is A read instruction signal is generated which includes identification information based on the type of read from the at least one register. A communication module that receives the read signal read from the at least one second subdevice based on the identification information. <10> <9> A communication module as described above, The aforementioned identification information is information indicating the data length of the read signal, in a communication module. <11> <8> from <10> A communication module as described in any of the following: The main signal includes the command signal indicating that the at least one second sub-device is set to write mode or read mode, The aforementioned first subdevice is Based on the interpretation result of the command signal, a mode setting signal is generated to set the at least one second sub-device to write mode or read mode. The mode setting signal is supplied to each of the at least one second sub-devices through the first signal line or the second signal line. A communication module that is set to read mode and receives a read signal read from one of the registers of the at least one second subdevice to which the read instruction signal has been supplied. <12> <1> from <11> A communication module as described in any of the following: The first subdevice is an amplification control device that controls a power amplification circuit. A communication module wherein the at least one second subdevice is an antenna switch that selects a signal amplified by a power amplification circuit and transmitted or received through an antenna, or a band select switch that selects the wavelength of a signal transmitted or received through the antenna. <14> <1> from <13> A communication module as described in any of the following: The first subdevice is a communication module that determines not to write the write data signal to any of the at least one second subdevice if an error exists in the main signal. <15> A first sub-device connected to a main device receives a main signal from the main device, which includes a command signal and a device ID signal indicating a device ID that identifies the device, interprets the command signal, and is assigned first device ID information. A second subdevice is connected to the first subdevice via a first signal line through which a clock signal is transmitted and a second signal line through which a data signal is transmitted, and to which second device ID information is assigned. The system comprises a third subdevice connected to the first subdevice via a third signal line through which a clock signal is transmitted and a fourth signal line through which a data signal is transmitted, and to which third device ID information is assigned, The aforementioned first subdevice is It is determined whether the device ID signal included in the main signal matches the first device ID information of the first sub-device. It is determined whether the device ID signal included in the main signal matches the second device ID information or the third device ID information possessed by the first sub-device. If the device ID signal included in the main signal matches the second device ID information of the first subdevice, a first subdevice control signal indicating data writing or reading is generated for the second subdevice based on the interpretation result of the command signal. The first subdevice control signal is supplied to the second subdevice. If the device ID signal included in the main signal matches the third device ID information of the first subdevice, a second subdevice control signal indicating data writing or reading is generated for the third subdevice based on the interpretation result of the command signal. The second subdevice control signal is supplied to the third subdevice. Communication module. [Explanation of Symbols]

[0147] 10, 110, 160…Communication module, 101, 1101, 1601…Amplification control device, 102, 1102, 1602…Antenna switch, 103, 1103, 1603…Band select switch, 104, 1104, 1604, 1606…Clock signal line, 105, 1105, 1605, 1607…Data signal line, 201…Main device, 301…Analog circuit, 1011…Data receiving unit, 1012…Command start determination unit, 1013…Data signal generation unit, 1014…Clock enable signal generation unit, 1015…Data transmission unit, 1021…Data receiving unit, 1022…Command start determination unit, 1023…Register unit

Claims

1. A first sub-device connected to the main device, The system includes at least one second subdevice, which is not connected to the main device but is connected to the first subdevice via a first signal line through which a clock signal is transmitted and a second signal line through which a data signal is transmitted. The first subdevice is A main signal is received from the main device, which includes a command signal, an address signal specifying the address of at least one register having at least one second subdevice, and a write data signal to be recorded in the register corresponding to the address, wherein the address signal is a signal following the command signal and the write data signal is a signal following the address signal. Interpreting the aforementioned command signal, When writing information based on the data signal to one of the at least one second sub-device based on the interpretation result of the command signal, a write instruction signal is generated after the reception of the command signal and while the reception of the main signal. Based on the interpretation result of the command signal, the data signal is supplied to each of the at least one second subdevice and is generated based on the address signal and the write data signal after the reception of the command signal and while the reception of the main signal. The write instruction signal is supplied to each of the at least one second sub-device via the first signal line or the second signal line, and the data signal is supplied via the second signal line, after the command signal is received and while the main signal is received. Each of the at least one second subdevice is, Determine whether the register corresponding to the address indicated by the address signal is included in the at least one second subdevice. A communication module that writes a write data signal to the register when the register is included in the at least one second subdevice and the write instruction signal is supplied from the first subdevice.

2. A communication module according to claim 1, The first subdevice is A data signal is generated which includes identification information based on the type of write of the write data signal to the at least one register, and the write instruction signal is included at the end of the data signal as the identification information. Each of the at least one second subdevice is a communication module that writes the write data signal to the register based on the identification information.

3. A communication module according to claim 2, The aforementioned identification information is information indicating the data length of the data signal, in a communication module.

4. A communication module according to claim 2, The aforementioned identification information is information indicating the type of data included in the data signal, in a communication module.

5. A communication module according to claim 4, The type of write includes a type of write that does not rewrite a predetermined bit of the register and writes a portion of the write data signal to the register. The identification information indicates whether the type of data included in the data signal is the write data signal or a mask signal indicating the predetermined bits that cannot be rewritten. Each of the at least one second subdevice is a communication module that writes a portion of the write data signal to the at least one register based on the write data signal and the mask signal.

6. A communication module according to claim 4, The write type includes a write type that indicates writing a first write data signal to a first register of at least one second subdevice and writing a second write data signal to a second register of at least one second subdevice. The identification information is included at the end of the first write data signal and the second write data signal, Each of the at least one second subdevice is a communication module that, based on the identification information, writes the first write data signal to the first register and the second write data signal to the second register.

7. A communication module according to claim 1, The aforementioned write instruction signal is the clock signal generated following the data signal, in a communication module.

8. A communication module according to claim 1, The main signal includes the command signal which instructs to read information from the at least one register of the at least one second subdevice. The first subdevice is When reading information stored in the at least one register from the at least one second subdevice based on the interpretation result of the command signal, a read instruction signal based on the address signal is generated. The read instruction signal is supplied to each of the at least one second sub-device through the first signal line or the second signal line. The read signal read from the register of at least one of the second subdevices is received. A communication module that transmits the read signal to the main device.

9. A communication module according to claim 8, The first subdevice is A read instruction signal is generated which includes identification information based on the type of read from the at least one register. A communication module that receives the read signal read from the at least one second subdevice based on the identification information.

10. A communication module according to claim 9, The aforementioned identification information is information indicating the data length of the read signal, in a communication module.

11. A communication module according to claim 8, The main signal includes the command signal indicating that the at least one second sub-device is set to write mode or read mode. The first subdevice is Based on the interpretation result of the command signal, a mode setting signal is generated to set the at least one second sub-device to write mode or read mode. The mode setting signal is supplied to each of the at least one second sub-devices through the first signal line or the second signal line. A communication module that is set to read mode and receives a read signal read from one of the registers of the at least one second subdevice to which the read instruction signal has been supplied.

12. A communication module according to claim 1, The first sub-device is an amplification control device that controls a power amplification circuit. A communication module in which at least one second subdevice is an antenna switch that selects a signal amplified by a power amplification circuit and transmitted or received through an antenna, or a band select switch that selects the wavelength of a signal transmitted or received through the antenna.

13. A communication module according to any one of claims 1 to 12, The first subdevice is a communication module that determines not to write the write data signal to any of the at least one second subdevice if an error exists in the main signal.

14. A first sub-device connected to a main device receives a main signal from the main device, which includes a command signal and a device ID signal indicating a device ID that identifies the device, interprets the command signal, and is assigned first device ID information. A second subdevice is connected to the first subdevice via a first signal line through which a clock signal is transmitted and a second signal line through which a data signal is transmitted, and to which second device ID information is assigned. The system comprises a third subdevice connected to the first subdevice via a third signal line through which a clock signal is transmitted and a fourth signal line through which a data signal is transmitted, and to which third device ID information is assigned, The first subdevice is It is determined whether the device ID signal included in the main signal matches the first device ID information of the first sub-device. It is determined whether the device ID signal included in the main signal matches the second device ID information or the third device ID information possessed by the first sub-device. If the device ID signal included in the main signal matches the second device ID information of the first subdevice, a first subdevice control signal indicating data writing or reading is generated for the second subdevice based on the interpretation result of the command signal. The control signal for the first subdevice is supplied to the second subdevice. If the device ID signal included in the main signal matches the third device ID information of the first subdevice, a second subdevice control signal indicating data writing or reading is generated for the third subdevice based on the interpretation result of the command signal. The second subdevice control signal is supplied to the third subdevice. Communication module.

Images