Semiconductor equipment

Abstract

To provide a semiconductor device capable of withstanding high voltage. [Solution] A semiconductor device comprising a first conductivity type dielectric strength retaining layer and a superjunction layer disposed in contact with the upper surface of the dielectric strength retaining layer. In the superjunction layer, a first region of the first conductivity type and a second region of the second conductivity type are alternately arranged repeatedly along a first direction. The second region comprises a lower second region in contact with the dielectric strength retaining layer and an upper second region disposed in contact with the upper surface of the lower second region. The lower second region has a lower maximum width, which is the maximum width in the first direction. The upper second region has an upper maximum width, which is the maximum width in the first direction. The lower maximum width is greater than the upper maximum width. The density of fixed charge during depletion is higher in the lower second region than in the upper second region.

Description

Technical Field

[0001] The technology disclosed in this specification relates to semiconductor devices.

Background Art

[0002] There is known a semiconductor device having a structure in which a super junction layer is laminated on a breakdown voltage holding layer (also called a drift layer) that performs breakdown voltage sharing. When the super junction layer is substantially completely depleted, a depletion layer is formed over a wide range, so that sufficient breakdown voltage can be ensured. Patent Document 1 discloses an example of a semiconductor device having such a structure.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] There are cases where the depletion layer is unlikely to progress from the super junction layer into the drift layer. In this case, since the electric field inside the drift layer is low, there is a possibility that the breakdown voltage of the drift layer cannot be sufficiently ensured.

Means for Solving the Problems

[0006] According to the above configuration, the density of fixed charge during depletion is higher in the lower second region than in the upper second region. Therefore, the higher density of fixed charge in the lower second region promotes the progression of the depletion layer to the breakdown-holding layer in contact with the lower second region. This increases the electric field shared by the drift layer, making it possible to improve the breakdown voltage of the drift layer. [Brief explanation of the drawing]

[0007] [Figure 1] This is a cross-sectional view of the main part of semiconductor device 1. [Figure 2] This is a magnified view of a portion of the vicinity of layer 14 of the SJ layer. [Figure 3] This is a partially enlarged view of the vicinity of the SJ layer 14 in the comparative example semiconductor device 101. [Figure 4] This is a partially enlarged view of the vicinity of the SJ layer 14 in the semiconductor device 1 of this embodiment. [Figure 5] This diagram illustrates the process of forming the SJ layer 14. [Figure 6] This diagram illustrates the process of forming the SJ layer 14. [Figure 7] This diagram illustrates the process of forming the SJ layer 14. [Figure 8]This is a cross-sectional view of the main part of the semiconductor device 201 of Example 2. [Figure 9] This figure illustrates the effects in Example 2. [Figure 10] This diagram illustrates the process of forming the SJ layer 214. [Figure 11] This is a cross-sectional view of the main part of the semiconductor device 301 of Example 3. [Figure 12] This figure shows examples of various cross-sectional shapes of the lower second region 32b. [Modes for carrying out the invention] [Examples]

[0008] The semiconductor devices disclosed herein will be described below with reference to the drawings. For the purpose of clarity in the illustrations, only one of the repeatedly arranged components may be given a reference numeral.

[0009] As shown in Figure 1, the semiconductor device 1 is a type of power semiconductor device called a MOSFET. The semiconductor device 1 comprises a semiconductor substrate 10, a drain electrode 22 covering the lower surface of the semiconductor substrate 10, a source electrode 24 covering the upper surface of the semiconductor substrate 10, and a plurality of trench gates 30 provided in the upper layer of the semiconductor substrate 10.

[0010] The material of the semiconductor substrate 10 is not particularly limited. In this embodiment, silicon carbide was used. Furthermore, the n-type impurity was nitrogen and the p-type impurity was aluminum. The semiconductor substrate 10 is n + A drain region 11 of type n - It comprises a drift region 12, a superjunction layer 14, a body region 15, a source region 16, and a body contact region 17. In the following, the superjunction layer may be abbreviated as "SJ layer".

[0011] The drain region 11 is provided at a position exposed on the lower surface of the semiconductor substrate 10. The drain region 11 contains n-type impurities at a high concentration and makes ohmic contact with the drain electrode 22. The drift region 12 is provided between the drain region 11 and the SJ layer 14 and is in contact with each of the drain region 11 and the SJ layer 14. The concentration of n-type impurities in the drift region 12 is lower than the concentration of n-type impurities in the drain region 11.

[0012] On the upper surface of the drift region 12, the SJ layer 14 is disposed. The SJ layer 14 includes a plurality of n-conductive first regions 31 and a plurality of p-conductive second regions 32. The first regions 31 and the second regions 32 are alternately and repeatedly arranged along the x direction. Although not particularly limited, the plurality of first regions 31 and the plurality of second regions 32 may be arranged, for example, in a stripe shape when viewed from the direction (+z direction) orthogonal to the upper surface 10s of the semiconductor substrate 10.

[0013] The second region 32 includes a lower second region 32b and an upper second region 32a. The lower second region 32b is a region where the concentration of p-type impurities is higher than that of the upper second region 32a. The lower second region 32b is in contact with the drift region 12. The upper second region 32a is disposed in contact with the upper surface of the lower second region 32b.

[0014] The lower second region 32b and the upper second region 32a will be described using FIG. 2. FIG. 2(A) is a partially enlarged view of the vicinity of the SJ layer 14. In FIG. 2(A), the description of the trench gate 30 is omitted. FIG. 2(B) is a diagram showing the depth direction distribution of the negative fixed charge amount when the second region 32 is depleted. The distribution of the negative fixed charge amount can be obtained, for example, by subtracting the donor impurity concentration distribution from the acceptor impurity concentration distribution.

[0015] The concentration of p-type impurities contained in the lower second region 32b is made higher than the concentration of p-type impurities contained in the upper second region 32a. Therefore, as shown in FIG. 2(B), when the second region 32 is depleted, the density of negative fixed charges is higher in the lower second region 32b than in the upper second region 32a. And there is a boundary BL1 where the amount of negative fixed charges changes abruptly between the lower second region 32b and the upper second region 32a.

[0016] The lower second region 32b has a lower maximum width W2b which is the maximum width in the x direction. In this embodiment, the width of the lower second region 32b in the x direction is constant in the depth direction (z direction). Therefore, the width of the lower second region 32b is the lower maximum width W2b throughout the depth direction. That is, the width of the lower second region 32b at the interface IF between the lower second region 32b and the drift region 12 is the lower maximum width W2b. Also, the upper second region 32a has an upper maximum width W2a which is the maximum width in the x direction. In this embodiment, the width of the upper second region 32a in the x direction is constant in the depth direction (z direction). Therefore, the width of the upper second region 32a is the upper maximum width W2a throughout the depth direction. And the lower maximum width W2b is made larger than the upper maximum width W2a.

[0017] Note that the upper maximum width W2a, the lower maximum width W2b, and the z-direction height of the lower second region 32b and the upper second region 32a may be various values. Also, the distribution of the amount of negative fixed charges (see FIG. 2(B)) is not limited to the aspect of this embodiment and may be various.

[0018] As shown in FIG. 1, the body region 15 is disposed on the SJ layer 14. The body region 15 is provided between the SJ layer 14 and the source region 16, is in contact with both the SJ layer 14 and the source region 16, and separates the SJ layer 14 and the source region 16. The concentration of p-type impurities in the body region 15 is adjusted according to a desired gate threshold voltage.

[0019] The source region 16 is located on the body region 15 and is positioned to be exposed on the upper surface 10s of the semiconductor substrate 10. The source region 16 is in contact with the upper side surface of the trench gate 30. The source region 16 contains a high concentration of n-type impurities and is in ohmic contact with the source electrode 24.

[0020] The body contact region 17 is located on the body region 15, positioned in the upper part of the semiconductor substrate 10, and exposed to the upper surface 10s of the semiconductor substrate 10. The body contact region 17 is in ohmic contact with the source electrode 24 that covers the upper surface 10s.

[0021] Multiple trenches TR penetrate the body region 15 from the surface of the source region 16 to the first region 31. A trench gate 30 is located inside each of the multiple trenches TR. Each of the multiple trench gates 30 has a gate electrode 33 and a gate insulating film 34. The gate insulating film 34 is made of silicon oxide and covers the inner wall of the trench. The gate electrode 33 is made of polysilicon containing impurities. Each of the multiple trench gates 30 extends along the y-direction in the cross-section of the semiconductor substrate 10. The multiple trench gates 30 are spaced apart from each other along the direction perpendicular to their longitudinal direction (x-direction). That is, when the semiconductor substrate 10 is viewed from above (viewed from the z-direction), the trench gates 30 are located within the region of the first region 31.

[0022] (Operation of semiconductor device 1) When the potential of the drain electrode 22 is positive compared to the potential of the source electrode 24, and the potential of the gate electrode 33 of the trench gate 30 is positive compared to the source electrode 24 and controlled to be higher than a threshold, the semiconductor device 1 turns on. At this time, an inversion layer is formed in the body region 15 that separates the source region 16 from the first region 31 of the SJ layer 14. Electrons supplied from the source region 16 reach the first region 31 of the SJ layer 14 via the channel of the inversion layer. Electrons that reach the first region 31 flow through the first region 31 to the drift region 12 and the drain region 11. Since the first region 31 has a high concentration of n-type impurities, the semiconductor device 1 can have the characteristic of low on-resistance.

[0023] When the potential of the gate electrode 33 of the trench gate 30 is controlled to be the same as the potential of the source electrode 24, the channel in the inversion layer disappears, and the semiconductor device 1 turns off. In the SJ layer 14, the density of positive fixed charge when multiple first regions 31 are depleted and the density of negative fixed charge when multiple second regions 32 are depleted are balanced in the repeating direction (x direction). Therefore, multiple first regions 31 and multiple second regions 32 are substantially completely depleted, and a wide area of ​​the SJ layer 14 is depleted. In addition, the electric field distribution of the SJ layer 14 is leveled in the depth direction. As a result, the SJ layer 14 can bear a large potential difference, and the semiconductor device 1 can have the characteristic of high breakdown voltage.

[0024] (Challenges and effects) Figure 3 shows a comparative example semiconductor device 101. Figure 4 shows the semiconductor device 1 of this embodiment. Figures 3(A) and 4(A) are enlarged views of a portion of the vicinity of the SJ layer. In Figures 3(A) and 4(A), the trench gate 30 is omitted, and the depletion layer during depletion is shown as a dotted line region. In addition, among the fixed charges present near the interface IF between the SJ layer and the drift region 12, positive fixed charges are simulated with + circles, and negative fixed charges are simulated with - circles. Figures 3(B) and 4(B) show the electric field distribution within the second region when the second region is depleted.

[0025] The problem will be explained using the comparative example in Figure 3. The SJ layer 140 of the comparative example (Figure 3) differs from the SJ layer 14 of this embodiment (Figure 4) in the structure of the second region 132. In the second region 132, the concentration of p-type impurities is constant throughout the depth direction (z direction). Therefore, the second region 132 is not divided into an upper region and a lower region. Also, the second region 132 has a constant width W102 throughout the depth direction. Similarly, the first region 131 has a constant width W101 throughout the depth direction.

[0026] When a voltage is applied to the semiconductor device 101, negative fixed charges are generated in the second region 132 near the interface IF, and positive fixed charges are generated in the first region 131 and the drift region 12 (see Figure 3(A)). In the semiconductor device 101, the amount of fixed charge in the second region 132 and the first region 131 is approximately the same at any given depth. Therefore, the SJ layer 140 is substantially completely depleted, and a depletion layer DL0 is formed throughout the entire SJ layer 140. Since the electric field distribution in the SJ layer 140 is approximately constant (see Figure 3(B)), it is possible to ensure sufficient breakdown voltage. However, in this case, because the positive and negative fixed charges are balanced within the SJ layer 140, the depletion layer DL0 does not easily propagate into the drift region 12. Because the electric field inside the drift region 12 is low, there is a risk that the breakdown voltage of the drift region 12 may not be sufficiently ensured (see Figure 3(A), region R0). In other words, in the electric field distribution ED0 in Figure 3(B), the area indicated by hatching represents the breakdown voltage, but the area within the drift region 12 is small.

[0027] The effects will be explained using this embodiment shown in Figure 4. In the semiconductor device 1 of this embodiment (Figure 4), as mentioned above, the lower second region 32b has a higher concentration of p-type impurities than the upper second region 32a. That is, the negative fixed charge density during depletion is higher in the lower second region 32b than in the upper second region 32a. Also, the lower maximum width W2b of the lower second region 32b is larger than the upper maximum width W2a of the upper second region 32a. That is, the amount of negative fixed charge during depletion is greater in the lower second region 32b than in the upper second region 32a. Due to these effects, the amount of negative fixed charge near the interface IF can be increased compared to the comparative example (see Figure 4, region R1). By increasing the amount of negative fixed charge near the interface IF of the lower second region 32b, the progression of the depletion layer DL1 into the drift region 12 in contact with the lower second region 32b can be promoted (see arrow Y1).

[0028] Figure 4(B) shows the electric field distribution ED1 (solid line) in this embodiment and the electric field distribution ED0 (dotted line) in the comparative example. In the electric field distribution ED1 of this embodiment, the electric field share of the drift region 12 can be increased compared to the electric field distribution ED0 of the comparative example. In other words, the area within the drift region 12 can be made larger in electric field distribution ED1 than in electric field distribution ED0 (see region R2). As a result, the breakdown voltage of the drift region 12 can be improved in the semiconductor device 1 of this embodiment.

[0029] In this embodiment, the electric field near the interface IF of the lower second region 32b increases (see region R3). Consequently, the electric field inside the SJ layer 14 is lower in the electric field distribution ED1 of this embodiment compared to the electric field distribution ED0 of the comparative example (see region R4). However, since the technology of this embodiment includes a structure that widens only the lower second region 32b, the influence of the shared electric field on the upper second region 32a can be reduced. Consequently, the amount of decrease in the electric field inside the SJ layer 14 (region R4) can be reduced. As a result, while maintaining a high electric field inside the SJ layer 14, the shared electric field of the drift region 12 can be increased, thereby further expanding the total area of ​​the electric field distribution ED1. This makes it possible to increase the breakdown voltage of the semiconductor device 1.

[0030] (Method of manufacturing semiconductor device 1) Next, with reference to Figures 5 to 7, the process of forming the SJ layer 14 in the manufacturing method of the semiconductor device 1 will be described. For the other processes for manufacturing the semiconductor device 1, known manufacturing techniques can be used.

[0031] First, n + A drain region 11, which is a silicon carbide substrate of type n, is prepared. Next, using epitaxial growth technology, an n-type silicon carbide drift region 12 and an epitaxial layer 114 are grown from the surface of the drain region 11. This completes the structure shown in Figure 5. The concentration of n-type impurities is lower in the drift region 12 than in the epitaxial layer 114. Furthermore, the concentration distribution of n-type impurities in the depth direction (z direction) is kept constant in the drift region 12 and the epitaxial layer 114, respectively. This concentration distribution of n-type impurities may be adjusted during the epitaxial growth of the drift region 12 and the epitaxial layer 114, or after epitaxial growth using ion implantation technology, or a combination of these.

[0032] Next, as shown in Figure 6, a mask 42 is deposited on the epitaxial layer 114 using known photolithography techniques. The mask 42 is a striped mask with openings corresponding to the upper second region 32a. The mask 42 may be a resist mask formed from resist, or a hard mask formed from a silicon oxide film or the like.

[0033] Next, as shown in Figure 6, an ion implantation process is performed. Specifically, p-type impurities are implanted in multiple stages throughout the depth direction of the epitaxial layer 114 via the mask 42. At this time, the ion implantation is controlled so that the amount of impurities implanted in the lower part of the epitaxial layer 114 is greater than the amount implanted in the upper part. This makes it possible to form an SJ layer 14 having multiple lower second regions 32b and multiple upper second regions 32a, as shown in Figure 7.

[0034] Here, we will explain a method for forming the width W2b of the lower second region 32b to be larger than the width W2a of the upper second region 32a. Implanted impurity ions have the property of scattering laterally (in a direction perpendicular to the implantation direction) within the semiconductor substrate. This lateral scattering tends to increase as the amount of impurity ions implanted increases. Therefore, by increasing the amount of implantation in the lower epitaxial layer 114 compared to the upper epitaxial layer 114, the amount of ion scattering in the lower region can be increased. Also, lateral scattering tends to increase as the range of impurity ions increases. Therefore, by implanting ions from the same substrate surface, the amount of ion scattering in the lower second region 32b can be increased compared to the amount of ion scattering in the upper second region 32a. As a result, it is possible to make the width W2b larger than the width W2a.

[0035] In the manufacturing method of this embodiment, a single mask 42 can be used to form a lower second region 32b and an upper second region 32a having different widths. Compared to the case where multiple masks are used for each region width and multiple ion implantations are performed, the number of steps can be reduced, thus lowering manufacturing costs. [Examples]

[0036] (Structure of semiconductor device 201) Figure 8 shows the semiconductor device 201 of Example 2. Figure 8 is a drawing of the same position as in Figure 2 of Example 1. The semiconductor device 201 includes an SJ layer 214. The structure of the first region 31 of the SJ layer 214 of Example 2 is different from that of the SJ layer 14 of Example 1. Common parts of Example 1 and Example 2 are given the same reference numerals, and their description is omitted.

[0037] The first region 31 of Embodiment 2 comprises a lower first region 31b and an upper first region 31a. The lower first region 31b is a region with a lower n-type impurity concentration than the upper first region 31a. The lower first region 31b is in contact with the drift region 12. The upper first region 31a is positioned in contact with the upper surface of the lower first region 31b. The lower first region 31b is positioned between two lower second regions 32b that are adjacent to each other in the x direction. The upper first region 31a is positioned between two upper second regions 32a that are adjacent to each other in the x direction.

[0038] The lower first region 31b has a lower maximum width W1b, which is its maximum width in the x-direction. In this embodiment, the x-direction width of the lower first region 31b is constant in the depth direction (z-direction). The upper first region 31a has an upper maximum width W1a, which is its maximum width in the x-direction. In this embodiment, the x-direction width of the upper first region 31a is constant in the depth direction (z-direction). The lower maximum width W1b is smaller than the upper maximum width W1a.

[0039] Figure 8(B) is a depth-direction distribution diagram of the amount of positive fixed charge when the first region 31 is depleted. The distribution of the amount of positive fixed charge can be obtained, for example, by subtracting the acceptor impurity concentration distribution from the donor impurity concentration distribution. The concentration of n-type impurities in the lower first region 31b is lower than the concentration of n-type impurities in the upper first region 31a. Therefore, as shown in Figure 8(B), when the first region 31 is depleted, the density of positive fixed charge is lower in the lower first region 31b than in the upper first region 31a. Furthermore, a boundary BL2 exists between the lower first region 31b and the upper first region 31a where the amount of positive fixed charge changes abruptly.

[0040] (effect) The effects in Example 2 will be explained using Figure 9. Figure 9 is a diagram similar to Figure 4 of Example 1. As mentioned above, the positive fixed charge density during depletion is lower in the lower first region 31b than in the upper first region 31a. As a result, the amount of positive fixed charge near the interface IF can be reduced compared to Example 1 (see Figure 9, region R11). Near the interface IF, the effect of spreading the depletion layer to the drift region 12 by the negative fixed charge amount (region R1) in the lower second region 32b can be enhanced by the amount by which the positive fixed charge amount (region R1) in the lower first region 31b can be reduced. In other words, the amount of positive fixed charge that balances the negative fixed charge amount in the lower second region 32b can be increased in the drift region 12 by the amount by which the negative fixed charge amount in the lower first region 31b has been reduced. This further promotes the spread of the depletion layer from depletion layer DL1 to depletion layer DL2, which is adjacent to the lower second region 32b (see arrow Y2).

[0041] (Manufacturing method for SJ layer 214) The manufacturing method for the SJ layer 214 of Example 2 will be described. Only the differences from the manufacturing method of Example 1 will be described. Using epitaxial growth technology, the n-type silicon carbide drift region 12 and the epitaxial layer 114 are grown from the surface of the drain region 11. At this time, as shown in Figure 10, the epitaxial layer 114 is formed to have a lower epitaxial layer 114b with a relatively low concentration of n-type impurities and an upper epitaxial layer 114a with a relatively high concentration of n-type impurities. The thickness T2 of the lower epitaxial layer 114b is the same as the thickness of the lower first region 31b.

[0042] Subsequently, as explained in Figure 6, p-type impurities are implanted in multiple stages via the mask 42. This completes the SJ layer 214 of Example 2, as shown in Figure 8. [Examples]

[0043] (Structure of semiconductor device 301) Figure 11 shows the semiconductor device 301 of Example 3. Figure 11 is a drawing of the same position as in Figure 9 of Example 2. Common parts in Example 2 and Example 3 are denoted by the same reference numerals, and their descriptions are omitted.

[0044] The SJ layer 214 has a repeating unit RU in the x-direction. The repeating unit RU is a unit defined by a pair of lower first regions 31b and lower second regions 32b. The drift region 12 also has an overlapping region 12o included in the repeating unit RU. The overlapping region 12o is the region that overlaps with the repeating unit RU when the SJ layer 214 is viewed from vertically above (+z direction).

[0045] Here, the total amount of positive fixed charge when the overlapping region 12o is depleted is defined as the total overlapping region charge COp. The total amount of positive fixed charge when the lower first region 31b is depleted is defined as the total first region charge C1p. The total amount of negative fixed charge when the lower second region 32b is depleted is defined as the total second region charge C2n. Then, the semiconductor device 301 of Example 3 has the relationship that "the total second region charge C2n is greater than or equal to the sum of the total first region charge C1p and the total overlapping region charge COp".

[0046] (effect) When a depletion layer is formed, electrons and holes recombine in a 1:1 ratio, so the number of fixed charges inside the depletion layer is the same on both the positive and negative sides. Therefore, in the technique of Example 3, the relationship "C2n≧C1p+COp" exists. In other words, the amount of negative fixed charge in the lower second region 32b is set to be sufficient to recombine with the amount of positive fixed charge in the lower first region 31b and the overlapping region 12o. This allows the depletion layer DL3 to extend to the interface between the drift region 12 and the drain region 11 (see Figure 11). Since the drift region 12 can be completely depleted, it is possible to maximize the breakdown voltage of the drift region 12.

[0047] Although specific examples of the present invention have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. Furthermore, the technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technologies illustrated in this specification or drawings can achieve multiple objectives simultaneously, and achieving even one of these objectives itself constitutes technical usefulness.

[0048] (modified version) The lower second region 32b can have various cross-sectional shapes, as long as it has a lower maximum width W2b that is greater than the upper maximum width W2a. Figure 12 shows examples of various cross-sectional shapes of the lower second region 32b. As shown in lower second region 32b_1, the width in the x-direction may increase as it gets deeper, and the lower maximum width W2b may be at the bottom surface. As shown in lower second region 32b_2, the width in the x-direction may increase as it gets shallower, and the lower maximum width W2b may be at the bottom surface. As shown in lower second region 32b_3, the width in the x-direction may increase linearly from the top surface toward the midpoint, reaching the lower maximum width W2b at the midpoint, and then decreasing linearly from the midpoint toward the bottom surface. Furthermore, as shown in the lower second region 32b_4, the width in the x-direction may be curved and widen from the top surface toward the midpoint, reaching the maximum lower width W2b at the midpoint, and then curvilinearly narrowing from the midpoint toward the bottom surface toward the bottom surface.

[0049] The SJ layer 14 described herein is applicable not only to MOSFETs but also to various device structures such as diodes. Furthermore, the SJ layer 14 described herein is not limited to trench gate structures but is applicable to various gate structures such as planar gate structures.

[0050] In the method for producing the SJ layer 14 described herein, the implantation steps for donor impurities and acceptor impurities may be reversed. That is, n-type impurities may be ion-implanted into the p-type epitaxial layer 114 via a mask.

[0051] In this specification, the case where the first conductivity type is n-type and the second conductivity type is p-type has been described, but the reverse is also possible. That is, the semiconductor device 1 in Figure 1 may have a structure in which n and p are swapped.

[0052] The SJ structure described herein is not limited to a stripe shape, and various shapes can be used. For example, multiple n-type columns and multiple p-type columns may be arranged in a grid pattern when the semiconductor substrate 10 is viewed from above.

[0053] The material of the semiconductor substrate 10 is not limited to silicon carbide; various materials can be used. For example, silicon or various wide-bandgap semiconductors (e.g., gallium nitride, gallium oxide, etc.) may be used.

[0054] The following are embodiments of this technology. [Aspect 1] A first-type conductive voltage-resistant holding layer (12), A superjunction layer (14) is disposed in contact with the upper surface of the pressure-resistant holding layer, wherein a first region (31) of a first conductivity type and a second region (32) of a second conductivity type are alternately and repeatedly arranged along a first direction (x direction), A semiconductor device (1) comprising, The second region comprises a lower second region (32b) in contact with the pressure-resistant holding layer and an upper second region (32a) positioned in contact with the upper surface of the lower second region. The lower second region has a lower maximum width (W2b) which is the maximum width in the first direction, The upper second region has an upper maximum width (W2a), which is the maximum width in the first direction. The aforementioned maximum lower width is greater than the aforementioned maximum upper width. The density of fixed charge during depletion is higher in the lower second region than in the upper second region. Semiconductor equipment. [Aspect 2] The semiconductor device according to embodiment 1, wherein the concentration of the second conductivity type impurity contained in the lower second region is higher than the concentration of the second conductivity type impurity contained in the upper second region. [Aspect 3] The semiconductor device according to embodiment 1 or 2, wherein the width in the first direction at the interface between the lower second region and the pressure-resistant holding layer is the lower maximum width. [Aspect 4] The first region comprises a lower first region (31b) in contact with the pressure-resistant holding layer and an upper first region (31a) positioned in contact with the upper surface of the lower first region. The lower first region is located between the lower second regions which are adjacent to each other in the first direction. The upper first region is located between the upper second regions which are adjacent to each other in the first direction. The semiconductor device according to any one of embodiments 1-3, wherein the density of fixed charge during depletion is lower in the lower first region than in the upper first region. [Aspect 5] When the superjunction layer is viewed from vertically above, the pressure-resistant holding layer has an overlapping region (12o) that overlaps with the lower first region and the lower second region. The total amount of fixed charge in the overlapping region when the overlapping region is depleted is defined as the total overlapping region charge (COp). The total amount of fixed charge in the lower first region when it is depleted is defined as the total charge of the first region (C1p). When the total amount of fixed charge in the lower second region during depletion is defined as the total charge of the second region (C2n), The semiconductor device according to embodiment 4, wherein the total charge of the second region is greater than or equal to the sum of the total charge of the first region and the total charge of the overlapping region. [Aspect 6] A semiconductor device according to any one of embodiments 1 to 5, wherein the first conductivity type is n-type and the second conductivity type is p-type. [Aspect 7] A first-type conductive voltage-resistant holding layer (12), A superjunction layer (14) is disposed in contact with the upper surface of the pressure-resistant holding layer, wherein a first region (31) of a first conductivity type and a second region (32) of a second conductivity type are alternately and repeatedly arranged along a first direction (x direction), A semiconductor device (1) comprising, The second region comprises a lower second region (32b) in contact with the pressure-resistant holding layer and an upper second region (32a) positioned in contact with the upper surface of the lower second region. The lower second region has a lower maximum width (W2b) which is the maximum width in the first direction, The upper second region has an upper maximum width (W2a), which is the maximum width in the first direction. The aforementioned maximum lower width is greater than the aforementioned maximum upper width. A semiconductor device wherein the concentration of the second conductivity type impurity contained in the lower second region is higher than the concentration of the second conductivity type impurity contained in the upper second region.

[0055] According to the configuration of Embodiment 2, the higher the concentration of the second conductivity type impurity in the lower second region, the more the depletion layer can be promoted to the breakdown holding layer in contact with the lower second region. This makes it possible to improve the breakdown pressure of the drift layer.

[0056] According to the configuration of embodiment 3, at the pn junction interface between the lower second region and the pressure-bearing layer, the density of fixed charge during depletion can be made higher in the lower second region than in the upper second region.

[0057] According to the configuration of embodiment 4, the amount of fixed charge in the lower first region can be reduced, thereby increasing the effect of spreading the depletion layer in the breakdown-proof holding layer by the amount of fixed charge in the lower second region.

[0058] According to the configuration of embodiment 5, the amount of fixed charge in the lower second region can be made sufficient to recombine with the amount of fixed charge in the lower first region and the overlapping region. This allows a depletion layer to develop throughout the entire pressure-resistant layer. By completely depleting the pressure-resistant layer, it is possible to maximize the pressure resistance of the pressure-resistant layer. [Explanation of Symbols]

[0059] 1: Semiconductor device 12: Drift region 14: SJ layer 31: First region 32: Second region 32a: Upper second region 32b: Lower second region W2a: Upper maximum width W2b: Lower maximum width

Claims

1. A first-type conductive pressure-resistant layer (12), A superjunction layer (14) is disposed in contact with the upper surface of the pressure-resistant holding layer, wherein a first region (31) of a first conductivity type and a second region (32) of a second conductivity type are alternately and repeatedly arranged along a first direction (x direction), A semiconductor device (1) equipped with, The second region comprises a lower second region (32b) in contact with the pressure-resistant holding layer and an upper second region (32a) positioned in contact with the upper surface of the lower second region. The lower second region has a lower maximum width (W2b), which is the maximum width in the first direction. The upper second region has an upper maximum width (W2a), which is the maximum width in the first direction. The aforementioned maximum lower width is greater than the aforementioned maximum upper width. The density of fixed charge during depletion is higher in the lower second region than in the upper second region. Semiconductor equipment.

2. The semiconductor device according to claim 1, wherein the concentration of the second conductivity type impurity contained in the lower second region is higher than the concentration of the second conductivity type impurity contained in the upper second region.

3. The semiconductor device according to claim 1, wherein the width in the first direction at the interface between the lower second region and the pressure-resistant holding layer is the lower maximum width.

4. The first region comprises a lower first region (31b) in contact with the pressure-resistant holding layer and an upper first region (31a) positioned in contact with the upper surface of the lower first region. The lower first region is located between the lower second regions which are adjacent to each other in the first direction. The upper first region is located between the upper second regions which are adjacent to each other in the first direction. The semiconductor device according to any one of claims 1 to 3, wherein the density of fixed charge during depletion is lower in the lower first region than in the upper first region.

5. When the superjunction layer is viewed from vertically above, the pressure-resistant holding layer has an overlapping region (12o) that overlaps with the lower first region and the lower second region. The total amount of fixed charge in the overlapping region when it is depleted is defined as the total overlapping region charge (COP). The total amount of fixed charge in the lower first region when it is depleted is defined as the total charge of the first region (C1p). When the total amount of fixed charge in the lower second region during depletion is defined as the total charge of the second region (C2n), The semiconductor device according to claim 4, wherein the total charge of the second region is greater than or equal to the sum of the total charge of the first region and the total charge of the overlapping region.

6. The semiconductor device according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

7. A first-type conductive pressure-resistant layer (12), A superjunction layer (14) is disposed in contact with the upper surface of the pressure-resistant holding layer, wherein a first region (31) of a first conductivity type and a second region (32) of a second conductivity type are alternately and repeatedly arranged along a first direction (x direction), A semiconductor device (1) equipped with, The second region comprises a lower second region (32b) in contact with the pressure-resistant holding layer and an upper second region (32a) positioned in contact with the upper surface of the lower second region. The lower second region has a lower maximum width (W2b), which is the maximum width in the first direction. The upper second region has an upper maximum width (W2a), which is the maximum width in the first direction. The aforementioned maximum lower width is greater than the aforementioned maximum upper width. A semiconductor device wherein the concentration of the second conductivity type impurity contained in the lower second region is higher than the concentration of the second conductivity type impurity contained in the upper second region.

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