Indication device

Abstract

To provide a display device that can improve image quality. [Solution] Each pixel is provided with a memory node, and the first data is stored in the memory node. This is possible. The second data is added to the first data by capacitive coupling, and the display element It can be supplied to the device. Therefore, the display device can display the corrected image. It is possible. In addition, the configuration is such that a reference potential for capacitive coupling operation is supplied from the power line, etc. The first data and the second data can be supplied on a shared signal line.

Description

Technical Field

[0001] One aspect of the present invention relates to a display device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the invention disclosed in this specification etc. is related to an object, a method, or a manufacturing method. Or, one aspect of the present invention is related to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, more specifically, the technical field of one aspect of the present invention disclosed in this specification includes, as an example, semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, power storage devices, storage devices, imaging devices, their driving methods, or their manufacturing methods. can be cited as an example. [[ID=2{3]]

[0003] Note that in this specification etc., a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one aspect of a semiconductor device. Also, a storage device, a display device, an imaging device, and an electronic device may have a semiconductor device.

Background Art

[0004] Although silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials. As oxide semiconductors, for example, not only oxides of single-element metals such as indium oxide and zinc oxide, but also oxides of multi-element metals are known. Among the oxides of multi-element metals, in particular, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) has been actively conducted.

[0005] ​Research on IGZO has shown that in oxide semiconductors, CAA is neither single-crystal nor amorphous. C (c-axis aligned crystalline) structure and nc (nan An ocrystalline structure was discovered (see Non-Patent Documents 1 to 3). Non-Patent Documents 1 and 2 describe using an oxide semiconductor having a CAAC structure to traverse The technology for fabricating the transistor is also disclosed. Furthermore, the CAAC structure and nc structure are superior. Even oxide semiconductors with low crystallinity have minute crystals, as shown in Non-Patent Document 4 and Non-Patent Document. This is shown in reference 5.

[0006] Furthermore, transistors using IGZO as the active layer have extremely low off-currents (non-specific (See Reference 6), LSIs and displays utilizing this characteristic have been reported (non-special (See authorized document 7 and non-patent document 8).

[0007] Furthermore, a memory device in which transistors with extremely low off-current are used as memory cells is described in the patent document. This is disclosed in Submission 1. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Publication No. 2011-119674 [Non-patent literature]

[0009] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-Patent Document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 [Non-Patent Document 3] S. Ito et al., “The Proceedings of AM-FPD'13 Digest of Technical Papers”, 2013, p.151-154 [Non-Patent Document 4] S. Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, p.Q3012-Q3022 [Non-Patent Document 5] S. Yamazaki, “ECS Transactions”,2014, volume 64, issue 10, p.155-164 [Non-Patent Document 6] K. Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p.021201-1-021201-7 [Non-Patent Document 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p.T216-T217 [Non-Patent Document 8] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, p.626-629 [Overview of the project] [Problems that the invention aims to solve]

[0010] Display devices are becoming higher resolution, with 8K4K (pixel count: 7680 x 4320) resolution or Hardware capable of displaying at even higher resolutions has been developed. The introduction of HDR (High Dynamic Range) display technology, which enhances image quality through adjustments, is also progressing. It is.

[0011] In order for a display device to display correctly, image data must be matched to the resolution of the display device. Yes, for example, if the resolution of the display device is 8K4K and the image data is 4K2K (number of pixels: 3 If it's for 840x2160 resolution, you must convert the data size fourfold to display it in full screen. It is not possible. Conversely, if the display device has a resolution of 4K2K and the image data is for 8K4K, In some cases, the number of data points needs to be reduced to 1 / 4.

[0012] Furthermore, dedicated circuits are required for generating image data and converting the number of data points using HDR processing. However, this also has the problem of increasing power consumption. At the very least, the original image data should not be converted to a display device. It is preferable that the input can be made to the pixels.

[0013] Therefore, in one aspect of the present invention, a display device capable of improving image quality is provided. One of the objectives is to provide a display device that can display image data appropriately without conversion. One of the purposes is to provide a display device capable of HDR display. One of the purposes is to provide a display device capable of upconversion. One of the objectives is to create a display device that can increase the brightness of the displayed image. One of the purposes is to provide a display device that can overlay two images. One of its purposes is to provide it.

[0014] Alternatively, one of the objectives is to provide a low-power display device. Or, to provide high reliability. One of the objectives is to provide a display device, or to provide a novel display device, etc. One of the objectives is to provide a method for driving the above-mentioned display device. Alternatively, one of the objectives is to provide novel semiconductor devices, etc.

[0015] Furthermore, the description of these problems does not preclude the existence of other problems. The approach does not need to solve all of these problems. This will become clear from the description in the specification, drawings, claims, etc., and the specification, drawings It is possible to extract other issues from the descriptions in the surfaces, claims, etc. [Means for solving the problem]

[0016] One aspect of the present invention relates to a display device that can improve image quality, or to image processing. This relates to a display device capable of performing the following actions.

[0017] One aspect of the present invention is a first transistor, a second transistor, and a third transistor A display device having a first capacitive element, a circuit block, a first wiring, and a second wiring. The configuration is such that either the source or drain of the first transistor is connected to the second transistor. It is electrically connected to either the source or drain of the second transistor, and the source or One end of the drain is electrically connected to one electrode of the first capacitive element, and the first capacitive element The other electrode is electrically connected to either the source or the drain of the third transistor. Either the source or drain of the third transistor is electrically connected to the circuit block. The source or drain of the first transistor, the other of which is electrically connected to the first wiring. The source or drain of the third transistor, the other of which is electrically connected to the first wiring. The gate of the second transistor is electrically connected to the second wiring, and the third transistor The gate is electrically connected to the second wiring, and the circuit block is a display device having a display element. It is placed there.

[0018] Another aspect of the present invention is a first transistor, a second transistor, and a first rotation A display device having a path and a second circuit, a first wiring, and a second wiring, the first Each of the first circuit and the second circuit includes a third transistor, a first capacitive element, and a circuit The block has, and one of the sources or drains of the third transistor is the first capacitor One electrode of the element is electrically connected to the circuit block, and one electrode of the first capacitive element is connected to the circuit block. Electrically connected, the other electrode of the first capacitive element is connected to the source or of the first transistor. It is electrically connected to one side of the drain, and to one side of the source or drain of the first transistor. It is electrically connected to either the source or drain of the second transistor, and the first circuit The source or drain of the third transistor is electrically connected to the first wiring. The source or drain of the first transistor is connected to the first wiring. The gate of the third transistor in the first circuit is electrically connected to the second wiring. The gate of the third transistor in the second circuit is electrically connected to the second wiring. The gate of the second transistor is electrically connected to the second wiring, and the circuit block is shown. It is a display device having an indicator element.

[0019] The circuit block consists of a fourth transistor, a fifth transistor, a second capacitive element, and a table The display element is an organic EL element, and one electrode of the organic EL element is a fifth transistor It is electrically connected to either the source or drain of the fifth transistor, and the source of the fifth transistor The other end of the drain is electrically connected to one electrode of the second capacitive element, and the second capacitive element One electrode is electrically connected to either the source or the drain of the fourth transistor. The gate of the fourth transistor is electrically connected to the other electrode of the second capacitive element, The other electrode of the second capacitive element is electrically connected to one electrode of the first capacitive element. It is possible.

[0020] In the above configuration, the source or drain of the fourth transistor is connected to the second transistor. It can be electrically connected to the source or drain of the zista.

[0021] The circuit block also includes a sixth transistor, a third capacitive element, and a liquid crystal display element. The device comprises a liquid crystal element and a third capacitive element, with one electrode of the liquid crystal element electrically connected to one electrode of the third capacitive element. And one electrode of the third capacitive element is connected to the source or drain of the sixth transistor. One side is electrically connected to the other, and the source or drain of the sixth transistor is connected to the first capacitor. The device may also be configured to be electrically connected to one of the electrodes of the quantitative element.

[0022] In the above configuration, the other electrode of the third capacitive element is the source or of the second transistor. It can be electrically connected to the other side of the drain.

[0023] The third transistor has a metal oxide in the channel formation region, and the metal oxide is In. Zn and M (where M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf) It is preferable that it has , [Effects of the Invention]

[0024] To provide a display device that can improve image quality by using one aspect of the present invention. This is possible. Or, to provide a display device that can display image data appropriately without converting it. This is possible. Alternatively, a display device capable of HDR display can be provided. Alternatively, a display device capable of upconversion can be provided. A display device can be provided that can increase the brightness of an image. Alternatively, two images can be displayed. A display device that can overlay information can be provided.

[0025] Alternatively, a low-power display device can be provided. Or, a highly reliable display device can be provided. We can provide a novel display device, or we can provide a novel display device, or This can provide a method for driving the above-mentioned display device. Alternatively, it can provide a novel semiconductor device, etc. It can be provided. [Brief explanation of the drawing]

[0026] [Figure 1] A diagram illustrating the pixel circuit. [Figure 2] A timing chart illustrating the operation of the pixel circuit. [Figure 3] A diagram illustrating image data correction and image synthesis. [Figure 4] A diagram illustrating a circuit block. [Figure 5] A diagram illustrating a circuit block. [Figure 6] A diagram illustrating the pixel circuit. [Figure 7] A diagram illustrating a pixel array. [Figure 8] A timing chart illustrating the operation of a pixel array. [Figure 9] A block diagram illustrating the display device. [Figure 10] A diagram illustrating an example of a neural network configuration. [Figure 11] A diagram illustrating the configuration of the pixel array used in the simulation. [Figure 12] A diagram illustrating the results of the simulation. [Figure 13] A diagram illustrating the results of the simulation. [Figure 14] A diagram illustrating the results of the simulation. [Figure 15] A diagram illustrating the structure of pixels. [Figure 16] A diagram illustrating a display device. [Figure 17] A diagram illustrating a touch panel. [Figure 18] A diagram illustrating a display device. [Figure 19] A diagram explaining transistors. [Figure 20] A diagram explaining transistors. [Figure 21] A diagram explaining transistors. [Figure 22] A diagram explaining transistors. [Figure 23] A diagram illustrating electronic devices. [Modes for carrying out the invention]

[0027] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Without departing from the spirit and scope of the present invention, its form and details may be changed in various ways. Those skilled in the art will readily understand that further improvements are possible. Therefore, the present invention can be implemented as follows: The description of the form is not to be interpreted as being limited to the content of the description. Furthermore, the structure of the invention described below In this context, the same reference numeral is used for identical parts or parts having similar functions across different drawings. It is used in this way, and the explanation of its repetition may be omitted. Note that the same elements that make up the figure Matching may be omitted or modified as appropriate between different drawings.

[0028] (Embodiment 1) In this embodiment, a display device that is one aspect of the present invention will be described with reference to the drawings.

[0029] One aspect of the present invention is a display device having a function for correcting image data within each pixel. A storage node is provided, and the first data can be stored in this storage node. Data 1 can be coupled with a second data point via capacitive coupling and supplied to the display element. Alternatively, the first data can be capacitively bound after the second data has been written to the memory node. It can also be added using .

[0030] Therefore, the display device can display the corrected image. This correction allows, It is possible to upconvert images. Or, part or all of the display unit. The image can be corrected and HDR display can be performed. Alternatively, the first data and the second data By using the same image data as the base image, the brightness of the displayed image can be significantly improved. Alternatively, by using different image data as the first and second data, You can overlay and display any image.

[0031] Furthermore, by using one aspect of the present invention, two image data, one for high resolution and one for low resolution, can be obtained. To display the content appropriately without upconverting or downconverting it. This is possible. When displaying at high resolution, the first transistor in each pixel is used as a path to each It supplies individual data to each pixel. When displaying at low resolution, multiple pixels are electrically connected. The same data is supplied to the multiple pixels via a second transistor.

[0032] Here, high-resolution image data refers to, for example, 8K4K (pixel count: 7680 x 4320). This corresponds to data that is compatible with ). Also, low-resolution image data is, for example, 4K2K. This corresponds to data with a resolution of 3840 x 2160 pixels. In other words, it is data for high resolution. The ratio of the number of effective data points (corresponding to the number of effective pixels) in image data to the number of effective data points in low-resolution image data is 4: Assume that the value is 1.

[0033] Furthermore, if the ratio of data points (number of pixels) is 4:1, this is not limited to the above example, but applies to high-resolution images. Image data is compatible with 4K2K, while image data for lower resolution is FullHD (pixel count). Data compatible with 1920x1080 resolution is also acceptable. Alternatively, high-resolution image data is also acceptable. Data compatible with 16K / 8K (pixel count: 15360 x 8640), images for lower resolution. The image data may also be data compatible with 8K4K.

[0034] Figure 1 illustrates a pixel 10 that can be used in a display device according to one embodiment of the present invention. Pixel 10 consists of transistor 101, transistor 102, transistor 103, and It has a quantitative element 104 and a circuit block 110. The circuit block 110 is a transistor, It may have capacitive elements and display elements, and further details will be described later.

[0035] Either the source or drain of transistor 101 is connected to the source of transistor 102. It is electrically connected to one side of the drain. The source or drain of transistor 102 One end is electrically connected to one electrode of the capacitive element 104. The other end of the capacitive element 104 is electrically connected to one electrode of the capacitive element 104. The poles are electrically connected to either the source or the drain of transistor 103. Either the source or drain of the zista 103 is electrically connected to the circuit block 110. ru.

[0036] Here, the source or drain of transistor 103 and the other side of capacitive element 104 The wiring to which the pole and circuit block 110 are connected is designated as node NM. The elements of the circuit block 110 that connect to it can make node NM floating. ru.

[0037] The gate of transistor 101 is electrically connected to wiring 122. Transistor 102 The gate of the transistor and the gate of transistor 103 are electrically connected to the wiring 121. The source or drain of transistor 101 and the other of transistor 103 The other end of the drain is electrically connected to wiring 123. The source of transistor 102 is also The other end of the drain is electrically connected to wiring capable of supplying a specific potential "Vref". It will continue.

[0038] Wires 121 and 122 function as signal lines to control the operation of the transistor. This is possible. Wiring 123 is a signal line that supplies either the first data or the second data. It can have the following functions. Examples of wiring that can supply “Vref” include For example, power lines that are electrically connected to the elements of the circuit block 110 can be used.

[0039] Note that in order to perform the capacitive coupling operation described later, the pixels must have "Vref" and the first data ( For example, correction data needs to be supplied during the same period. Therefore, “Vref” is used as a signal. If supplied via a line, at least the signal line supplying the first data and “Vref” Alternatively, a signal line is needed to supply a second data (for example, image data).

[0040] On the other hand, in a display device according to one aspect of the present invention, since "Vref" is supplied from a power line or the like, By switching between the two data sources, the supply of the first data or the supply of the second data can be switched to one. This can be done from the signal line (wiring 123). In other words, it can be constructed with a small number of wires. can.

[0041] Node NM is a memory node, and by making transistor 103 conductive, it connects to wiring 123. The supplied data can be written to node NM. Also, transistor 103 is not By making it conductive, the data can be stored in node NM. Transistor 10 By using a transistor with extremely low off-current in step 3, the potential of node NM can be maintained for a long time. This becomes possible. The transistor can, for example, have a metal oxide in the channel formation region. The transistor used in the previous step (hereinafter referred to as OS transistor) can be used.

[0042] Furthermore, not only transistor 103, but also other transistors that make up the pixels are OS transistors. A transistor may be applied. Also, the transistor 103 may have Si in the channel formation region. A transistor (hereinafter referred to as a Si transistor) may be used. Alternatively, an OS transistor may be used. Both a t-type transistor and a Si transistor may be used. Note that the above Si transistor is transistors containing amorphous silicon, crystalline silicon (typically, low-temperature silicon Examples include transistors made of silicon (such as single-crystal silicon).

[0043] For semiconductor materials used in OS transistors, an energy gap of 2 eV or more is preferred. A metal oxide with a voltage of 2.5 eV or higher, more preferably 3 eV or higher, can be used. Typical examples include indium-containing oxide semiconductors, such as CAAC, which will be discussed later. -OS or CAC-OS can be used. CAAC-OS forms a crystal. Its atoms are stable, making it suitable for transistors and other applications where reliability is paramount. Furthermore, CAC-OS is... Because it exhibits high mobility characteristics, it is suitable for transistors and other applications that require high-speed operation.

[0044] OS transistors exhibit extremely low off-current characteristics due to their large energy gap. Furthermore, OS transistors utilize impact ionization, avalanche breakdown, and short channel properties. It has characteristics different from Si transistors, such as not producing any effects, and forms a highly reliable circuit. It is possible.

[0045] The semiconductor layer of an OS transistor is made of, for example, indium, zinc, and M(aluminum). Titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium It is expressed as an In-M-Zn oxide containing metals such as tin, neodymium, or hafnium. It can be made into a film.

[0046] When the oxide semiconductor constituting the semiconductor layer is an In-M-Zn oxide, In-M-Zn oxidation The atomic ratio of metal elements in a sputtering target used to deposit thin films is In≧M It is preferable that Zn≧M is satisfied. In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In :M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4. 1, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5: 1:8, etc. are preferable. The atomic ratio of the semiconductor layer to be formed includes a plus or minus 40% variation in the atomic ratio of the metal elements contained in the above sputtering ring target.

[0047] As the semiconductor layer, an oxide semiconductor with a low carrier density is used. For example, the carrier density of the semiconductor layer is 1×10 / cm 17 or less, preferably 1×10 3 / cm 15 or less, more preferably 1×10 3 / cm or less, still more preferably 1×10 13 / cm 3 or less, even more preferably 1×10 11 / cm 3 or less, and even more preferably 1×10 / cm 10 or less, and less than 1×10 3 / cm -9 or more, and an oxide semiconductor with a carrier density of 1×10 3 / cm or more can be used. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. It can be said that the oxide semiconductor has a low density of defect levels and stable characteristics.

[0048] Note that it is not limited to these, and those with an appropriate composition may be used according to the required semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the transistor. Also, in order to obtain the required semiconductor characteristics of the transistor, the carrier density, impurity concentration, and defects of the semiconductor layer of the semiconductor layer It is preferable to ensure that the density, the atomic ratio of metal elements to oxygen, the interatomic distance, and other parameters are appropriate. stomach.

[0049] In oxide semiconductors that constitute semiconductor layers, silicon and carbon, which are among the Group 14 elements, When it is included, oxygen vacancies increase, and it becomes n-type. Therefore, silicon in semiconductor layers The concentration of ions and carbon (concentration obtained by secondary ion mass spectrometry) is 2 × 10⁻¹⁰ 18 Atom s / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0050] Furthermore, alkali metals and alkaline earth metals generate carriers when they bond with oxide semiconductors. This can occur, and the transistor's off-current may increase. Therefore, Concentration of alkali metals or alkaline earth metals in the conductive layer (by secondary ion mass spectrometry) The concentration obtained is 1 × 10 18 atoms / cm 3 The following is preferably 2 × 10 16 a toms / cm 3 Do the following:

[0051] Furthermore, if nitrogen is present in the oxide semiconductor that makes up the semiconductor layer, the electrons, which are carriers, This leads to an increase in carrier density and makes it easier to convert to n-type. As a result, nitrogen-containing oxide semiconducting Transistors using conductors tend to exhibit normally-on characteristics. Therefore, in the semiconductor layer... The nitrogen concentration (concentration obtained by secondary ion mass spectrometry) is 5 × 10⁻⁶ 18 atom / cm 3 The following is preferable:

[0052] Furthermore, the semiconductor layer may have, for example, a non-single-crystal structure. The non-single-crystal structure may be, for example, oriented along the c-axis. CAAC-OS (C-Axis Aligned Crystallix) has crystals formed by this process. (Oxide Semiconductor), polycrystalline structure, microcrystalline structure, or non It includes a crystalline structure. In non-single crystal structures, the amorphous structure has the highest defect level density, CAA C-OS has the lowest defect level density.

[0053] Amorphous oxide semiconductor films, for example, have a disordered atomic arrangement and do not contain crystalline components. Alternatively, an amorphous oxide film may have a completely amorphous structure and no crystalline parts. stomach.

[0054] Furthermore, the semiconductor layer consists of regions with an amorphous structure, regions with a microcrystalline structure, regions with a polycrystalline structure, and CAAC. - A mixed film having two or more regions from among the OS region and the single-crystal structure region. The film may have a monolayer structure or a multilayer structure, for example, containing two or more of the regions described above. It may have a structure.

[0055] Below, we will discuss CAC (Cloud-Aligned C), which is one form of a non-single-crystal semiconductor layer. This section describes the configuration of the OS (composite).

[0056] CAC-OS refers to, for example, an oxide semiconductor in which the elements constituting the semiconductor are between 0.5 nm and 10 nm. Below, preferably, a structure of material that is unevenly distributed with a size of 1 nm to 2 nm or near that size. It is formed. Furthermore, in the following, in oxide semiconductors, one or more metal elements are The region containing the metal element is unevenly distributed and is 0.5 nm to 10 nm, preferably 1 nm. A mixture of particles smaller than or equal to 2 nm in size, or near that size, can appear as a mosaic or patch. It is also said that.

[0057] Furthermore, the oxide semiconductor preferably contains at least indium. In particular, indium It is preferable to include zinc. In addition to these, aluminum, gallium, and t Thorium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, ginger Lumanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium, Contains one or more elements selected from tantalum, tungsten, or magnesium. It's okay if they're born.

[0058] For example, CAC-OS in In-Ga-Zn oxide (among CAC-OS, In-Ga α-Zn oxide may also be specifically referred to as CAC-IGZO. ) is indium oxide (Hereinafter, InO X1 (Let X1 be a real number greater than 0.) ) or indium zinc acid In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) Let's assume that...) and gallium oxide (hereinafter referred to as GaO X3 (Let X3 be a real number greater than 0) . ), or gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (X4, Y4, and Let Z4 be a real number greater than 0. The material separates into parts such as ), resulting in a mosaic pattern. and a mosaic-like InO X1 , or In X2 Zn Y2 O Z2 However, it was uniformly distributed in the membrane. This configuration (hereinafter also referred to as cloud-based) is as follows.

[0059] In other words, CAC-OS is GaOX3 The region in which is the main component, and In X2 Zn Y2 O Z2 , or InO X1 A composite oxide semiconductor having a structure in which a region is the main component and a region is mixed. In this specification, for example, the atomic ratio of In to element M in the first region. However, the first region is greater than the atomic ratio of In to element M in the second region. Assume that the concentration of In is higher in this region compared to region 2.

[0060] Note that IGZO is a common name and refers to a single compound composed of In, Ga, Zn, and O. There are combinations. A typical example is InGaO3(ZnO). m1 (m1 is a natural number), or In ( 1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is any number) Examples of crystalline compounds include those that are produced.

[0061] The above crystalline compounds have a single-crystal structure, a polycrystalline structure, or a CAAC structure. A CAAC structure is one in which multiple IGZO nanocrystals have c-axis orientation and in the ab-plane. This is a crystal structure in which the elements are linked without orientation.

[0062] On the other hand, CAC-OS relates to the material composition of oxide semiconductors. CAC-OS is In, G In a material composition containing a, Zn, and O, a portion of it is observed to be in the form of nanoparticles mainly composed of Ga. The region where the substance is suspected and the region where it is observed as nanoparticles mainly composed of In are, respectively This refers to a configuration where elements are randomly distributed in a mosaic-like pattern. Therefore, in CAC-OS, Crystal structure is a secondary factor.

[0063] Furthermore, CAC-OS does not include a layered structure of two or more films with different compositions. For example, a structure consisting of two layers, one with In as the main component and the other with Ga as the main component, is included. do not have.

[0064] Note that GaO X3 The region in which is the main component, and In X2 Zn Y2 O Z2 , or InO X1 but In some cases, a clear boundary may not be observable between the principal component region and the surrounding area.

[0065] Note that aluminum, yttrium, copper, vanadium, and beryllium can be used instead of gallium. Boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum Lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium If one or more species selected from Cium, etc., are included, CAC-OS will be partially The region is observed to be in the form of nanoparticles mainly composed of the metal element, and a part of it is mainly composed of In. The regions observed in the nanoparticle form are randomly dispersed in a mosaic-like manner. say.

[0066] CAC-OS is formed, for example, by sputtering under conditions where the substrate is not intentionally heated. It is possible. Also, when forming CAC-OS by sputtering, the deposition gas and Then, selected from inert gases (typically argon), oxygen gas, and nitrogen gas. You may use one or more of them. Also, the oxygen in relation to the total flow rate of the deposition gas during film formation. A lower gas flow rate ratio is preferable; for example, a flow rate ratio of oxygen gas of 0% or more and less than 30% is preferable. Alternatively, it is preferable to have a value of 0% or more and 10% or less.

[0067] CAC-OS is a type of X-ray diffraction (XRD) measurement method. When measured using the θ / 2θ scan method, which is the only Out-of-plane method, It is characterized by the absence of a clear peak. In other words, from X-ray diffraction measurements, It can be seen that no orientation is observed in the ab-plane direction or the c-axis direction of the region.

[0068] Furthermore, CAC-OS uses an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam). In the electron diffraction pattern obtained by irradiation, there is a ring-shaped region of high brightness, and Multiple bright spots are observed in the ring region. Therefore, from the electron diffraction pattern, CAC- The crystal structure of OS is non-oriented in both the planar and cross-sectional directions. It can be seen that it has an o-crystal structure.

[0069] Furthermore, for example, in CAC-OS in In-Ga-Zn oxide, energy-dispersive X Linear spectroscopy (EDX: Energy Dispersive X-ray spectrometer) GaO X3 The region in which is the main component And, In X2 Zn Y2 O Z2 , or InO X1 Regions where it is the main component are unevenly distributed and mixed. It can be confirmed that it has the following structure.

[0070] CAC-OS has a different structure from IGZO compounds in which metal elements are uniformly distributed, It has different properties from ZO compounds. In other words, CAC-OS is GaO X3 These are the main components. In a certain area, X2 ZnY2 O Z2 , or InO X1 The region in which is the main component, and It exhibits phase separation, and has a mosaic-like structure in which regions composed of each element are the main components.

[0071] Here, In X2 Zn Y2 O Z2 , or InO X1 The region in which is the main component is GaO X3 Compared to regions where these are the main components, this region has high conductivity. In other words, In X2 Zn Y 20 Z2 , or InO X1 In the region where this is the main component, the carrier flows, causing oxidation. Conductivity as a material semiconductor is exhibited. Therefore, In X2 Zn Y2 O Z2 , or In O X1 Regions where this is the main component are distributed in a cloud-like manner within the oxide semiconductor, resulting in a high electric field. Effective mobility (μ) can be achieved.

[0072] On the other hand, GaO X3 Regions in which these are the main components are In X2 Zn Y2 O Z2 , or InO X This region has higher insulating properties compared to the region where 1 is the main component. In other words, GaO X3 etc. The distribution of the main component region within the oxide semiconductor suppresses leakage current and improves performance. It can perform itching operations.

[0073] Therefore, when CAC-OS is used in semiconductor devices, GaO X3 Insulation caused by factors such as And, In X2 Zn Y2 O Z2, or InO X1 The conductivity resulting from this works in a complementary manner. By doing so, a high on-current (I on ), and achieving high field-effect mobility (μ) It is possible.

[0074] Furthermore, semiconductor devices using CAC-OS have high reliability. Therefore, CAC-OS is It is suitable as a component material for various semiconductor devices.

[0075] Correction data is added to the image data using the timing charts shown in Figures 2(A) and (B). An example of the operation of pixel 10 is described below. In the following explanation, high potential is referred to as "H". Low potential is represented by "L". Also, correction data is "Vp", image data is "Vs", and specific electricity Let the position be "Vref". "Vref" can be, for example, 0V, GND potential, or a specific A reference potential can be used. Note that "Vp" is an arbitrary first data point, and "Vs" is arbitrary. This could also be considered a second set of data.

[0076] First, we will explain the process of writing the correction data "Vp" to node NM using Figure 2(A). Here, we will discuss the distribution, coupling, or loss of potential, including the circuit configuration and operating timing. Detailed changes resulting from this will not be considered. Also, the potential change due to capacitive coupling will be considered on the supply side and the supplied side. Although it depends on the capacity ratio of the sides, for the sake of clarity, the capacity value of node NM is a sufficiently small value. Let's assume that.

[0077] At time T1, the potential of wire 121 is set to "H", the potential of wire 122 is set to "L", and the potential of wire 123 is set to If we consider "Vp", then transistor 102 conducts, and the potential of one electrode of capacitive element 104 is This results in "Vref". This operation is a reset to perform a subsequent correction operation (capacitive coupling operation). It is an action.

[0078] Furthermore, transistor 103 conducts, and the potential of wiring 123 at node NM (correction data "Vp") The following is written:

[0079] At time T2, the potential of wiring 121 is set to "L", the potential of wiring 122 is set to "L", and the potential of wiring 123 is set to If set to "L", transistors 102 and 103 become non-conductive, and the node The correction data "Vp" is stored in NM. In addition, the capacitive element 104 stores "Vp-Vref " is retained.

[0080] This completes the writing operation of the correction data "Vp". Note that if no correction is performed, the above In this operation, the correction data "Vp" should be supplied with the same potential as "Vref".

[0081] Next, using Figure 2(B), the correction operation of the image data "Vs" and the circuit block 110 This section explains the display operation of the display element it possesses.

[0082] The operations shown in Figures 2(A) and (B) can be performed continuously within one horizontal period. Alternatively, Figure 2 Perform the operation in (A) in the kth frame (where k is a natural number), and perform the operation in Figure 2(B) in the k+1th frame. This can be done using a frame. Alternatively, after the action in Figure 2(A), the action in Figure 2(B) can be performed multiple times. That's fine.

[0083] At time T11, the potential of wiring 121 is "L", the potential of wiring 122 is "H", and the potential of wiring 123 is If we denote this as "Vs", then transistor 101 conducts, and capacitive coupling with capacitive element 104 causes the noise The potential "Vs" of wiring 123 is added to the potential of node NM. At this time, the potential of node NM The formula is "Vp - Vref + Vs", and if "Vref" = 0, then the potential at node NM is It becomes "Vp + Vs".

[0084] At time T12, the potential of wiring 121 is "L", the potential of wiring 122 is "L", and the potential of wiring 123 is If we set this to "L", transistor 103 becomes non-conductive, and the potential of node NM is "Vp+". It is held in "Vs".

[0085] Subsequently, the display element of the circuit block 110 displays according to the potential of node NM. The operation will be performed. Depending on the configuration of the circuit block, the display may start from time T1 or time T11. It may also perform actions.

[0086] Here, the image data correction process will be explained using Figure 3(A).

[0087] The diagram shown in Figure 3(A) shows four pixels (P1 to P4) in the horizontal and vertical directions, and from left to right, Image data to be processed (Vs1, Vs2, Vs3), correction data to be input (+Vp1, V p0, -Vp1), and the corrected image data that is generated. Note that in the following explanation, In a display element, high brightness is displayed when the potential of the image data is relatively high, and low brightness is displayed when it is low. This will be permitted.

[0088] For example, in pixel P1, a positive correction data "+Vp" is applied to the image data "Vs1". When 1" is applied, the image data becomes "Vs1 ​​+ Vp1", and the brightness increases. Pixel P In 2 and P3, the correction data " is essentially no correction applied to the image data Vs2. When "Vp0" is applied, the image data becomes "Vs2 + Vp0 = Vs1", and the brightness changes. No. In pixel P4, negative correction data "-V" is applied to the image data "Vs3". When "p1" is applied, the image data becomes "Vs1-Vp1", and the brightness decreases.

[0089] In combinations of image data and correction data like this, upconversion, HD Reduction (R) display, correction of display unevenness inherent to the display device, and correction of the threshold voltage of the transistors in the pixels. Corrections and other actions can be performed.

[0090] In upconversion, for example, the same image data is supplied to all four pixels. Each pixel can display a different image. For example, the number of pixels in 8K4K Suitable for a specific 4 pixels of a display device having a 4K2K pixel count, and for a specific 1 pixel of a display device having a 4K2K pixel count. By inputting the data to be used, it is possible to display it with improved resolution.

[0091] In a broader sense, it is image data correction, but it can also be used to overlay and display different images. Figure 3(B) shows an image of the entire display unit, consisting of image data "Vs" from left to right. The first image, the second image composed of correction data "Vp", the first image and the second image This is a composite image.

[0092] In such combinations of image data and correction data, the composite display of different images is In addition, it is possible to improve the overall brightness of the displayed image. For example, text insertion and AR (A) It can be applied to displays such as (Augmented Reality).

[0093] Figures 4(A) to (C) can be applied to circuit block 110 and include an EL element as a display element. This is an example of a configuration.

[0094] The configuration shown in Figure 4(A) consists of a transistor 111, a capacitive element 113, and an EL element 114. It has. One of the sources or drains of transistor 111 is one of the EL elements 114. The electrodes are electrically connected. One electrode of the EL element 114 is connected to one electrode of the capacitive element 113. It is electrically connected to the pole. The other electrode of the capacitive element 113 is connected to the gate of transistor 111. It is electrically connected to node NM. The gate of transistor 111 is electrically connected to node NM. ru.

[0095] The source or drain of transistor 111 is electrically connected to wiring 128. The other electrode of the EL element 114 is electrically connected to the wiring 129. Wirings 128, 12 9 has the function of supplying power. For example, wiring 128 can supply a high potential power supply. Yes, it is possible. Furthermore, wiring 129 can supply a low-potential power supply.

[0096] Here, the source of transistor 103 for supplying “Vref” as shown in Figure 1 or The other end of the drain can be electrically connected to wiring 128. “Vref” is 0V. Since it is preferable to be GND or a low potential, the wiring 128 is at least at those potentials. It also has the function of supplying either of the following. Wiring 128 has the function of writing data to node NM. During the timing phase, "Vref" is supplied, and a high potential is applied when the EL element 114 is made to emit light. All you need to do is supply power.

[0097] In the configuration shown in Figure 4(A), the potential of node NM is greater than or equal to the threshold voltage of transistor 111. When this happens, current flows through the EL element 114. Therefore, the timing shown in Figure 2(A) In some cases, the EL element 114 may start emitting light at time T1 in the chart, limiting its applications. It can happen.

[0098] Figure 4(B) shows the configuration of Figure 4(A) with the addition of transistor 112. Either the source or drain of transistor 112 is connected to the source or drain of transistor 111. It is electrically connected to one side of the transistor. The other side of the source or drain of transistor 112 is The EL element 114 is electrically connected. The gate of transistor 112 is electrically connected to wiring 126. They are electrically connected. Wiring 126 is a signal line that controls the conduction of transistor 112. It can have a function.

[0099] In this configuration, the potential of node NM is greater than or equal to the threshold voltage of transistor 111, When the transistor 112 conducts, current flows through the EL element 114. Therefore, Figure 2( The EL element 114 should start emitting light after time T12 in the timing chart shown in B). This allows for and is suitable for operations that involve correction.

[0100] Figure 4(C) shows the configuration of Figure 4(B) with the addition of transistor 115. Either the source or drain of transistor 115 is connected to the source or drain of transistor 111. It is electrically connected to one side of the transistor. The other side of the source or drain of transistor 115 is It is electrically connected to wiring 130. The gate of transistor 115 is electrically connected to wiring 131. It is connected to the following. Wiring 131 functions as a signal line that controls the conduction of transistor 115. It can have the following. Note that the gate of transistor 115 is electrically connected to the wiring 122. You may continue.

[0101] Wiring 130 can be electrically connected to a source of a specific potential, such as a reference potential. A specific potential is supplied from line 130 to either the source or the drain of transistor 111. This also helps to stabilize the writing of image data.

[0102] Furthermore, wiring 130 can be connected to circuit 120 and has the function of a monitor line. It is also possible to do this. Circuit 120 is the source of the specific potential mentioned above, and the electrical characteristics of transistor 111 It may have one or more functions for acquiring data and for generating correction data.

[0103] When wiring 130 is used as a monitor line, the correction data "Vp" mentioned above is used as the tracer The circuit 120 can generate a potential that corrects the threshold voltage of the inverter 111.

[0104] Figures 5(A) to (C) are applicable to the circuit block 110 and include a liquid crystal element as a display element. This is an example of a configuration.

[0105] The configuration shown in Figure 5(A) includes a capacitive element 116 and a liquid crystal element 117. One electrode of 7 is electrically connected to one electrode of the capacitive element 116. Capacitive element 116 One of the electrodes is electrically connected to node NM.

[0106] The other electrode of the capacitive element 116 is electrically connected to the wiring 132. One electrode is electrically connected to the wiring 133. Wirings 132 and 133 are connected to the power supply unit. It has the ability to connect to a reference potential such as GND or 0V or any other potential. For example, wiring 132 and 133 can connect to a reference potential such as GND or 0V or any other potential. It can be supplied.

[0107] Here, the source of transistor 103 for supplying “Vref” as shown in Figure 1 or The other end of the drain can be electrically connected to wiring 132.

[0108] In this configuration, when the potential of node NM exceeds the operating threshold of the liquid crystal element 117, the liquid crystal element The operation of the crystal element 117 begins. Therefore, the timing chart shown in Figure 2(A) The display operation may begin at time T1, which may limit its applications. However, In the case of a transmissive liquid crystal display, the backlight is turned off until time T12 as shown in Figure 2(B). By using these actions in combination, it is possible to suppress visibility even if unnecessary display actions are performed. ru.

[0109] Figure 5(B) shows the configuration of Figure 5(A) with the addition of transistor 118. One of the sources or drains of the sta 118 is electrically connected to one of the electrodes of the capacitive element 116. The source or drain of transistor 118 is electrically connected to node NM. The gate of transistor 118 is electrically connected to wire 126. Wiring 1 Line 26 can function as a signal line that controls the conduction of transistor 118. .

[0110] In this configuration, the potential of node NM in the liquid crystal element 117 increases as the transistor 118 conducts. It is applied. Therefore, the liquid crystal is applied from time T12 onwards in the timing chart shown in Figure 2(B). It can initiate the operation of the element and is suitable for operations that involve correction.

[0111] Furthermore, when transistor 118 is in a non-conductive state, it supplies power to capacitive element 116 and liquid crystal element 117. Because the supplied potential is maintained, before rewriting the image data, the capacitive element 116 and It is preferable to reset the potential supplied to the liquid crystal element 117. This reset is, for example, Then, a reset potential is supplied to the wiring 123 to simultaneously turn on the transistor 103 and the transistor 118. That's all.

[0112] Figure 5(C) shows a configuration in which the transistor 119 is added to the configuration of Figure 5(B). One of the source or drain of the transistor 119 is electrically connected to one electrode of the liquid crystal element 117. One of the source or drain of the transistor 119 is electrically connected to one electrode of the liquid crystal element 117. The other of the source or drain of the transistor 119 is electrically connected to the wiring 130. The gate of the transistor 119 is electrically connected to the wiring 131. The wiring 131 can function as a signal line for controlling the conduction of the transistor 119. The gate of the transistor 119 may be electrically connected to the wiring 122. The circuit 120 electrically connected to the wiring 130 is the same as the description of Figure 4(C) mentioned above. In addition, it may have a function of resetting the potentials supplied to the capacitor element 116 and the liquid crystal element 117. The gate of the transistor 119 may be electrically connected to the wiring 122.

[0113] The circuit 120 electrically connected to the wiring 130 is the same as the description of Figure 4(C) mentioned above. In addition, it may have a function of resetting the potentials supplied to the capacitor element 116 and the liquid crystal element 117. The circuit 120 electrically connected to the wiring 130 is the same as the description of Figure 4(C) mentioned above. In addition, it may have a function of resetting the potentials supplied to the capacitor element 116 and the liquid crystal element 117. That's all.

[0114] In addition, in Figures 4 and 5, an example of supplying "Vref" from the power supply line is shown, but it can also be supplied from the scanning line. For example, as shown in Figure 6(A), "Vref" may be supplied from the wiring 122. As shown in Figure 6(A), when writing correction data (when the transistor 103 is turned on), the wiring 122 is supplied with a potential corresponding to "L", so this potential can be used as "Vref". In addition, in Figures 4 and 5, an example of supplying "Vref" from the power supply line is shown, but it can also be supplied from the scanning line. For example, as shown in Figure 6(A), "Vref" may be supplied from the wiring 122. As shown in Figure 6(A), when writing correction data (when the transistor 103 is turned on), the wiring 122 is supplied with a potential corresponding to "L", so this potential can be used as "Vref". In addition, in Figures 4 and 5, an example of supplying "Vref" from the power supply line is shown, but it can also be supplied from the scanning line. For example, as shown in Figure 6(A), "Vref" may be supplied from the wiring 122., when writing correction data (when the transistor 103 is turned on), the wiring 122 is supplied with a potential corresponding to "L", so this potential can be used as "Vref". In addition, in Figures 4 and 5, an example of supplying "Vref" from the power supply line is shown, but it can also be supplied from the scanning line. For example, as shown in Figure 6(A), "Vref" may be supplied from the wiring 122. As shown in Figure 6(A), when writing correction data (when the transistor 103 is turned on), the wiring 122 is supplied with a potential corresponding to "L", so this potential can be used as "Vref". In addition, in Figures 4 and 5, an example of supplying "Vref" from the power supply line is shown, but it can also be supplied from the scanning line. For example, as shown in Figure 6(A), "Vref" may be supplied from the wiring 122. As shown in Figure 6(A), when writing correction data (when the transistor 103 is turned on), the wiring 122 is supplied with a potential corresponding to "L", so this potential can be used as "Vref".

[0115] In addition, as shown in Figures 6(B) and (C), the transistors 101, 102, and 103 may have a configuration with a back gate. Figure 6(B) shows a configuration where the back gate is electrically connected to the front gate. In addition, as shown in Figures 6(B) and (C), the transistors 101, 102, and 103 may have a configuration with a back gate. Figure 6(B) shows a configuration where the back gate is electrically connected to the front gate. This shows a configuration that is electrically connected and has the effect of increasing the on-current. Figure 6(C) shows The diagram shows a configuration in which the gate is electrically connected to wiring 134 that can supply a constant potential. The threshold voltage of the transistor can be controlled. See Figures 4(A) to (C) and The transistors in the circuit block 110 shown in Figures 5(A) to (C) also have back gates. You may provide one.

[0116] Figure 7 shows a portion (4 pixels) of a pixel array having pixel 11 to which the basic configuration of pixel 10 is applied. This is a diagram showing the following: Pixel 11 contains a transistor 103, a capacitive element 104, and a circuit block. Section 110 is provided. Note that the n and m in parentheses attached to the symbols indicate a specific row, and i indicates a specific column. (where n, m, and i are natural numbers)

[0117] Each of the 11 pixels is arranged in a matrix, with the nth row and ith column, and the nth row and (i+x)th column (x is It can be placed in the (n+1)th row, i-th column and the (n+1)th row, (i+x)-th column (natural numbers). Figure 7 shows the configuration when x=1.

[0118] Furthermore, the pixel array includes four pixels 11 and a transistor 101 electrically connected to them. Transistor 102a and transistor 102b are provided. Transistor 102a, 1 02b has the function of transistor 102 in pixel 10.

[0119] Furthermore, transistor 101 is an element of each pixel 11 and is shared by four pixels. It can also be said that transistor 102a controls pixels 11[n,i] and 11[n,i+1]. It is an element of the pixel, and it can also be said that it is shared by two pixels. Transistor 102b is a pixel Elements of 11[n+1,i] and pixel 11[n+1,i+1], which are shared by two pixels. It could also be said that it possesses. Furthermore, transistors 101, 102a, and 102b are either They may be distributed across the pixel area.

[0120] In each pixel 11, either the source or the drain of the transistor 103 is connected to a capacitive element 1 It is electrically connected to one electrode of 04. One electrode of the capacitive element 104 is connected to the circuit block It is electrically connected to 110. The other electrode of the capacitive element 104 is connected to the base of transistor 101. It is electrically connected to either the source or the drain of transistor 101. One side of the rain is electrically connected to either the source or drain of transistor 102a. Also, either the source or drain of transistor 101 is connected to transistor 102. It is electrically connected to either the source or the drain of b.

[0121] In this pixel array, the number of wirings and Several identical operations can be performed with a configuration that uses fewer transistors.

[0122] Furthermore, even if the resolution of the display device and the image data are different, the image data and correction data Switching the input path of the data allows for upconversion or downconversion. It allows for appropriate labeling without any issues.

[0123] Using the timing charts shown in Figures 8(A1) and (A2), different timings are applied to each pixel 11. An example of the operation of writing data will be explained. This operation is performed, for example, when the number of pixels is 8K or 4K. A corresponding display device when inputting high-resolution image data (8K4K data) This applies to one pixel 11. Although the description is given for one pixel 11, the same operation can be applied to the other pixels 11.

[0124] In the following description, a high potential is represented by "H", a low potential by "L", and a specific potential between the high and low potentials by "M". Note that "M" can be a reference potential such as 0V or GND, but it can also be other potentials. Also, the image data for high resolution is denoted as "VsH" and the correction data for high resolution is denoted as "Vp1". Note that "Vp1" can be any first data and "VsH" can be any second data.

[0125] First, the operation of writing the image data "VsH" to the node NM using FIG. 8(A1) will be described. Here, detailed changes due to circuit configuration, operation timing, etc. in potential distribution, coupling, or loss are not taken into account.

[0126] At time T1, when the potential of wiring 121 is "H", the potential of wiring 122 is "L", and the potential of wiring 123 is "VsH", transistor 102 conducts, and the potential of the other electrode of capacitor element 10 is "Vref". This operation is a reset operation for performing a subsequent correction operation (capacitive coupling operation). <00​​​​​​​​​​​​​​ The "ef" value is retained.

[0129] This completes the writing operation of the image data "VsH". Next, using Figure 8(A2) , Correction operation of image data "VsH" and display on the display element of circuit block 110 Let's explain the operation.

[0130] The operations shown in Figures 8(A1) and (A2) can be performed continuously within one horizontal period. Alternatively, Perform the operation shown in Figure 8(A1) in the kth frame (where k is a natural number), and perform the operation shown in Figure 8(A2) in the kth frame. It may also be done in +1 frame. Alternatively, the action in Figure 8(A1) followed by the action in Figure 8(A2) You may perform this multiple times.

[0131] At time T11, the potential of wiring 121 is "L", the potential of wiring 122 is "H", and the potential of wiring 123 is If we call this "Vp1", then transistor 101 conducts, and capacitive coupling of capacitive element 104 occurs. The potential "Vp1" of wiring 123 is added to the potential of node NM. At this time, node NM The potential is "VsH - Vref + Vp1", and if "Vref" = 0, then at node NM The potential becomes "VsH + Vp1". Note that if no correction is performed, in the above operation, For the correction data "Vp1", simply supply the same potential as "Vref".

[0132] At time T12, the potential of wiring 121 is "L", the potential of wiring 122 is "L", and the potential of wiring 123 is If we denote this as "M", then transistor 101 becomes non-conductive, and the potential of node NM is "VsH+". It is stored in "Vp1".

[0133] Subsequently, the display element of the circuit block 110 displays according to the potential of node NM. The operation will be performed. Depending on the configuration of the circuit block, the display may start from time T1 or time T11. It may also perform actions.

[0134] By applying correction to the selected pixels in this way, HDR display and other similar effects can be achieved. Although the correction data "Vp1" will have the same value for all four pixels, to obtain a visual effect of light and dark... That is sufficient. Also, if no correction is made, at time T11, the potential of wiring 123 will be " It should be maintained at "M". Alternatively, set the potential of wiring 122 to "L" and transistor 101 You just need to avoid making it conductive.

[0135] Next, using the timing charts shown in Figures 8(B1) and (B2), the same timing is applied to the four pixels 11. This section describes the operation of writing data. This operation is, for example, compatible with 8K and 4K resolutions. This refers to a display device that accepts low-resolution image data (4K2K data) as input. ru.

[0136] First, we will explain the process of writing the correction data "Vp2" to node NM using Figure 8(B1). In the following, image data for low resolution will be referred to as "VsL", and correction data for low resolution will be referred to as "Vp Let's set it to 2. Note that "Vp2" is any first data, and "VsL" is any second data. That is also possible.

[0137] At time T1, the potential of wire 121 is set to "H", the potential of wire 122 is set to "L", and the potential of wire 123 is set to When set to "Vp2", transistor 102 conducts, and the potential of the other electrode of capacitive element 104 This becomes "Vref". This operation is a reset to perform a subsequent correction operation (capacitive coupling operation). It is a T action.

[0138] Furthermore, transistor 103 conducts, and the potential of wiring 123 at node NM (correction data "Vp") "2") is written.

[0139] At time T2, the potential of wiring 121 is set to "L", the potential of wiring 122 is set to "L", and the potential of wiring 123 is set to If we set it to "M", transistors 102 and 103 become non-conductive, and the node The correction data "Vp2" is stored in NM. In addition, the capacitive element 104 stores "Vp2-Vr The "ef" value is retained.

[0140] This completes the writing operation of the correction data "Vp2". Note that if no correction is performed, In the above operation, the correction data "Vp2" should be supplied with the same potential as "Vref". .

[0141] Next, using Figure 8(B2), we will explain the correction operation of the image data "VsL" and circuit block 1. The display operation of the display element in 10 will be explained.

[0142] The operations shown in Figures 8(B1) and (B2) can be performed continuously within one horizontal period. Alternatively, Figure The operation in 8(B1) is performed in the kth frame, and the operation in 8(B2) is performed in the k+1th frame. You may do so. Alternatively, you may perform the action in Figure 8(B2) multiple times after the action in Figure 8(B1). good.

[0143] At time T11, the potential of wiring 121 is "L", the potential of wiring 122 is "H", and the potential of wiring 123 is If we denote this as "VsL", then transistor 101 conducts, and capacitive coupling of capacitive element 104 occurs. The potential "VsL" of wiring 123 is added to the potential of node NM. At this time, node NM The potential is "Vp2 - Vref + VsL", and if "Vref" = 0, then at node NM The potential is "Vp2 + VsL".

[0144] At time T12, the potential of wiring 121 is "L", the potential of wiring 122 is "L", and the potential of wiring 123 is If we call this "M", then transistor 101 becomes non-conductive, and the potential of node NM is "Vp2+". It is stored in "VsL".

[0145] Subsequently, the display element of the circuit block 110 displays according to the potential of node NM. The operation will be performed. Note that depending on the configuration of the circuit block, the display operation may start from time T11. There are also others.

[0146] As correction data "Vp2", different values ​​can be input to each pixel 11, Even if the image data "VsL" is the same, each pixel 11 can display different information. This allows for upscaling. Note that if no correction is applied, the same image will be displayed at 4 pixels. This will be displayed.

[0147] By operating as described above, the original image data can be displayed without upconverting it. Input can be placed in the designated area, and the appropriate display can be achieved. Alternatively, appropriate supplementary information can be provided for image display. It is possible to perform the correct action.

[0148] Figure 9(A) is an example of a block diagram of a display device according to one embodiment of the present invention. This display device is A pixel array 12 in which pixels 11 are arranged in a matrix, a low driver 13, and a column It has a driver 14, a circuit 15, and a selection circuit 16. Note that in Figure 9(A), the transistor Transistors 102a and 102b are represented as a single block, and the potential "Vref" is supplied. The connection method to the supply wiring is omitted.

[0149] The low driver 13 combines, for example, a shift register 20 and a buffer circuit 21. This configuration can be achieved by controlling the continuity of the buffer circuit 21, and the wiring 121 Alternatively, data can be output to wiring 122.

[0150] The column driver 14 combines, for example, a shift register 22 and a buffer circuit 23. This configuration can be achieved by controlling the conductivity of the buffer circuit 23, and the wiring 12 Data can be output to 3.

[0151] Circuit 15 has the function of generating correction data. It can also be described as an external device for that purpose.

[0152] The low driver 13 conducts transistors 101 and 102a and 102b. It can control the following. The column driver 14 connects the wiring 123 to correction data or image data We can supply data.

[0153] Circuit 15 is used to store high-resolution image data "VsH" (e.g., 8K4K data) or low-resolution image data. Image data for resolution, "VsL" (for example, 4K2K data), is input. When "VsH" is input, correction data "Vp1" is generated, and image data "VsL" When this is entered, correction data "Vp2" is generated.

[0154] In addition to the correction data "Vp1" and "Vp2" generated by circuit 15, the selection circuit 16 also uses external Correction data "Vp1", "Vp2" or image data "VsH", "VsL" generated by This can be output to column driver 14.

[0155] In the configuration shown in Figure 9(A), for example, when performing display operation at low resolution without correction, each driver Since the output stage of the amplifier can be halved, power consumption can be reduced.

[0156] Circuit 15 may have a neural network. For example, it may have a large number of images as training data. By using a deep neural network trained as the data, highly accurate correction data can be obtained. It is possible to generate data.

[0157] As shown in Figure 10(A), the neural network NN consists of an input layer IL, an output layer OL, and a middle layer. It can be composed of an intermediate layer (hidden layer) HL. Input layer IL, output layer OL, intermediate layer H Each L has one or more neurons (units). Note that the intermediate layer HL has one It may be one layer or two or more layers. A neural network having two or more intermediate layers (HL). The network can also be called a DNN (Deep Neural Network), and deep Learning using neural networks can also be called deep learning.

[0158] Each neuron in the input layer (IL) receives input data, and each neuron in the hidden layer (HL) receives pre- Output signals from neurons in the output layer or subsequent layer are input, and each neuron in the output layer OL receives the output signal from the previous layer The output signal of the neuron is input. Note that each neuron is connected to all the neurons in the preceding and succeeding layers. It may be connected to all neurons (fully connected), or it may be connected to some neurons.

[0159] Figure 10(B) shows an example of computation by neurons. Here, neuron N and new This shows two neurons in the front layer that output signals to neuron N. Neuron N is in the front layer The output x1 of the neuron and the output x2 of the neuron in the previous layer are input. Then, the new In Ron-N, the product of output x1 and weight w1 (x1w1) and the product of output x2 and weight w2 After the sum of the calculation results (x2w2), x1w1 + x2w2, is calculated, bias b is applied as needed. These are added together, and the value a = x1w1 + x2w2 + b is obtained. Then, the value a is used in the activation function h. Therefore, the signal is converted, and the output signal y=h(a) is output from neuron N.

[0160] Thus, the calculation performed by neurons involves adding up the products of the outputs and weights of the neurons in the previous layer. This includes multiplication operations, namely the sum-of-products operation (x1w1 + x2w2 above). This can be done using a program in software, or it can be done by hardware. This is also acceptable. When performing multiply-accumulate operations in hardware, a multiply-accumulate circuit can be used. This multiply-accumulate circuit may use a digital circuit or an analog circuit. That's good too.

[0161] The multiply-accumulate circuit may be constructed using Si transistors, or OS transistors. It may also be configured as follows. In particular, because the OS transistor has an extremely small off-current, the sum-of-accumulate operation cycle It is suitable as a transistor for constituting the analog memory of the circuit. A multiply-accumulate circuit may be constructed using both an and an OS transistor.

[0162] Note that the generation of correction data can also be performed using the aforementioned circuit 120, not just circuit 15. See Figure 9(B). In addition, the display unit displays in grayscale, and the brightness of the display is set to luminance. Correction data is generated based on the data read by the meter and the data read from the photograph of the display. This is also good. In addition, a sensor 24 capable of detecting the brightness of the display is provided to detect the deterioration of the display element and compensate for it. A circuit 25 capable of generating positive data may be provided (see Figure 9(C)).

[0163] Next, we apply the circuit block shown in Figure 4(A) to the pixel array shown in Figure 7 (see Figure 11). The simulation results for (illumination) are explained below. The parameters are as follows: The sizes are L / W=6μm / 6μm (transistor 111), L / W=4μm / 4μm ( (Other transistors), capacitance value of capacitive element 104 150fF, capacitance value of capacitive element 113 5 0fF, EL element 114 is an FN diode model, wiring 128 has an anode potential of +1 0V, +1V as "Vref", wiring 129 as cathode potential -5V, image data The minimum value of the correction data was set to +1V and the maximum value to +8V. SPICE was used for the software.

[0164] Figures 12(A) to (C) show the simulation results verifying high-resolution display (uncorrected). This is the result. Figure 12(A) is the timing chart used for verification. By making transistor 103 conduct at times T1 to T2, a picture is drawn from wiring 123. The image data "Vs" (s[n]) is written. Also, at times T3 to T4, the image data Write data "Vs" (s[n+1]). At this time, wiring 128 is the anode power It will be assigned a rank.

[0165] Figure 12(B) shows the current (I) that flows through the EL element 114 in response to the image data "Vs". LED )of This is the result of the simulation. Figure 12(B) shows the simulation for a single pixel. The result confirms that grayscale display is possible in any of the pixels (pix1 to pix4). It is being done.

[0166] Furthermore, Figure 12(C) shows the potential "V" of node NM relative to the image data "Vs". NM "Change This is the result of the simulation. In every pixel, the potential of node NM is "V NM "The picture It has been confirmed that it is proportional to the image data "Vs".

[0167] In other words, it is possible to display the high-resolution image data "Vs" supplied from wiring 123. Confirmed.

[0168] Figures 13(A) to (D) show the simulation results verifying low-resolution display (uncorrected). This is the result. Figures 13(A) and (B) are the timing charts used for verification. First, distribution The potential of line 123 is set to its minimum value (+1V), and all of the values ​​are obtained from time T1 to T4 in Figure 13(A). Correction data "Vp" (p) is written to the pixel. At this time, wiring 128 is at potential "V Since we set it to "ref" (+1V), the differential potential held by the capacitive element 104 is 0. In other words, no correction is needed.

[0169] Subsequently, at times T1 to T2 shown in Figure 13(B), transistor 101 is made to conduct. This allows the image data "Vs" (s[m]) to be written from wiring 123.

[0170] Figure 13(C) shows the current (I) that flows through the EL element 114 in response to the image data "Vs". LED )of This is the result of the simulation. Figure 13(C) shows the simulation for a single pixel. The result confirms that grayscale display is possible in all pixels (pix1 to pix4). is done.

[0171] Also, FIG. 13(D) shows the change in the potential “V NM ” of the node NM with respect to the image data “Vs”. This is the result of simulating it. It has been confirmed that the potential “V NM ” of the node NM is proportional to the image data “Vs” for any pixel. That is, it has been confirmed that the low-resolution image data “Vs” supplied from the wiring 123 can be displayed.

[0172] FIGS. 14(A) to (D) are the simulation results for verifying the low-resolution display (with correction). FIGS. 14(A) and (B) are the timing charts used for the verification. First, the desired correction data “Vp” is supplied to the wiring 123, and the correction data “Vp” (p[n]) is written at times T1 to T2 in FIG. 14(A). Also, the correction data “Vp” (p[n + 1]) is written at times T3 to T4. At this time, since the wiring 128 is set to the potential “Vre f” (+1V), the differential potential held in the capacitive element 104 is “Vp - 1”.

[0173] Then, at times T1 to T2 shown in FIG. 14(B), the transistor 101 is turned on to write the image data “Vs” from the wiring 123, and the correction data is added to the image data. At this time, the wiring 128 is set to the anode potential. FIG. 14(C) shows the result of simulating the current (I

[0174]

[0175] [[ID=...]]... FIG. 14(C) shows the result of simulating the current (I LED ) flowing through the EL element 114 for each correction data. As the correction data “Vp”, from 1V to 8

[0176] <00012...

[0177]

[0178]

[0179]

[0180]

[0181]

[0182] <In either case, where V is written and combined with the image data "Vs", grayscale display is possible. This has been confirmed.

[0176] Furthermore, Figure 14(D) shows the potential "V" of node NM relative to the image data "Vs". NM "Change This is the result of the simulation for each correction data "Vp". In any case where 1V to 8V is written and combined with the image data "Vs", The potential of the NM is "V NM It has been confirmed that there is a proportional trend.

[0177] In other words, correction data "Vp" and low-resolution image data " supplied from wiring 123 It was confirmed that combining "Vs" results in a valid display.

[0178] Figure 15 shows an example of applying a pixel according to one aspect of the present invention to an EL display device capable of color display. For example, pixels in a display device capable of displaying color are generally R (red), G (green), and B (blue). ) has a combination of subpixels that emit each of the colors. In Figure 15, the subpixels are arranged horizontally. Each pixel consists of three sub-pixels of different colors: pixel 10R, sub-pixel 10G, and sub-pixel 10B. This represents four pixels in the horizontal and vertical directions. Note that in Figure 15, transistor 102 A and transistor 102b are represented as a single block.

[0179] As described above, in one aspect of the present invention, the transistors are arranged in a matrix via the transistor 101. The four pixels (corresponding in this case to four sub-pixels emitting the same color) are corrected with the data "Vp1" or Image data "VsL" can be input. Also, transistors 102a and 102b A potential is transmitted to two pixels arranged horizontally via (in this case, corresponding to two sub-pixels emitting the same color). "Vref" can be supplied.

[0180] In a stripe array, it is preferable that each subpixel is arranged at equal intervals, but each subpixel When wiring and transistors are shared, the spacing between each sub-pixel (elements with the same function) It may be difficult to maintain a constant interval.

[0181] Therefore, the pixel electrodes connected to sub-pixel 10R, sub-pixel 10G, and sub-pixel 10B are respectively When electrodes 26R, 26G, and 26B are used, as shown in Figure 15, electrodes 26R, 26G, 2 It is preferable to have a configuration in which 6B is arranged at equal intervals. The pixel electrodes are the elements of each subpixel and It could also be said that, but here it is treated as a different element for the sake of clarity in the explanation. This configuration is top-level This is effective for mission-type EL display devices or reflective liquid crystal display devices.

[0182] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0183] (Embodiment 2) In this embodiment, an example of a display device configuration using liquid crystal elements and a display device using EL elements are provided. A configuration example will be described. In this embodiment, the display described in Embodiment 1 will be used. The description of the device's elements, operation, and function will be omitted.

[0184] Figures 16(A) to (C) show the configuration of a display device that can use one aspect of the present invention. This is a diagram.

[0185] In Figure 16(A), the display unit 215 provided on the first substrate 4001 is surrounded by A sealing material 4005 is provided, and the display unit 215 is connected to the sealing material 4005 and the second substrate 4 It is sealed by 006.

[0186] The display unit 215 can be provided with the pixel array shown in Figure 7 of Embodiment 1. The scan line driving circuit described below is a low driver, and the signal line driving circuit is a column driver. It is correct.

[0187] Figure 16(A) shows the scan line drive circuit 221a, the signal line drive circuit 231a, and the signal line drive circuit 232a and the common line drive circuit 241a are each provided on the printed circuit board 4041. The system has multiple integrated circuits 4042. The integrated circuits 4042 are made of single-crystal or polycrystalline semiconductors. It is made of semiconductor material. Signal line driving circuits 231a and 232a are actually The column driver has the function shown in Embodiment 1. The scan line drive circuit 221a is It has the function of a low driver as shown in Embodiment 1. The common line drive circuit 241a is as shown in Embodiment 1 It has the function of supplying a specified potential to the power supply wiring and Vref supply wiring shown. do.

[0188] Scan line drive circuit 221a, common line drive circuit 241a, signal line drive circuit 231a, and signal The various signals and potentials supplied to the line drive circuit 232a are FPC (Flexible Printed Circuit). Supplied via printed circuit (4018).

[0189] The integrated circuit 4042 in the scan line drive circuit 221a and the common line drive circuit 241a is shown in the table. It has the function of supplying a selection signal to the display unit 215. Signal line drive circuit 231a and signal line drive The integrated circuit 4042 in the moving circuit 232a has the function of supplying image data to the display unit 215. The integrated circuit 4042 is surrounded by a sealing material 4005 on the first substrate 4001. It is implemented in a different area than the one it is currently implemented in.

[0190] The connection method for the integrated circuit 4042 is not particularly limited; wire bonding is also an option. Methods include the COG (Chip On Glass) method and the TCP (Tape Carrier) method. Methods such as the Package method and the COF (Chip On Film) method can be used. .

[0191] Figure 16(B) shows the integrated components included in signal line drive circuits 231a and 232a. This shows an example of implementing circuit 4042 using the COG method. It also shows how to implement part or all of the drive circuit. The body can be integrally formed on the same substrate as the display unit 215 to form a system-on-panel. Cut.

[0192] In Figure 16(B), the scan line drive circuit 221a and the common line drive circuit 241a are shown in the display unit 2 This shows an example where it is formed on the same substrate as 15. The drive circuit is the same as the pixel circuit in the display unit 215. By forming parts at certain times, the number of parts can be reduced. Therefore, productivity can be increased. can.

[0193] Furthermore, in Figure 16(B), the display unit 215 provided on the first substrate 4001 and the scan line drive The moving circuit 221a and the common line drive circuit 241a are surrounded by a sealing material 4005 A display unit 215, a scan line drive circuit 221a, and a common line drive circuit are provided. A second substrate 4006 is provided on top of 241a. Therefore, the display unit 215, scan line drive The drive circuit 221a and the common line drive circuit 241a are connected to the first substrate 4001 and the sealing material 40 The display element is sealed together with 05 and the second substrate 4006.

[0194] Furthermore, in Figure 16(B), the signal line drive circuits 231a and 232a are shown separately. An example of forming and mounting on the first substrate 4001 is shown, but the configuration is not limited to this. The scan line drive circuit may be formed and implemented separately, or it may be part of the signal line drive circuit or the scan line The drive circuit may be formed and implemented separately. Also, as shown in Figure 16(C), the signal The line drive circuit 231a and the signal line drive circuit 232a are formed on the same substrate as the display unit 215. That's fine.

[0195] Furthermore, the display device includes a panel in which the display elements are sealed, and a controller on the panel. This may include modules with ICs and other components mounted on them.

[0196] Furthermore, the display unit and scan line driving circuit provided on the first substrate have multiple transistors. The transistor shown in the above embodiment is used as the transistor in question. It is possible.

[0197] The structure of the transistors in the peripheral drive circuit and the transistors in the pixel circuit of the display unit is They may be the same or they may be different. All transistors in the peripheral drive circuit The transistors may have the same structure, and the system may have two or more transistors with different structures. That is also fine. Similarly, all transistors in the pixel circuit are transistors of the same structure. It is also possible to have two or more types of transistor structures.

[0198] Furthermore, an input device 4200 can be provided on the second substrate 4006. (See Figure 16) A configuration in which the display device is equipped with an input device 4200 can function as a touch panel. .

[0199] The detection element (also called a sensor element) of a touch panel according to one embodiment of the present invention is not limited. Various sensors capable of detecting the proximity or contact of an object to be detected, such as a finger or stylus. It can be applied as a detection element.

[0200] Examples of sensor types include capacitive, resistive, surface acoustic wave, and infrared sensors. Various methods can be used, such as optical, pressure-sensitive, and other similar methods.

[0201] In this embodiment, a touch panel having a capacitive sensing element will be used as an example for explanation. .

[0202] Capacitive capacitance methods include surface capacitance and projected capacitance. Capacitive capacitance methods include self-capacitance methods and mutual capacitance methods. This is preferable because it enables simultaneous multi-point detection.

[0203] A touch panel according to one aspect of the present invention is formed by bonding together a separately manufactured display device and a detection element. The configuration includes a substrate supporting the display element and a detection element on one or both of the opposing substrates. Various configurations can be applied, such as those that include electrodes.

[0204] Figures 17(A) and (B) show examples of touch panels. Figure 17(A) shows touch panel 4 This is a perspective view of 210. Figure 17(B) is a schematic perspective view of the input device 4200. For clarity, only representative components are shown.

[0205] The touch panel 4210 has a configuration in which a display device and a sensing element, which are manufactured separately, are bonded together. be.

[0206] The touch panel 4210 has an input device 4200 and a display device, which are stacked on top of each other. It is being done.

[0207] The input device 4200 includes a substrate 4263, electrodes 4227 and 4228, and multiple wirings 4237. , has multiple wirings 4238 and multiple wirings 4239. For example, electrode 4227 is wiring It can be electrically connected to 4237 or wiring 4239. Also, electrode 4228 is It can be electrically connected to wire 4239. FPC4272b has multiple wires 4237 and electrically connects to each of the multiple wires 4238. FPC4272b has IC427 3b can be provided.

[0208] Alternatively, a touch sensor may be provided between the first substrate 4001 and the second substrate 4006 of the display device. It may be done. When a touch sensor is provided between the first substrate 4001 and the second substrate 4006. In addition to capacitive touch sensors, optical touch sensors using photoelectric conversion elements are also available. You may apply this.

[0209] Figures 18(A) and 18(B) show the region indicated by the dashed line N1-N2 in Figure 16(B). This is a cross-sectional view. The display devices shown in Figures 18(A) and 18(B) have electrodes 4015. Therefore, the electrode 4015 is connected to the terminals of the FPC 4018 via the anisotropic conductive layer 4019, and electricity They are connected by air. Also, in Figures 18(A) and 18(B), electrode 4015 is Wiring in openings formed in insulating layer 4112, insulating layer 4111, and insulating layer 4110 It is electrically connected to 4014.

[0210] Electrode 4015 is formed from the same conductive layer as the first electrode layer 4030, and wiring 4014 is Source and drain electrodes of transistor 4010 and transistor 4011, and It is formed with a conductive layer.

[0211] Furthermore, the display unit 215 and the scan line drive circuit 221a provided on the first substrate 4001 are It has multiple transistors, and in Figures 18(A) and 18(B), the display unit 215 The transistor 4010 included, and the transistor included in the scan line drive circuit 221a The 4011 is shown as an example. Note that in Figures 18(A) and 18(B), transistor 4 Bottom-gate transistors are exemplified as 010 and transistor 4011. However, a top-gate transistor would also work.

[0212] In Figures 18(A) and 18(B), transistors 4010 and 401 An insulating layer 4112 is provided on 1. Also, in Figure 18(B), on the insulating layer 4112 A partition wall 4510 is formed.

[0213] Furthermore, transistors 4010 and 4011 are provided on the insulating layer 4102. Furthermore, transistors 4010 and 4011 are connected to the insulating layer 4111. It has an electrode 4017 formed on top. Electrode 4017 functions as a back gate electrode. It is possible.

[0214] Furthermore, the display devices shown in Figures 18(A) and 18(B) have a capacitive element 4020. Capacitive element 4020 has electrodes 4 formed using the same process as the gate electrode of transistor 4010. It has 021 and electrodes formed in the same process as the source electrode and drain electrode. Each electrode overlaps with an insulating layer 4103 in between.

[0215] Generally, the capacitance of a capacitive element provided in the pixel portion of a display device is determined by the transients arranged in the pixel portion. The device is set to retain charge for a predetermined period, taking into account the leakage current of the sta, etc. The capacitance of the element should be set considering the transistor's off-current, etc.

[0216] The transistor 4010 provided in the display unit 215 is electrically connected to the display element. Figure 18 (A) is an example of a liquid crystal display device that uses liquid crystal elements as display elements. Figure 18(A) In this, the liquid crystal element 4013, which is a display element, has a first electrode layer 4030 and a second electrode layer 40 31 and the liquid crystal layer 4008 are included. The alignment film is configured to sandwich the liquid crystal layer 4008. An insulating layer 4032 and an insulating layer 4033 that function as are provided. The second electrode layer 4031 is The second electrode layer 4030 and the second electrode layer 4031 are provided on the second substrate 4006 side and are liquid crystal. It is superimposed via layer 4008.

[0217] Furthermore, the spacer 4035 is a columnar space obtained by selectively etching the insulating layer. This is a control of the gap (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. It is provided for control purposes. A spherical spacer may also be used.

[0218] Additionally, a black matrix (light-blocking layer), a colored layer (color filter), and polarizing elements can be added as needed. Optical components (optical substrates) such as members, phase difference members, and anti-reflective members may be provided as appropriate. For example, circularly polarized light from a polarizing substrate and a phase difference substrate may be used. Also, a battery may be used as the light source. You may also use backlights, sidelights, etc. Furthermore, the above-mentioned backlights and sidelights may be used. Micro LEDs or similar can be used as the light source.

[0219] In the display device shown in Figure 18(A), between the second substrate 4006 and the second electrode layer 4031, A light-shielding layer 4132, a colored layer 4131, and an insulating layer 4133 are provided.

[0220] Materials that can be used as a light-shielding layer include carbon black, titanium black, and gold. Examples include metal oxides, metal oxides, and composite oxides containing solid solutions of multiple metal oxides. The light-shielding layer is It may be a film containing a resin material, or a thin film of an inorganic material such as a metal. Furthermore, a laminated film containing the material of the colored layer can be used as the light-shielding layer. For example, a light of a certain color A film containing a material used for a colored layer that transmits light, and a material used for a colored layer that transmits light of other colors. A laminated structure with a film containing the material can be used. By using the same material for the colored layer and the light-shielding layer, This is preferable because it allows for the standardization of equipment and simplifies the process.

[0221] Materials that can be used for the colored layer include metal materials, resin materials, pigments, or dyes. Examples include resin materials. The light-shielding layer and the colored layer are formed by, for example, an inkjet method. It can be formed using [this method].

[0222] Furthermore, the display devices shown in Figures 18(A) and 18(B) consist of insulating layer 4111 and insulating layer 41 It has 04. The insulating layer 4111 and insulating layer 4104 are insulating layers that are less permeable to impurity elements. Layers are used. By sandwiching the semiconductor layer of the transistor between insulating layer 4111 and insulating layer 4104, It can prevent the intrusion of impurities from the outside.

[0223] Furthermore, as a display element included in the display device, an electroluminescent light-emitting element is used. An EL element can be applied. An EL element is a light-emitting compound between a pair of electrodes. It has a layer containing (also called the "EL layer"). Between a pair of electrodes, the threshold voltage of the EL element is lower than When a large potential difference is generated, holes are injected into the EL layer from the anode side, and electrons are injected from the cathode side. They are injected. The injected electrons and holes recombine in the EL layer, and the luminescence contained in the EL layer The compound emits light.

[0224] Furthermore, EL elements are distinguished by whether the light-emitting material is an organic compound or an inorganic compound. Generally speaking, the former are called organic EL elements, and the latter are called inorganic EL elements.

[0225] Organic EL elements, when a voltage is applied, release electrons from one electrode and holes from the other electrode. These are each injected into the EL layer. Then, these carriers (electrons and holes) recombine. This causes the luminescent organic compound to form an excited state, and then that excited state returns to the ground state. It emits light at that time. From this mechanism, such a light-emitting element is a current-excited type light-emitting element. They are called children.

[0226] In addition to luminescent compounds, the EL layer also contains materials with high hole injection potential and materials with high hole transport potential. , hole-blocking materials, materials with high electron transport properties, materials with high electron injection properties, or bipolar It may contain substances with high electron transport and hole transport properties.

[0227] The EL layer can be created using vapor deposition (including vacuum deposition), transfer, printing, inkjet, or coating methods. It can be formed by any of the following methods.

[0228] Inorganic electroluminescent (EL) elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements based on their element configuration. They are classified as such. Dispersive inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The luminescence mechanism utilizes donor and acceptor levels, and the donor-acceptor level is the key to this process. This is a receptor recombination type light emission. Thin-film inorganic EL elements sandwich the light-emitting layer between dielectric layers. Furthermore, it has a structure where it is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. This is a localized light emission. Here, we will explain using an organic EL element as the light-emitting element. ru.

[0229] A light-emitting element only needs to have at least one of its pair of electrodes transparent in order to extract light. Then, a transistor and a light-emitting element are formed on the substrate, and light is emitted from the side opposite to the substrate. Top emission structures that emit light from the top surface, and bottom emission structures that extract light from the substrate side. (Bottom emission) structure, or double-sided emission (dual emission) that extracts light from both sides. There are light-emitting elements with an (n) structure, and any light-emitting element with an injection structure can be applied.

[0230] Figure 18(B) shows a light-emitting display device (also known as an "EL display device") that uses a light-emitting element as a display element. This is an example of a display element, the light-emitting element 4513, which is provided in the display unit 215. It is electrically connected to transistor 4010. The configuration of the light-emitting element 4513 is as follows: The structure is a laminated structure consisting of an electrode layer 4030, a light-emitting layer 4511, and a second electrode layer 4031. It is not limited to this. Depending on the direction of the light extracted from the light-emitting element 4513, the light-emitting element 45 The 13 configurations can be changed as needed.

[0231] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. In particular, photosensitive resin Using a lipid material, an opening is formed on the first electrode layer 4030, and the side surface of the opening is continuous. It is preferable to form the surface so that it is an inclined surface with curvature.

[0232] Even if the light-emitting layer 4511 consists of a single layer, it is configured so that multiple layers are stacked. Either way is fine.

[0233] The light-emitting color of the light-emitting element 4513 depends on the material that makes up the light-emitting layer 4511, and can be white, red, green, or blue. These can be cyan, magenta, or yellow, etc.

[0234] One way to achieve color display is to combine a light-emitting element 4513 with a white light-emitting layer with a colored layer. There are two methods: one that combines the two methods that provide a light-emitting element 4513 with a different emission color for each pixel. The first method is more productive than the second method. On the other hand, in the second method, each pixel has an emissive layer 4511 Because it is necessary to produce different types, it is less productive than the former method. However, the latter method This method allows for obtaining a more color-pure emission than the former method. In addition to the latter method, By adding a microcavity structure to element 4513, the color purity can be further enhanced. It is possible.

[0235] The light-emitting layer 4511 may also contain inorganic compounds such as quantum dots. For example, By using the child dots in the light-emitting layer, they can also function as light-emitting materials.

[0236] To prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting element 4513, the second electrode layer A protective layer may be formed on 4031 and the partition wall 4510. The protective layer may be made of silica nitride. N, silicon nitride, aluminum oxide, aluminum nitride, aluminum oxide nitride, Forms aluminum nitride oxide, DLC (Diamond-Like Carbon), etc. It is possible to do so. Also, the first substrate 4001, the second substrate 4006, and the sealing material 4 The space sealed by 005 is filled with a filler material 4514 and sealed in this manner. Therefore, a protective film with high airtightness and minimal degassing (laminate film) is used to prevent exposure to the outside air. It is preferable to package (enclose) the product with film, UV-curing resin film, or other covering material. It seems so.

[0237] In addition to inert gases such as nitrogen and argon, filler material 4514 can also be UV-curing resin. Thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic resins, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) and other materials can be used. Also, filler material 4514 It may contain a desiccant.

[0238] The sealing material 4005 contains glass materials such as glass frit and two-component resins, etc. Resin materials such as heat-curing resins, photocurable resins, and thermosetting resins can be used. Yes, it is possible. Furthermore, the sealant 4005 may contain a desiccant.

[0239] Additionally, if necessary, a polarizing plate or circular polarizing plate (including elliptical polarizing plate) may be placed on the emission surface of the light-emitting element. Even if optical films such as phase difference plates (λ / 4 plate, λ / 2 plate) and color filters are appropriately provided, That's good. Alternatively, an anti-reflective coating may be provided on the polarizing plate or circular polarizing plate. For example, on the surface irregularities. An anti-glare treatment can be applied to further diffuse reflected light and reduce glare.

[0240] Furthermore, by using a microcavity structure for the light-emitting element, it is possible to extract light with high color purity. This is possible. In addition, by combining a microcavity structure and a color filter, the image can be improved. This reduces congestion and improves the visibility of the displayed images.

[0241] A first electrode layer and a second electrode layer (pixel electrode layer, common electrode layer, In the counter electrode layer (also called the counter electrode layer), the direction of the light to be extracted, the location where the electrode layer is provided, and Transmittance and reflectivity can be selected based on the pattern structure of the electrode layer.

[0242] The first electrode layer 4030 and the second electrode layer 4031 are made of indium acid containing tungsten oxide. Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide Indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide By using a light-transmitting conductive material such as indium tin oxide with added silicon dioxide... It is possible.

[0243] Furthermore, the first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W) and molybdenum. (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N) b) Tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium Metals such as titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag). It can be formed using one or more of the alloy thereof, or its metal nitride. .

[0244] Furthermore, the first electrode layer 4030 and the second electrode layer 4031 are made of conductive polymer (conductive polymer It can be formed using a conductive composition containing (also called mer). For example, a so-called π-electron conjugated conductive polymer can be used. or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives The body, or a copolymer consisting of two or more of aniline, pyrrole and thiophene or Examples include its derivatives.

[0245] Furthermore, transistors are susceptible to damage from static electricity, etc., therefore, a protection circuit for the drive circuit is necessary. It is preferable to provide this. The protection circuit is preferably constructed using nonlinear elements.

[0246] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0247] (Embodiment 3) In this embodiment, it is used in place of each transistor shown in the above embodiment. An example of a transistor will be explained using a diagram.

[0248] A display device according to one aspect of the present invention uses a bottom-gate type transistor or a top-gate type transistor. It can be fabricated using various types of transistors, such as DISTROs. Therefore, existing Easily replace the semiconductor layer materials and transistor structures used to match the manufacturing line. It is possible.

[0249] [Bottom-gate transistor] Figure 19(A1) shows a channel-protected transistor, which is a type of bottom-gate transistor. This is a cross-sectional view of the ZISTA 810 in the channel length direction. In Figure 19(A1), the transistor 810 is formed on substrate 771. Also, transistor 810 is formed on substrate 771 The electrode 746 is connected via an insulating layer 772. Furthermore, an insulating layer 726 is connected to the electrode 746. It has a semiconductor layer 742. The electrode 746 can function as a gate electrode. The insulating layer 726 is It can function as an insulating layer.

[0250] Furthermore, an insulating layer 741 is provided on the channel formation region of the semiconductor layer 742. Electrodes 744a and 744b are located on the insulating layer 726, in contact with a portion of 42. Electrode 744a can function as either the source electrode or the drain electrode. Electrode 744b is, It can function as either the source electrode or the other of the drain electrode. Part of electrode 744a, and A portion of electrode 744b is formed on the insulating layer 741.

[0251] The insulating layer 741 can function as a channel protection layer. The insulating layer 741 is placed on the channel formation region. By providing this, the exposure of the semiconductor layer 742 that occurs when electrodes 744a and 744b are formed This prevents leakage. Therefore, when forming electrodes 744a and 744b, the semiconductor layer This prevents the channel formation region of 742 from being etched. One aspect of the present invention According to this, it is possible to realize transistors with good electrical characteristics.

[0252] Furthermore, the transistor 810 has an insulating layer 741 on electrode 744a, electrode 744b and insulating layer 741. It has a layer 728, and an insulating layer 729 on top of the insulating layer 728.

[0253] When an oxide semiconductor is used for the semiconductor layer 742, the electrodes 744a and 744b are small However, in the area in contact with semiconductor layer 742, oxygen is removed from a part of semiconductor layer 742, resulting in an oxygen deficiency. It is preferable to use a material capable of causing oxygen vacancies in the semiconductor layer 742. The resulting region has an increased carrier concentration, and the region becomes n-type, creating an n-type region (n + It becomes a layer. Therefore, this region can function as either a source region or a drain region. When an oxide semiconductor is used in the conductive layer 742, oxygen is removed from the semiconductor layer 742, creating an oxygen vacancy. Examples of materials that can be used to produce this include tungsten and titanium. ru.

[0254] By forming a source region and a drain region in the semiconductor layer 742, the electrode 744a Furthermore, the contact resistance between electrode 744b and semiconductor layer 742 can be reduced. Therefore, the electric field The goal is to improve the electrical characteristics of the transistor, such as effective mobility and threshold voltage. can.

[0255] When using a semiconductor such as silicon for the semiconductor layer 742, the semiconductor layer 742 and electrode 744a Between the semiconductor layer 742 and the electrode 744b, as an n-type semiconductor or a p-type semiconductor It is preferable to provide a functional layer. The layer that functions as an n-type semiconductor or a p-type semiconductor is It can function as either the source or drain region of a transistor.

[0256] The insulating layer 729 has the function of preventing or reducing the diffusion of impurities from the outside into the transistor. It is preferable to form it using a material having the following properties. The insulating layer 729 may be omitted if necessary. It is also possible.

[0257] The transistor 811 shown in Figure 19(A2) has a back gate electrode on the insulating layer 729. It differs from transistor 810 in that it has a functional electrode 723. Electrode 723 is an electrode It can be formed using the same materials and methods as 746.

[0258] Generally, the back gate electrode is formed from a conductive layer, and the gate electrode and back gate electrode form a semiconductor. It is positioned so as to sandwich the channel formation region of the layer. Therefore, the back gate electrode is the gate electrode It can function similarly to a pole. The potential of the buck gate electrode is the same potential as the gate electrode. It may be used as the ground potential (GND potential) or any other potential. By changing the potential of the gate electrode independently of the gate electrode, the transistor's characteristics can be controlled. The voltage can be changed.

[0259] Both electrodes 746 and 723 can function as gate electrodes. The insulating layer 726, insulating layer 728, and insulating layer 729 each serve as gate insulating layers. It can function in this way. The electrode 723 is provided between the insulating layer 728 and the insulating layer 729. That's fine.

[0260] Note that when one of the electrodes 746 or 723 is referred to as the "gate electrode," the other is referred to as the "battery electrode." This is called the "gate electrode." For example, in transistor 811, electrode 723 is called the "gate electrode." When referring to "pole," electrode 746 is called the "back gate electrode." Also, electrode 723 is called the "gate electrode." When used as a "top-gate electrode," transistor 811 is one of the top-gate type transistors. It can be considered a species. Also, either electrode 746 or electrode 723 can be considered as the "first The first gate electrode is sometimes called the "first gate electrode," and the other is sometimes called the "second gate electrode."

[0261] By providing electrodes 746 and 723 with the semiconductor layer 742 in between, further, electrode 74 By setting electrode 6 and electrode 723 to the same potential, the carrier flow region in semiconductor layer 742 As the region becomes larger in the film thickness direction, the amount of carrier movement increases. As a result, As the on-current of the transistor 811 increases, the field-effect mobility also increases.

[0262] Therefore, transistor 811 has a large on-current relative to its occupied area. It is a st. In other words, the area occupied by transistor 811 is relative to the required on-current. It can be made smaller. According to one aspect of the present invention, the area occupied by the transistor can be reduced. Therefore, according to one aspect of the present invention, a semiconductor device with a high degree of integration can be realized. It is possible.

[0263] Furthermore, since the gate electrode and back gate electrode are formed of conductive layers, outside the transistor... A function to prevent the generated electric field from acting on the semiconductor layer in which the channel is formed (especially static electricity). It has an electric field shielding function against such things. By forming this structure and covering the semiconductor layer with a back gate electrode, the electric field shielding function can be enhanced. .

[0264] Furthermore, by forming the back gate electrode with a light-shielding conductive film, the back gate electrode This prevents light from entering the semiconductor layer from the side. Therefore, it prevents photodegradation of the semiconductor layer. This prevents degradation of electrical characteristics, such as a shift in the transistor's threshold voltage. .

[0265] According to one aspect of the present invention, a transistor with good reliability can be realized. Furthermore, This enables the creation of highly reliable semiconductor devices.

[0266] Figure 19(B1) shows a channel-protected transistor 82 with a different configuration than that of Figure 19(A1). This is a cross-sectional view of transistor 0 in the channel length direction. Transistor 820 is approximately the same as transistor 810. Although they have a similar structure, they differ in that the insulating layer 741 covers the edge of the semiconductor layer 742. Furthermore, an opening is formed by selectively removing a portion of the insulating layer 741 that overlaps with the semiconductor layer 742. In this section, the semiconductor layer 742 and the electrode 744a are electrically connected. In another opening formed by selectively removing a portion of the insulating layer 741 that overlaps with 42, a semiconductor The body layer 742 and the electrode 744b are electrically connected. Channel formation region of the insulating layer 741. The overlapping region can function as a channel protection layer.

[0267] The transistor 821 shown in Figure 19(B2) has a back gate electrode on the insulating layer 729. It differs from transistor 820 in that it has a functional electrode 723.

[0268] By providing the insulating layer 741, the semiconductor generated during the formation of electrodes 744a and 744b is prevented. This prevents the exposure of layer 742. Therefore, when forming electrodes 744a and 744b This prevents the semiconductor layer 742 from becoming thin.

[0269] Furthermore, transistors 820 and 821 are transistors 810 and 821. The distance between electrode 744a and electrode 746, and between electrode 744b and electrode 7 The distance between 46 increases. Therefore, the parasitic capacitance that occurs between electrode 744a and electrode 746 It can be made smaller. Also, the parasitic capacitance that occurs between electrode 744b and electrode 746 can be reduced. This can be achieved. According to one aspect of the present invention, a transistor with good electrical characteristics can be realized. Cut.

[0270] Figure 19(C1) shows a channel-etched type transistor, which is a type of bottom-gate transistor. This is a cross-sectional view of transistor 825 in the channel length direction. Transistor 825 has an insulating layer 7 Electrodes 744a and 744b are formed without using 41. Therefore, electrode 744a In addition, a portion of the semiconductor layer 742 that is exposed during the formation of electrode 744b may be etched. On the other hand, since the insulating layer 741 is not provided, the productivity of transistors can be increased.

[0271] The transistor 826 shown in Figure 19(C2) has a back gate electrode on the insulating layer 729. It differs from transistor 825 in that it has a functional electrode 723.

[0272] Figures 20(A1) through (C2) show transistors 810, 811, 820, 821, 825, The cross-sectional views of channel 826 in the channel width direction are shown.

[0273] In the structure shown in Figures 20(B2) and (C2), the gate electrode and the back gate electrode are connected. The potentials of the gate electrode and the back gate electrode become the same. Also, the semiconductor layer 742 is It is sandwiched between the back electrode and the back gate electrode.

[0274] The length of the gate electrode and back gate electrode in the channel width direction is given by the semiconductor layer 74 The length of the semiconductor layer 742 is longer than the length of the channel width, and the entire channel width of the semiconductor layer 742 is the insulating layer 726, 741, 728, and 729 are placed in between and cover the gate electrode or back gate electrode. It has a well-structured configuration.

[0275] By adopting this configuration, the semiconductor layer 742 included in the transistor is used as the gate electrode and the b It can be electrically surrounded by the electric field of the gate electrode.

[0276] Like transistor 821 or transistor 826, gate electrode and back gate The electric field of the electrodes electrically surrounds the semiconductor layer 742 in which the channel formation region is formed. The device structure of a transistor is called a Surrounded channel (S-channel) This can be called an el) structure.

[0277] By using an S-channel structure, either the gate electrode or the back gate electrode or The two methods effectively apply an electric field to the semiconductor layer 742 to induce a channel. This allows for improved transistor current drive capability and the acquisition of high on-current characteristics. This enables the miniaturization of transistors, as it allows for higher on-currents. This becomes possible. Furthermore, by using an S-channel structure, the mechanical properties of the transistor It can increase strength.

[0278] [Top-gate transistor] The transistor 842 shown in Figure 21(A1) is a top-gate type transistor. Electrodes 744a and 744b are formed in insulating layers 728 and 729. The opening is electrically connected to the semiconductor layer 742.

[0279] Furthermore, a portion of the insulating layer 726 that does not overlap with electrode 746 is removed, leaving electrode 746 and the remaining insulating layer By using 726 as a mask to introduce impurity 755 into semiconductor layer 742, the semiconductor layer Impurity regions can be formed in 742 through self-alignment. The transistor 842 has a region in which the insulating layer 726 extends beyond the end of the electrode 746. The impurity concentration in the region where impurity 755 is introduced through the insulating layer 726 of the semiconductor layer 742 is: The region where impurity 755 is introduced without going through the insulating layer 726 becomes smaller. Therefore, semiconductor Body layer 742 has LDD (Lightly Doped D) in a region that does not overlap with electrode 746. A rain region is formed.

[0280] The transistor 843 shown in Figure 21(A2) has an electrode 723 at the point where transistor 84 This differs from 2. Transistor 843 has electrodes 723 formed on substrate 771. Electrode 723 has a region that overlaps with the semiconductor layer 742 via the insulating layer 772. It can function as a back gate electrode.

[0281] Also, transistor 844 shown in Figure 21(B1) and transistor shown in Figure 21(B2) As in the case of TA845, the entire insulating layer 726 in the region that does not overlap with electrode 746 may be removed. Also, transistor 846 shown in Figure 21(C1) and transistor shown in Figure 21(C2) As with Ta847, the insulating layer 726 may be left intact.

[0282] Transistors 842 through 847 also form electrodes 746 after the electrodes 746 have been formed. By using as a mask to introduce impurity 755 into semiconductor layer 742, semiconductor layer 742 An impurity region can be formed within it in a self-aligned manner. According to one aspect of the present invention, electrical properties A transistor with good performance can be realized. Furthermore, according to one aspect of the present invention, This enables the realization of highly advanced semiconductor devices.

[0283] Figure 22(A1) to (C2) shows transistors 842, 843, 844, 845, 846, The cross-sectional views of channel 847 in the channel width direction are shown.

[0284] Transistors 843, 845, and 847 were first This is the S-channel structure described. However, it is not limited to this, transistor 84 3. Transistors 845 and 847 are not made into an S-channel structure. That's fine.

[0285] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0286] (Embodiment 4) Electronic devices that can use a display device according to one aspect of the present invention include display devices and personal computers. Computer, image storage device or image playback device equipped with recording medium, mobile phone, mobile Game consoles including mobile data terminals, e-readers, video cameras, digital still cameras Cameras such as RA, goggle-type displays (head-mounted displays), navigation systems Audio systems, sound reproduction equipment (car audio, digital audio players, etc.), copying Machines, fax machines, printers, multifunction printers, automated teller machines (ATMs), self Examples include vending machines. Specific examples of these electronic devices are shown in Figure 23.

[0287] Figure 23(A) shows a digital camera, consisting of a housing 961, a shutter button 962, and a microphone 9 63, speaker 967, display unit 965, operation keys 966, zoom lever 968, lens 9 It has 69, etc. By using a display device according to one aspect of the present invention in the display unit 965, various images It is possible to display this.

[0288] Figure 23(B) shows a digital signage display unit 922, which has a large display unit 922. For example, column 92 It is attached to the side of 1. By using a display device according to one aspect of the present invention in the display unit 922, It can display various images.

[0289] Figure 23(C) shows a mobile phone, comprising a casing 951, a display unit 952, operation buttons 953, and external It has connection ports 954, a speaker 955, a microphone 956, a camera 957, etc. The telephone has a touch sensor on the display unit 952. It can be used to make phone calls or input text. All operations such as these can be performed by touching the display unit 952 with a finger or stylus. Furthermore, the housing 951 and the display unit 952 are flexible and can be bent as shown in the figure. It can be used. By using a display device according to one aspect of the present invention in the display unit 952, various It can display images.

[0290] Figure 23(D) shows a portable data terminal, consisting of a housing 911, a display unit 912, a speaker 913, and a cable. It has a mer 919, etc. Information is input and output by the touch panel function of the display unit 912. This is possible. By using a display device according to one aspect of the present invention in the display unit 912, various images can be displayed. It is possible to display this.

[0291] Figure 23(E) shows a television, consisting of a casing 971, a display unit 973, operation keys 974, and a speaker 9 75, it has a communication connection terminal 976, an optical sensor 977, etc. The display unit 973 has a touch sensor A sash is provided, and input operations can be performed. Display unit 973 displays a display device according to one aspect of the present invention. By using this, various images can be displayed.

[0292] Figure 23(F) shows an information processing terminal, consisting of a housing 901, a display unit 902, a display unit 903, and a sensor. It has 904, etc. Display unit 902 and display unit 903 consist of a single display panel and are flexible. It possesses flexibility. Furthermore, the housing 901 is also flexible and can be bent and used as shown in the figure. In addition to this, it can also be used in a flat, tablet-like form. Sensor 90 4 can sense the shape of the housing 901, for example, when the housing is bent, the display unit 9 The display of 02 and the display unit 903 can be switched. By using a display device according to one aspect of the present invention in 03, various images can be displayed. .

[0293] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible. [Explanation of symbols]

[0294] 10 pixels 10B subpixel 10G sub-pixels 10R sub-pixel 11 pixels 12-pixel array 13 Low Driver 14 Column Driver 15 circuits 16 Selection Circuit 20 Shift Registers 21 Buffer Circuit 22 Shift Registers 23 Buffer Circuit 24 sensors 25 circuits 26B electrode 26G electrode 26R electrode 101 Transistors 102 transistors 102a Transistor 102b Transistor 103 Transistors 104 Capacitive element 110 Circuit Blocks 111 transistors 112 transistors 113 Capacitive elements 114 EL elements 115 transistors 116 Capacitive elements 117 Liquid crystal elements 118 transistors 119 Transistors 120 circuits 121 Wiring 122 Wiring 123 Wiring 126 Wiring 128 Wiring 129 Wiring 130 Wiring 131 Wiring 132 Wiring 133 Wiring 134 Wiring 215 Display section 221a Scan line drive circuit 231a Signal line drive circuit 232a Signal line drive circuit 241a Common Line Drive Circuit 723 Electrode 726 Insulating layer 728 Insulating layer 729 Insulating layer 741 Insulating layer 742 Semiconductor layer 744a electrode 744b electrode 746 Electrode 755 Impurities 771 circuit board 772 Insulating layer 810 transistors 811 Transistors 820 transistors 821 Transistors 825 Transistors 826 transistors 842 transistors 843 Transistors 844 transistors 845 transistors 846 transistors 847 transistors 901 cabinet 902 Display section 903 Display section 904 Sensor 911 cabinet 912 Display section 913 Speaker 919 Camera 921 pillars 922 Display section 951 cabinet 952 Display section 953 Operation Buttons 954 External connection port 955 Speaker 956 Mike 957 Camera 961 cabinet 962 Shutter button 963 Mike 965 Display section 966 Operation Keys 967 Speakers 968 Zoom Lever 969 Lens 971 cabinet 973 Display section 974 Operation Keys 975 Speaker 976 Communication connection terminal 977 Light Sensor 4001 circuit board 4005 Sealant 4006 circuit board 4008 Liquid Crystal Layer 4010 Transistor 4011 Transistor 4013 Liquid crystal element 4014 Wiring 4015 Electrode 4017 Electrode 4018 FPC 4019 Anisotropic conductive layer 4020 Capacitive element 4021 Electrode 4030 Electrode layer 4031 Electrode layer 4032 Insulating layer 4033 Insulating layer 4035 Spacer 4041 Printed Circuit Board 4042 Integrated Circuit 4102 Insulating layer 4103 Insulating layer 4104 Insulating layer 4110 Insulating layer 4111 Insulating layer 4112 Insulating layer 4131 Colored layer 4132 Light blocking layer 4133 Insulating layer 4200 Input Device 4210 Touch Panel 4227 Electrode 4228 Electrode 4237 Wiring 4238 Wiring 4239 Wiring 4263 circuit board 4272b FPC 4273b IC 4510 Bulkhead 4511 Emitting layer 4513 Light-emitting element 4514 Filling material

Claims

[Claim 1] The first transistor and The second transistor, The first circuit and the second circuit, The first wiring and, A display device having a second wiring, Each of the first and second circuits comprises a third transistor, a first capacitive element, and a circuit block. Either the source or drain of the third transistor is electrically connected to one electrode of the first capacitive element. One electrode of the first capacitive element is electrically connected to the circuit block. The other electrode of the first capacitive element is electrically connected to either the source or the drain of the first transistor. Either the source or drain of the first transistor is electrically connected to either the source or drain of the second transistor. The source or drain of the third transistor in the first circuit is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the first wiring, The gate of the third transistor in the first circuit is electrically connected to the second wiring. The gate of the third transistor in the second circuit is electrically connected to the second wiring. The gate of the second transistor is electrically connected to the second wiring, The circuit block is a display device having a display element.

Images