Semiconductor equipment

Abstract

To provide a semiconductor device with a novel configuration. [Solution] The system comprises multiple memory circuits, a switching circuit, a first arithmetic circuit, and a second arithmetic circuit. Each of the multiple memory circuits has the function of holding weight data. The switching circuit is It has a function to switch the conduction state between one of the memory circuits and the first arithmetic circuit. The arithmetic circuit is based on the sum-of-products operation of the input data and the weight data selected by the switching circuit. The first output signal is then output to the second arithmetic circuit. Layers having multiple memory circuits are switched It is provided stacked on a layer having a circuit, a first arithmetic circuit, and a second arithmetic circuit.

Description

[Technical Field]

[0001] This specification describes semiconductor devices and the like.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. One aspect of the technical field is semiconductor devices, imaging devices, display devices, light-emitting devices, and energy storage devices. , storage devices, display systems, electronic devices, lighting devices, input devices, input / output devices, and their drives Methods, or methods for manufacturing them, can be given as examples. [Background technology]

[0003] It includes a semiconductor device containing a CPU (Central Processing Unit), etc. Electronic devices that do this are becoming widespread. Such electronic devices process large amounts of data at high speed. Therefore, technological development related to improving the performance of semiconductor devices is active. For example, a GPU (Graphics Processing Unit) A so-called SoC (System on Chip) in which the accelerator and CPU are tightly coupled. There is a change. In semiconductor devices that have become high-performance through SoC integration, heat generation and power consumption increase. This will become a problem.

[0004] In AI (Artificial Intelligence) technology, computational complexity and parameters Because the number of data points becomes enormous, the amount of computation increases. This increase in computation leads to heat generation and power consumption. Because this is a factor that increases computation time, architectures to reduce computation time are being actively proposed. Yes, there is. A typical architecture is the Binary Neural Network. There are BNNs and Ternary Neural Networks (TNNs), and It is particularly effective for reducing the circuit scale and power consumption (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In AI technology, in order to repeat the multiplication and addition operation using weight data and input data a huge number of times it is necessary to hold a large amount of weight data and intermediate data in the memory cell array. Also in AI technology, in addition to the multiplication and addition operation, processing other than the multiplication and addition operation such as activation operation and pooling operation is generally performed. Therefore, in the case of realizing the operation by AI technology in an integrated circuit there is a significant risk of a large increase in the circuit area for arranging the memory cell array and dedicated operation circuits.

[0007] Also, in AI technology, high-speed operation processing is required. When realizing the operation by AI technology in an integrated circuit in the memory cell array, the weight data and intermediate data are read out to the operation circuit via the bit line. In the bit line, the frequency of reading the weight data and intermediate data increases. Therefore, there is a risk that the charge and discharge energy of the bit line increases and the power consumption increases.

[0008] In order to reduce the charge and discharge energy of the bit line, it is effective to shorten the bit line. However, since the operation circuit and the memory cell array are arranged alternately This could lead to a significant increase in the area of ​​the surrounding circuits.

[0009] One aspect of the present invention aims to provide a miniaturized semiconductor device. One aspect of the present invention aims to provide a semiconductor device with reduced power consumption. Alternatively, one aspect of the present invention provides a semiconductor device in which the processing speed of calculations has been improved. One of the objectives is to provide a semiconductor device with a novel configuration.

[0010] Furthermore, one aspect of the present invention does not necessarily have to solve all of the above problems, but at least It would be good if it could solve one of the problems. Also, the description of the above problem is due to the existence of other problems. This does not preclude the following. Other issues are described in the specification, claims, drawings, etc. Therefore, it becomes clear from the description in the specification, claims, drawings, etc. It is possible to identify other issues besides those mentioned above. [Means for solving the problem]

[0011] One aspect of the present invention comprises a plurality of memory circuits, a switching circuit, a first arithmetic circuit, and a second arithmetic circuit. The system has a plurality of memory circuits, each having the function of holding weight data, and a switching circuit. This function switches the conduction state between one of several memory circuits and the first arithmetic circuit. The first arithmetic circuit performs a sum-of-products operation on the input data and the weight data selected by the switching circuit. The first output signal based on the processing is output to the second arithmetic circuit, and multiple memory circuits are switched by a switching circuit, A semiconductor device provided in a layer stacked on a layer having a first arithmetic circuit and a second arithmetic circuit. be.

[0012] One aspect of the present invention comprises a plurality of memory circuits, a switching circuit, a first arithmetic circuit, and a second arithmetic circuit. The system has a plurality of memory circuits, each having the function of holding weight data, and a switching circuit. This function switches the conduction state between one of several memory circuits and the first arithmetic circuit. The first arithmetic circuit performs a sum-of-products operation on the input data and the weight data selected by the switching circuit. The first output signal based on the processing is output to the second arithmetic circuit, and the second arithmetic circuit performs activation function calculations. It has the function of performing calculations, quantization operations, and first pooling operations, and has multiple memory circuits It is provided in a layer stacked on top of a layer having a switching circuit, a first arithmetic circuit, and a second arithmetic circuit. It is a semiconductor device.

[0013] One aspect of the present invention comprises a plurality of memory circuits, a switching circuit, a first arithmetic circuit, and a second arithmetic circuit. It has a third arithmetic circuit and multiple memory circuits, each with the function of holding weight data. The switching circuit has a connection between one of the multiple memory circuits and the first arithmetic circuit, and the conduction state of the two. It has a switching function, and the first arithmetic circuit processes the input data and the weight data selected by the switching circuit. The first output signal, based on the sum-of-accumulate operation of , is output to the second arithmetic circuit, and the second arithmetic circuit then... It has the functionality to perform activation function calculations, quantization calculations, and first pooling calculations. The third arithmetic circuit performs the second pooling operation on the second output signal output by the second arithmetic circuit. The memory circuit has a function and includes a switching circuit, a first arithmetic circuit and a second arithmetic circuit. A semiconductor device provided in a layer stacked on top of another layer is preferred.

[0014] In one embodiment of the present invention, the memory circuit has a first transistor, and the first transistor A semiconductor device is preferred that has a semiconductor layer containing a metal oxide in the channel-forming region.

[0015] In one embodiment of the present invention, the metal oxide comprises In, Ga, and Zn, and is used in semiconductor devices. It is placed there.

[0016] In one embodiment of the present invention, the switching circuit, the first arithmetic circuit, and the second arithmetic circuit are connected to the second transistor The transistor has a semiconductor layer having silicon in the channel formation region. It is a semiconductor device.

[0017] Further aspects of the present invention will be described in the following embodiments, and It is also indicated in the drawings. [Effects of the Invention]

[0018] One aspect of the present invention can provide a miniaturized semiconductor device. Alternatively, the present invention One aspect of the present invention can provide a semiconductor device with reduced power consumption. One embodiment can provide a semiconductor device with improved processing speed. Or, We can provide a semiconductor device with a novel configuration.

[0019] The description of multiple effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention is It is not necessarily required to have all of the effects exemplified. Furthermore, with respect to one embodiment of the present invention, For issues, effects, and novel features other than those mentioned above, please refer to the description and drawings in this specification. It will become clear eventually. [Brief explanation of the drawing]

[0020] [Figure 1] Figures 1A and 1B illustrate an example of the configuration of a semiconductor device. [Figure 2] Figure 2 illustrates an example of a semiconductor device configuration. [Figure 3] Figure 3 illustrates an example of a semiconductor device configuration. [Figure 4] Figures 4A and 4B illustrate an example of the configuration of a semiconductor device. [Figure 5] Figures 5A and 5B illustrate an example of the configuration of a semiconductor device. [Figure 6] Figures 6A, 6B, and 6C illustrate an example of a semiconductor device configuration. [Figure 7] Figures 7A and 7B illustrate an example of the configuration of a semiconductor device. [Figure 8] Figure 8 illustrates an example of a semiconductor device configuration. [Figure 9] Figures 9A and 9B illustrate an example of the configuration of a semiconductor device. [Figure 10] Figure 10 is a diagram illustrating an example of a semiconductor device configuration. [Figure 11] Figure 11 is a diagram illustrating an example of a semiconductor device configuration. [Figure 12] Figure 12 illustrates an example of a semiconductor device configuration. [Figure 13] Figures 13A and 13B illustrate an example of a semiconductor device configuration. [Figure 14] Figures 14A and 14B illustrate an example of the configuration of a semiconductor device. [Figure 15] Figure 15 is a diagram illustrating an example of a semiconductor device configuration. [Figure 16] Figures 16A and 16B illustrate an example of a semiconductor device configuration. [Figure 17] Figure 17 illustrates an example of the configuration of a computing system. [Figure 18] Figure 18 is a diagram illustrating an example of a CPU configuration. [Figure 19] Figures 19A and 19B illustrate an example of a CPU configuration. [Figure 20] Figure 20 shows an example of a CPU configuration. [Figure 21] Figure 21 shows an example of a transistor configuration. [Figure 22] Figures 22A and 22B show examples of transistor configurations. [Figure 23] Figures 23A and 23B illustrate an example of an integrated circuit configuration. [Figure 24] Figures 24A and 24B illustrate examples of applications for integrated circuits. [Figure 25] Figures 25A and 25B illustrate examples of applications for integrated circuits. [Figure 26] Figures 26A, 26B, and 26C illustrate examples of applications for integrated circuits. [Figure 27] Figure 27 illustrates an example of an integrated circuit application. [Modes for carrying out the invention]

[0021] Embodiments of the present invention will be described below. However, one embodiment of the present invention is not limited to the following description. The invention is not defined, and its form and details may vary without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that this can be changed. Therefore, one embodiment of the present invention is The description of the embodiments shown below shall not be interpreted as being limited to the following.

[0022] In this specification, the ordinal numbers "1st," "2nd," and "3rd" refer to the constituent elements. This is added to avoid confusion. Therefore, it does not limit the number of constituent elements. Furthermore, this does not limit the order of the components. Also, for example, the embodiments described herein The component referred to as "first" in one is in another embodiment or in the claims. It may also be the component referred to in "Second" in [the relevant section]. Furthermore, for example, in this specification, etc. In one embodiment, the component referred to as "first" is used in other embodiments, or It may be omitted in the claims.

[0023] In the drawing, elements that are identical or have similar functions, elements made of the same material, or Elements formed simultaneously may be assigned the same reference numeral, and the explanation of this repetition is omitted. It may happen.

[0024] In this specification, for example, the power supply potential VDD may be abbreviated as potential VDD, VDD, etc. This can happen. This is due to other components (e.g., signals, voltages, circuits, elements, electrodes, wiring). The same applies to (etc.).

[0025] Furthermore, when using the same sign for multiple elements, especially when it is necessary to distinguish between them... The symbols are followed by identification codes such as "_1", "_2", "[n]", and "[m,n]". In some cases, it may be written as follows: For example, the second wiring GL may be written as wiring GL[2].

[0026] (Embodiment 1) The configuration and operation of a semiconductor device according to one aspect of the present invention will be described.

[0027] In this specification, a semiconductor device refers to a device that can function by utilizing semiconductor properties. This refers to semiconductor devices in general, including semiconductor elements such as transistors, semiconductor circuits, computing devices, and memory devices. A device is one form of a semiconductor device. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection Devices, lighting devices, electro-optical devices, energy storage devices, memory devices, semiconductor circuits, imaging devices, electronic equipment Some devices, such as those mentioned above, can be said to possess semiconductor devices.

[0028] Figure 1A is a diagram illustrating a semiconductor device 10 according to one aspect of the present invention. Figure B is a diagram illustrating an example of the configuration of the arithmetic block in the semiconductor device 10.

[0029] The semiconductor device 10 is a program called from the host program (kernel, or Also called a kernel program. It has the function of an accelerator that executes (the program). The semiconductor device 10 is used for, for example, parallel processing of matrix operations in graphics processing, neural networks. Parallel processing of multiply-accumulate operations in multinetworks, parallel processing of floating-point operations in scientific and technical computing. It is possible to do things like this.

[0030] As shown in Figure 1A, the semiconductor device 10 has a plurality of arithmetic blocks 20. Block 20 consists of a memory circuit section 30 (also called a memory cell array) and an arithmetic circuit section 4 It has 0. The memory circuit section 30 and the arithmetic circuit section 40 are shown in Figures 1A and 1B. As shown, they are provided in different layers in a direction roughly perpendicular to the xy-plane in the figure (z-direction in Figure 1A). In other words, the memory circuit section 30 and the arithmetic circuit section 40 are stacked and provided in a stacked configuration.

[0031] "Approximately perpendicular" refers to a state where the objects are positioned at an angle of 85 degrees or more and 95 degrees or less. In this specification, the X, Y, and Z directions shown in Figure 1B, etc., are mutually exclusive. These are directions that are perpendicular or intersecting. Also, the X and Y directions are parallel to the substrate surface. The planes are roughly parallel, and the Z-direction is perpendicular or roughly perpendicular to the substrate surface.

[0032] The memory circuit section 30 has a plurality of circuit blocks 31. Each circuit block 31 has a plurality It has a memory circuit 32. Writing and reading data to and from the memory circuit 32 is performed by the drive It is controlled by circuit 12 and drive circuit 13. Drive circuits 12 and 13 are controlled by data It is also called the "official circuit."

[0033] The data stored in the memory circuit 32 is used in the multiply-accumulate operation of the neural network. This is the data corresponding to the weight parameters (weight data). Weight data is digital data. This makes it possible to create a semiconductor device that is resistant to noise and capable of high-speed calculations. The weight data can be analog data.

[0034] The layer having the memory circuit section 30 is such that the memory circuit 32 of the circuit block 31 is, for example, The wiring shown is LBL_1 to LBL_4 (also called local bit lines or read bit lines). The switching circuit 41 of the arithmetic circuit unit 40 is connected via this. The memory circuit unit 30 has The memory circuit 32 has an oxide semiconductor transistor (OS transistor) in the channel formation region. It has a zista.

[0035] The layer having the arithmetic circuit section 40 includes a switching circuit 41, a multiply-accumulate circuit 42, and a dedicated arithmetic circuit. It has an activation function operation circuit 43, a quantization operation circuit 44, and a pre-pooling operation circuit 45. The control and processing of data input and output in the arithmetic circuit section 40 are handled by the control circuit 14 and the processing cycle. It is controlled by path 15. The control circuit 14 and processing circuit 15 are arithmetic control circuit and arithmetic processing circuit. It is also called a path or arithmetic circuit.

[0036] The switching circuit 41 connects the wiring LBL_1 to L that extends from each of the multiple circuit blocks 31. This function selects the potential of BL_4 and transmits it to the wiring GBL (also called the global bit line). It has. The switching circuit 41 is a three-state switch whose output potential state is controlled by a control signal, for example. A buffer can be used. The switching circuit 41 has silicon in the channel formation region. It is preferable to have a transistor (Si transistor) that is configured in this way. This allows for a configuration that enables high-speed switching of connection states.

[0037] Note that wiring LBL_1 to LBL_4 (wiring LBL) stores weight data in memory circuit section 30. This is the wiring for transmitting information from the arithmetic circuit section 40. The weight is transmitted from the memory circuit section 30 to the wiring LBL. To read data at high speed, it is preferable to shorten the wiring LBL. The BL (bulb) is preferably made shorter in order to reduce the energy consumption associated with charging and discharging. The switching circuit 41 is provided with wiring LBL (in the figure, the arrows extending in the z direction) which extends in the z direction. It is preferable to arrange them so that they are close to the ). Arithmetic circuit section 40 and memory circuit section By reducing the physical distance between 30 components, for example, by shortening the wiring distance through stacking, By reducing parasitic capacitance in signal lines, it is possible to lower power consumption.

[0038] The multiply-accumulate circuit 42 has the function of performing calculations such as multiply-accumulate operations. The circuit 42 is sometimes simply called the arithmetic circuit or the first arithmetic circuit. The sum-of-accumulate circuit 42 is The input data received from the control circuit 14 and the weight data given to the wiring GBL, Perform a sum-of-products operation. Input data and weight data are preferably in digital format. The data is less susceptible to noise. Therefore, the multiply-accumulate circuit 42 produces highly accurate calculation results. It is suitable for performing the required arithmetic processing. The multiply-accumulate circuit 42 uses Si transistors. It is preferable that it is composed of ta.

[0039] The activation function calculation circuit 43 processes the data obtained from the sum-of-products operation based on the activation function. It has the function of performing calculations. Examples of activation functions include the sigmoid function and the tanh function. softmax function, ReLU (Rectified Linear Unit) function, Threshold functions and the like can be used. The ReLU function returns "0" if the input value is negative. This function outputs ", and if the input value is greater than or equal to "0", it outputs the input value as is. The activation function calculation circuit 43 is preferably composed of Si transistors.

[0040] The quantization circuit 44 reduces the amount of computation in subsequent calculations by biting the input data. It has the function of performing quantization operations to reduce the width. In sum-of-products operations, repeated operations The bit width increases due to this principle. Therefore, the quantization arithmetic circuit 44 processes the input data bitwise. By rounding the data at the decimal point, the bit width is reduced. The child arithmetic circuit 44 is preferably composed of Si transistors.

[0041] The pre-pooling calculation circuit 45 has the function of performing some of the calculations for the pooling calculation process. For example, in the case of 3x3 pooling, the calculation does not use all the numbers in the 3x3 area, Performing calculations using a subset of numerical values ​​is called prepooling, prepooling calculations, or It is sometimes called the first pooling operation. Or, the pre-pooling operation is pooling. Since it is an arithmetic process that performs a part of the pooling arithmetic process, it is called partial pooling arithmetic process or first part This is sometimes called pooling calculation processing. The pre-pooling calculation circuit 45 is, for example, Max In pooling, the maximum value of a portion of the data, for example, in one dimension, is pre-pooled. This corresponds to the circuit that extracts the output data from circuit 45. Note that this is the pre-pooling calculation circuit 45. It is preferable that it be composed of Si transistors.

[0042] Furthermore, the output data obtained from the pre-pooling calculation circuit 45 is output to the processing circuit 15. For example, by performing calculations in the post-pooling calculation circuit within the processing circuit 15 This can result in data that has undergone arithmetic processing equivalent to pooling. For example, 3 In the case of 3x pooling, a pre-pooling operation is performed using the numerical values ​​of a 3x1 area, and then... Using the data obtained from the repooling calculation, a pooling operation equivalent to 3x3 pooling is performed. Performing arithmetic operations is called post-pooling, post-pooling arithmetic operations, or second pulley It is sometimes called pooling operation processing. Or, post-pooling operation processing is pooling operation processing. Since it is an operation that performs a part of the logic, it is called partial pooling operation or second partial pooling. It is sometimes called a post-pooling arithmetic process. A processing circuit that has a post-pooling arithmetic circuit is an arithmetic circuit Alternatively, it may be called the third arithmetic circuit. Pre-pooling arithmetic circuit and post-pooling Specific examples of arithmetic processing in arithmetic circuits will be discussed later.

[0043] Switching circuit 41, multiply-accumulate operation circuit 42, dedicated operation circuit activation function operation circuit 43, quantum Each of the calculation circuit 44 and the pre-pooling calculation circuit 45 shall be made of Si transistors. Therefore, it can be stacked with OS transistors. In other words, it is composed of OS transistors. The memory circuit section 30 can be made up of an arithmetic circuit section 40 made of Si transistors. They can be stacked. Therefore, without increasing the circuit area, the memory circuit section The area where 30 can be placed can be increased. The area where the memory circuit section 30 is provided is calculated. By placing the circuit section 40 on a substrate, the memory circuit section 30 and the arithmetic circuit section 40 are provided. Compared to the case where they are placed on the same layer, the semiconductor device 10 that functions as an accelerator This increases the memory capacity required for computational processing. With increased memory capacity, external... This reduces the number of data transfers required for arithmetic processing from the storage device to the semiconductor device. Therefore, it is possible to reduce power consumption.

[0044] The memory circuit 32 in the memory circuit section 30 can be configured as a NOSRAM. "NOSRAM (registered trademark)" stands for "Nonvolatile Oxide S NOSRAM is an abbreviation for "electronconductor RAM". NOSRAM has 2 tons of memory cells. It is a transistor type (2T) or 3-transistor type (3T) gain cell, and access transistor The term "memory" refers to memory that uses an OS transistor.

[0045] OS transistors have a current flowing between their source and drain when they are off, i.e., leakage current. The current is extremely small. NOSRAM uses the characteristic of extremely low leakage current to process data. By retaining the generated charge within the memory circuit, it can be used as a non-volatile memory. In particular, NOSRAM allows for reading data without destroying it (non-destructive reading). Because it is possible to extract data, neural networks can repeatedly perform data retrieval operations. It is suitable for parallel processing of sum-of-products operations.

[0046] The memory circuit 32 uses OS transistors such as NOSRAM or DOSRAM. The memory (hereinafter also referred to as OS memory) is preferable. It functions as an oxide semiconductor. Because the band gap of metal oxides is 2.5 eV or more, OS transistors are extremely small. It has a current. For example, when the voltage between the source and drain is 3.5V and the room temperature (25℃) is below. In this case, the off-current per 1 μm of channel width is 1 × 10⁻⁶. -20 Less than A, 1 × 10 -22 A Less than, or 1 × 10⁻⁶ -24 It can be less than A. Therefore, OS memory is O The amount of charge leaking from the holding node via the S transistor is extremely small. Therefore, OS Since the memory can function as a non-volatile memory circuit, the power gate of the semiconductor device 10 This makes it possible to do so.

[0047] High-density integrated semiconductor devices with transistors generate heat through circuit operation. There is a risk of this happening. This heat generation causes the temperature of the transistor to rise, which affects the characteristics of the transistor. The properties can change, which can lead to changes in field-effect mobility and a decrease in operating frequency. Transistors have higher thermal resistance than Si transistors, so the field effect shifts due to temperature changes. Changes in dynamics are less likely to occur, and a decrease in operating frequency is also less likely. Furthermore, OS Trans The DISTRA maintains an exponential relationship between the gate-source voltage and the drain current, even at high temperatures. It is easy to maintain the characteristic of increasing speed. Therefore, by using OS transistors, high It can operate stably in high-temperature environments.

[0048] The metal oxides used in OS transistors are Zn oxide, Zn-Sn oxide, and Ga- Sn oxide, In-Ga oxide, In-Zn oxide, In-M-Zn oxide (where M is Ti Examples include Ga, Y, Zr, La, Ce, Nd, Sn or Hf. In particular, Ga as M. When using metal oxides in OS transistors, adjusting the ratio of elements can lead to electric fields. This is preferable because it allows for the creation of transistors with excellent electrical characteristics such as field effect mobility. In addition, oxides containing indium and zinc, aluminum, gallium, yttrium, and copper Vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, Zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, ta It may contain one or more elements selected from ngsten, magnesium, etc.

[0049] To improve the reliability and electrical characteristics of OS transistors, metal oxides are applied to the semiconductor layer. These are metal oxides having crystalline parts such as CAAC-OS, CAC-OS, and nc-OS. Preferably, CAAC-OS refers to c-axis-aligned crystal CAC-OS is an abbreviation for line oxide semiconductor. Cloud-Aligned Composite Oxide Semiconductor It is an abbreviation for tor. nc-OS stands for nanocrystalline oxide. It is an abbreviation for semiconductor.

[0050] CAAC-OS has c-axis orientation and multiple nanocrystals are linked in the ab-plane direction. It has a crystalline structure that is linked and distorted. Note that distortion refers to the linkage between multiple nanocrystals. Within a region, between a region with a aligned grid arrangement and another region with a aligned grid arrangement, This refers to the part where the direction has changed.

[0051] CAC-OS has the function of conducting electrons (or holes) that act as carriers, and the function of conducting electrons (or holes) that act as carriers It has a function that prevents electrons from flowing. It separates the function that allows electrons to flow from the function that prevents electrons from flowing. This allows both functions to be maximized. In other words, CAC-OS can be used as an OS transition. By using it in the channel formation region of the sta, both high on-current and extremely low off-current can be achieved. This can be achieved.

[0052] Metal oxides have a large band gap, making them difficult to excite electrons, and the effective quality of holes Due to its large size, OS transistors are different from typical Si transistors. Avalanche collapse and the like may be less likely to occur. Therefore, for example, avalanche collapse may be less likely to occur. This can suppress hot carrier degradation, etc. By suppressing hot carrier degradation, high performance can be achieved. OS transistors can be driven with rain voltage.

[0053] OS transistors are storage-type transistors that use electrons as the majority carriers. Compared to inverting transistors with pn junctions (typically Si transistors), the short One of the channel effects is DIBL (Drain-Induced Barrier L). The effect of power (worring) is small. In other words, OS transistors are less powerful than Si transistors. It also has high resistance to short-channel effects.

[0054] OS transistors have high resistance to short-channel effects, therefore OS transistors By using OS transistors, the channel length can be reduced without degrading reliability. The integration density of the circuit can be increased. As the channel length is miniaturized, the drain electric field becomes stronger. However, as shown above, OS transistors exhibit avalanche decay more readily than Si transistors. It is less likely to happen.

[0055] Furthermore, OS transistors have high resistance to short-channel effects, unlike Si transistors. It becomes possible to make the gate insulating film thicker than the star. For example, channel length and channel Even in minute transistors with a width of 50 nm or less, a gate insulating film thickness of about 10 nm is used. It may be possible to implement this. By increasing the thickness of the gate insulating film, parasitic capacitance can be reduced. This allows for improved circuit operation speed. Also, by increasing the thickness of the gate insulating film, the gate Because leakage current through the insulating film is reduced, static current consumption is reduced.

[0056] As described above, the semiconductor device 10 has a memory circuit 32 which is an OS memory, so the power supply Data can be retained even if the pressure supply is stopped. Therefore, the power gate of semiconductor device 10 This enables a significant reduction in power consumption.

[0057] Next, in Figure 2, a arithmetic processing system including a semiconductor device 10 that functions as an AI accelerator is shown. This section describes the block diagram showing the entire Stem 100.

[0058] Figure 2 shows an accelerator unit 1 having multiple semiconductor devices 10 as described in Figures 1A and 1B. In addition to 30, the CPU 110 and bus 120 are also shown. The CPU 110 is the CPU core It has 200 and a backup circuit 222. The accelerator unit 130 has multiple semiconductors In addition to the main body device 10, there is a control unit 131 for controlling the input and output of data between the semiconductor devices 10. do.

[0059] CPU110 is responsible for running the operating system, controlling data, performing various calculations and programming. It has the ability to perform general-purpose processing such as executing RAM. CPU110 has 200 CPU cores. It has. CPU core 200 corresponds to one or more CPU cores. Also CPU 11 0 indicates a backup that can retain data within the CPU core 200 even if the power supply voltage is interrupted. It has a power circuit 222. The power supply voltage is supplied from the power domain. - It can be controlled by electrical disconnection using a switch, etc. The power supply voltage is, It is sometimes referred to as the drive voltage. For example, the backup circuit 222 uses an OS transistor. OS memory having the following characteristics is preferred.

[0060] The backup circuit 222, which is composed of OS transistors, is composed of Si transistors. A CPU core 200 can be stacked with a backup circuit 22. Since the area of ​​2 is smaller than the area of ​​200 CPU cores, C does not increase the circuit area. A backup circuit 222 can be placed on the PU core 200. 222 has the function of holding the data of the registers of CPU core 200. The up circuit 222 is also called the data holding circuit. Note that the backup circuit has an OS transistor. Details of the configuration of the CPU core 200 equipped with the top circuit 222 are also described in Embodiment 3. I will reveal it.

[0061] The control unit 131 has internal memory circuits such as SRAM. The control unit 131 has multiple semiconductors The output data obtained from the conductor device 10 is stored in the memory circuit. The output data MAC is output to multiple semiconductor devices. It is possible to perform parallel computing with a high degree of parallelism using a number of semiconductor devices.

[0062] Bus 120 electrically connects the CPU 110 and the accelerator unit 130. The CPU 110 and the semiconductor device 10 can transmit data via the bus 120. .

[0063] In Figure 3, the arithmetic block 20 shown in Figure 1B includes a memory circuit section 30 and an arithmetic circuit. This is a diagram illustrating a suitable transistor for part 40.

[0064] The memory circuit section 30 has a memory circuit 32. The memory circuit 32 has a transistor 21 The semiconductor layer 22 of the transistor 21 is made of an oxide semiconductor (metal oxide). This allows for the creation of a memory circuit 32 composed of the OS transistors described above.

[0065] The arithmetic circuit section 40 includes a switching circuit 41, a multiply-accumulate circuit 42, and a dedicated arithmetic circuit, which is an activation function. It has an arithmetic circuit 43, a quantization arithmetic circuit 44, and a pre-pooling arithmetic circuit 45. Each circuit of 40 has a transistor 23. The semiconductor layer of transistor 23 24 is made of silicon, and the arithmetic circuit section 40 is composed of the Si transistors mentioned above. These can be the various circuits that it possesses.

[0066] By making the area where the memory circuit section 30 is provided on the same substrate as the arithmetic circuit section 40, Compared to the case where the memory circuit section 30 and the arithmetic circuit section 40 are arranged on the same layer, The memory capacity required for arithmetic processing in the semiconductor device 10, which functions as a cellator, that is, me The number of Mori circuits can be increased. Increased memory capacity allows for the transfer of data from external memory devices to semiconductors. Because the number of data transfers required for calculation processing to the device can be reduced, it consumes less power. It is possible to achieve transformation.

[0067] Figure 4A illustrates the data input and output of each circuit in a semiconductor device 10 according to one aspect of the present invention. This is a block diagram for the purpose of [doing something]. In Figure 4A, the switching circuit 41, the multiply-accumulate circuit 42, and the dedicated calculation circuit are shown. The circuits are activation function operation circuit 43, quantization operation circuit 44, and prepooling operation circuit. Figure 45 is shown.

[0068] The switching circuit 41 controls the conduction state between one of the memory circuits 32 and the sum-of-accumulate circuit 42. It has a switching function. For example, the switching circuit 41 is the circuit block 31 of the memory circuit section 30. Weight data W1 is output to wiring GBL from the data held in memory circuit 32 located there. To W N (N is a natural number greater than or equal to 2) is selected. Then the switching circuit 41 selects the weight data The weight data W SEL The output is then sent to the multiply-accumulate circuit 42 via wiring GBL.

[0069] The sum-of-products circuit 42 calculates the sum of products of the input data and the weight data selected by the switching circuit 41. The data (output signal) based on the calculation process is output to the dedicated calculation circuit 46. For example, the sum-of-accumulate calculation circuit Route 42 is the weight data W SEL And input data A is input from control circuit 14. IN Based on A sum-of-products operation is performed. The data MAC obtained by this sum-of-products operation is sent to the dedicated arithmetic circuit 46. The output is sent to a certain activation function arithmetic circuit 43.

[0070] The dedicated arithmetic circuit 46 performs multiply-accumulate operations in the neural network used for convolution operations. Calculation processes, such as calculations based on activation functions, calculations for quantization, pulleys Calculation processing for calculation processing, or calculation processing for normalization (normalization) This is a circuit for performing operations such as (n). The dedicated arithmetic circuit 46 is an arithmetic circuit, or a second arithmetic circuit. There are cases like this. For example, the dedicated arithmetic circuit 46 is an activation function arithmetic circuit 43, quantization function The diagram shows a configuration having an arithmetic circuit 44 and a pre-pooling arithmetic circuit 45, but other It may have the following configuration:

[0071] The activation function calculation circuit 43 performs calculations based on the activation function on the input data MAC. The processing is performed and the data obtained from the activation function-based calculation is output as FUNC. This is the circuit. The data FUNC is output to the quantization arithmetic circuit 44 located in the dedicated arithmetic circuit 46. It can be done.

[0072] The quantization arithmetic circuit 44 performs quantization processing on the input data FUNC. This is a circuit for outputting data as QUA. The quantization calculation process is performed on the input data. To adjust the bit width, bit shifts are performed on the input data, and the position of the decimal point is adjusted. Round the data. Data QUA is a pre-pooling calculation circuit located in the dedicated calculation circuit 46. Output to 45.

[0073] The pre-pooling calculation circuit 45 performs pooling calculations on the input data QUA. By performing some calculations, the data PPD with pre-pooling calculations is output. This is a special circuit. By having a pre-pooling calculation circuit 45, the dedicated calculation circuit 46 does not pool. It can perform part of the ring calculation process. The data PPD is as shown in Figure 4B. The output is sent to the post-pooling calculation circuit 47 of the processing circuit 15. The processing circuit 15 having the arithmetic circuit 47 may be called an arithmetic circuit or a third arithmetic circuit. ru.

[0074] The post-pooling arithmetic circuit 47 performs arithmetic processing on the input data PPD, This is a circuit for outputting data PD, which has undergone pooling calculation processing on data QUA. The processing circuit 15 has a post-pooling calculation circuit 47, which performs pooling calculation processing. Compared to performing all the calculations, this allows for space savings. The data PD controls Input data A in circuit 14 IN It is used as such.

[0075] Figure 5A shows the circuit block of the memory circuit section 30 in the semiconductor device 10 of the present invention. This figure illustrates an example of a circuit configuration applicable to 31. In Figure 5A, M rows and N columns (M, N (where is a natural number greater than or equal to 2) Word lines for writing, arranged in the matrix direction WWL_1 to WWL_ M, read word lines RWL_1 to RWL_M, write bit lines WBL_1 to WBL_ N and the wiring LBL_1 to LBL_N are shown. Also, each word line and bit are illustrated. The diagram shows a memory circuit 32 connected to a wire.

[0076] Figure 5B is a diagram illustrating an example of a circuit configuration applicable to the memory circuit 32. Circuit 32 consists of transistor 61, transistor 62, transistor 63, and capacitive element 64. It has a capacitor (also called a capacitor).

[0077] Either the source or drain of transistor 61 is connected to the write bit line WBL. The gate of transistor 61 is connected to the write word line WWL. The source or drain of transistor 61 is connected to one electrode of capacitive element 64 and the transistor. It is connected to the gate of transistor 62. Either the source or drain of transistor 62 and the capacitance. The other electrode of element 64 is connected to a wire that provides a fixed potential, such as ground potential. The other end of the source or drain of transistor 62 is the source or drain of transistor 63. It is connected to one side of the rain. The gate of transistor 63 is connected to the read word line RWL. The source or drain of transistor 63 is connected to wiring LBL. Wiring LBL is connected to wiring GBL via switching circuit 41. Wiring LBL is connected to the arithmetic circuit The Si transistor of part 40 is provided extending in a direction approximately perpendicular to the substrate surface on which the Si transistor is provided. It is connected to the switching circuit 41 via the wiring.

[0078] The circuit configuration of the memory circuit 32 shown in Figure 5B is a 3-transistor type (3T) gain cell N This corresponds to OSRAM. Transistors 61 through 63 are OS transistors. Yes. In an OS transistor, the current flowing between the source and drain when it is off is called the reed. The leakage current is extremely low. NOSRAM uses the characteristic of extremely low leakage current to process data. By holding a corresponding charge within the memory circuit, it can be used as a non-volatile memory. ru.

[0079] The circuit configuration applicable to the memory circuit 32 in Figure 5A is limited to the 3T type NOSRAM in Figure 5B. No. For example, a circuit equivalent to the DOSRAM shown in Figure 6A would also be acceptable. In Figure 6A, A memory circuit 32A having a transistor 61A and a capacitive element 64A is shown. The transistor 61A is an OS transistor. The memory circuit 32A has bit lines BL and An example of connection to the code line WL and the back gate line BGL is illustrated.

[0080] The circuit configuration applicable to the memory circuit 32 in Figure 5A is the 2T type NOSR shown in Figure 6B. A circuit equivalent to AM may also be used. In Figure 6B, transistors 61B and 62B A memory circuit 32B having a transistor 61B and a capacitance element 64B is shown. Transistor 62B is an OS transistor. Transistors 61B and Transistor The 62B can be an OS transistor in which semiconductor layers are arranged on different layers, or on the same layer. An OS transistor on which a semiconductor layer is placed may also be used. The memory circuit 32B is for writing bits. Line WBL, wiring LBL which functions as a read bit line, write word line WWL, read An example of connecting to the word line RWL, source line SL, and backgate line BGL is illustrated. It is.

[0081] The circuit configuration applicable to the memory circuit 32 in Figure 5A is the 3T type NOSR shown in Figure 6C. A circuit combining AM (Automatic Memory) is also acceptable. Figure 6C shows a memory capable of holding data with different logic. The diagram shows a memory circuit 32C having circuit 32_P and memory circuit 32_N. In 6C, transistors 61_P, 62_P, 63_P and A memory circuit 32_P having a capacitive element 64_P, and a transistor 61_N, a transistor Memory circuit 32_N having 62_N, transistor 63_N and capacitive element 64_N The diagram shows the transistors of memory circuit 32_P and memory circuit 32_N. The transistor is an OS transistor. Memory circuits 32_P and 32_N have Each transistor may be an OS transistor in which semiconductor layers are arranged on different layers, or the same An OS transistor with a semiconductor layer arranged in layers may also be used. The memory circuit 32C is a writing transistor. Bit line WBL_P, wiring LBL_P, write bit line WBL_N, wiring LBL_N, write An example of being connected to the word line WWL for writing and the word line RWL for reading is illustrated. The memory circuit 32C can hold data with different logics and read data with different logics to the wiring LBL_P and also the wiring LBL_N.

[0082] In the configuration of FIG. 6C, an exclusive OR circuit (XOR circuit) may be provided so that data corresponding to the multiplication of the data held in the memory circuit 32_P and the memory circuit 32_N is output to the wiring LBL. With such a configuration, the operation corresponding to the multiplication in the product-sum operation circuit 42 can be omitted, and thus power consumption can be reduced.

[0083] FIG. 7A is a diagram for explaining the switching circuit 41. In FIG. 7A, it is assumed that weight data W1 to W6 are read from a certain memory circuit 32 in the circuit block 31 to the wirings LBL_1 to LBL_6. Also, the weight data selected from the weight data W1 to W6 by the switching circuit 41 and given to the wiring GBL is described as weight data W <00> It is assumed that the input data A is given to the product-sum operation circuit 42, and data MAC corresponding to the product-sum operation data is obtained. SEL IN

[0084] The wiring LBL that extends in the vertical direction connecting the upper layer and the lower layer in the wirings LBL_1 to LBL_6 is shorter than the wiring extending in the horizontal direction. Therefore, the parasitic capacitance of the wirings LBL_1 to LBL_6 can be reduced, the charge required for charging and discharging the wiring can be reduced, and power consumption can be reduced and the P operation efficiency can be improved. Also, from the memory circuit 32 to the wirings LBL_1 to LBL ​​​​​​​​​ This allows for faster reading to _6.

[0085] Through the wiring GBL, the weight data W is processed in the sum-of-products operation circuit 42. SEL Perform calculations using It is possible to do so. Weight data W SEL This is connected to multiple multiply-accumulate circuits 42 via wiring GBL. The configuration can be set up to perform calculations using the same weight data. It is suitable for computational processing of embedded neural networks.

[0086] Figure 7B shows an example of a circuit configuration applicable to the switching circuit 41 shown in Figure 7A. The three-state buffer shown in the diagram controls the potential of wiring LBL according to the control signal EN, and wiring G It has the function of amplifying and transmitting to BL. The switching circuit 41 can be considered as a multiplexer. It can. It has the function of selecting one from multiple input signals.

[0087] In Figure 7A, the switching circuit 41 selects one wiring from multiple wiring LBLs and weights data TaW SEL The diagram illustrates a configuration for supplying the wiring GBL, but other configurations are also possible. For example, A configuration with multiple switching circuits as alternative circuits is also possible. Also, in Figure 7A, each memory circuit 32 holds 1 bit of data (i.e., data of '1' or '0'), and uses that data Although it was described as a configuration that performs calculations, it is a configuration that performs calculations using multi-bit data. One aspect of the present invention is also applicable to the case of multi-bit (e.g., n-bit) data. Using a switching circuit 41 connected to wiring LBL_1 to LBL_n in a number corresponding to the number of tents Therefore, a configuration that selects multi-bit weight data to be provided to the wiring GBL should be used.

[0088] If the memory circuit section 30 and the arithmetic circuit section 40 are on separate chips, the bus width will vary according to the number of pins on the chip. This is limited. On the other hand, as in the configuration of one aspect of the present invention, the memory circuit section 30 and the arithmetic circuit section 4 In a configuration where 0 and are stacked, the arrangement of data necessary for calculation processing is according to the openings where wiring LBL is provided. Because the number of columns can be increased, more efficient calculations can be performed.

[0089] Figure 8 shows a timing chart to illustrate the operation of each configuration described in Figure 7A. The sum-of-accumulate circuit 42 performs a toggle operation of the clock signal CLK (for example, between time T0 and T6). The calculation is performed accordingly. By configuring the clock signal CLK to have a higher frequency, the calculation is performed. Processing speed can be increased.

[0090] Input Data A IN When switching the weight data at high speed according to the clock signal CLK, The data for the supplied wiring GBL needs to be switched at high speed.

[0091] In one embodiment of the present invention, the switching circuit 41 selects the wiring LBL from wiring GBL. The system should be configured to pre-load the data into wiring LBL_1 through LBL_6. Therefore, the data of the wiring GBL that provides weight data can be switched at high speed. For example, At time T0, the weight data W1 is read to wiring LBL_1, and at time T1, the switching circuit 41 is switched off. By changing the configuration, it is possible to output weight data W1 from wiring LBL_1 to wiring GBL. It is possible. At times T1 to T6, the weight data W1 to W6 can be read from the wiring LBL and Weight data W in wiring GBL SEL By selecting and setting different times, the clock signal Weighted data W corresponding to CLK number SEL The configuration can be set up to allow switching between these two states.

[0092] Figure 9A shows a specific example of the configuration of the sum-of-accumulate circuit 42. In Figure 9A, 8 bits weight Configuration of the sum-of-accumulate circuit 42 that can perform sum-of-accumulate operations on data and 8-bit input data. An example is illustrated. In Figure 9A, the multiplier circuit 51, the adder circuit 52, and the register 53 are As shown in the diagram, the 16-bit data multiplied by the multiplication circuit 51 is input to the adder circuit 52. The output of the adder circuit 52 is held in the register 53, and the data to be multiplied by the multiplier circuit 51 is... The sum-of-accumulate operation is performed by adding the values ​​in the adder circuit 52. Register 53 is a clock signal. It is controlled by the CLK signal and the reset signal reset_B. Note that in the diagram, it is labeled "17+α". In this case, "α" represents the carry-over that occurs when multiplying data is added. By adopting this configuration, the weight data W SEL and input data A IN Data equivalent to a sum-of-products operation You can obtain a MAC.

[0093] Furthermore, although Figure 9A describes a configuration that performs arithmetic processing using 8 bits of data, 1 One aspect of the present invention is also applicable to configurations using bit data. Figure shows the configuration. As shown in Figure 9A, this is illustrated in Figure 9B. In the case of 1-bit data, as shown in Figure 9B, You just need to perform calculations according to the number of items.

[0094] Figure 10 shows an example of the configuration of the activation function arithmetic circuit 43 described above. In the activation function calculation circuit 43 shown in the figure, an activation function based on the ReLU function is calculated as an example. This is a circuit that has the function of performing calculations.

[0095] The activation function calculation circuit 43 shown in Figure 10 has multiple multiplexers 54. For example, the lutiplexer 54 receives 8-bit data MAC[0] through MAC[7] as input. The data 0 is input to the multiplexer 54. The multiplexer 54 is The most significant bit of the data MAC, which is the data MAC[7], determines the data MAC[0] to MAC[7] or data 0 is output as data FUNC[0] or FUNC[7]. If the data MAC is a signed integer, then if the most significant bit of the data MAC is 0, it is a positive value. Since 1 represents a negative value, the activation function calculation circuit 43 uses the ReLU function for activation. Function operations can be performed.

[0096] Figure 11 shows an example of the configuration of the pre-pooling calculation circuit 45 described above. The pre-pooling calculation circuit 45 shown in Figure 1 is based on max pooling as an example. This is a circuit that has the function of performing calculations for pre-pooling operations.

[0097] The pre-pooling calculation circuit 45 shown in Figure 11 uses a comparison circuit 55 and a register 56. It has. The comparison circuit 55 takes the data that will be the initial value, or the data input from register 56. The data QUA output from the quantization arithmetic circuit 44 is input. Comparison circuit 5 Step 5 compares the two input data and assigns the data with the larger value as data QUA[C]. Output to register 56. Data QUA[C] is held in register 56. The data QUA[C] is the output signal of the pre-pooling calculation circuit 45, data PPD, Alternatively, the data QUA[MAX] input to the comparison circuit 55 becomes the data.

[0098] The operation of the pre-pooling calculation circuit 45 will be explained with reference to Figure 12. , as data QUA output from the quantization arithmetic circuit 44, data QUA[1], data QUA[2] through data QUA[N] are input sequentially in response to changes in the clock signal CLK. Assume that this will be done. The comparison circuit 55 will use the data input as the initial value as data QUA[0] do.

[0099] During period P1, data QUA[0] and data QUA[1] are input to the comparator circuit 55. If data QUA[1] is greater than data QUA[0], then data QUA[1] This is the output data of the comparison circuit 55, that is, the data QUA[C], which is stored in register 56. ru.

[0100] Next, during period P2, data QUA[2] is compared in accordance with the change in the clock signal CLK. The input is given to circuit 55. The comparison circuit 55 also receives the data held in register 56 for a period P1. Data QUA[1] is input. If data QUA[2] is greater than data QUA[1] In total, data QUA[2] is the output data of the comparison circuit 55, i.e., data QUA[C] It is stored in register 56.

[0101] In the comparison circuit 55, the magnitude of the data QUA values ​​that are input in order is compared, and the larger data By storing the data in register 56, register 56 contains the input data QUA. The largest data QUA[MAX] will be retained. In period PN, data Q UA[N] is input to the comparator circuit 55. The comparator circuit 55 also receives a period P in register 56. The data QUA[MAX] held up to (N-1) is entered. If X is greater than data QUA[N], then data QUA[MAX] is the output of comparator circuit 55. The force data, or data QUA[C], is stored in register 56. The data QUA[MAX] held in 56 is output as data PPD.

[0102] The operation described in Figure 12 is performed using multiple dedicated calculation circuits, and the resulting data PPD is compared again. By doing so, data PD can be obtained through pooling operations.

[0103] For example, as shown in the configuration example in Figure 13A, it is equipped with dedicated calculation circuits 46_1 to 46_3, 3× This explanation will be given for the case where 3-pooling calculations are performed. The quantization arithmetic circuit 44 divides and processes the data QUA[1] to [9], and the prepulley The data PPD[1] to [3] can be obtained using the arithmetic circuit 45. The ring calculation circuit 45 takes the maximum value of the data in one dimension from the pre-pooling calculation circuit 45. The output data can be extracted as PPD. Data PPD[1] to [3] are The data PD is then compared in the post-pooling calculation circuit 47 in the processing circuit 15 to obtain the data PD. This is possible. The post-pooling arithmetic circuit 47 compares the magnitude of the input data PPD value. It has the function of a comparison circuit. In other words, the post-pooling arithmetic circuit 47 is 3 x 3. The output data PD is the maximum value of the two-dimensional data, i.e., a 3x3 max pooling. It can be extracted as data.

[0104] The example in Figure 13A specifically involves the operation illustrated in Figure 13B, which results in the data QUA[1] The data up to [9] is divided and processed, and the pre-pooling calculation circuit 45 processes the data PPD [1] to [3] ] can be obtained. For example, in the dedicated arithmetic circuit 46_1, data QUA[1] to [3 The data PPD[1] is obtained by comparing ]. In addition, the dedicated arithmetic circuit 46_2 obtains the data QU The data PPD[2] is obtained by comparing A[4] through [6]. Also, the dedicated arithmetic circuit 46_3 Then, data QUA[7] to [9] are compared to obtain data PPD[3]. By doing so, data PPD is obtained using different dedicated arithmetic circuits, with fewer clock cycles. Data PPD can be obtained.

[0105] For example, as shown in Figure 14A, the data PPD is obtained by the pre-pooling calculation circuit 45. Without any need to, data QUA[1] to [9] is obtained from multiple quantization circuits 44_1 to 44_9. When the output of ] to the post-pooling calculation circuit 47 is used to obtain data PD, the distribution that transmits the data The number of wires increases. Therefore, it becomes difficult to miniaturize and reduce the power consumption of the semiconductor device 10. There are cases where this happens.

[0106] Also, as shown in Figure 14B, for example, input to one pre-pooling calculation circuit 45 When obtaining data PD by comparing data QUA[1] to [9], the number of data QUAs Because it takes time to obtain the data PD accordingly, the high speed of the calculation processing in the semiconductor device 10 There are cases where the transformation becomes difficult.

[0107] In the configuration of the semiconductor device 10 in this embodiment, each of the neural networks When performing calculations using a dedicated arithmetic circuit, multiple data sets are used, such as in pooling calculations. In a configuration that performs calculations, a configuration that performs distributed calculations can be used. Because the wiring connecting the arithmetic circuit and the multiply-accumulate circuit can be shortened, a dedicated arithmetic circuit can be placed. This allows for minimizing the increase in area required. Furthermore, multiple memory circuits can be placed within the dedicated arithmetic circuit. Since it can be configured in this way, the area where the memory circuit can be arranged can be increased. As a result, a huge amount of weight data can be held in the memory circuit section, and the number of times of transferring weight data from an external memory circuit can be reduced, so that power consumption can be reduced.

[0108] In FIG. 15, a configuration example of the memory circuit section 30 provided by being stacked on the arithmetic circuit section 40, which was described in FIGS. 1A and 1B, and its peripheral circuit is illustrated. Specifically, in FIG. 15, a drive circuit 12, a drive circuit 13, a control circuit 14, a processing circuit 15, a switching circuit 41, a multiply-accumulate arithmetic circuit 42, an activation function arithmetic circuit 43, a quantization arithmetic circuit 44, and a pre-pulling arithmetic circuit 45 are illustrated. Further, in FIG. 15, a post-pulling arithmetic circuit 47 in the processing circuit 15 is illustrated.

[0109] Although not illustrated in FIG. 15, for each circuit in FIG. 15, a control signal, input data, and output data for controlling each circuit are configured to be input and output between the external circuit.

[0110] <000^920>

[0111] FIG. 16A is a diagram in which blocks for controlling the memory circuit section 30 are extracted for each configuration illustrated in FIG. 15. In FIG. 16A, in addition to the memory circuit 32 included in the circuit block 31 in the memory circuit section 30, the drive circuit 12 and the drive circuit 13 are extracted and illustrated.

[0112] The drive circuit 12 and the drive circuit 13 process an input signal from the outside and generate a signal for writing weight data into the memory circuit and a signal for reading weight data from the memory circuit. The generated signal is given to the memory circuit via wiring.

[0113] Figure 16B shows the blocks that control the arithmetic circuit section 40 for each configuration shown in Figure 15. This is an extracted diagram. In Figure 16B, the switching circuit 41 and the sum-of-accumulate circuit of the arithmetic circuit section 40 are shown. Path 42, activation function operation circuit 43, quantization operation circuit 44 and pre-pooling operation circuit 4 In addition to 5, there is a control circuit 14, a processing circuit 15, and a post-pooling function within the processing circuit 15. The calculation circuit 47 is shown in the diagram.

[0113] The control circuit 14 receives input data A IN It generates and outputs to the sum-of-accumulate circuit 42. Control circuit 14 outputs a control signal to control the switching circuit 41. The switching circuit 41 is controlled by the memory circuit 32 Select the weight data read from the weight data W SEL As a result, the sum-of-accumulate circuit 42 Output. Dedicated arithmetic circuits: activation function arithmetic circuit 43, quantization arithmetic circuit 44 and The repooling arithmetic circuit 45 performs calculations on the data MAC generated by the sum-of-accumulate arithmetic circuit 42. The data PPD, which has undergone pre-pooling calculation processing, is then sent to the post-processing circuit 15. Output to the pooling calculation circuit 47. (Post-pooling calculation circuit 47 located within the processing circuit 15) The pooling-processed data PD is output to the control circuit 14, and the control circuit 14 inputs Force Data A IN The following is generated. The generated data is re-input to the arithmetic circuit unit 40.

[0114] In the semiconductor device 10, the control circuit 14 processes the data and then sends it back to the calculation circuit unit 40. It can be output as input data. Therefore, data in the middle of a calculation can be output outside the semiconductor device 10. It is possible to perform calculations without reading to main memory or other locations. In case 0, the electrical connection between the memory circuit section and the arithmetic circuit section is made by an opening in an insulating film or the like. Since it can be performed via the wiring of the section, it is possible to increase the parallel number by increasing the number of wirings. Therefore, in the semiconductor device 10, parallel calculation with a bit number equal to or greater than the data bus width of the CPU 110 becomes possible. In addition to the multiply-accumulate circuit, a circuit for performing dedicated arithmetic processing such as activation function arithmetic processing is provided in a stacked manner with the memory circuit, so that the area where the memory circuit can be arranged can be increased. As a result, a huge number of weight data can be held in the memory circuit section, and the number of times of transferring weight data from an external memory circuit can be reduced, so that power consumption can be reduced.

[0115] In one aspect of the present invention, a configuration in which one arithmetic processing such as pooling arithmetic processing is distributed and performed at a plurality of locations can shorten the wiring connecting the dedicated arithmetic circuit and the multiply-accumulate circuit. Therefore, the configuration in which arithmetic processing is distributed and performed at a plurality of locations is effective in suppressing an increase in the area for arranging the dedicated arithmetic circuit. The said configuration is a configuration in which the memory circuit section and the arithmetic circuit section illustrated in FIG. 1 are not stacked, for example, in the configurations illustrated in FIGS. 15, 16A, and 16B, the memory circuit section 30, the arithmetic circuit section 40, and peripheral circuits such as the drive circuits 12 and 13, the control circuit 14, and the processing circuit 15 are configured with Si transistors, and even when the memory circuit section 30 and the arithmetic circuit section 40 are not stacked. is effective.

[0116] As described above, one aspect of the present invention can provide a semiconductor device that functions as an accelerator and is miniaturized. Or, one aspect of the present invention can provide a semiconductor device that functions as an accelerator and is reduced in power consumption. Or, ​​​​​​​​​​We can provide a semiconductor device with a novel configuration that functions as an accelerator.

[0117] (Embodiment 2) In this embodiment, the program executed by the CPU 110 described in the above embodiment is executed An example of operation when a part of the calculation is performed by the accelerator described as semiconductor device 10. Explain.

[0118] Figure 17 shows the case where part of the calculations of a program executed on the CPU are performed on an accelerator. This is a diagram illustrating an example of its operation.

[0119] The host program is executed on the CPU (host program execution; step S1). .

[0120] The CPU memorizes the data area required when performing calculations using the accelerator. When an instruction to allocate memory in the recirculation section is confirmed (memory allocation instruction; step S2), the data A memory area is allocated in the memory circuit section (memory allocation; step S3).

[0121] Next, the CPU receives input data from the main memory or external storage device to the memory circuit section. The weight data is transmitted (data transmission; step S4). The memory circuit section transmits the weight The data is received and the weight data is stored in the area reserved in step S3 (data Received; step S5).

[0122] The CPU, upon confirming the instruction to start the kernel program (kernel program) Startup; step S6), the accelerator starts executing the kernel program ( Start of calculation; step S7).

[0123] Immediately after the accelerator starts executing the kernel program, the CPU is in a state where it is performing calculations. You may switch from the state to the PG (Power Gating) state (PG state transition; step). S8). In that case, just before the accelerator finishes executing the kernel program, CP U is switched from the PG state to the state for performing calculations (PG state terminated; step S9). During the period from step S8 to step S9, the CPU is put into a PG state, thereby reducing the computational processing The entire system can suppress power consumption and heat generation.

[0124] When the accelerator finishes executing the kernel program, the output data is from the accelerator. The calculation result is stored in the memory unit that holds the calculation result (completion complete; step S10).

[0125] After the kernel program has finished executing, the CPU will retrieve the output data stored in memory. When a command to send data to main memory or external storage device is confirmed (data transmission request) Est; step S11) Send the above output data to main memory or external storage device The data is transmitted and stored in main memory or external storage device (data transmission; step S12) ).

[0126] By repeating the operations from step S1 to step S12 above, the CPU and While suppressing the power consumption and heat generation of the accelerator, a portion of the calculations performed by the CPU is performed by It can be executed by an accelerator. One embodiment of the present invention is a semiconductor device that is a non-von Neumann type. - A von Neumann architecture has a structure in which power consumption increases as processing speed increases. Compared to Kucha, it can perform calculations with extremely low power consumption.

[0127] This embodiment can be appropriately combined with descriptions of other embodiments.

[0128] (Embodiment 3) In this embodiment, an example of a CPU having a CPU core capable of power gating is described. I will explain.

[0129] Figure 18 shows an example configuration of CPU 110. CPU 110 consists of CPU cores (CPU Co re)200, L1 (Level 1) Cache Memory Device (L1 Cache)202, L 2 Cache memory device (L2 Cache) 203, Bus interface section (Bus It has an interface (I / F) 205, power switches 210-212, and a level shifter (LS) 214. The CPU core 200 has 220 flip-flops.

[0130] The bus interface unit 205 connects the CPU core 200 and L1 cache memory. The device 202 and the L2 cache memory device 203 are interconnected.

[0131] Interrupt signals received from an external source, issued by CPU110 In response to signals such as SLEEP1, the PMU193 receives the clock signal GCLK1 and various P The generation of the G (power gating) control signal (PG control signal) The clock signal GCLK1 and PG control signal are input to the CPU 110. This unit controls power switches 210-212 and flip-flop 220.

[0132] Power switches 210 and 211 are connected to a virtual power line V_VDD (hereinafter referred to as the V_VDD line). The power switch 212 controls the supply of voltages VDDD and VDD1 to the following: Controls the supply of voltage VDDH to the bell shifter (LS) 214. CPU110 and PM The voltage VSSS is input to U193 without going through the power switch. The voltage VDDD is input without going through the power switch.

[0133] Voltages VDDD and VDD1 are drive voltages for CMOS circuits. Voltage VDD1 is equal to voltage VD It is lower than DD and is the drive voltage in sleep mode. Voltage VDDH is for OS transistors. This is the drive voltage, and it is higher than the voltage VDDD.

[0134] L1 cache memory device 202, L2 cache memory device 203, bus interface Each face section 205 has at least one power-gated power domain It has. Power-gated power domains have one or more power switches. These power switches are provided. These power switches are controlled by a PG control signal.

[0135] Flip-flop 220 is used as a register. Flip-flop 220 has a A backup circuit is provided. The flip-flop 220 will be described below.

[0136] Figure 19A shows an example of the circuit configuration of a flip-flop 220. The flip-flop 220 is a scan flip-flop. 1. It has a backup circuit 222.

[0137] Scan flip-flop 221 controls nodes D1, Q1, SD, SE, RT, CK, and It has a lock buffer circuit 221A.

[0138] Node D1 is a data input node, and node Q1 is a data output node. Yes, node SD is the input node for scan test data. Node SE is the signal SC. E is an input node. Node CK is an input node for the clock signal GCLK1. The clock signal GCLK1 is input to the clock buffer circuit 221A. The analog switch of rop 221 is located at node CK1 of the clock buffer circuit 221A, C It is connected to KB1. Node RT is the input node for the reset signal. It is.

[0139] The signal SCE is the scan enable signal and is generated by PMU193. 93 generates signals BK and RC. Level shifter 214 shifts the BK and RC signals to a higher level. Then, signals BKH and RCH are generated. Signal BK is the backup signal, and signal RC is the recovery signal. It's a signal.

[0140] The circuit configuration of scan flip-flop 221 is not limited to Figure 19. A typical circuit You can apply the flip-flops provided in the library.

[0141] The backup circuit 222 consists of nodes SD_IN, SN11, and transistors M11~M1 3. It has a capacitive element C11.

[0142] Node SD_IN is the input node for scan test data, and scan flip It is connected to node Q1 of rop 221. Node SN11 is connected to backup circuit 222. This is a holding node. Capacitor element C11 is a holding capacitance for holding the voltage of node SN11. be.

[0143] Transistor M11 controls the conduction state between node Q1 and node SN11. Transistor M12 controls the conduction state between node SN11 and node SD. Transistor M13 This controls the conduction state between node SD_IN and node SD. Transistors M11, M13 The on / off state of is controlled by signal BKH, and the on / off state of transistor M12 is controlled by signal RCH. It will be done.

[0144] Transistors M11 to M13 are the same as transistor 61 in the memory circuit 32 described above. Similar to transistor 63, it is an OS transistor. Transistors M11-M13 are back gates. The diagram shows a configuration having the following characteristics. The back gates of transistors M11 to M13 are connected to the voltage VB It is connected to the power line that supplies G1.

[0145] It is preferable that at least transistors M11 and M12 are OS transistors. Due to the OS transistor's characteristic of extremely low current, the voltage at node SN11 Because it can suppress degradation and consumes almost no power to retain data, The quap-up circuit 222 has non-volatile properties. Data is collected by charging and discharging the capacitive element C11. Because it can be rewritten, the backup circuit 222 has no limitations on the number of rewrites in principle, and is low energy Data can be written to and read using energy.

[0146] It is very important that all transistors in backup circuit 222 are OS transistors. Preferred. As shown in Figure 19B, a scan flip consisting of a silicon CMOS circuit. A backup circuit 222 can be stacked on top of the flop 221.

[0147] The backup circuit 222 has a significantly smaller number of elements compared to the scan flip-flop 221. Since there are few, scan flip-flops 222 are used to stack backup circuits 222. No changes to the circuit configuration and layout of 1 are necessary. In other words, the backup circuit 222 is This is a highly versatile backup circuit. Also, the scan flip-flop 221 is Since a backup circuit 222 can be provided within the formed region, Even with the incorporation of circuit 222, the area overhead of flip-flop 220 remains zero. Therefore, a backup circuit 222 is provided for the flip-flop 220. This enables power gating of 200 CPU cores. Because it requires less energy, it enables highly efficient power gating of the 200 CPU cores. This is possible.

[0148] By providing the backup circuit 222, the parasitic capacitance of transistor M11 is reduced. This will be added to node Q1, but it will be a parasitic capacitance due to the logic circuit connected to node Q1. Since it is smaller in comparison, it does not affect the operation of scan flip-flop 221. In other words, Even with the backup circuit 222, the performance of the flip-flop 220 does not substantially decrease. stomach.

[0149] For example, a low-power state for CPU core 200 is a clock gating state, power It is possible to set the gated state and the hibernation state. The PMU193 is an interrupt signal Based on signals such as SLEEP1, the low-power mode of CPU core 200 is selected. When transitioning from the normal operating state to the clock gating state, the PMU193 clock Stop generating the GCLK1 signal.

[0150] For example, when transitioning from normal operation to hibernation, the PMU193 will check the voltage and / Alternatively, frequency scaling can be performed. For example, when performing voltage scaling, PMU193 To input voltage VDD1 to the CPU core 200, the power switch 210 is turned off. Turn on power switch 211. Voltage VDD1 is set to scan flip-flop 22 This is the voltage that does not cause data loss. When frequency scaling is performed, the PMU193 is The frequency of the clock signal GCLK1 is reduced.

[0151] When transitioning CPU core 200 from normal operation to power gating state, The data from flip-flop 221 is backed up to backup circuit 222. The operation will be performed. The 200 CPU cores will be returned from power gating to normal operation. In that case, the data from the backup circuit 222 is recovered to the scan flip-flop 221. The action is performed.

[0152] Figure 20 shows an example of the power gating sequence for CPU core 200. In 20, t1 to t7 represent time. Signals PSE0 to PSE2 are power switches. This is a control signal for switches 210-212, generated by PMU193. Signal PSE0 is “H When " / "L", power switch 210 is on / off. Signals PSE1, PSE2 The same applies to this matter.

[0153] Before time t1, it was in normal operation state. Switch 210 is ON, and the voltage VDDD is input to CPU core 200. The flip-flop 221 operates normally. At this time, the level shifter 214 operates. Since there is no need to do so, power switch 212 is off, and signals SCE, BK, RC are “L Therefore, since node SE is "L", scan flip-flop 221 is at node D Store data 1. In the example in Figure 20, at time t1, backup circuit 2 Node SN11 of 22 is "L".

[0154] This explains the operation during backup. At time t1, PMU193 is chrome Stop the GCLK1 signal and set the PSE2 and BK signals to "H". Level shifter 214 It becomes active and outputs the "H" signal BKH to the backup circuit 222.

[0155] The transistor M11 of backup circuit 222 turns on, and scan flip-flop The data from node Q1 of circuit 221 is written to node SN11 of backup circuit 222. If node Q1 of scan flip-flop 221 is "L", then node SN11 is If it remains "L" and node Q1 is "H", then node SN11 will also be "H".

[0156] PMU193 sets signal PSE2, BK to "L" at time t2, and at time t3, signal PSE Change 0 to "L". At time t3, the state of CPU core 200 switches to power gating state. Perform the operation. Alternatively, signal PSE0 may be lowered at the same time as signal BK is lowered.

[0157] This section explains the operation during power-gating. Signal PSE0 When it becomes "L", the voltage of the V_VDD line drops, so the data from node Q1 is lost. Node SN11 continues to hold the data from node Q1 at time t3.

[0158] This section describes the operation during recovery. At time t4, PMU193 receives a signal. Setting PSE0 to "H" transitions the system from power gating to recovery mode. Charging of the V_VDD line begins, and the voltage of the V_VDD line becomes VDDD (time t5) ) Then, PMU193 sets signals PSE2, RC, and SCE to "H".

[0159] Transistor M12 turns on, and the charge of capacitive element C11 is transferred to node SN11 and node S It is distributed to D. If node SN11 is "H", the voltage at node SD will rise. Since code SE is "H", the input latch circuit of scan flip-flop 221 is no longer Data is written to the SD card. At time t6, the clock signal GCLK1 is input to node CK. When activated, the data from the input latch circuit is written to node Q1. In other words, node S This means that the data from N11 has been written to node Q1.

[0160] At time t7, PMU193 sets signals PSE2, SCE, and RC to "L" and performs recovery operation. The process is ending.

[0161] The backup circuit 222 using OS transistors has both dynamic and static power consumption. Due to its small size, it is very suitable for normally-off computing. The CPU 110 includes a CPU core 200 having a backup circuit 222 using a zista. It can be called NoffCPU (registered trademark). NoffCPU is a non-volatile polymer. It has a harpoon, and when operation is not required, the power supply can be shut off. Flip flow Even with the 220 CPU core, there is almost no performance degradation or increase in dynamic power consumption compared to the 200 CPU cores. It can be prevented from happening.

[0162] Furthermore, even though CPU Core 200 has multiple power domains capable of power gating... Good. Multiple power domains have one or more power units to control the voltage input. A switch is provided. Also, the CPU core 200 has one or more power gatings. It may have power domains where power gating is not performed. For example, power gating may not be performed. The power domain controls the flip-flop 220 and power switches 210-212. A power gating control circuit may be provided to perform this operation.

[0163] Note that the application of flip-flop 220 is not limited to CPU 110. In the power domain where power gating is possible, a register is provided, flip-flop The LOPP220 can be applied.

[0164] This embodiment can be appropriately combined with descriptions of other embodiments.

[0165] (Embodiment 4) In this embodiment, the CPU 110 and semiconductor device 10 described in the above embodiment are used. An example of a transistor configuration applicable to the accelerator described above will be explained. As an example, we will explain a configuration in which transistors with different electrical characteristics are stacked. This configuration allows for greater design flexibility in semiconductor devices. By stacking transistors with specific electrical characteristics, the integration density of semiconductor devices can be increased. It is possible.

[0166] A portion of the cross-sectional structure of a semiconductor device is shown in Figure 21. The semiconductor device shown in Figure 21 is a transistor It has a 550 transistor, a 500 capacitor, and a 600 capacitive element. Figure 22A shows the transistor Figure 22B is a cross-sectional view of transistor 500 in the channel length direction, and Figure 22B shows the channel of transistor 500. This is a cross-sectional view in the width direction of the panel. For example, transistor 500 is shown in the above embodiment. The OS transistor in the recirculation circuit 32, that is, the channel formation region, has an oxide semiconductor. It corresponds to a transistor. Furthermore, transistor 550 is the arithmetic circuit shown in the above embodiment. The Si transistor in part 40, that is, the transistor having silicon in the channel formation region This corresponds to a sta. Also, the capacitive element 600 corresponds to the capacitive element in the memory circuit 32.

[0167] Transistor 500 is an OS transistor. OS transistors have a polarity of off-current. It is very small. Therefore, the data voltage written to the memory node via transistor 500 is Therefore, it is possible to retain the charge for a long period of time. In other words, the refresh operation of the memory node By reducing the frequency or eliminating the need for refresh operations, the power consumption of semiconductor devices is reduced. It can be reduced.

[0168] In Figure 21, transistor 500 is located above transistor 550, and capacitive element 6 00 is located above transistors 550 and 500.

[0169] The transistor 550 is mounted on the substrate 311. The substrate 311 is, for example, a p-type silicon This is a silicon substrate. Substrate 311 may be an n-type silicon substrate. The oxide layer 314 is a substrate An insulating layer (BO) formed by burried oxide in 311 The X layer (also called the X layer) is preferably made of silicon oxide, for example. Transistor 550 is based Single crystal silicon, so-called SOI (Sil), is provided on plate 311 via an oxide layer 314. (Icon On Insulator) Provided on the circuit board.

[0170] In the SOI substrate, the substrate 311 is provided with an insulator 313 that functions as an element isolation layer. The substrate 311 also has a well region 312. The well region 312 is a transistor This is a region on the SOI substrate that is given n-type or p-type conductivity depending on the conductivity type of 550. In the single-crystal silicon, the semiconductor region 315 is used as the source region or drain region. Low-resistance regions 316a and 316b are provided that enable this function. Also, on the well region 312 It has a low-resistance region 316c.

[0171] Transistor 550 is located in a well region 312 to which impurity elements that impart conductivity have been added. They can be stacked. The well region 312 independently controls the potential through the low-resistance region 316c. By changing its orientation, it can function as the bottom gate electrode of transistor 550. This is possible. Therefore, the threshold voltage of transistor 550 can be controlled. In particular By applying a negative potential to the well region 312, the threshold voltage of transistor 550 is reduced. It becomes possible to increase the voltage and reduce the off-current. Therefore, well region 31 By applying a negative potential to 2, the potential applied to the gate electrode of the Si transistor becomes 0V. The drain current can be reduced. As a result, the transistor 550 has This reduces power consumption based on through-currents, etc., in the calculation circuit section 40, thereby improving calculation efficiency. It is possible.

[0172] Transistor 550 has an insulator 317 on the top surface and side surface in the channel width direction of the semiconductor layer. It is preferable to have a so-called Fin type, where the conductor 318 is covered via a transit. By making the ST550 a Fin type, the effective channel width is increased, thus improving traction. The ON characteristics of the inverter 550 can be improved. Also, the contribution of the electric field of the gate electrode can be improved. Because the value can be increased, the off-state characteristics of transistor 550 can be improved.

[0173] Note that transistor 550 is either a p-channel type transistor or an n-channel type transistor. Any transistor will do.

[0174] Conductor 318 may function as the first gate (also called the top gate) electrode. Furthermore, the well region 312 functions as the second gate (also called the bottom gate) electrode. In some cases, the potential applied to the well region 312 is applied via the low-resistance region 316c. It can be controlled.

[0175] The region where the channel of the semiconductor region 315 is formed, the neighboring region, the source region, or The drain region is a low-resistance region 316a, and the low-resistance region 316b, and the well region 312 In a low-resistance region 316c connected to an electrode that controls the potential, a silicon-based semiconductor It is preferable to include semiconductors such as G e (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), It may also be formed from a material containing GaAlAs (gallium aluminum arsenide), etc. A silicon-based structure in which the effective mass is controlled by applying stress to the particles and changing the lattice spacing. Alternatively, by using GaAs and GaAlAs, the transistor 550 can be made HEMT (High Electron Mobility Transistor) and You may do so.

[0176] Well region 312, low resistance region 316a, low resistance region 316b, and low resistance region 31 6c is a semiconductor material applied to semiconductor region 315, as well as n-type conductive materials such as arsenic and phosphorus. It contains an element that imparts properties, or an element that imparts p-type conductivity, such as boron.

[0177] The conductor 318, which functions as a gate electrode, imparts n-type conductivity to arsenic, phosphorus, etc. Semiconductor materials such as silicon containing elements, or elements that impart p-type conductivity, such as boron. Conductive materials such as cellulose, metallic materials, alloy materials, or metal oxide materials can be used. Furthermore, the conductor 318 may be a silicide such as nickel silicide.

[0178] Furthermore, since the work function is determined by the material of the conductor, the material of the conductor must be selected accordingly. This allows you to adjust the threshold voltage of the transistor. Specifically, by using nitride in the conductor... It is preferable to use materials such as tan or tantalum nitride. Furthermore, both conductivity and embedding properties are desirable. To achieve this, metal materials such as tungsten and aluminum are used as laminates in the conductive material. This is preferable, and using tungsten is particularly preferable in terms of heat resistance.

[0179] Low-resistance region 316a, low-resistance region 316b, and low-resistance region 316c are made of another conductor For example, a configuration in which silicides such as nickel silicide are laminated may be used. By doing so, the conductivity of the region that functions as an electrode can be increased. , the side of the conductor 318 which functions as the gate electrode, and the insulating film which functions as the gate insulating film The sides of the edge body have an insulator that functions as a sidewall spacer (also called a sidewall insulating layer). A configuration may be provided that includes the conductor 318 and the low-resistance region 316. This prevents a and the low-resistance region 316b from becoming conductive.

[0180] The transistor 550 is covered with insulators 320, 322, 324, and The edge members 326 are arranged in a sequential stacking fashion.

[0181] For example, acid Silicon oxide, silicon nitride, silicon nitride, silicon nitride, aluminum oxide, Aluminum oxide nitride, aluminum nitride oxide, aluminum nitride, etc., can be used.

[0182] In this specification, silicon oxidnitride refers to a material whose composition contains more oxygen than nitrogen. It refers to materials with a high content of nitrogen, and silicon nitride, in terms of its composition, contains more nitrogen than oxygen. This indicates a material with a high concentration of [amount]. Furthermore, in this specification, aluminum oxide nitride is defined as [component]. It refers to a material in which the oxygen content is higher than the nitrogen content, and aluminum nitride oxide is a combination of these materials. This refers to materials in which the nitrogen content is higher than the oxygen content.

[0183] The insulator 322 provides a step created by the transistor 550 and the like located below it. It may also function as a planarizing film that flattens the surface. For example, the upper surface of the insulator 322 is To improve flatness, the surface is flattened using a planarization treatment such as chemical mechanical polishing (CMP). It's fine if you do that.

[0184] Furthermore, the insulator 324 receives transistors from the substrate 311 or transistors 550, etc. A barrier film is provided in the region where the STA500 is installed, so as not to diffuse hydrogen or impurities. It is preferable to use it.

[0185] As an example of a film that has barrier properties against hydrogen, for example, silica nitride formed by CVD A semiconductor can be used. Here, a semiconductor having an oxide semiconductor such as transistor 500 can be used. The diffusion of hydrogen into the semiconductor element may degrade the characteristics of that semiconductor element. So, a film that suppresses hydrogen diffusion is placed between transistor 500 and transistor 550. It is preferable to use it. Specifically, a membrane that suppresses hydrogen diffusion is one in which the amount of hydrogen desorption is small. It will be called a membrane.

[0186] The amount of hydrogen desorption can be analyzed, for example, using a thermodynamic desorption gas analysis (TDS) method. Yes, it is possible. For example, the amount of hydrogen desorption from insulator 324 can be determined by TDS analysis when the film surface temperature is In the range of 50°C to 500°C, the amount of desorption converted to hydrogen atoms is the area of ​​the insulator 324. Converted to a single win, 10 x 10 15 atoms / cm 2 The following is preferably 5 × 10 15 a toms / cm 2 The following is acceptable.

[0187] Furthermore, it is preferable that the dielectric constant of the insulator 326 is lower than that of the insulator 324. For example, The relative permittivity of the edge material 326 is preferably less than 4, and more preferably less than 3. Also, for example, an insulator... The relative permittivity of 326 is preferably 0.7 times or less, and preferably 0.6 times or less, than the relative permittivity of the insulator 324. This is more preferable. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between the wiring is reduced. It can be reduced.

[0188] Furthermore, insulators 320, 322, 324, and 326 contain capacitive elements. Conductors 328 and 330, etc., which connect to transistor 600 or transistor 500, are embedded. It is embedded. Note that conductors 328 and 330 are used as plugs or wiring. It has the function of a plug or wiring. In addition, a conductor that has multiple configurations In some cases, the same code may be assigned to multiple components. Also, in this specification, etc., wiring and wiring and The plug to be connected may be an integral part of the device. That is, a part of the conductor may function as wiring. In some cases, a portion of the conductor may function as a plug.

[0189] The materials for each plug and wiring (conductor 328, conductor 330, etc.) are metal materials. Conductive materials such as alloy materials, metal nitride materials, or metal oxide materials are used in a single layer or in a multilayer structure. It can be used in this way. High heat resistance and conductivity can be achieved with tungsten, molybdenum, and other materials. It is preferable to use a melting point material, and it is preferable to use tungsten. Alternatively, aluminum It is preferable to form it with a low-resistance conductive material such as aluminum or copper. This can lower the wiring resistance.

[0190] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Figure 21 Insulators 350, 352, and 354 are arranged in a sequential stack. Furthermore, a conductor 356 is formed on insulators 350, 352, and 354. Conductor 356 functions as a plug or wire connecting to transistor 550. It has the same material as conductors 328 and 330. It can be established.

[0191] Furthermore, for example, insulator 350 has a barrier property against hydrogen, similar to insulator 324. It is preferable to use an insulator. Furthermore, the conductor 356 has barrier properties against hydrogen. It is preferable to include a conductor. In particular, it is preferable to include an insulator 350 that has barrier properties against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. With this configuration, The transistor 550 and the transistor 500 can be separated by a barrier layer. This can suppress the diffusion of hydrogen from transistor 550 to transistor 500.

[0192] For example, tantalum nitride can be used as a conductor that has barrier properties against hydrogen. It would be good to do so. Also, by laminating tantalum nitride and highly conductive tungsten, the wiring can be made It is possible to suppress the diffusion of hydrogen from transistor 550 while maintaining conductivity. In this case, the tantalum nitride layer having barrier properties against hydrogen has barrier properties against hydrogen It is preferable that the insulator 350 having the above characteristics is in contact with the insulator 350.

[0193] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in Figure 21 Insulators 360, 362, and 364 are arranged in a series of layers. Furthermore, a conductor 366 is formed on insulators 360, 362, and 364. Conductor 366 has the function of a plug or wiring. It can be provided using the same material as conductors 328 and 330.

[0194] Furthermore, for example, insulator 360 has a barrier property against hydrogen, similar to insulator 324. It is preferable to use an insulator. Furthermore, the conductor 366 has barrier properties against hydrogen. It is preferable to include a conductor. In particular, an insulator 360 having barrier properties against hydrogen is preferable. A conductor having a barrier property against hydrogen is formed in the opening. With this configuration, The transistor 550 and the transistor 500 can be separated by a barrier layer. This can suppress the diffusion of hydrogen from transistor 550 to transistor 500.

[0195] A wiring layer may be provided on the insulator 364 and the conductor 366. For example, in Figure 21 Insulators 370, 372, and 374 are arranged in a sequential stack. Furthermore, a conductor 376 is formed on insulators 370, 372, and 374. It is present. Conductor 376 has the function of a plug or wiring. Note that Conductor 376 is It can be provided using the same material as conductors 328 and 330.

[0196] Furthermore, for example, insulator 370, like insulator 324, has barrier properties against hydrogen. It is preferable to use an insulator. Furthermore, the conductor 376 has barrier properties against hydrogen. It is preferable to include a conductor. In particular, an insulator 370 having barrier properties against hydrogen is preferable. A conductor having a barrier property against hydrogen is formed in the opening. With this configuration, The transistor 550 and the transistor 500 can be separated by a barrier layer. This can suppress the diffusion of hydrogen from transistor 550 to transistor 500.

[0197] A wiring layer may be provided on the insulator 374 and the conductor 376. For example, in Figure 21 Insulators 380, 382, ​​and 384 are arranged in a sequential stack. Furthermore, a conductor 386 is formed on insulators 380, 382, ​​and 384. Conductor 386 functions as a plug or wiring. It can be provided using the same material as conductors 328 and 330.

[0198] For example, insulator 380, like insulator 324, has barrier properties against hydrogen. It is preferable to use an insulator. Furthermore, the conductor 386 has barrier properties against hydrogen. It is preferable to include a conductor. In particular, an insulator 380 having barrier properties against hydrogen is preferable. A conductor having a barrier property against hydrogen is formed in the opening. With this configuration, The transistor 550 and the transistor 500 can be separated by a barrier layer. This can suppress the diffusion of hydrogen from transistor 550 to transistor 500.

[0199] In the above, a wiring layer containing a conductor 356, a wiring layer containing a conductor 366, and a conductor 376 A wiring layer including and a wiring layer including the conductor 386 have been described, but in this embodiment The semiconductor device is not limited to this. Wiring layers similar to those containing the conductor 356 The number of layers may be three or fewer, or the number of wiring layers similar to the wiring layer containing conductor 356 may be five or more. That's fine.

[0200] Insulator 384 is on insulator 510, insulator 512, insulator 514, and insulator 516 However, they are arranged in layers in order. Insulator 510, insulator 512, insulator 514, and It is preferable that one of the insulators 516 be made of a material that has barrier properties against oxygen and hydrogen. It's nice.

[0201] For example, the insulator 510 and the insulator 514 are connected to, for example, the substrate 311 or a transistor. From the area where the transistor 550 is installed, hydrogen and impurities are transferred to the area where the transistor 500 is installed. It is preferable to use a film that has barrier properties against [the substance]. Therefore, similar to insulator 324. These materials can be used.

[0202] As an example of a film with hydrogen barrier properties, silicon nitride formed by CVD is used. It is possible to have a semiconductor device having an oxide semiconductor such as transistor 500. Furthermore, hydrogen diffusion can degrade the properties of the semiconductor device. Therefore, A film that suppresses hydrogen diffusion is used between the transistor 500 and the transistor 550. This is preferable.

[0203] Furthermore, as a film having barrier properties against hydrogen, for example, insulator 510 and insulator 514 uses metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide. It is preferable to do so.

[0204] In particular, aluminum oxide is a source of oxygen and water, which can cause variations in the electrical properties of transistors. It has a high barrier effect that prevents both elements and impurities such as water from passing through the membrane. Therefore, Aluminum oxide is affected by hydrogen, moisture, etc. during and after the transistor fabrication process. This prevents impurities from entering transistor 500. The release of oxygen from the oxides that make up 00 can be suppressed. Therefore, the transient It is suitable for use as a protective film for Ta500.

[0205] Furthermore, for example, the insulators 512 and 516 are made of the same material as the insulator 320. It can be used. Furthermore, these insulators can be made by applying materials with relatively low dielectric constants. This reduces parasitic capacitance between wires. For example, insulator 512, and As the edge 516, a silicon oxide film or a silicon oxide-nitride film can be used.

[0206] Furthermore, insulators 510, 512, 514, and 516 contain conductive materials. 518, and the conductors (e.g., conductor 503) that make up transistor 500 are embedded It is embedded. Furthermore, the conductor 518 is in contact with the capacitive element 600 or the transistor 550. It functions as a connecting plug or wiring. Conductor 518 is connected to conductor 328, and It can be provided using the same material as the conductor 330.

[0207] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is oxygen, hydrogen Preferably, the material is a conductor that has barrier properties against water. With this configuration, The Rangista 550 and Transistor 500 have barrier properties against oxygen, hydrogen, and water. In the layer having, it can be separated, and hydrogen from transistor 550 to transistor 500 This can suppress the spread of [the substance].

[0208] A transistor 500 is provided above the insulator 516.

[0209] As shown in Figures 22A and 22B, transistor 500 is connected to insulator 514 and A conductor 503 is arranged to be embedded in the edge 516, and the insulator 516 and the conductor An insulator 522 placed on top of 503, and an insulator 524 placed on top of insulator 522 , an oxide 530a placed on the insulator 524, and an acid placed on the oxide 530a The oxide 530b and the conductors 542a and conductive materials arranged apart from each other on the oxide 530b Body 542b, and a conductor 542a and a conductor 542b are disposed on the conductor 542a and the conductor 542a and the conductor An insulator 580 superimposed between the electric bodies 542b with an opening formed therein, and the bottom surface and side surface of the opening It comprises an arranged insulator 545 and a conductor 560 arranged on the forming surface of the insulator 545. ru.

[0210] Furthermore, as shown in Figures 22A and 22B, oxide 530a, oxide 530b, and conductive An insulator 544 is placed between the body 542a, the conductor 542b, and the insulator 580. This is preferable. Also, as shown in Figures 22A and 22B, the conductor 560 is an insulator 5 A conductor 560a is provided inside 45, and is embedded inside the conductor 560a It is preferable to have a conductor 560b provided. Also, Figures 22A and 22B As shown, an insulator 574 is placed on top of an insulator 580, a conductor 560, and an insulator 545. It is preferable that they be arranged in this manner.

[0211] In this specification, oxides 530a and 530b are collectively referred to as oxidation. There are cases where the item is listed as 530.

[0212] Furthermore, in transistor 500, in the region where the channel is formed and in its vicinity, acid The present invention describes a configuration in which two layers, oxide 530a and oxide 530b, are stacked, but The possibilities are not limited to this. For example, a single layer of oxide 530b, or a layer of three or more layers. A layered configuration may also be used.

[0213] Furthermore, in transistor 500, the conductor 560 is shown as a two-layer stacked structure, The present invention is not limited thereto. For example, the conductor 560 may have a single-layer configuration. Furthermore, a laminated structure of three or more layers is also acceptable. Also, as shown in Figures 21, 22A, and 22B The transistor 500 shown is just one example, and is not limited to its configuration; circuit configurations and driving methods may also be considered. You should use the appropriate transistor depending on the situation.

[0214] Here, conductor 560 functions as the gate electrode of the transistor, and conductor 542a The conductor 542b functions as either a source electrode or a drain electrode, respectively. Thus, the conductor 560 is located at the opening of the insulator 580, and the conductors 542a and 542b It is formed to be embedded in the region sandwiched between the conductor 560, conductor 542a and The arrangement of the conductor 542b is self-aligned with the opening of the insulator 580. In transistor 500, the gate electrode is placed between the source electrode and the drain electrode. They can be arranged in a self-aligned manner. Therefore, a margin for alignment is provided for the conductor 560. Since it can be formed without any modifications, the occupied area of ​​transistor 500 can be reduced. This makes it possible to miniaturize and highly integrate semiconductor devices.

[0215] Furthermore, the conductor 560 is self-aligned in the region between conductor 542a and conductor 542b. As a result, the conductor 560 is formed in a region that overlaps with the conductor 542a or the conductor 542b. It does not have. As a result, between conductor 560 and conductors 542a and conductor 542b The parasitic capacitance that is formed can be reduced. Therefore, the switching of transistor 500 This allows for improved speed and enhanced frequency response.

[0216] Conductor 560 may function as the first gate (also called the top gate) electrode. Furthermore, when the conductor 503 functions as the second gate (also called the bottom gate) electrode... In that case, the potential applied to the conductor 503 is the same as the potential applied to the conductor 560. By controlling the threshold voltage of transistor 500 independently without moving it, it is possible to control the threshold voltage of transistor 500. This can be done. In particular, by applying a negative potential to the conductor 503, the transistor 500 This makes it possible to increase the threshold voltage and reduce the off-current. Applying a negative potential to the electric element 503 is more effective than not applying a negative potential to the conductor 560. The drain current can be reduced when the potential is 0V.

[0217] The conductor 503 is positioned to overlap with the oxide 530 and the conductor 560. Therefore, when a potential is applied to the conductor 560 and the conductor 503, the conductor 560 produces The electric field generated by the conductor 503 connects with the electric field generated by the conductor 503, and a chain reaction is formed in the oxide 530. It can cover the channel formation region.

[0218] In this specification, etc., a pair of gate electrodes (a first gate electrode and a second gate electrode) The electric field of ) electrically surrounds the transistor configuration that forms the channel formation region, This is called a rounded channel (S-channel) configuration. The S-channel configuration disclosed is different from the Fin-type configuration and the Planar-type configuration. By adopting an S-channel configuration, resistance to short-channel effects is increased, in other words This makes it possible to create a transistor that is less susceptible to short-channel effects.

[0219] Furthermore, the conductor 503 has the same configuration as the conductor 518, and the insulator 514 and the insulator A conductor 503a is formed in contact with the inner wall of the opening 516, and a conductor 503b is further inside. It is formed. In transistor 500, conductor 503a and conductor 503b The present invention describes a configuration in which layers are stacked, but is not limited thereto. For example, The conductor 503 may be provided as a single layer or as a laminated structure of three or more layers.

[0220] Here, the conductor 503a diffuses impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. It is preferable to use a conductive material that has the function of suppressing (the above-mentioned impurities are less likely to permeate) It is difficult. Or, it inhibits the diffusion of oxygen (for example, at least one such as an oxygen atom or oxygen molecule). It is preferable to use a conductive material that has the function of (being impermeable to the above-mentioned oxygen). In this specification, the function of suppressing the diffusion of impurities or oxygen means the above-mentioned impurities, and This function suppresses the diffusion of any one or all of the above-mentioned oxygen molecules.

[0221] For example, the conductor 503a has the function of suppressing the diffusion of oxygen, This can suppress the oxidation of b, which reduces its conductivity.

[0222] Furthermore, if the conductor 503 also functions as wiring, the conductor 503b may be tungsten or copper. Alternatively, it is preferable to use a highly conductive material, such as one primarily composed of aluminum. In this embodiment, the conductor 503 is shown as a laminate of conductor 503a and conductor 503b. However, the conductor 503 may have a single-layer configuration.

[0223] Insulators 522 and 524 function as second gate insulating films.

[0224] Here, the insulator 524 in contact with the oxide 530 is more abundant than the oxygen that satisfies the stoichiometric composition. It is preferable to use an insulator containing oxygen. This oxygen is released from the film by heating. It is easily released. In this specification, the oxygen released by heating is sometimes referred to as "excess oxygen." In other words, the insulator 524 has a region containing excess oxygen (also called the "excess oxygen region"). It is preferable that such an insulator containing excess oxygen is brought into contact with oxide 530. By providing this, oxygen deficiencies (V) in oxide 530 are eliminated. O :oxygen vacancy This reduces (also known as) and improves the reliability of transistor 500. If hydrogen enters the oxygen vacancy in compound 530, the defect (hereinafter referred to as V) O It is sometimes referred to as H. ) can function as a donor, and electrons, which are carriers, can be generated. Also, hydrogen In some cases, it combines with oxygen atoms that bond with metal atoms, generating electrons, which act as carriers. Therefore, transistors using oxide semiconductors with a high hydrogen content are normally-on It is prone to becoming a characteristic. Also, hydrogen in oxide semiconductors moves due to stress such as heat and electric fields. Because it is prone to this, if oxide semiconductors contain a lot of hydrogen, the reliability of transistors deteriorates. There is a risk that V in oxide 530 OReduce H as much as possible, It is preferable to make it highly pure or substantially highly pure. Thus, V O H is sufficient To obtain an oxide semiconductor with reduced impurities, it is necessary to remove water, hydrogen, and other impurities from the oxide semiconductor. This involves (also called "dehydration" or "dehydrogenation") supplying oxygen to the oxide semiconductor. It is important to compensate for the oxygen deficiency (also called "oxygenation treatment"). O H etc. Using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor. This allows for the provision of stable electrical characteristics.

[0225] As an insulator having an excess oxygen region, specifically, an acid in which some of the oxygen is removed by heating. It is preferable to use an oxide material. Oxides that desorb oxygen upon heating include TDS(Th In urinary desorption spectroscopy analysis, oxygen atoms were found to The amount of oxygen removed after conversion is 1.0 × 10⁻⁶ 18 atoms / cm 3 Preferably 1.0 ×10 19 atoms / cm 3 More preferably 2.0 × 10 19 ate / c m 3 Above, or 3.0 × 10 20 atoms / cm 3 The above describes the oxide film. The surface temperature of the film during the above TDS analysis is 100°C to 700°C, or 1 A temperature range of 00°C to 400°C is preferred.

[0226] Furthermore, the insulator having the above excess oxygen region and oxide 530 are brought into contact and heat treated, One or more of the following processes may be performed: Kuroh wave processing or RF processing. By doing so, water or hydrogen can be removed from oxide 530. For example, oxide At 530, a reaction occurs in which the VoH bond is broken, or in other words, "V O H→Vo+ The reaction H occurs, which can lead to dehydrogenation. Some of the hydrogen produced at this time is It combines with oxygen to form H2O and is removed from oxide 530 or the insulator near oxide 530. This may occur. Also, some of the hydrogen may be gettered by the conductor 542. .

[0227] Furthermore, the above microwave processing is performed using, for example, an apparatus having a power supply that generates high-density plasma. Alternatively, it is preferable to use a device that has a power supply that applies RF to the substrate side. For example, acid By using a gas containing elements and employing a high-density plasma, high-density oxygen radicals are generated. This can be achieved by applying RF to the substrate side, generating high-density plasma. Efficiently introduce oxygen radicals into oxide 530 or an insulator near oxide 530. This can be done. Furthermore, the above microwave treatment is performed at a pressure of 133 Pa or higher, preferably 200 Pa. The Pa should be Pa or higher, more preferably 400 Pa or higher. For example, oxygen and argon are used as gases introduced into the apparatus, with an oxygen flow rate ratio (O2 The process should be carried out with (O2+Ar) content of 50% or less, preferably between 10% and 30%.

[0228] Furthermore, during the manufacturing process of transistor 500, the surface of oxide 530 is exposed. Therefore, heat treatment is preferable. This heat treatment is, for example, 100°C to 450°C. More preferably, the heating should be carried out at a temperature of 350°C to 400°C. The heat treatment is performed using nitrogen gas. Alternatively, an inert gas atmosphere, or an oxidizing gas at 10 ppm or more, 1% or more, The procedure should be carried out in an atmosphere containing 10% or more of the substance. For example, heat treatment is preferably carried out in an oxygen atmosphere. This supplies oxygen to oxide 530, thus eliminating oxygen deficiency (V O ) can be reduced. Furthermore, the heat treatment may be carried out under reduced pressure. Alternatively, the heat treatment may be carried out under nitrogen gas or After heat treatment in an active gas atmosphere, an oxidizing gas is added at 10 pJ to replenish the desorbed oxygen. The procedure may be carried out in an atmosphere containing 1% or more of the substance, or 10% or more of the substance. Alternatively, an oxidizing gas may be used. After heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more, then continuously The heat treatment may be carried out in a nitrogen gas or inert gas atmosphere.

[0229] Furthermore, by performing an oxygenation treatment on oxide 530, the oxygen deficiencies in oxide 530 are supplied. The oxygen used for repair, or in other words, the reaction "Vo + O → null" is promoted. Furthermore, the oxygen supplied reacts with the hydrogen remaining in oxide 530. This allows the hydrogen to be removed as H2O (dehydrated). This eliminates oxidation. The hydrogen remaining in substance 530 recombines with the oxygen vacancy and V O Suppresses the formation of H It is possible.

[0230] Furthermore, if the insulator 524 has an excess oxygen region, the insulator 522 will have oxygen (for example, It has the function of suppressing the diffusion of oxygen atoms, oxygen molecules, etc. (making it difficult for the above-mentioned oxygen to permeate). This is preferable.

[0231] The insulator 522 has the function of suppressing the diffusion of oxygen and impurities, so the oxide 530 The oxygen present does not diffuse towards the conductor 503, which is preferable. This suppresses the reaction between the insulator 524 and the oxygen present in the oxide 530.

[0232] The insulator 522 is, for example, aluminum oxide, hafnium oxide, aluminum and Humium-containing oxides (hafnium aluminate), tantalum oxide, zirconium oxide, Lead zirconate titanate (PZT), strontium titanate (SrTiO3), or ( A single layer of insulator containing so-called high-k materials such as Ba,Sr)TiO3(BST) Alternatively, it is preferable to use them in a stacked configuration. As transistors become smaller and more integrated, Thinning the gate insulating film can sometimes lead to problems such as leakage current. By using a high-k material as an insulator that functions in this way, the physical film thickness is maintained while transforming This allows for a reduction in gate potential during DISTRO operation.

[0233] In particular, it has the function of suppressing the diffusion of impurities and oxygen (the above oxygen does not permeate easily). i) An insulator containing an oxide of either aluminum or hafnium, or both, which are insulating materials. It is recommended to use an insulator containing an oxide of either aluminum or hafnium, or both. aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium ( It is preferable to use materials such as hafnium aluminate. When 522 is formed, the insulator 522 prevents the release of oxygen from the oxide 530 and the transient It functions as a layer that suppresses the incorporation of impurities such as hydrogen from the peripheral area of ​​T500 into the oxide 530. ru.

[0234] Alternatively, these insulators may be, for example, aluminum oxide, bismuth oxide, germanium oxide. Umium, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, Zirconium oxide may be added. Alternatively, these insulators may be subjected to nitriding treatment. Silicon oxide, silicon oxide nitride, or silicon nitride may be laminated as the insulator. .

[0235] Note that the transistor 500 in Figures 22A and 22B has a three-layer stacked structure. Insulators 522 and 524 are shown as gate insulating films of 2, but 2 The gate insulating film may have a single layer, two layers, or a stacked structure of four or more layers. Furthermore, the laminated structure is not limited to that made of the same material, but may also be made of different materials.

[0236] Transistor 500 is an oxide semiconductor in oxide 530 including a channel formation region. A functional metal oxide is used. For example, as oxide 530, In-M-Zn oxide (original The elements M are aluminum, gallium, yttrium, copper, vanadium, beryllium, and boron. Titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium Choose from materials such as magnesium, neodymium, hafnium, tantalum, tungsten, or magnesium. It is preferable to use one or more types of metal oxides.

[0237] The formation of metal oxides that function as oxide semiconductors may be carried out by sputtering. Alternatively, the Atomic Layer Deposition (ALD) method may be used. The metal oxides that function as oxide semiconductors will be described in detail in other embodiments. do.

[0238] Furthermore, the metal oxide that functions as a channel-forming region in oxide 530 is bandg It is preferable to use a cap with a voltage of 2 eV or more, preferably 2.5 eV or more. By using metal oxides with a large band gap, the off-current of the transistor can be reduced. It can be reduced.

[0239] Oxide 530 has oxide 530a beneath oxide 530b, so oxide 530a The diffusion of impurities from the components formed below to oxide 530b is suppressed. can.

[0240] Furthermore, oxide 530 has a layered structure of multiple oxide layers with different atomic ratios of each metal atom. It is preferable to do so. Specifically, in the metal oxide used in oxide 530a, the constituent elements The atomic ratio of element M in the elementary oxide is the ratio of constituent elements in the metal oxide used in oxide 530b. It is preferable that it is greater than the atomic ratio of element M. Also, the metal oxide used in oxide 530a In the material, the atomic ratio of element M to In is the same as that of the metal oxide used in oxide 530b. It is preferable that the atomic ratio of element M to In is greater than that of In. Also, oxide 530b In the metal oxide used, the atomic ratio of In to element M is used in oxide 530a. It is preferable that the atomic ratio of In to element M in the metal oxide is greater than that of In.

[0241] Furthermore, the energy at the lower end of the conduction band of oxide 530a is equal to the energy at the lower end of the conduction band of oxide 530b. It is preferable that it be higher than the energy. In other words, the electron affinity of oxide 530a. However, it is preferable that it be smaller than the electron affinity of oxide 530b.

[0242] Here, at the junction of oxide 530a and oxide 530b, the energy at the lower end of the conduction band The Ghee level changes smoothly. In other words, the junction of oxide 530a and oxide 530b The energy levels at the lower end of the conduction band at the junction are said to change continuously or form a continuous junction. This can be done. In order to do this, at the interface between oxide 530a and oxide 530b It is desirable to lower the defect level density of the mixed layer that is formed.

[0243] Specifically, oxides 530a and 530b have a common element other than oxygen (main By using it as a component, a mixed layer with a low defect level density can be formed. For example, oxidation If substance 530b is an In-Ga-Zn oxide, then oxide 530a is In-Ga-Zn Oxides, Ga-Zn oxide, and gallium oxide are good choices to use.

[0244] In this case, the main carrier pathway is oxide 530b. Oxide 530a is constructed as described above. By doing so, the defect level density at the interface between oxide 530a and oxide 530b is reduced. This makes it possible. Therefore, the influence of interfacial scattering on carrier conduction is reduced, and traction The 500 inverter can achieve high on-current.

[0245] On the oxide 530b are conductors 542, which function as source and drain electrodes. a and conductor 542b are provided. It is aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum Tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium Nium, beryllium, indium, ruthenium, iridium, strontium, lanthanum A metal element selected from the above, or an alloy containing the above metal elements, or the above metal elements It is preferable to use an alloy that combines these elements. For example, tantalum nitride, titanium nitride, t sten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum , ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, lanthanum It is preferable to use oxides containing nitriding and nickel. Also, tantalum nitride, titanium nitride Titanium nitrides containing titanium and aluminum, tantalum nitrides containing tantalum and aluminum, oxides Thenium, ruthenium nitride, oxides containing strontium and ruthenium, lanthanum and nickel Oxides containing Kel are conductive materials that are resistant to oxidation, or that maintain their conductivity even after absorbing oxygen. It is preferable because it is a material that does so. Furthermore, metal nitride films such as tantalum nitride are hydrogen or It is preferable because it has barrier properties against oxygen.

[0246] Furthermore, in Figure 22A, the conductors 542a and 542b are shown as single-layer structures. However, a laminated structure of two or more layers is also possible. For example, a tantalum nitride film and a tungsten film can be laminated. This is a good idea. Alternatively, a titanium film and an aluminum film may be laminated. Also, a tungsten film may be used. A two-layer structure with an aluminum film laminated on top, and copper on a copper-magnesium-aluminum alloy film. Two-layer structure with stacked films, two-layer structure with a copper film stacked on a titanium film, copper film on a tungsten film A two-layer structure with stacked layers is also possible.

[0247] Furthermore, a titanium film or titanium nitride film, and a layer on top of the titanium film or titanium nitride film. A luminium film or copper film is laminated, and then a titanium film or titanium nitride film is formed on top of it. A three-layer structure consisting of a molybdenum film or molybdenum nitride film, and the molybdenum film or molybdenum nitride film. An aluminum film or copper film is laminated on top of the butene film, and then a molybdenum film is laid on top of that. Alternatively, there are three-layer structures that form a molybdenum nitride film. Furthermore, indium oxide, tin oxide, and A transparent conductive material containing zinc oxide may also be used.

[0248] Furthermore, as shown in Figure 22A, the oxide 530 has conductor 542a (conductor 542b) and At the interface and its vicinity, regions 543a and 543b are formed as low-resistance regions. In some cases, this may occur. In this case, region 543a may be either the source region or the drain region. It functions, and region 543b functions as either the source region or the drain region. A channel-forming region is formed in the region sandwiched between region 543a and region 543b.

[0249] By providing the conductor 542a (conductor 542b) in contact with the oxide 530, The oxygen concentration in region 543a (region 543b) may decrease. Also, region 543a ( In region 543b), the metal contained in conductor 542a (conductor 542b) and oxide 530 A metal compound layer containing the component may be formed. In such cases, region 543a (region The carrier density in region 543b increases, and region 543a (region 543b) becomes a low-resistance region. Yes.

[0250] The insulator 544 is provided so as to cover the conductors 542a and 542b, and is conductive The oxidation of body 542a and conductor 542b is suppressed. At this time, the insulator 544 is oxidized. It may be provided so as to cover the side of object 530 and be in contact with the insulator 524.

[0251] Insulator 544 includes hafnium, aluminum, gallium, yttrium, and zirconium. Umium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum Alternatively, a metal oxide containing one or more metals selected from magnesium, etc., may be used. It can be. Also, as insulator 544, silicon nitride or silicon nitride It can be used in any way.

[0252] In particular, as insulator 544, an oxide of either aluminum or hafnium or both Insulators containing materials, such as aluminum oxide, hafnium oxide, aluminum, and haf It is preferable to use an oxide containing nium (such as hafnium aluminate). In particular, Hafnium aluminate has higher heat resistance than hafnium oxide film. Therefore, in subsequent processes... In heat treatment, it is preferable because it does not easily crystallize. Note that conductor 542a and conductive Body 542b is a material that is oxidation-resistant, or whose conductivity does not significantly decrease even when it absorbs oxygen. In some cases, the insulator 544 is not an essential component. Depending on the desired transistor characteristics, it can be configured as appropriate. Just calculate it.

[0253] The presence of the insulator 544 allows water and other impurities such as hydrogen contained in the insulator 580 to be absorbed. Diffusion to oxide 530b via insulator 545 can be suppressed. The excess oxygen present in the insulator 580 can suppress the oxidation of the conductor 560. ru.

[0254] The insulator 545 functions as the first gate insulating film. The insulator 545 is the insulating film as described above. Similar to body 524, an insulator that contains excess oxygen and releases oxygen upon heating is used. It is preferable to form it.

[0255] Specifically, silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon oxide containing excess oxygen silicon dioxide, silicon oxide with added fluorine, silicon oxide with added carbon, carbon, Silicon oxide with added nitrogen and porous silicon oxide can be used. Furthermore, silicon oxide and silicon oxide-nitride are preferred because they are stable to heat.

[0256] By providing an insulator containing excess oxygen as insulator 545, acid is released from insulator 545. It can effectively supply oxygen to the channel-forming region of compound 530b. Also, an insulator Similar to 524, the concentration of impurities such as water or hydrogen in the insulator 545 is reduced. It is preferable that the film thickness of the insulator 545 be between 1 nm and 20 nm. Even if the microwave treatment described above is performed before and / or after the formation of the insulator 545, good.

[0257] Furthermore, in order to efficiently supply the excess oxygen contained in the insulator 545 to the oxide 530, A metal oxide may be provided between the edge 545 and the conductor 560. The metal oxide is an insulating material. It is preferable to suppress oxygen diffusion from body 545 to conductor 560. By providing a metal oxide, the diffusion of excess oxygen from the insulator 545 to the conductor 560 is suppressed. This means that the decrease in the amount of excess oxygen supplied to oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to excess oxygen can be suppressed. For the insulator 544, any material suitable for use in the insulator 544 may be used.

[0258] Furthermore, the insulator 545 may be in a laminated configuration, similar to the second gate insulating film. As DISTRS become smaller and more highly integrated, the gate insulating film becomes thinner, reducing leakage current. Because any of these problems may occur, the insulator that acts as the gate insulating film is high-k By creating a laminated structure of one material and a thermally stable material, the physical film thickness is maintained while... This allows for a reduction in gate potential during transistor operation. Furthermore, it offers thermal stability and a high dielectric constant. A laminated structure can be formed.

[0259] The conductor 560, which functions as the first gate electrode, has a two-layer structure in Figures 22A and 22B. Although shown as a single-layer structure, it may also be a laminated structure of three or more layers.

[0260] Conductor 560a contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules. Conductive material (such as N2O, NO, NO2, etc.) has the function of suppressing the diffusion of impurities such as copper atoms. It is preferable to use a material with low oxygen content. Alternatively, a small amount of oxygen (for example, oxygen atoms, oxygen molecules, etc.) It is preferable to use a conductive material that has the function of suppressing the diffusion of (1). Conductor 5 Because 60a has the function of suppressing oxygen diffusion, the oxygen contained in the insulator 545 This suppresses the oxidation of the conductor 560b and the resulting decrease in conductivity. Examples of conductive materials that have the function of suppressing dispersion include tantalum, tantalum nitride, and luteinizing agent. It is preferable to use nium or ruthenium oxide. Also, the conductor 560a is used. Therefore, an oxide semiconductor applicable to oxide 530 can be used. In that case, conductor 5 By depositing 60b using the sputtering method, the electrical resistance of the conductor 560a is reduced. It can be made into a conductor. This is called an OC (Oxide Conductor) electrode. It is possible.

[0261] Furthermore, the conductive material 560b is a conductive material whose main components are tungsten, copper, or aluminum. It is preferable to use a conductive material. Also, since the conductive material 560b also functions as wiring, It is preferable to use a highly conductive material. For example, tungsten, copper, or aluminum. A conductive material mainly composed of nium can be used. In addition, the conductive material 560b has a laminated structure. It may also be a laminated structure of titanium or titanium nitride and the above conductive material. good.

[0262] The insulator 580 is connected to the conductors 542a and 542b via the insulator 544. It is provided. The insulator 580 preferably has an excess oxygen region. For example, insulator 5 As 80, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, fluorine silicon oxide with added nitrogen, silicon oxide with added carbon, carbon, and nitrogen Preferably, it has silicon oxide, porous silicon oxide, or a resin. In particular, silicon oxide and silicon oxide-nitride are preferred because they are thermally stable. Silicon oxide, including porous silicon oxide, readily forms excess oxygen regions in subsequent processes. This is preferable because it allows for this.

[0263] The insulator 580 preferably has an excess oxygen region. Oxygen is released upon heating. By providing the insulator 580, oxygen in the insulator 580 is efficiently supplied to the oxide 530. This is possible. Furthermore, the concentration of impurities such as water or hydrogen in the insulator 580 is reduced. It is preferable to do so.

[0264] The opening in the insulator 580 is formed superimposed on the region between the conductor 542a and the conductor 542b. This allows the conductor 560 to communicate with the opening of the insulator 580 and the conductor 542a. It is formed so as to be embedded in the region sandwiched between body 542b.

[0265] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but the conductor 5 It is necessary to prevent the conductivity of 60 from decreasing. To that end, the film thickness of conductor 560 is increased. As a result, the conductor 560 can have a shape with a high aspect ratio. In this embodiment, In order to embed the body 560 into the opening of the insulator 580, the conductor 560 is aspect ratio Even when forming a shape with a high ratio, it is possible to form the conductive material 560 without causing it to collapse during the process. Cut.

[0266] The insulator 574 is located on the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 545. It is preferable that it be provided in contact with the surface. The insulator 574 is deposited by sputtering. This allows for the creation of excess oxygen regions in insulators 545 and 580. Therefore, oxygen can be supplied to the oxide 530 from the excess oxygen region.

[0267] For example, as insulator 574, hafnium, aluminum, gallium, yttrium, Zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium It is possible to use metal oxides containing one or more types of metals selected from nesium, etc. Cut.

[0268] In particular, aluminum oxide has high barrier properties and is suitable for thin films of 0.5 nm to 3.0 nm. However, the diffusion of hydrogen and nitrogen can be suppressed. Therefore, sputtering The aluminum oxide film formed by this method serves as an oxygen source and also acts as a barrier against impurities such as hydrogen. It can also function as a membrane.

[0269] Furthermore, it is preferable to provide an insulator 581 that functions as an interlayer film on top of the insulator 574. i. Insulator 581, like insulator 524, has an impurity concentration of water or hydrogen in the film. It is preferable that this is reduced.

[0270] Furthermore, the insulators 581, 574, 580, and 544 are formed Conductors 540a and 540b are placed in the opening. Body 540b is provided opposite the conductor 560, with the conductor 540a and conductor 54 0b has the same configuration as conductors 546 and 548, which will be described later.

[0271] An insulator 582 is provided on the insulator 581. The insulator 582 is designed to absorb oxygen and hydrogen. In contrast, it is preferable to use a barrier material. Therefore, the insulator 582 is an insulating material. The same material as the edge 514 can be used. For example, aluminum oxide can be used for the insulator 582. It is preferable to use metal oxides such as nium, hafnium oxide, and tantalum oxide.

[0272] In particular, aluminum oxide is a source of oxygen and water, which can cause variations in the electrical properties of transistors. It has a high barrier effect that prevents both elements and impurities such as water from passing through the membrane. Therefore, Aluminum oxide is affected by hydrogen, moisture, etc. during and after the transistor fabrication process. This prevents impurities from entering transistor 500. The release of oxygen from the oxides that make up 00 can be suppressed. Therefore, the transient It is suitable for use as a protective film for Ta500.

[0273] Furthermore, an insulator 586 is provided on the insulator 582. The insulator 586 is an insulator Similar materials to 320 can be used. In addition, these insulators have a relatively low dielectric constant. By applying a suitable material, parasitic capacitance between wires can be reduced. For example, As the edge element 586, silicon oxide film or silicon oxide nitride film can be used.

[0274] Also, insulators 522, 524, 544, 580, 574, The edge 581, insulator 582, and insulator 586 contain conductor 546 and conductor 54 An 8th place prize is embedded.

[0275] Conductors 546 and 548 are connected to the capacitive element 600, the transistor 500, or It functions as a plug or wiring for connecting to transistor 550. Conductor 546 , and conductor 548 are provided using the same material as conductor 328 and conductor 330. It is possible.

[0276] Furthermore, after the formation of the transistor 500, an opening is formed to surround the transistor 500. An insulator with high barrier properties against hydrogen or water may be formed to cover the opening. By encasing the transistor 500 in the aforementioned highly barrier-type insulator, moisture from the outside is prevented... And it can prevent hydrogen from entering. Or, multiple transistors 500 They may be encapsulated together in an insulator with high barrier properties against hydrogen or water. When forming an opening to surround the transistor 500, for example, an insulator 522 or an insulator An opening is formed that reaches 514, and the above-mentioned bar is made to contact the insulator 522 or the insulator 514. By forming a highly reflective insulator, it can also serve as part of the manufacturing process for transistor 500. Therefore, it is suitable. Furthermore, an insulator with high barrier properties against hydrogen or water is, for example, Alternatively, the same material as insulator 522 or insulator 514 may be used.

[0277] Next, a capacitive element 600 is provided above the transistor 500. 600 comprises a conductor 610, a conductor 620, and an insulator 630.

[0278] Furthermore, a conductor 612 may be provided on the conductor 546 and the conductor 548. 612 functions as a plug or wire connecting to transistor 500. The electric element 610 functions as an electrode for the capacitive element 600. Furthermore, the conductor 612, and The conductor 610 can be formed simultaneously.

[0279] Conductors 612 and 610 contain molybdenum, titanium, tantalum, and tungsten. Metal film containing elements selected from aluminum, copper, chromium, neodymium, and scandium. , or metal nitride films containing the above-mentioned elements (tantalum nitride film, titanium nitride film, nitride film) Molybdenum film, tungsten nitride film, etc. can be used. Alternatively, indium stinic acid Indium oxides containing tungsten oxide, indium oxides containing tungsten oxide, indium tungsten oxide Lead oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, Suitable conductive materials include indium zinc oxide and indium tin oxide with added silicon dioxide. It can also be used.

[0280] In this embodiment, the conductor 612 and the conductor 610 are shown in a single-layer configuration, but The structure is not limited to a single layer, and may consist of two or more layers. For example, a conductive material with barrier properties and a conductive material. A conductor with barrier properties between a highly conductive material and a highly conductive material. A conductive material with high adhesion may be formed.

[0281] The conductor 620 is provided so as to overlap with the conductor 610 via the insulator 630. The conductor 620 uses a conductive material such as a metal material, alloy material, or metal oxide material. High-melting-point materials such as tungsten and molybdenum that offer both heat resistance and conductivity. It is preferable to use a conductor, and it is particularly preferable to use tungsten. When forming with other components, low-resistance metal materials such as Cu (copper) and Al (aluminium) are used. You can use something like "um" (um).

[0282] An insulator 640 is provided on the conductor 620 and the insulator 630. 40 can be provided using the same material as the insulator 320. Also, the insulator 640 is It may also function as a planarizing film that covers the uneven shape below it.

[0283] By using this configuration, semiconductor devices using transistors with oxide semiconductors This allows for miniaturization or high integration.

[0284] The configuration, structure, and methods shown in this embodiment are not described in other embodiments and examples. It can be used in appropriate combination with the composition, structure, method, etc.

[0285] (Embodiment 5) In this embodiment, each of the configurations of the arithmetic processing system 100 described in the above embodiment The configuration of the integrated circuit, including the above, will be explained with reference to Figures 23A and 23B.

[0286] Figure 23A illustrates the integrated circuit including each component of the arithmetic processing system 100. This is an example of a schematic diagram. The integrated circuit 390 shown in Figure 23A is the CPU 110 and semiconductor A portion of the circuitry of the accelerator described as device 10 is composed of OS transistors. By doing so, each circuit can be integrated into a single integrated circuit.

[0287] As shown in Figure 23A, in the CPU 110, the O is located on the upper layer of the CPU core 200. A backup circuit 222 can be provided in the layer containing the S transistor. Furthermore, as shown in Figure 23A, in the accelerator described as semiconductor device 10 In the upper layer of the layer having Si transistors that constitute the arithmetic circuit section 40, there are OS transistors. The memory circuit section 30 can be provided in a layer having the following characteristics. The layer containing the st is configured to include OS memory 300N, etc. As for 300N, in addition to the NOSRAM described in the above embodiment, DOSRAM can also be applied. This is possible. In addition, in the OS memory 300N, it is provided in the layer having Si transistors. By stacking layers containing OS transistors on the drive circuit, the memory density is improved. It is possible.

[0288] As shown in Figure 23A, the accelerator described as CPU 110 and semiconductor device 10 In the case of an SoC in which various circuits such as the data processor and OS memory 300N are tightly coupled, there is a problem of heat generation. However, OS transistors have a smaller variation in electrical properties due to heat compared to Si transistors. Therefore, it is suitable. Also, as shown in Figure 23A, the circuit is integrated in three dimensions. By doing so, through silicon vias (TSVs) Compared to laminated structures using ) etc., parasitic capacitance can be reduced. This reduces the power consumption required for discharge. Therefore, it improves the efficiency of computational processing. It is possible.

[0289] Figure 23B shows an example of a semiconductor chip incorporating the integrated circuit 390. The semiconductor chip 391 has a lead 392 and an integrated circuit 390. The integrated circuit 390 is As explained in Figure 23A, the various circuits shown in the above embodiment are provided on one die. The integrated circuit 390 has a stacked structure, and the layer containing the Si transistor (Si transistor Layer 393), wiring layer 394, layer having OS transistors (OS transistor layer 395 They are broadly classified into the following. The OS transistor layer 395 is stacked on the Si transistor layer 393. Because it can be provided, the semiconductor chip 391 can be easily miniaturized.

[0290] Figure 23B shows that the semiconductor chip 391 is packaged in a QFP (Quad Flat Packet) package. The package is applied, but the package configuration is not limited to this. Other configurations Examples include the DIP (Dual In-line Package), which is an in-place insertion type. PGA (Pin Grid Array), surface mount type SOP (Small Outlet) tline Package), SSOP(Shrink Small Outline Package), TSOP (Thin-Small Outline Packag) e), LCC (Leaded Chip Carrier), QFN (Quad Fla tNon-leaded package), BGA(Ball Grid Arra y), FBGA (Fine pitch Ball Grid Array), Contact implementation The types are DTP (Dual Tape Carrier Package) and QTP (Q Structures such as the uad Tape-carrier Package can be used as appropriate. ru.

[0291] An arithmetic circuit and a switching circuit having Si transistors, and a memo having OS transistors. The recirculation consists entirely of Si transistor layer 393, wiring layer 394, and OS transistor layer 3 It can be formed at 95. That is, the elements constituting the above semiconductor device are manufactured by the same manufacturer. It is possible to form them in the process. Therefore, the IC shown in Figure 23B is composed of elements Even if the number increases, there is no need to increase the manufacturing process, and the above semiconductor devices can be incorporated at low cost. It is possible.

[0292] The present invention, according to one aspect described above, provides a novel semiconductor device and electronic device. This is possible. Alternatively, according to one aspect of the present invention, semiconductor devices and electronic devices with low power consumption can be made. It can be provided. Or, according to one aspect of the present invention, a semiconductor device capable of suppressing heat generation. We can provide electronic equipment.

[0293] This embodiment can be appropriately combined with descriptions of other embodiments.

[0294] (Embodiment 6) In this embodiment, the integrated circuit 390 described in the above embodiment can be applied. Electronic devices, mobile devices, and computing systems will be explained with reference to Figures 24 through 27.

[0295] Figure 24A shows an external view of an automobile as an example of a mobile device. Figure 24B shows an automobile. This is a simplified diagram illustrating the data exchange within the vehicle. The vehicle 590 has multiple cameras 591, etc. It has infrared radar, millimeter-wave radar, and laser radar. It is equipped with various sensors (not shown), etc.

[0296] In the automobile 590, the above integrated circuit 390 (or the above integrated circuit) is installed in the camera 591, etc. A semiconductor chip 391) incorporating 390 can be used. The automobile 590 is a turtle The multiple images obtained in multiple imaging directions 592 in the RA 591 are integrated as described in the above embodiment. The circuit 390 processes the data, and the host controller 594, etc., processes it via the bus 593, etc., and multiple images are sent to the host controller 594, etc. By analyzing the images together, we can determine the surrounding traffic conditions, such as the presence of guardrails and pedestrians. It can perform autonomous driving. It can also be used in systems that provide road guidance and predict hazards. It is possible.

[0297] The integrated circuit 390 processes the obtained image data using computational methods such as neural networks. By doing so, for example, image resolution can be increased, image noise can be reduced, and facial recognition (for security purposes, etc.) can be performed. Object recognition (for purposes such as autonomous driving), image compression, image correction (wide dynamic range), Image restoration, positioning, character recognition, and reflection reduction processing for lensless image sensors. It is possible to do so.

[0298] In the above, an automobile was described as an example of a moving object, but the moving object is an automobile. It is not limited to these. For example, examples of moving objects include trains, monorails, ships, and aircraft (helicopters). Other examples include unmanned aerial vehicles (drones), airplanes, and rockets, and these can be moved By applying a computer according to one aspect of the present invention to a moving object, a system utilizing artificial intelligence is provided. It is possible.

[0299] Figure 25A is an external view showing an example of a portable electronic device. Figure 25B is a portable electronic device. This is a simplified diagram of data exchange within the device. The portable electronic device 595 uses printed circuit boards. It includes a circuit board 596, a speaker 597, a camera 598, a microphone 599, etc.

[0300] In the portable electronic device 595, the above integrated circuit 390 is provided on the printed wiring board 596. It is possible. The portable electronic device 595 has a speaker 597, a camera 598, and a micro Multiple data obtained from Phon 599, etc., are used with the integrated circuit 390 described in the above embodiment. By processing and analyzing the data, user convenience can be improved. Additionally, voice guidance is available. It can be used in systems that perform image searches and other similar tasks.

[0301] The integrated circuit 390 processes the obtained image data using computational methods such as neural networks. By doing so, for example, image resolution can be increased, image noise can be reduced, and facial recognition (for security purposes, etc.) can be performed. Object recognition (for purposes such as autonomous driving), image compression, image correction (wide dynamic range), Image restoration, positioning, character recognition, and reflection reduction processing for lensless image sensors. It is possible to do so.

[0302] The portable game console 1100 shown in Figure 26A consists of a casing 1101, a casing 1102, and a casing 110 3. It has a display unit 1104, a connection unit 1105, an operation key 1107, etc. Housing 1101, enclosure Body 1102 and housing 1103 are removable. Provided in housing 1101 By attaching the connection part 1105 to the housing 1108, the output is displayed on the display unit 1104. The video can be output to another video device. On the other hand, housing 1102 and housing 1103 By attaching it to housing 1109, housings 1102 and 1103 are integrated, and operation To function as a part. Chips provided on the circuit boards of housing 1102 and housing 1103 The integrated circuit 390 shown in the previous embodiment can be incorporated into any of these.

[0303] Figure 26B shows a USB-connected stick-type electronic device 1120. 20 consists of the housing 1121, the cap 1122, the USB connector 1123, and the circuit board 1124. The circuit board 1124 is housed in the housing 1121. For example, the circuit board 1124 has A memory chip 1125 and a controller chip 1126 are mounted on board 11. The 24 controller chips 1126 and the like incorporate the integrated circuit 390 shown in the previous embodiment. It is possible.

[0304] Figure 26C shows a humanoid robot 1130. The robot 1130 is equipped with sensors 2101 to It has 2106 and a control circuit 2110. For example, the control circuit 2110 has a previous embodiment The integrated circuit 390 shown in the form can be incorporated.

[0305] The integrated circuit 390 described in the above embodiment is not built into an electronic device, but rather... It can also be used as a server to communicate with. In this case, it is performed by electronic devices and the server. The calculation system is configured. Figure 27 shows an example of the configuration of system 3000.

[0306] System 3000 consists of electronic equipment 3001 and server 3002. Communication between the child device 3001 and the server 3002 is performed via the internet connection 3003. It is possible.

[0307] Server 3002 has multiple racks 3004. Multiple racks contain multiple bases A board 3005 is provided, and the integrated circuit 390 described in the above embodiment is placed on the substrate 3005. This allows the server 3002 to be equipped with a neural network. And the server 3002 connects to the internet line 30 from the electronic device 3001. The neural network can perform calculations using the data input via 03. The results of the calculations performed by server 3002 will be transmitted to the internet connection 3003 as needed. This allows it to be transmitted to the electronic device 3001 via. This can reduce the computational burden.

[0308] This embodiment can be appropriately combined with descriptions of other embodiments.

[0309] (Notes regarding the descriptions in this specification, etc.) The above embodiments and a description of each component in those embodiments are provided below. .

[0310] The configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments or examples. This can be one embodiment of the present invention. Furthermore, multiple configurations can be included in one embodiment. When examples are provided, it is possible to combine the example configurations as appropriate.

[0311] Furthermore, the content described in one embodiment (even a part of it) may be subject to change in implementation. Other content (even partial content) described in form, and / or one or more other The contents described in the embodiment (even if only some of the contents) may be applied, combined, or It is possible to perform substitutions, etc.

[0312] Furthermore, the content described in each embodiment refers to the use of various figures in each embodiment. This refers to the content described or the content described using the text included in the specification.

[0313] Note that a diagram (even a part of it) described in one embodiment may be a part of that diagram. , another figure (even a part of it) described in that embodiment, and / or one or This involves combining the figures (or even just some of them) described in multiple other embodiments. This allows for the creation of even more diagrams.

[0314] Furthermore, in this specification, etc., block diagrams classify components according to their function and treat them as independent of each other. It is shown as a block. However, in actual circuits, the components are arranged functionally. It is difficult to separate the functions, and when multiple functions are involved in a single circuit, or when multiple circuits are involved... In some cases, one function may be involved. Therefore, the blocks in the block diagram are specified in the specification. The components described are not limited to those explained, and can be appropriately rephrased depending on the situation.

[0315] Furthermore, in the drawings, the size, layer thickness, or area may be arbitrarily depicted for the sake of explanation. This is what is shown. Therefore, it is not necessarily limited to that scale. Note that the drawings are for clarity. This is a schematic representation for illustrative purposes only and is not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or timing discrepancies. This can include variations in signals, voltages, or currents.

[0316] Furthermore, the positional relationships of the components shown in drawings are relative. Therefore, drawings When referring to and explaining the components, terms such as "above" and "below" that indicate positional relationships are for convenience. It may be used in this way. The positional relationship of the components is not limited to what is described herein, and may vary. It can be rephrased appropriately depending on the situation.

[0317] In this specification and other documents, when describing the connection relationships of transistors, the term "source or drain" is used. One side of the source is called the first electrode, or the first terminal, and the other side of the source and drain is called the source The notation used is "the other side of the drain" (or second electrode, or second terminal). The source and drain of a transistor can vary depending on the transistor's structure or operating conditions. This is for the purpose of dividing. Regarding the terms source and drain of a transistor, source (drain) Depending on the context, terms such as "in" terminal or "source (drain) electrode" can be appropriately rephrased. .

[0318] Furthermore, in this specification, the terms "electrode" and "wiring" refer to these components functionally. It is not limited to this. For example, "electrode" can be used as part of "wiring". And the reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes" and This includes cases where the wiring is formed as an integrated unit.

[0319] Furthermore, in this specification, voltage and potential may be used interchangeably as appropriate. Voltage is a base This refers to the potential difference from a reference potential. For example, the reference potential is the ground voltage (earth). If we consider voltage as a unit of measurement, then voltage can be rephrased as potential. Ground potential is not necessarily 0V. This does not necessarily mean that. Furthermore, electric potential is relative, and depending on the reference potential, This may change the potential supplied to wiring, etc.

[0320] Furthermore, in this specification, a node is defined as having terminals and wiring, depending on the circuit configuration and device structure. These can be rephrased as electrodes, conductive layers, conductors, impurity regions, etc. Also, terminals, distribution Lines and other elements can be rephrased as nodes.

[0321] In this specification, etc., "A and B are connected" means that A and B are electrically connected. This refers to things that are electrically connected. Here, A and B are said to be electrically connected to each other. The object (a switch, transistor element, or diode or other element, or said element and A connection (referring to a circuit including wiring, etc.) that allows electrical signals to be transmitted between A and B is possible when such a connection exists. This refers to a continuation. Furthermore, if A and B are electrically connected, then A and B are directly connected. This includes cases where A and B are directly connected. Here, A and B are said to be directly connected via the above-mentioned object. However, it is possible to transmit electrical signals between A and B via wiring (or electrodes), etc. It refers to a certain type of connection. In other words, a direct connection is a connection that, when represented in an equivalent circuit, looks like the same circuit diagram. It refers to a connection that can be made.

[0322] In this specification, a switch means a conductive state (on state) or a non-conductive state (off state). It refers to a device that enters a state (F) and has the function of controlling whether or not to allow current to flow. Or, A switch is a device that has the function of selecting and switching the path through which electric current flows.

[0323] In this specification, channel length refers, for example, to the length of a semiconductor in a top view of a transistor. The body (or the part of the semiconductor through which current flows when the transistor is ON) and the gate The distance between the source and drain in the region where they overlap, or in the region where a channel is formed. It means separation.

[0324] In this specification, channel width refers to, for example, the state in which a semiconductor (or transistor) is ON. The region where the part of the semiconductor through which current flows and the gate electrode overlap when the semiconductor is in a certain state, or the channel This refers to the length of the portion where the source and drain face each other in the region where the drain is formed. .

[0325] In this specification, the terms "film," "layer," etc. may be used in some cases, or in some cases, in a manner. Depending on the situation, they can be interchanged. For example, the term "conductive layer" can be replaced with " In some cases, the term can be changed to "conductive film." Or, for example, "insulating film." In some cases, it is possible to change the term "insulating layer" to "insulating layer." [Explanation of symbols]

[0326] C11: Capacitor element, CK1: Node, D1: Node, GCLK1: Clock signal, LBL _n: wiring, LBL_N: wiring, LBL_1: wiring, LBL_4: wiring, LBL_6: wiring Line, M11: Transistor, M12: Transistor, M13: Transistor, PSE0: Signal, PSE1: Signal, PSE2: Signal, Q1: Node, RWL_M: Read word line, RWL_1: Read word line, SLEEP1: Signal, SN11: Node, t1: Time, t 2: Time, t3: Time, t4: Time, t5: Time, t6: Time, t7: Time, T0: Time T1: Time, T6: Time, WBL_1: Write bit line, WWL_M: Write word line WWL_1: Word line for writing, 10: Semiconductor device, 12: Drive circuit, 13: Drive circuit, 14: Control circuit, 15: Processing circuit, 20: Arithmetic block, 21: Transistor, 22: Semiconductor Conductor layer, 23: Transistor, 24: Semiconductor layer, 30: Memory circuit section, 31: Circuit block K, 32: memory circuit, 32_N: memory circuit, 32_P: memory circuit, 32A: memory Circuit, 32B: Memory circuit, 32C: Memory circuit, 40: Arithmetic circuit section, 41: Switching circuit, 42: Multiply-accumulate operation circuit, 43: Activation function operation circuit, 44: Quantization operation circuit, 44_1: Quantity Quantization arithmetic circuit, 44_9: Quantization arithmetic circuit, 45: Pre-pooling arithmetic circuit, 47: Pos Toppooling arithmetic circuit, 46: Dedicated arithmetic circuit, 46_1: Dedicated arithmetic circuit, 46_2: Dedicated Arithmetic circuits, 46_3: Dedicated arithmetic circuits, 51: Multiplication circuits, 52: Addition circuits, 53: Registers 54: Multiplexer, 55: Comparator circuit, 56: Resistor, 61: Transistor, 61 _N: Transistor, 61_P: Transistor, 61A: Transistor, 61B: Transistor Zista, 62: Transistor, 62_N: Transistor, 62_P: Transistor, 62 B: Transistor, 63: Transistor, 63_N: Transistor, 63_P: Transistor Sta, 64: Capacitive element, 64_N: Capacitive element, 64_P: Capacitive element, 64A: Capacitive element, 64B: Capacitive element, 100: Arithmetic processing system, 110: CPU, 120: Bus, 130 :Accelerator unit, 131:Control unit, 193:PMU, 200:CPU core, 202: Cache memory device, 203: Cache memory device, 205: Bus interface Part, 210: Power switch, 211: Power switch, 212: Power switch, 21 4: Level shifter, 220: Flip-flop, 221: Scan flip-flop, 2 21A: Clock buffer circuit, 222: Backup circuit, 300N: OS memory, 3 11: Substrate, 312: Well area, 313: Insulator, 314: Oxide layer, 315: Semiconductor region, 316a: low resistance region, 316b: low resistance region, 316c: low resistance region, 317: Insulator, 318: Conductor, 320: Insulator, 322: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 360: Insulator, 362: Insulator, 364: Insulator, 366: Conductor, 370: Insulator, 372: Insulator, 374: Insulator, 376: Conductor, 380: Insulator, 382: Insulator, 384: Insulator, 386: Conductor, 390: Integrated circuit, 391 : Semiconductor chip, 392: Lead, 393: Si transistor layer, 394: Wiring layer, 39 5: OS transistor layer, 500: transistor, 503: conductor, 503a: conductor, 503b: Conductor, 510: Insulator, 512: Insulator, 514: Insulator, 516: Insulator 518: Conductor, 522: Insulator, 524: Insulator, 530: Oxide, 530a: Oxide Material, 530b: Oxide, 540a: Conductor, 540b: Conductor, 542: Conductor, 542 a: Conductor, 542b: Conductor, 543a: Region, 543b: Region, 544: Insulator, 5 45: Insulator, 546: Conductor, 548: Conductor, 550: Transistor, 560: Conductor Body, 560a: Conductor, 560b: Conductor, 574: Insulator, 580: Insulator, 581: Insulator, 582: Insulator, 586: Insulator, 590: Automobile, 591: Camera, 592: Imaging direction, 593: bus, 594: host controller, 595: portable electronic device, 59 6: Printed circuit board, 597: Speaker, 598: Camera, 599: Microphone 600: Capacitive element, 610: Conductor, 612: Conductor, 620: Conductor, 630: Insulator Body, 640: Insulator, 1100: Portable game console, 1101: Casing, 1102: Casing, 1 103: Enclosure, 1104: Display unit, 1105: Connection unit, 1107: Operation keys, 1108: Enclosure, 1109: Enclosure, 1120: Electronic equipment, 1121: Enclosure, 1122: Cap, 1 123: USB connector, 1124: circuit board, 1125: memory chip, 1126: controller Roller tip, 1130: robot, 2101: sensor, 2106: sensor, 2110: Control circuits, 3000: Systems, 3001: Electronic equipment, 3002: Servers, 3003: Internet connection, 3004: rack, 3005: circuit board

Claims

1. It has a first layer having a memory circuit section, a second layer having an arithmetic circuit section, a control circuit, a first wiring, and a second wiring, The first layer is placed on the second layer, The first layer comprises a first memory circuit and a second memory circuit. The second layer includes a switching circuit, a multiply-accumulate circuit, an activation function circuit, a quantization circuit, a pre-pooling circuit, a processing circuit, and a third wiring. The first and second wiring each have regions that extend in a direction substantially perpendicular to the second layer, The first memory circuit is electrically connected to the switching circuit via the first wiring, The second memory circuit is electrically connected to the switching circuit via the second wiring, The switching circuit is electrically connected to the sum-of-accumulate circuit via the third wiring. The switching circuit switches the electrical connection between the first wiring and the second wiring. The sum-of-products circuit performs a sum-of-products operation on the first data input from the control circuit and the weight data provided to the third wiring. The activation function calculation circuit performs processing based on the activation function on the second data obtained by the sum-of-accumulate calculation circuit. The quantization operation circuit has the function of reducing the bit width of the third data input from the activation function operation circuit. The pre-pooling calculation circuit has the function of performing a first partial pooling calculation, A semiconductor device having a post-pooling calculation circuit in the processing circuit that performs a second pooling calculation using the output data obtained by the pre-pooling calculation circuit.

2. In claim 1 or 2, The transistors in the first memory circuit and the second memory circuit are semiconductor devices having a semiconductor layer containing a metal oxide.

3. In claim 2, The aforementioned metal oxide comprises In, Ga, and Zn, and is a semiconductor device.

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