Techniques for performing outer product operations

JP2025519452A5Pending Publication Date: 2026-05-25ARM LTD
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Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
ARM LTD
Filing Date
2023-05-23
Publication Date
2026-05-25

AI Technical Summary

Technical Problem

Existing data processing systems face inefficiencies in performing outer product operations due to suboptimal utilization of array storage devices and processing circuitry resources.

Method used

The implementation of a processing circuit with an instruction decoder that performs multiple outer product operations using sub-vectors within source vector operands, storing results in a two-dimensional array within an array storage device.

Benefits of technology

This approach enhances processing efficiency and throughput by enabling multiple outer product operations to be performed in response to a single instruction, while optimizing the use of memory elements and hardware resources.

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Abstract

The apparatus includes a processing circuit that performs vector operations, an instruction decoder that decodes instructions for controlling the processing circuit to perform associated vector operations, and an array storage device that includes storage elements for storing data elements, the array storage device storing at least one two-dimensional array of data elements. The instruction set includes a multiple outer product instruction that identifies a given two-dimensional array of data elements within the array storage device that forms a first source vector operand, a second source vector operand, and a destination operand. At least the first source vector operand identifies at least one vector of data elements treated as including a plurality of sub-vectors, and at least the second source vector operand identifies a plurality of vectors of data elements. In response to the multiple outer product instruction, the instruction decoder controls the processing circuit to perform an outer product operation for each sub-vector identified by the first source vector operand. Each outer product operation includes multiplying each data element of an associated group of data elements selected from the second source vector operand by each data element of an associated sub-vector identified by the first source vector operand to generate a plurality of outer product results, and updating values held in associated storage elements within a given two-dimensional array of the storage elements using each outer product result. A selection circuit controls the selection of data elements processed by each outer product operation to switch vectors of the second source vector operand when switching between different sub-vectors within a given vector of the first source vector operand.
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