Liquid crystal display device

Abstract

When a semiconductor layer is provided on a gate electrode layer, a source electrode layer, and a drain electrode layer, However, one of the objectives is to improve the characteristics of the element and to improve the reliability of the element. . [Solution] A gate electrode layer, a gate insulating layer provided on the gate electrode layer, and gate insulating Source electrode layer and drain electrode, provided so as to overlap a portion of the gate electrode layer through a layer. It has a layer, a gate insulating layer, a source electrode layer, and a semiconductor layer provided on the drain electrode layer. In the structure, the thickness of the gate insulating layer located in the region between the source electrode layer and the drain electrode layer. The gate insulating layer and the gate electrode layer are provided between the gate electrode layer and the source electrode layer. It is provided so as to be smaller than the thickness of the gate insulating layer provided between the in electrode layers.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background Art

[0002] In recent years, techniques for fabricating thin film transistors (also referred to as TFTs) using oxide semiconductors and applying them to electronic devices etc. have attracted attention. For example, in Patent Document 1 and Patent Document 2, zinc oxide, In-Ga-Zn-O-based oxide semiconductors, etc. are used as the oxide semiconductor layer to fabricate switching elements of image display devices and the like.

[0003] In addition, various structures have been proposed as the structure of transistors using an oxide semiconductor layer. For example, in Patent Document 2 and Patent Document 3 described above, a bottom gate-bottom contact structure in which an oxide semiconductor layer is formed on a source electrode layer and a drain electrode layer provided on a gate insulating layer is shown. [[ID=3)]

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0005] Generally, in order to reduce the driving voltage of a transistor and perform high-speed operation, the Reducing the film thickness is effective. However, the bottom gate / bottom contact type structure In this configuration, the gate electrode layer, the source electrode layer, and the drain electrode layer are separated by a gate insulating layer. In the case of partial overlap, as the thickness of the gate insulating layer decreases, the gate electrode layer and the saw Parasitic capacitance may form between the drain electrode layer and the drain electrode layer, potentially affecting the device characteristics. Yes, this can result in variations in the device characteristics, potentially reducing the reliability of the device.

[0006] Furthermore, the source electrode layer and drain electrode layer cover the edges of the gate electrode layer via the gate insulating layer. When an electrode layer is provided, the thickness of the gate insulating layer covering the edge of the gate electrode layer is small. This can lead to a problem where leakage becomes more likely between the gate electrode layer and the source or drain electrode layer. This occurs.

[0007] In view of the above problem, the semiconductor layer is provided on the gate electrode layer, source electrode layer, and drain electrode layer. Even in such cases, the aim is to improve the element characteristics and the reliability of the element. Let it be one. [Means for solving the problem]

[0008] A gate electrode layer, a gate insulating layer provided on the gate electrode layer, and through the gate insulating layer The source electrode layer and drain electrode layer are provided so as to overlap a part of the gate electrode layer, The structure has a semiconductor layer provided on a source insulating layer, a source electrode layer, and a drain electrode layer. And the thickness of the gate insulating layer located in the region between the source electrode layer and the drain electrode layer is A gate insulating layer or gate electrode layer and a drain electrode are provided between the electrode layer and the source electrode layer. It is provided so that its thickness is smaller than the thickness of the gate insulating layer provided between the pole layers. In this case, saw To reduce the parasitic capacitance that occurs between the drain electrode layer and the gate electrode layer, and This allows for improved element characteristics.

[0009] Furthermore, one aspect of the disclosed invention is a gate electrode layer provided on a substrate, and on the gate electrode layer A gate insulating layer is provided, and a portion of the gate electrode layer is provided so as to overlap with the gate insulating layer. The source electrode layer and drain electrode layer are provided, and the gate electrode layer is on the source electrode layer and drain It is provided in contact with the gate insulating layer located in the region between the rain electrode layers, and the source electrode layer and The device has an oxide semiconductor layer provided on the drain electrode layer, and the gate electrode layer is on the source The thickness of the gate insulating layer located in the region between the electrode layer and the drain electrode layer is such that the gate electrode layer and the drain electrode layer are different. A gate insulating layer provided between the electrode layers or between the gate electrode layer and the drain electrode layer It is characterized by being smaller than the thickness of the gate insulating layer.

[0010] Furthermore, one aspect of the disclosed invention is a gate electrode layer provided on a substrate, and on the gate electrode layer A first insulating layer is provided, and on the first insulating layer, overlapping with a part of the gate electrode layer A second insulating layer is provided therein, and one of the gate electrode layers is connected via the first insulating layer and the second insulating layer. A source electrode layer and a drain electrode layer are provided so as to overlap with the part, and on the gate electrode layer It is provided in contact with a first insulating layer located in the region between the source electrode layer and the drain electrode layer, Furthermore, it is characterized by having an oxide semiconductor layer provided on the source electrode layer and the drain electrode layer. It is stated that the region on the gate electrode layer, between the source electrode layer and the drain electrode layer, The thickness of the first insulating layer located therein is provided between the gate electrode layer and the source electrode layer Smaller than the film thickness of the first insulating layer provided between the edge layer or the gate electrode layer and the drain electrode layer It may be.

[0011] Also, one aspect of the disclosed invention is a gate electrode layer provided on a substrate, and on the gate electrode layer A first insulating layer and a second insulating layer laminated in sequence, and the first insulating layer and the second insulating layer A source electrode layer and a drain electrode layer provided so as to overlap a part of the gate electrode layer through And a second located in a region between the source electrode layer and the drain electrode layer on the gate electrode layer An oxide semiconductor layer provided in contact with the insulating layer and provided on the source electrode layer and the drain electrode layer Having, located in a region between the source electrode layer and the drain electrode layer on the gate electrode layer The film thickness of the second insulating layer is smaller than the film thickness of the second insulating layer provided between the gate electrode layer and the source electrode layer And the film thickness of the second insulating layer provided between the gate electrode layer and the drain electrode layer It is characterized by that.

[0012] Also, one aspect of the disclosed invention is to form a gate electrode layer on a substrate, and a gate on the gate electrode layer Form an insulating layer, form a source electrode layer and a drain electrode layer on the gate insulating layer, and source By etching the upper layer portion of the gate insulating layer provided in the region between the electrode layer and the drain electrode layer The film thickness of the gate insulating layer located in the region between the source electrode layer and the drain electrode layer is Smaller than the film thickness of the gate insulating layer provided between the gate electrode layer and the source electrode layer or the gate insulating layer provided between the gate electrode layer and the drain An electrode layer, and forming an oxide semiconductor layer on the gate insulating layer, the source electrode layer and the drain electrode layer It is characterized by that.

[0013] Furthermore, one aspect of the disclosed invention involves forming a gate electrode layer on a substrate, and on the gate electrode layer, a first An insulating layer is formed, a second insulating layer is formed on the first insulating layer, and a source electric current is placed on the second insulating layer. A polar layer and a drain electrode layer are formed and provided in the region between the source electrode layer and the drain electrode layer. By etching the second insulating layer, the first insulating layer is exposed, and the first insulating layer, The invention is characterized by forming an oxide semiconductor layer on the drain electrode layer and the drain electrode layer.

[0014] An example of an oxide semiconductor that can be used in this specification is InMO3(Zn O) m There are some that are expressed as (m>0, m is not necessarily an integer). Here, M is Iron (Ga), iron (Fe), nickel (Ni), manganese (Mn), and cobalt (Co This indicates one or more metallic elements selected from ). For example, Ga is selected as M. In addition to the case of Ga alone, other metals such as Ga and Ni, or Ga and Fe, are also used. This includes cases where a group element is selected. Also, in the above oxide semiconductor, gold is included as M. In addition to the group elements, impurity elements include Fe, Ni, and other transition metal elements, or acids of said transition metals. Some contain oxides. In this specification, among the above oxide semiconductors, M is referred to as Materials containing at least gallium are called In-Ga-Zn-O oxide semiconductors, and the said material Thin films using this material are called In-Ga-Zn-O non-single-crystal films.

[0015] In this specification, a semiconductor device refers to a device that can function by utilizing semiconductor properties. This term encompasses a wide range of electronic devices, including electro-optical devices, semiconductor circuits, and electronic equipment. Furthermore, in this specification, "display device" includes light-emitting devices and liquid crystal display devices. Light-emitting devices emit light A liquid crystal display device includes a liquid crystal element. The light-emitting element's brightness is determined by current or voltage. This category includes elements whose properties are controlled, specifically inorganic EL (Electroluminescent Luminous Light). This includes minescence elements, organic EL elements, etc. [Effects of the Invention]

[0016] A gate electrode layer, a gate insulating layer provided on the gate electrode layer, and through the gate insulating layer The source electrode layer and drain electrode layer are provided so as to overlap a part of the gate electrode layer, The structure has a semiconductor layer provided on a source insulating layer, a source electrode layer, and a drain electrode layer. And the thickness of the gate insulating layer located in the region between the source electrode layer and the drain electrode layer is A gate insulating layer or gate electrode layer and a drain electrode are provided between the electrode layer and the source electrode layer. By providing it so that the thickness is smaller than the thickness of the gate insulating layer provided between the pole layers, To reduce the parasitic capacitance that occurs between the drain electrode layer and the gate electrode layer, and This allows for improved element characteristics. [Brief explanation of the drawing]

[0017] [Figure 1] A diagram illustrating an example of a semiconductor device according to Embodiment 1 or Embodiment 2. [Figure 2] A diagram illustrating an example of a method for manufacturing a semiconductor device according to Embodiment 1. [Figure 3] A diagram illustrating an example of a method for manufacturing a semiconductor device according to Embodiment 2. [Figure 4] A diagram illustrating an example of an apparatus used for plasma processing according to Embodiment 2. [Figure 5] A diagram illustrating an example of a semiconductor device according to Embodiment 3. [Figure 6] A diagram illustrating an example of a method for manufacturing a semiconductor device according to Embodiment 3. [Figure 7] A diagram illustrating an example of a semiconductor device according to Embodiment 4. [Figure 8] A diagram illustrating an example of a method for manufacturing a semiconductor device according to Embodiment 4. [Figure 9] A diagram illustrating an example of a method for manufacturing a semiconductor device according to Embodiment 5. [Figure 10] A diagram illustrating an example of a method for manufacturing a semiconductor device according to Embodiment 5. [Figure 11] A diagram illustrating an example of a method for manufacturing a semiconductor device according to Embodiment 5. [Figure 12] A diagram illustrating an example of a method for manufacturing a semiconductor device according to Embodiment 5. [Figure 13] A diagram illustrating an example of a method for manufacturing a semiconductor device according to Embodiment 5. [Figure 14] A diagram illustrating an example of a method for manufacturing a semiconductor device according to Embodiment 5. [Figure 15] A diagram illustrating an example of a method for manufacturing a semiconductor device according to Embodiment 5. [Figure 16] A diagram illustrating an example of a semiconductor device according to Embodiment 6. [Figure 17] A diagram illustrating an example of a semiconductor device according to Embodiment 6. [Figure 18] A diagram illustrating an example of a semiconductor device according to Embodiment 7. [Figure 19] A diagram illustrating an example of a pixel equivalent circuit of a semiconductor device according to Embodiment 8. [Figure 20] A diagram illustrating an example of a semiconductor device according to Embodiment 8. [Figure 21] A diagram illustrating an example of a semiconductor device according to Embodiment 8. [Figure 22] A diagram illustrating an example of how electronic paper can be used. [Figure 23] An external view showing an example of an e-book. [Figure 24] External view showing examples of television equipment and digital photo frames. [Figure 25] An external view showing an example of a gaming machine. [Figure 26]An external view showing an example of a mobile phone. [Modes for carrying out the invention]

[0018] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following embodiments. The description of the form is not limited to the actual form, and the form and details may be changed in various ways without departing from the spirit of the invention. It is obvious to those skilled in the art that this is possible. Furthermore, configurations relating to different embodiments can be combined as appropriate. They can be implemented in combination. In addition, in the configuration of the invention described below, the same part Alternatively, the same symbol is used for parts with similar functions, and the explanation of their repetition is omitted.

[0019] (Embodiment 1) First, with reference to Figure 1(A), the configuration of the thin-film transistor shown in this embodiment will be explained. I will reveal it.

[0020] The thin-film transistor 250 shown in this embodiment has a gate electrode layer provided on the substrate 200. 202, gate insulating layer 204 provided on gate electrode layer 202 and substrate 200, A source electrode layer 206a and a drain electrode layer 206b are provided on the insulating layer 204, The source electrode layer 206a and the drain electrode layer 206b are provided on the source electrode layer 206 an acid is provided in contact with the gate insulating layer 204 located between a and the drain electrode layer 206b It has a ionized semiconductor layer 210. Furthermore, it has a source electrode layer 206a and a drain electrode layer 2 06b is provided so as to overlap a portion of the gate electrode layer 202 via the gate insulating layer 204. The gate insulating layer located in the region between the source electrode layer 206a and the drain electrode layer 206b The film thickness t2 of 204 is provided between the gate electrode layer 202 and the source electrode layer 206a. The gate is provided between the insulating layer 204 and the gate electrode layer 202 and the drain electrode layer 206b. It is provided so as to be smaller than the film thickness t1 of the insulating layer 204 (see Figure 1(A)).

[0021] In other words, in the region where the gate insulating layer 204 overlaps with the gate electrode layer 202, there is a recess (a depression ( The gate insulating layer 204 has a recess 207, and the recess 207 of the gate insulating layer 204 contains an oxide A semiconductor layer 210 is provided. Note that the recess 207 of the gate insulating layer 204 and When observed from the cross-sectional direction connecting the source electrode layer and the drain electrode layer, the gate insulating layer 20 This refers to the depression formed in area 4.

[0022] Thus, by using the configuration shown in Figure 1(A), the gate is placed on the gate electrode layer 202. The source electrode layer 206a and the drain electrode layer 206b are connected via the insulating layer 204 to the gate electrode The polar layer 202 is provided so as to partially overlap with the source electrode layer 206a and the drain electrode layer 20 Even when an oxide semiconductor layer 210 is provided on 6b, the source electrode layer 206a and Dre To reduce the parasitic capacitance that occurs between the in electrode layer 206b and the gate electrode layer 202, The drive voltage of the transistor can be reduced, improving the characteristics of the element.

[0023] Note that in Figure 1(A), both the source electrode layer 206a and the drain electrode layer 206b are gates. Although the case where the insulating layer 204 overlaps with a portion of the gate electrode layer 202 has been shown, this embodiment This is not limited to the above. Either the source electrode layer 206a or the drain electrode layer 206b When the gate electrode layer 202 overlaps with the gate insulating layer 204, the overlapping electrode layer The thickness t1 of the gate insulating layer 204 provided between the gate electrode layers 202 is the source electrode layer 2 The thickness t2 of the gate insulating layer 204 located in the region between 06a and the drain electrode layer 206b It should be made thicker.

[0024] Next, referring to Figure 2, one embodiment of the method for fabricating the thin-film transistor 250 shown in Figure 1(A) I will explain the details.

[0025] First, a gate electrode layer 202 is formed on the substrate 200, and then on the gate electrode layer 202 A gate insulating layer 204 is formed (see Figure 2(A)).

[0026] The substrate 200 can be any substrate having an insulating surface; for example, a glass substrate can be used. It is possible. The glass substrate is preferably an alkali-free glass substrate. Examples of glass substrates include aluminosilicate glass, aluminoborosilicate glass, and Glass materials such as lium borosilicate glass are used. In addition, as substrate 200, Insulating substrates made of ceramic substrates, insulators such as quartz substrates and sapphire substrates, silicon, etc. A semiconductor substrate made of semiconductor material, with its surface coated with an insulating material, such as a conductive material made of metal or stainless steel. A conductive substrate made of an electrolytic material can be used, in which the surface of the conductive substrate is coated with an insulating material. Plastic substrates can also be used, provided they can withstand the heat treatment during the manufacturing process.

[0027] The gate electrode layer 202 is formed by a photolithography method after a conductive layer has been formed over the entire surface of the substrate 200. It can be formed by etching the conductive layer using the following method. Guard electrode layer 202 This includes gate wiring and other electrodes and wiring formed by the conductive layer described above.

[0028] The gate electrode layer 202 is made of aluminum (Al), copper (Cu), molybdenum (Mo), and tan. It is preferable to form it with conductive materials such as Gusten (W) or Titanium (Ti). Furthermore, when using aluminum as an electrode, aluminum alone has low heat resistance and corrodes. Due to issues such as being prone to damage, it is preferable to form it in combination with a heat-resistant conductive material. .

[0029] Heat-resistant conductive materials include titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum. Selected from den (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc). Elements, alloys containing the above-mentioned elements, alloys combining the above-mentioned elements, or the above-mentioned It can be formed from nitrides composed of elements. Films made of these heat-resistant conductive materials. By laminating aluminum (or copper), wiring and electrodes can be formed.

[0030] Furthermore, the gate electrode layer 202 is applied to the substrate 200 using methods such as droplet ejection or screen printing. It is also possible to form them selectively.

[0031] The gate insulating layer 204 consists of a silicon oxide film, a silicon oxide nitride film, a silicon nitride film, and an acid nitride film. It can be formed from a silicon oxide film, an aluminum oxide film, or a tantalum oxide film, etc. These films may be layered together. These films are made to a thickness of 5 using a sputtering method or the like. It can be formed in a range of 0 nm to 250 nm. For example, as the gate insulating layer 204 By sputtering, a silicon oxide film can be formed to a thickness of 200 nm.

[0032] In this specification, silicon oxidnitride refers to a silicon oxide with a composition that contains more oxygen than nitrogen. It has a high content, and preferably, Rutherford backscattering (RBS: Rutherford (Fford Backscattering Spectrometry) and hydrogen forward Scattering method (HFS: Hydrogen Forwardscattering Spect When measured using rometry, the concentration range for oxygen is 50-70 atomic%, and for nitrogen, it is 50-70 atomic%, and for nitrogen, it is 50-70 atomic%, and for nitrogen, it is 50-70 atomic%, and for nitrogen, it is 50-70 atomic%, and for nitrogen, it is 50-70 atomic%, and for nitrogen, it is 50-70 atomic%, and for nitrogen, it is 50-70 atomic%, and for nitrogen, when measured using rometry, and for oxygen, it is 50-70 atomic%, and for nitrogen The range is 0.5-15 atomic percent for elemental material, 25-35 atomic percent for silicon, and 0.1-10 atomic percent for hydrogen. It refers to the substances contained within the enclosure. Furthermore, silicon nitride oxide, in terms of its composition, is composed of more nitrogen than oxygen. It is a substance with a high elemental content, and preferably when measured using RBS and HFS. The concentration ranges are 5-30 atomic percent for oxygen, 20-55 atomic percent for nitrogen, and 25-3 atomic percent for silicon. This refers to materials containing 5 atomic percent and hydrogen in the range of 10 to 30 atomic percent. However, silicate oxidnitridation When the total amount of atoms constituting CON or silicon nitride oxide is set to 100 atomic%, nitrogen and oxygen The content ratio of silicon and hydrogen shall be within the above range.

[0033] Next, a source electrode layer 206a and a drain electrode layer 206b are formed on the gate insulating layer 204. (See Figure 2(B)).

[0034] The source electrode layer 206a and the drain electrode layer 206b have a conductive layer on the gate insulating layer 204. After formation, the conductive layer is etched using photolithography to shape it. This can be achieved. Here, as an example, the source electrode layer 206a and the drain electrode layer 2 A portion of 06b is formed to overlap with the gate electrode layer 202 via the gate insulating layer 204. This illustrates the case.

[0035] The source electrode layer 206a and the drain electrode layer 206b are formed using sputtering, vacuum deposition, etc. Aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten Ten (W), Molybdenum (Mo), Chromium (Cr), Neodymium (Nd), Scandium ( Metals containing elements selected from Sc), alloys composed of the above elements, or the above elements It can be formed from a material consisting of nitrides or the like.

[0036] For example, the source electrode layer 206a and the drain electrode layer 206b are made of a molybdenum film or a titanium film. It can be formed as a single-layer structure. Also, the source electrode layer 206a and the drain electrode layer 2 06b may be formed in a laminated structure, for example, a laminated structure of an aluminum film and a titanium film. It is possible to stack a titanium film, an aluminum film, and a titanium film in that order. A layered structure is also possible. Alternatively, a molybdenum film, an aluminum film, and another molybdenum film can be layered in sequence. A three-layer structure may also be used. Furthermore, as the aluminum film used in these laminated structures, An aluminum (Al-Nd) film containing odium may also be used. Furthermore, the source electrode layer 20 6a and the drain electrode layer 206b can also be a single-layer structure of an aluminum film containing silicon. good.

[0037] Furthermore, the source electrode layer 206a and the drain electrode layer 206b are made using a droplet ejection method or screen printing. It is also possible to selectively form the material on the substrate 200 using a brushing method or the like.

[0038] The source electrode layer 206a formed in Figure 2(B) functions as the source of the transistor. Furthermore, the drain electrode layer 206b functions as the drain of the transistor. Depending on the drive method of the starter, the source electrode layer 206a may function as a drain, and the drain electricity It is also possible that polar layer 206b functions as a source.

[0039] Next, a gate insulating layer is provided in the region between the source electrode layer 206a and the drain electrode layer 206b. By performing an etching process on the upper part of the edge layer 204 (exposed gate insulating layer 204) A recess 207 is formed in the gate insulating layer 204 (see Figure 2(C)).

[0040] By performing an etching process, the source electrode layer 206a and the drain electrode layer 206b The thickness t2 of the gate insulating layer 204 located in the region between the gate electrode layer 202 and the source electrode The gate insulating layer 204 and gate electrode layer 202 are provided between the pole layers 206a and the drain The thickness t1 of the gate insulating layer 204 provided between the pole layers 206b can be made smaller. Preferably, the film thickness t2 of the gate insulating layer 204 is 1 / 5 to 4 / 5 of the film thickness t1 (t2 Let = t1 / 5 ~ 4t1 / 5.

[0041] Etching processes include plasma treatment using inert gas and / or reactive gas, Etching and other similar processes can be used.

[0042] Furthermore, in the etching process, the source electrode layer 206a and the drain electrode layer 206b are etched It can be used as a screw. In addition, the source electrode layer 206a and the drain electrode layer 20 The photomask used during the formation of 6b (Figure 2(B)) was used to create the edge of the gate insulating layer 204. Ching can also be performed. In this case, the source electrode layer 206a and the drain electrode layer 206 The gate insulating layer 204 that does not overlap with b is etched.

[0043] By performing an etching process, the film thickness of the gate insulating layer 204 is made to differ in each region. At the same time, impurities adhering to the surface of the exposed gate insulating layer 204, as well as impurity elements, are incorporated. The embedded surface layer can be removed (see Figure 2(C)).

[0044] Next, cover the gate insulating layer 204, the source electrode layer 206a and the drain electrode layer 206b A sea urchin oxide semiconductor layer 209 is formed (see Figure 2(D)).

[0045] The oxide semiconductor layer 209 can be formed from an In-Ga-Zn-O non-single crystal film. For example, an oxide semiconductor target containing In, Ga, and Zn (In2O3:Ga2O3) The oxide semiconductor layer 209 can be formed by sputtering using ZnO (1:1:1). Yes, it is possible. For sputtering conditions, for example, the distance between the substrate 200 and the target should be 30 mm. ~500mm, pressure 0.1Pa~2.0Pa, DC power supply 0.25kW~5. 0kW, temperature 20℃~100℃, atmosphere argon atmosphere, oxygen atmosphere, or argon A mixed atmosphere of oxygen can be created.

[0046] Furthermore, using a pulsed DC power supply can reduce dust and result in a more uniform film thickness distribution. Preferred. Furthermore, after the plasma treatment described above, the oxide semiconductor layer is not exposed to the atmosphere. By forming 209, dust can be placed at the interface between the gate insulating layer 204 and the oxide semiconductor layer 209. This can suppress the adhesion of moisture. Also, the thickness of the oxide semiconductor layer 209 is A range of approximately 5nm to 200nm is sufficient.

[0047] The sputtering methods mentioned above include RF sputtering, which uses a high-frequency power supply for sputtering, and direct DC sputtering method using a current power supply, pulsed DC sputtering method applying a DC bias in a pulsed manner These can be used.

[0048] Furthermore, when plasma treatment is used as the etching process, the plasma treatment and the oxide semiconductor layer It is preferable to perform the formation of 209 continuously within the same chamber. Exposing the surfaces of the insulating layer 204, source electrode layer 206a, and drain electrode layer 206b to the atmosphere By forming the oxide semiconductor layer 209 without any problems, the gate insulating layer 204, source Impurities may adhere to the surfaces of the electrode layer 206a and the drain electrode layer 206b, and oxide films may be formed. This can be prevented from happening.

[0049] In this embodiment, the semiconductor layer that forms the channel formation region of the thin-film transistor 250 is The example shown uses an oxide semiconductor layer, but the applicable semiconductor layers are not limited to this. In addition, other semiconductor layers, such as those using organic semiconductor materials, can be used as semiconductor layers. Furthermore, in addition to the In-Ga-Zn-O non-single crystal film, at least one other semiconductor layer is also used. Oxide semiconductors containing one of the following elements: um, gallium, or zinc, such as ZnO, IZO, and ITO. Alternatively, oxide semiconductors such as SnO, or compound semiconductors such as SiGe and GaAs may be used. .

[0050] Next, the oxide semiconductor layer 209 is etched to form island-shaped oxide semiconductor layers 210. See Figure 2(E).

[0051] Through the above process, a thin film transient is formed using the oxide semiconductor layer 210 as a channel formation region. It is possible to form a sta250.

[0052] Furthermore, after forming the oxide semiconductor layer 210, the temperature is 100°C to 600°C, typically 200°C to A heat treatment at 400°C is recommended. For example, a heat treatment at 350°C for 1 hour under a nitrogen atmosphere can be performed. This can be done. This heat treatment causes the island-shaped oxide semiconductor layer 210 to be composed of In-Ga Atomic-level rearrangement occurs in Zn-O oxide semiconductors. This heat treatment (including photo-annealing) is also performed. (including) releases strain that inhibits carrier movement in the island-shaped oxide semiconductor layer 210. This is important because it allows for this process. The timing of the above heat treatment is as follows: It is not particularly limited after the formation of [the object].

[0053] Furthermore, the island-shaped oxide semiconductor layer 210 may be subjected to oxygen radical treatment. By performing a CAL treatment, the oxide semiconductor layer 210 becomes a thin film transient with a channel formation region. The sta can be turned off normally. Also, by performing radical treatment, island-like Damage caused by etching of the oxide semiconductor layer 210 can be repaired. The process can be carried out in an atmosphere containing O2, N2O, oxygen-containing N2, He, Ar, etc. Alternatively, the procedure may be carried out in an atmosphere in which Cl2 and CF4 are added to the above atmosphere. It is preferable to perform the processing without applying a bias voltage to the substrate 200.

[0054] Furthermore, it includes an oxide semiconductor layer 210, a source electrode layer 206a, and a drain electrode layer 206b, etc. A protective insulating layer may be formed to cover the thin-film transistor 250. For example, using CVD or sputtering methods, silicon oxide films, silicon nitride films, and silicon oxidnitridation films are produced. Silicon nitride film, silicon nitride film, aluminum oxide film, aluminum nitride film, aluminum nitride film, aluminum nitride The luminium film or aluminum nitride oxide film may be formed as a single layer or a multilayer structure.

[0055] Subsequently, by forming various electrodes and wiring, a semiconductor device having a thin-film transistor 250 is formed. It's finished.

[0056] As described above, after forming the source electrode layer 206a and the drain electrode layer 206b, exposure By performing an etching process on the gate insulating layer 204, the source electrode layer 206a and The thickness t2 of the gate insulating layer 204 located between the gate electrode layer 206b and the drain electrode layer 206b is Gate insulating layer 204 and gate electrode layer provided between layer 202 and source electrode layer 206a The thickness of the gate insulating layer 204 provided between 202 and the drain electrode layer 206b is smaller than the thickness t1. It can be cut. As a result, the source electrode layer and the drain electrode layer and the gate electrode layer This reduces parasitic capacitance that occurs between the two components and improves the characteristics of the component.

[0057] (Embodiment 2) In this embodiment, with reference to Figure 1(B), the transistor configuration differs from that of the above embodiment. I will explain the details.

[0058] The thin-film transistor 260 shown in Figure 1(B) is the same as the thin-film transistor 250 shown in Figure 1(A). In this, the source electrode layer 206a and the drain electrode layer 206b are tapered, When the upper ends of the drain electrode layer 206a and the drain electrode layer 206b are provided to have a curved surface. This shows the other structures (gate electrode layer 202, gate insulating layer 204, source). The positional relationship between the electrode layer 206a, the drain electrode layer 206b, and the oxide semiconductor layer 210 is shown in Figure 1. It can be provided in the same way as (A).

[0059] The source electrode layer 206a and the drain electrode layer 206b are tapered, and the source electrode layer 2 By providing the upper ends of 06a and the drain electrode layer 206b to have curved surfaces, Oxide for gate insulating layer 204, source electrode layer 206a and drain electrode layer 206b The coverage of the semiconductor layer 210 can be improved, and step breaks can be suppressed. In particular, the source electrode layer The thickness t of the gate insulating layer 204 located in the region between 206a and the drain electrode layer 206b 2 is a gate insulating layer provided below the source electrode layer 206a and the drain electrode layer 206b. Even when the thickness t1 is made sufficiently small, the oxide semiconductor layer 210 is stepped. It can be effectively suppressed.

[0060] The following is an example of a method for fabricating the thin-film transistor 260 shown in Figure 1(B), with reference to Figure 3. I will explain this further. Note that the manufacturing process in Figure 3 is largely the same as that in Figure 1(B). Therefore, in the following explanation, we will omit explanations of overlapping parts and focus on the differences. I will explain in detail. Also, in Figure 3, plasma is used as the etching process for the gate insulating layer 204. This shows when the process is used.

[0061] First, a gate electrode layer 202 is formed on a substrate 200 having an insulating surface, and then the gate A gate insulating layer 204 is formed on the electrode layer 202 (see Figure 3(A)). When forming layer 202, the coverage of the gate insulating layer 204 that is formed later is improved, and step breaks are eliminated. To prevent this, the edges of the gate electrode layer 202 are etched to a tapered shape. This is preferable. For example, the taper angle θ1 is 20° or more and less than 90°, preferably 30° or more. It is preferable to have a shape such that the taper angle is 80° or less. Note that "taper angle θ1" refers to the A layer having a super-shaped form (here, the gate electrode layer 202) is defined in the cross-sectional direction (surface of the substrate 200). When observed from a plane perpendicular to the surface, the inclination angle on the inner side of the layer formed by the side and bottom surfaces of the layer is This shows the lower end of the gate electrode layer 202 in contact with the substrate 200 when observed from the cross-sectional direction. This corresponds to the angle of the part.

[0062] Furthermore, the materials and manufacturing methods for the gate electrode layer 202 and gate insulating layer 204 are as follows: You can refer to state 1.

[0063] Next, a source electrode layer 206a and a drain electrode layer 206b are formed on the gate insulating layer 204. (See Figure 3(B)). Note that the material of the source electrode layer 206a and the drain electrode layer 206b For details on the materials and manufacturing method, please refer to Embodiment 1.

[0064] Next, the gate insulating layer 204 is etched. Here, the substrate 200 is placed. Plasma is generated in the chamber, exposing the gate insulating layer 204 and the source electrode layer 206. By applying plasma 208 to the surface of a and the drain electrode layer 206b, gate isolation is achieved. This shows the case where a recess 207 is formed in the margin layer 204 (see Figure 3(C)).

[0065] Plasma treatment involves, for example, placing an inert gas such as argon (Ar) in a vacuum chamber. By introducing this, a bias voltage is applied to the workpiece (in this case, the substrate 200) to create a plasma state. This can be done. When Ar gas is introduced into the chamber, electrons and A are present in the plasma. The presence of r cations accelerates Ar cations toward the cathode (towards the substrate 200). The cations of Ar are formed on the substrate 200, forming a gate insulating layer 204 and a source electrode layer 2 By colliding with the surface of 06a and the drain electrode layer 206b, the surface is sputtered. Etched, gate insulating layer 204, source electrode layer 206a and drain electrode layer 206 The surface of b can be etched. This type of plasma treatment is called "reverse sputtering". It is sometimes called "..."

[0066] By applying a bias voltage to the substrate 200 and performing plasma treatment, the gate insulating layer 204. Sputter etching of the surface of the source electrode layer 206a and the drain electrode layer 206b. This can be done effectively.

[0067] Furthermore, if irregularities are formed on the surface of the gate insulating layer 204, plasma treatment is performed. As a result, sputter etching is preferentially performed on the protrusions of the gate insulating layer 204, and the gate The flatness of the surface of the insulating layer 204 can be improved.

[0068] Furthermore, helium gas is used instead of argon gas as the gas used in the plasma treatment described above. Alternatively, the process may be carried out in an atmosphere in which oxygen, hydrogen, nitrogen, etc., are added to an argon atmosphere. Alternatively, the procedure may be carried out in an argon atmosphere with added Cl2, CF4, etc.

[0069] For example, in this embodiment, plasma processing is performed using a sputtering apparatus as shown in Figure 4. It is possible.

[0070] The sputtering apparatus shown in Figure 4 has a chamber 190 into which the workpiece 195 (in this case, a substrate 2) is placed. A first electrode 191 that holds (00) and a second electrode 192 that faces it are provided. Furthermore, the first electrode 191 is connected to the RF power supply (high-frequency power supply) 197, and the second electrode 192 It is connected to RF power supply 198 and DC power supply 199. The first electrode 191 and RF power supply 19 Between 7, and between the second electrode 192 and the RF power supply 198, impedance matching is performed. Matching boxes 193 and 194 are provided.

[0071] Using the sputtering apparatus shown in Figure 4, the workpiece 195 is subjected to plasma treatment (also known as reverse sputtering). When performing this procedure, an inert gas such as argon gas is introduced from the inlet 196, and the first electrode A high-frequency voltage is applied to 191 to create a gap between the first electrode 191 and the second electrode 192 in an inert gas. A rasma is generated, creating a negative self-bias towards the workpiece 195 located on the first electrode 191. By generating (applying a bias voltage), positive ions in the plasma are generated. The object is accelerated and made to collide with the workpiece 195. At this time, the surface of the gate insulating layer 204 has irregularities. If present, the protrusions are preferentially sputter-etched, and the gate insulating layer 204 The surface can be flattened.

[0072] Furthermore, a film is formed on the workpiece 195 using the sputtering apparatus shown in Figure 4 (sputtering film formation). In this case, a target made of the material to be deposited is placed on the second electrode 192 side. Then, a DC voltage or high-frequency voltage is applied to the second electrode 192, and the first electrode 191 and the second electrode A plasma is generated between electrodes 192, and positive ions in the plasma are accelerated to collide with the target. Just do it.

[0073] Therefore, when a film is formed on the workpiece 195 after plasma treatment, After plasma treatment of material 195 without exposure to the atmosphere, the workpiece 1 is subsequently treated using the sputtering method. A film can be formed on 95.

[0074] In this embodiment, when applying a bias voltage to the substrate 200 side during plasma processing... As explained above, if a recess 207 can be formed in the gate insulating layer 204, then Plasma treatment may be performed without applying an ass voltage.

[0075] Furthermore, by performing plasma treatment, the surface of the gate insulating layer 204 and the source electrode layer 206 It has the advantage of being able to remove impurities adhering to the surface of a and the drain electrode layer 206b. Yes, they are.

[0076] Furthermore, in Figure 3, not only the gate insulating layer 204, but also the source electrode layer 206a and the drain electrode By performing plasma treatment on the polar layer 206b, the source electrode layer 206a and the drain electrode This shows the case where the end of layer 206b is tapered. For example, when the taper angle θ2 is 2 It is preferable to have a shape that is between 0° and less than 90°, preferably between 30° and 80°. It seems so. Furthermore, "taper angle θ2" refers to a layer having a tapered shape (here, source electricity). The polar layer 206a or the drain electrode layer 206b is positioned in the cross-sectional direction (perpendicular to the surface of the substrate 200). When observed from the surface, the inclination angle of the tip portion on the inner side of the layer, formed by the side and bottom surfaces of the layer, is This shows the source electrode layer 2 in contact with the gate insulating layer 204 when observed from the cross-sectional direction. This corresponds to the angle of the lower end of 06a or the drain electrode layer 206b. Source electrode layer 206a Furthermore, by making the end of the drain electrode layer 206b tapered, the acid that is later formed This improves the coverage of the synthetic semiconductor layer and suppresses step breaks.

[0077] Furthermore, in Figure 3, not only the gate insulating layer 204, but also the source electrode layer 206a and the drain electrode By performing plasma treatment on the polar layer 206b, the source electrode layer 206a and the drain electrode This shows the case where the upper end of layer 206b is formed to have a curved surface (to have a curved shape). For example, the radius of curvature of the upper ends of the source electrode layer 206a and the drain electrode layer 206b. R is 1 / of the thickness of the source electrode layer 206a and drain electrode layer 206b after plasma treatment. 100 to 1 / 2, preferably the source electrode layer 206a and the drain electrode layer 206b The material is formed to be between 3 / 100 and 1 / 5 of its original thickness.

[0078] For example, the thickness of the source electrode layer 206a and the drain electrode layer 206b after plasma treatment is 1 If it is 00 nm, the upper ends of the source electrode layer 206a and the drain electrode layer 206b The radius of curvature R is set to be between 1 nm and 50 nm, preferably between 3 nm and 20 nm. Furthermore, the radius of curvature R of the upper ends of the source electrode layer 206a and the drain electrode layer 206b is within this range. The shape may change continuously. Source electrode layer 206a and drain electrode layer 206 By providing the upper end of b to have a curved surface, the oxide semiconductor layer that is later formed will be Coverage can be improved and step breaks can be suppressed. In particular, the thickness of the oxide semiconductor layer is related to the source power The length (step) is the sum of the thickness of the electrode layer 206a or the drain electrode layer 206b and the depth of the recess. The effect of suppressing step breakage becomes more pronounced when the thickness is less than the difference.

[0079] Furthermore, if the ends of the source electrode layer 206a and the drain electrode layer 206b are tapered, In both cases, it is preferable to form the recess 207 of the gate insulating layer 204 to have a tapered shape. In this case, the gate insulating layer 204 and the source electrode layer 206a or drain electrode layer 206 This improves the coverage of the oxide semiconductor layer formed at the point of contact with b, effectively preventing step breakage. This is possible. Note that making the recess 207 of the gate insulating layer 204 tapered means that The angle of inclination θ3 on the recessed side of the recessed portion of the gate insulating layer 204, between the side and bottom surfaces (or recessed portion) The inclination angle (the angle of inclination on the recessed side between the side of the recessed portion and the surface of the substrate 200) should be 90° or more. say.

[0080] Thus, not only the gate insulating layer 204, but also the source electrode layer 206a and the drain electrode layer By applying plasma treatment to 206b, a recess 207 is formed in the gate insulating layer 204. In addition, the source electrode layer 206a and the drain electrode layer 206b are tapered, The upper ends of the - electrode layer 206a and the drain electrode layer 206b are provided to have curved surfaces. It is possible.

[0081] Next, cover the gate insulating layer 204, the source electrode layer 206a and the drain electrode layer 206b After forming an oxide semiconductor layer, selective etching of the oxide semiconductor layer is performed. Further oxide semiconductor layer 210 is formed (see Figure 3(D)). Note that oxide semiconductor layer 210 For information on the materials and manufacturing method, please refer to Embodiment 1.

[0082] This embodiment provides a semiconductor device composed of transistors having high characteristics. This can be done. Furthermore, this embodiment can be used in appropriate combination with other embodiments. It is possible.

[0083] (Embodiment 3) In this embodiment, with reference to Figure 5, we will discuss a transistor configuration different from that of the above embodiment. explain.

[0084] The thin-film transistor 270 shown in Figure 5(A) has a first insulating layer 2 provided on the substrate 200. 51, a second insulating layer 252 provided on the first insulating layer 251, and the first insulating layer 251 and a second insulating layer 252 is provided so as to overlap with a portion of the gate electrode layer 202 - Electrode layer 206a and drain electrode layer 206b, source electrode layer 206a and drain Provided on electrode layer 206b and between source electrode layer 206a and drain electrode layer 206b The first insulating layer 251 located in the region has an oxide semiconductor layer 210 provided in contact with it. Yes, they are.

[0085] In other words, in the region where the second insulating layer 252 overlaps with the gate electrode layer 202, the source electrode The structure is such that the region where layer 206a and drain electrode layer 206b do not overlap is removed. In this case, the insulating layer located between the source electrode layer 206a and the drain electrode layer 206b is It consists of one insulating layer 251 and is provided between the gate electrode layer 202 and the source electrode layer 206a. The insulating layer and the insulating layer provided between the gate electrode layer 202 and the drain electrode layer 206b It is composed of a laminated structure of a first insulating layer 251 and a second insulating layer 252.

[0086] Furthermore, the thickness t of the insulating layer located between the source electrode layer 206a and the drain electrode layer 206b 2 is an insulating layer and gate electrode layer provided between the gate electrode layer 202 and the source electrode layer 206a. The thickness t1 of the insulating layer provided between the electrode layer 202 and the drain electrode layer 206b becomes smaller than the thickness t1 of the insulating layer. In Figure 5(A), the film thickness t1 is the sum of the film thicknesses of the first insulating layer 251 and the second insulating layer 252. This corresponds to a value, and the film thickness t2 corresponds to the film thickness value of the first insulating layer 251.

[0087] Thus, by using the configuration shown in Figure 5(A), the first gate electrode layer 202 The source electrode layer 206a and the drain electrode layer are separated by the insulating layer 251 and the second insulating layer 252. A 206b is provided, and an oxide semiconductor is placed on the source electrode layer 206a and the drain electrode layer 206b. Even when a body layer 210 is provided, the source electrode layer 206a and drain electrode layer 206b This reduces the parasitic capacitance that occurs between the transistor and the gate electrode layer 202, and also reduces the driving power of the transistor. This can reduce pressure and improve element characteristics.

[0088] Furthermore, in the configuration shown in Figure 5(A), the first insulating layer 251 and the second insulating layer 252 are used It is preferable to use different materials. Preferably, the material used for the first insulating layer 251 is different. The dielectric constant of the first insulating layer 251 is made higher than the dielectric constant of the material used for the second insulating layer 252. By making the power ratio higher than the dielectric constant of the second insulating layer 252, the drive voltage of the transistor is increased. Because it can be reduced, the source electrode layer 206a and the drain electrode layer 206b and the gate The effect of parasitic capacitance between the electrode layer 202 and the electrode layer can be effectively reduced.

[0089] By using different materials for the first insulating layer 251 and the second insulating layer 252, the second This makes it easier to obtain an etching selectivity ratio when etching the insulating layer 252. Furthermore, the ability to obtain an etching selectivity ratio means, for example, when etching layer A and layer B, A This means there is a sufficient difference between the etching rate of layer B and the etching rate of layer B. Furthermore, "etching rate" refers to the amount of etching per unit time (amount of material etched). ) means. Therefore, "high etching rate" means that more is etched and It means that it is difficult to etch, and "low etching rate" means that it is less likely to be etched. It means...

[0090] Furthermore, the film thickness of the first insulating layer 251 and the film thickness of the second insulating layer 252 are appropriately determined depending on the materials used. It can be configured as follows: For example, the first insulating layer 251 can be a silicon nitride film, aluminum oxide film, etc. An insulating layer made of a nium film, a hafnium oxide film, or a combination of these films, with a thickness of 5 nm to 20 nm. Formed at 0 nm, the second insulating layer 252 is an aluminum oxide film, a polyimide film, or These films can be combined to form insulating layers and the like with a film thickness of 5 nm to 200 nm. Furthermore, the drive voltage is further reduced, and the source electrode layer 206a and drain electrode layer 206b and gate voltage are reduced. To reduce the parasitic capacitance that occurs between the pole layer 202 and the first insulating layer 251, the film thickness of the first insulating layer 251 is reduced. It is preferable to make the thickness smaller than that of the insulating layer 252.

[0091] Note that the transistor shown in this embodiment is not limited to the configuration in Figure 5(A). The structure may also be as shown in Figure 5(B) and Figure 5(C).

[0092] The thin-film transistor 271 shown in Figure 5(B) is provided on a first insulating layer 2 on a substrate 200. 51, a second insulating layer 252 provided on the first insulating layer 251, and the first insulating layer 251 and a second insulating layer 252 is provided so as to overlap with a portion of the gate electrode layer 202 - Electrode layer 206a and drain electrode layer 206b, source electrode layer 206a and drain Provided on electrode layer 206b and between source electrode layer 206a and drain electrode layer 206b It has an oxide semiconductor layer 210 provided in contact with a second insulating layer 252 located in the region, - A second insulating layer 252 located in the region between electrode layer 206a and drain electrode layer 206b The upper part has been removed.

[0093] In other words, the second insulating layer 252 has a recess 207 in the region where it overlaps with the gate electrode layer 202. The oxide semiconductor layer 210 is provided in the recess 207 of the second insulating layer 252.

[0094] The transistor 272 shown in Figure 5(C) has a second insulating layer in the configuration shown in Figure 5(A). 252 is a region that overlaps with the gate electrode layer 202, and the source electrode layer 206a and drain electrode In the region located between the polar layers 206b, the first insulating layer 251 has a recess 207. Furthermore, an oxide semiconductor layer 210 is provided in the recess 207 of the first insulating layer 251.

[0095] Even when the configuration shown in Figure 5(B) or Figure 5(C) is used, the source electrode layer 206a and The thickness t2 of the insulating layer located between the drain electrode layer 206b is saw between the gate electrode layer 202 and the saw An insulating layer and gate electrode layer 202 and drain electrode layer 20 are provided between the electrode layers 206a The thickness t1 of the insulating layer provided between 6b can be made smaller than the thickness t1 of the insulating layer.

[0096] Furthermore, in Figure 5, the gate electrode layer 202, the source electrode layer 206a and the drain electrode layer 20 The insulating layer to be provided between 6b is a two-layer structure consisting of a first insulating layer 251 and a second insulating layer 252. Although the example shows a case where a structure is provided, this embodiment is not limited to a two-layer structure and may also be a three-layer structure.

[0097] Next, referring to Figure 6, we will discuss an example of a method for fabricating the transistor 270 shown in Figure 5(A). Let me explain. Note that the manufacturing process in Figure 6 is largely the same as in Figure 1. Therefore, In the following explanation, we will omit explanations of overlapping parts and explain the differences in detail. ru.

[0098] First, a gate electrode layer 202 is formed on a substrate 200 having an insulating surface, and then the gate A first insulating layer 251 and a second insulating layer 252 are sequentially laminated on the electrode layer 202 (Figure 6(A)).

[0099] The first insulating layer 251 and the second insulating layer 252 are silicon oxide film, silicon oxide nitride film, and nitrogen Silicon oxide film, silicon nitride film, aluminum oxide film, tantalum oxide film, hafni oxide film It can be formed using a umbellate film or the like.

[0100] Furthermore, the first insulating layer 251 and the second insulating layer 252 can be formed using different materials. Preferably, the dielectric constant of the first insulating layer 251 is higher than that of the second insulating layer 252. It is preferable to determine the material and film thickness accordingly. For example, as the first insulating layer 251 A film is formed by sequentially stacking silicon oxide film and silicon nitride film to a thickness of 5 nm to 200 nm. Then, a silicon oxide film is formed as the second insulating layer 252 with a thickness of 5 nm to 200 nm. It is possible.

[0101] Furthermore, as mentioned above, the first insulating layer 251 can be a silicon nitride film, aluminum oxide, etc. An insulating layer consisting of a film, a hafnium oxide film, or a combination of these films, with a film thickness of 5 nm to 200 nm. A second insulating layer 252 is formed, and an aluminum oxide film, a polyimide film, or a film made of these materials is used. An insulating layer or the like can be formed with a film thickness of 5 nm to 200 nm by combining these elements.

[0102] For details regarding the material and manufacturing method of the gate electrode layer 202, please refer to Embodiment 1. can.

[0103] Next, a source electrode layer 206a and a drain electrode layer 206b are formed on the second insulating layer 252. (See Figure 6(B)). Note that the material of the source electrode layer 206a and the drain electrode layer 206b For details on the materials and manufacturing method, please refer to Embodiment 1.

[0104] Next, a second insulating layer 2 is formed between the source electrode layer 206a and the drain electrode layer 206b. By etching 52 (exposed second insulating layer 252), the second insulating layer Remove 252 to expose the first insulating layer 251 (see Figure 6(C)).

[0105] By performing an etching process, the source electrode layer 206a and the drain electrode layer 206b The film thickness t2 of the insulating layer located in the intermediate region (here, the first insulating layer 251) is the gate electrode. An insulating layer provided between layer 202 and source electrode layer 206a and gate electrode layer 202 and Dre An insulating layer provided between the in electrode layers 206b (here, the first insulating layer 251 and the second insulating layer The film thickness t1 of the laminated film (edge ​​layer 252) becomes smaller.

[0106] For the etching process, dry etching or wet etching can be used. For example, as an etching process, dry etching is performed using a mixed gas of C4F8 and Ar. By performing this process, the etching selectivity ratio between the silicon oxide film and the silicon nitride film is determined. The second insulating layer 252 can be effectively removed.

[0107] Furthermore, by controlling the etching conditions, the source electrode layer 206a and the drain electrode A portion of the second insulating layer 252 formed between the polar layers 206b may be left intact (Figure 5( (Corresponding to B), a second formed between the source electrode layer 206a and the drain electrode layer 206b The insulating layer 252 is removed, and the upper part of the first insulating layer 251 is etched to remove the first insulating layer. A recess may be formed in layer 251 (corresponding to Figure 5(C)).

[0108] Furthermore, in the etching process, the source electrode layer 206a and the drain electrode layer 206b are etched It can be used as a screw. In addition, the source electrode layer 206a and the drain electrode layer 20 Using the photomask used during the formation of 6b (Figure 6(B)), the ec of the second insulating layer 252 You can also play games.

[0109] Next, the first insulating layer 251, the second insulating layer 252, the source electrode layer 206a and the drain electrode After forming the oxide semiconductor layer 209 so as to cover the polar layer 206b (see Figure 6(D)), The oxide semiconductor layer 210 is formed by selectively etching the oxide semiconductor layer 209. (See Figure 6(E)). Note that the material of oxide semiconductor layer 209 (oxide semiconductor layer 210) For details on the manufacturing method, please refer to Embodiment 1.

[0110] This embodiment provides a semiconductor device composed of transistors having high characteristics. This can be done. Furthermore, this embodiment can be used in appropriate combination with other embodiments. It is possible.

[0111] (Embodiment 4) In this embodiment, with reference to Figure 7, we will discuss a transistor configuration different from that of the above embodiment. explain.

[0112] The thin-film transistor 280 shown in Figure 7(A) has a gate insulating layer 2 provided on the substrate 200. 04 is provided so as to overlap with a portion of the gate electrode layer 202 via the gate insulating layer 204. The source electrode layer 206a and the drain electrode layer 206b, and the source electrode layer 206a and the drain The source electrode is provided on the in electrode layer 206b via buffer layers 217a and 217b. It is provided in contact with the gate insulating layer 204 located between layer 206a and the drain electrode layer 206b. It has an oxide semiconductor layer 210. Furthermore, it has a source electrode layer 206a and a drain electrode The thickness t2 of the gate insulating layer 204 located in the region between the pole layers 206b is the same as that of the gate electrode layer 20 The gate insulating layer 204 and gate electrode layer 202 are provided between 2 and the source electrode layer 206a. The thickness t1 of the gate insulating layer 204 provided between the drain electrode layer 206b is smaller than the thickness t1 of the gate insulating layer 204. It is designed to allow this (see Figure 7(A)).

[0113] In other words, the transistor shown in Figure 7(A) has a buffer layer added to the transistor shown in Figure 1(A). The configuration includes the addition of 217a and 217b.

[0114] Buffer layers 217a and 217b are formed in the manufacturing process from the source electrode layer 206a and drain It suppresses oxidation of the surface of electrode layer 206b and functions as a channel-forming region. The oxide semiconductor layer 210 and the source electrode layer 206a and drain electrode layer 206b are connected. It functions as a layer to ensure good aerodynamic connectivity.

[0115] The buffer layers 217a and 217b have the same conductivity as the oxide semiconductor layer 210 or are of the same conductivity as the oxide semiconductor layer 210. It can be formed using an oxide semiconductor layer with higher conductivity. For example, a buffer layer. 217a and 217b are formed from an In-Ga-Zn-O non-single crystal film, and oxide semiconductor layer 2 10 can be formed of an In-Ga-Zn-O-based polycrystalline film having a lower conductivity than the buffer layers 217a and 217b.

[0116] Thus, by providing the buffer layers 217a and 217b between the source electrode layer 206a and the drain electrode layer 206b and the oxide semiconductor layer 21 0, the contact resistance can be reduced and the device characteristics of the transistor can be improved.

[0117] Next, referring to FIG. 8, an example of a method for manufacturing the thin film transistor 280 shown in FIG. 7(A) will be described. Note that many parts of the manufacturing process in FIG. 8 are common to FIG. 1. Therefore, in the following description, descriptions of overlapping parts will be omitted, and different points will be described in detail.

[0118] First, a gate electrode layer 202 is formed on a substrate 200 having an insulating surface, and then a gate insulating layer 204 is formed on the gate electrode layer 202 (see FIG. 8(A)). Note that for the materials and manufacturing methods of the gate electrode layer 202 and the gate insulating layer 204, reference can be made to Embodiment 1.

[0119] Next, after forming a conductive layer 206 on the gate insulating layer 204, an oxide semiconductor layer 217 is formed on the conductive layer 206 (see FIG. 8(B)).

[0120] The conductive layer 206 is made of a metal containing an element selected from aluminum (Al), copper (Cu ), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), scandium (Sc), an alloy containing the above-described elements as components, or a nitride or the like containing the above-described elements as components. ​​​​​​ It can be formed.

[0121] For example, the conductive layer 206 can be formed with a single-layer structure of a molybdenum film or a titanium film. Also, the conductive layer 206 may be formed with a laminated structure. For example, it can be made into a laminated structure of an aluminum film and a titanium film. Moreover, it may be a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated in sequence. Also, it may be a three-layer structure in which a molybdenum film, an aluminum film, and a molybdenum film are laminated in sequence. Further, as the aluminum film used in these laminated structures, an aluminum (Al-Nd) film containing neodymium may be used. Additionally, the conductive layer 206 may have a single-layer structure of an aluminum film containing silicon.

[0122] The oxide semiconductor layer 217 can be formed of an In-Ga-Zn-O-based non-single crystal film. For example, by a sputtering method using an oxide semiconductor target (In2O3:Ga2O3:ZnO = 1:1:1) containing In, Ga, and Zn, the oxide semiconductor layer 217 can be formed on the conductive layer 206. As the sputtering conditions, for example, the distance between the substrate 200 and the target is 30 mm to 500 mm, the pressure is 0.1 Pa to 2.0 Pa, the DC power supply is 0.25 kW to 5.0 kW, the temperature is 20 °C to 100 °C, and the atmosphere can be an argon atmosphere, an oxygen atmosphere, or a mixed atmosphere of argon and oxygen.

[0123] The oxide semiconductor layer 217 suppresses the oxidation of the surfaces of the source electrode layer and the drain electrode layer to be formed later, and also functions as a buffer for favorably making electrical connection between the oxide semiconductor layer that functions as a channel formation region to be formed later, and the source electrode layer and the drain electrode layer. It functions as a layer.

[0124] Furthermore, in the process shown in Figure 8(B), after forming the conductive layer 206, the conductive layer 206 is exposed to the atmosphere. It is preferable to continuously form the oxide semiconductor layer 217 without exposure to the conductive layer 206. By forming the oxide semiconductor layer 217 without exposing it to the atmosphere, the surface of the conductive layer 206 The adhesion of impurities and the formation of oxide films are suppressed between the conductive layer 206 and the oxide semiconductor layer 21. This is because it allows for a reduction in the contact resistance of 7.

[0125] Furthermore, the gas used when forming the oxide semiconductor layer 217 is used to oxidize the surface of the conductive layer 206. It is preferable to use a gas that is difficult to use. For example, in the film formation conditions for the oxide semiconductor layer 217 , increase the ratio of the flow rate of argon gas to the flow rate of oxygen gas (preferably, oxygen gas (Not introduced). Specifically, the deposition of the oxide semiconductor layer 217 is performed using argon or helium, etc. Under a noble gas atmosphere, or under an atmosphere with less than 10% oxygen and more than 90% noble gas This can be done by reducing the ratio of the oxygen gas flow rate to the argon gas flow rate. This makes it possible to suppress the formation of an oxide film on the surface of the conductive layer 206. This makes it possible to reduce the contact resistance between the conductive layer 206 and the oxide semiconductor layer 217.

[0126] Furthermore, by reducing the ratio of the oxygen gas flow rate to the argon gas flow rate, The conductivity of the oxide semiconductor layer can be increased. In this case, the channel formed later can be increased. The oxide semiconductor layer, which functions as a formation region, and the electrical relationship between the source electrode layer and the drain electrode layer It can establish a good connection.

[0127] Next, using a photolithography method, the conductive layer 206 and the oxide semiconductor layer 217 are etched to form the source electrode layer 206a and the drain electrode layer 206b, and the buffer layers 2 17a and the buffer layer 217b.

[0128] Next, an etching process is performed on the gate insulating layer 2 04 (the exposed gate insulating layer 204), so as to form a recess 207 in the gate insulating layer 204 (see FIG. 8(C)).

[0129] Next, after forming the oxide semiconductor layer 209 so as to cover the gate insulating layer 204, the source electrode layer 206a, the drain electrode layer 206b, the buffer layers 217a and the buffer layer 217b (see FIG. 8(D)), the oxide semiconductor layer 209 is selectively etched to form the oxide semiconductor layer 210 (see FIG. 8(E)). At this time, a part of the buffer layers 217a and the buffer layers 217b is also etched. For the material and manufacturing method of the oxide semiconductor layer 209 (the oxide semiconductor layer 210), reference can be made to Embodiment 1. For the material and manufacturing method of the oxide semiconductor layer 209 (the oxide semiconductor layer 210), reference can be made to Embodiment 1.

[0130] Note that in FIG. 7(A), a configuration in which buffer layers 217a and 217b are provided for the transistor shown in FIG. 1(A) is shown, but the present invention is not limited to this. For example, as shown in FIG. 7(B), buffer layers 217a and 217b may be provided for the transistor shown in FIG. 5( A). Alternatively, buffer layers 217a and 217b may be provided for the configurations shown in FIG. 1 (B), FIG. 5(B), and FIG. 5(C). (B), FIG. 5(B), and FIG. 5(C). This is also possible.

[0131] According to the present embodiment, a semiconductor device composed of transistors having high characteristics is provided. This can be done. Furthermore, this embodiment can be used in appropriate combination with other embodiments. It is possible.

[0132] (Embodiment 5) In this embodiment, a display device is an example of a semiconductor device equipped with a transistor. The manufacturing process will be explained using drawings. Note that the manufacturing process shown in this embodiment is extensive. This part is common with Embodiment 1. Therefore, the following will explain the overlapping parts. The explanation will be omitted, and the differences will be explained in detail. Note that in the following explanation, Figures 9 and 1 will be used. Figure 0 shows a cross-sectional view, and Figures 11 to 14 show top views.

[0133] First, wiring and electrodes (including a gate electrode layer 202) are placed on a substrate 200 having an insulating surface. Form the (seat wiring, capacitance wiring 308, first terminal 321) (see Figures 9(A) and 11). .

[0134] Capacitive wiring 308 and the first terminal 321 are formed simultaneously using the same material as the gate electrode layer 202. This can be achieved. Furthermore, the materials and manufacturing methods for the gate electrode layer 202 are described in the implementation details. You can refer to state 1.

[0135] Next, a gate insulating layer 204 is formed on the gate electrode layer 202, and then the gate insulating layer 204 A conductive layer 206 is formed on top (see Figure 9(B)).

[0136] The conductive layer 206 is made using methods such as sputtering and vacuum deposition, using aluminum (Al) and copper (Cu ), Titanium (Ti), Tantalum (Ta), Tungsten (W), Molybdenum (Mo), A metal containing elements selected from chromium (Cr), neodymium (Nd), and scandium (Sc). A material consisting of an alloy containing the above-mentioned elements, or a nitride containing the above-mentioned elements. It can be formed.

[0137] For example, the conductive layer 206 can be formed as a single-layer structure of a titanium film. 06 may be formed in a laminated structure, for example, a laminated structure of an aluminum film and a titanium film. It is possible to use a titanium film and an aluminum (Al-Nd) film containing neodymium. A three-layer structure of titanium film may also be used. Furthermore, the conductive layer 206 may be made of silicon-containing aluminum. It may also be a single-layer structure of a film.

[0138] In Figure 9(B), after forming the gate insulating layer 204, By forming the contact hole 213 and then forming the conductive layer 206, the first terminal 3 Ensure that 21 and the conductive layer 206 are electrically connected.

[0139] Next, by etching the conductive layer 206, the source electrode layer 206a and the drain electrode Layer 206b, connecting electrode 320, and second terminal 322 are formed (see Figures 9(C) and 12). .

[0140] The second terminal 322 is electrically connected to the source wiring (source wiring including the source electrode layer 206a). A configuration in which connections are made is possible. Furthermore, the connecting electrode 320 is formed in the gate insulating layer 204. The configuration involves directly connecting to the first terminal 321 via the contact hole 213. It is possible.

[0141] Next, the gate insulating layer 2 provided between the source electrode layer 206a and the drain electrode layer 206b By performing an etching process on 04 (exposed gate insulating layer 204), the gate insulating layer A recess 207 is formed in 204 (see Figure 9(D)).

[0142] By performing an etching process, the source electrode layer 206a and the drain electrode layer 206b The thickness t2 of the gate insulating layer 204 located in the intermediate region is such that it is the same thickness as the gate electrode layer 202 and the source electrode. The gate insulating layer 204 and gate electrode layer 202 are provided between layers 206a and the drain electrode. The thickness t1 of the gate insulating layer 204 provided between layers 206b becomes smaller than the thickness t1 of the gate insulating layer 204.

[0143] Etching processes include plasma treatment using inert gas and / or reactive gas, Etching and other similar processes can be used.

[0144] Here, as part of the etching process, the gate insulating layer 204, the source electrode layer 206a, and the dray When plasma treatment is performed on the surface of the electrode layer 206b, the connecting electrode 320, and the second terminal 322. This shows the source electrode layer 206a, drain electrode layer 206b, and connecting electrode 3. 20. The end of the second terminal 322 is tapered, and the upper end is formed to have a curved surface. This can be done. For details on the plasma processing method, please refer to Embodiment 2 above. It is possible.

[0145] Furthermore, by reducing the thickness of the gate insulating layer 204 formed on the capacitive wiring 308, This allows for a larger capacitance in the capacitive elements that are formed later.

[0146] Next, the gate insulating layer 204, the source electrode layer 206a, the drain electrode layer 206b, and the connecting electrode. 320, an oxide semiconductor layer 209 is formed to cover the second terminal 322 (Figure 10(A)). reference).

[0147] Plasma treatment and the formation of the oxide semiconductor layer 209 can be performed continuously within the same chamber. Preferably, by performing plasma treatment and the formation of the oxide semiconductor layer 209 in succession, Impurities on the surfaces of the insulating layer 204, source electrode layer 206a, and drain electrode layer 206b Adhesion or formation of oxide films, etc., on the surfaces of the source electrode layer 206a and the drain electrode layer 206b This can suppress the following. You can refer to Embodiment 1.

[0148] Next, the oxide semiconductor layer 209 is selectively etched to form island-shaped oxide semiconductor layers 210. This completes the process, forming a thin-film transistor 290 (see Figures 10(B) and 13).

[0149] Next, it is preferable to perform heat treatment at 100°C to 600°C, typically 200°C to 400°C. For example, heat treatment is performed at 250°C for 1 hour under a nitrogen atmosphere. This heat treatment causes island-like Atomic-level rearrangement of the In-Ga-Zn-O non-single-crystal film constituting the oxide semiconductor layer 210 The process is carried out. This heat treatment releases the strain that hinders carrier movement, so here Heat treatment (including photo-annealing) is effective. The timing of the heat treatment depends on the oxidation stage. The procedure is not particularly limited as long as it is performed after the deposition of the monocrystalline semiconductor layer 209; for example, it can also be performed after the formation of the pixel electrodes. good.

[0150] Alternatively, the exposed island-shaped oxide semiconductor layer 210 may be subjected to oxygen radical treatment. By performing oxygen radical treatment, the island-like oxide semiconductor layer 210 is transformed into a channel-forming region. Thin-film transistors can be made normally off. Also, radical processing can be performed. This allows for the recovery of damage caused by etching to the island-shaped oxide semiconductor layer 210. Radical treatment is performed under an atmosphere of O2, N2O, preferably oxygen-containing N2, He, Ar. It is preferable to do so. Alternatively, it may be carried out in an atmosphere in which Cl2 and CF4 are added to the above atmosphere. stomach.

[0151] Next, a protective insulating layer 340 is formed to cover the thin-film transistor 290. Selectively etch the contact hole 325 that reaches the drain electrode layer 206b, Contact hole 326 reaching the second electrode 320 and contact reaching the second terminal 322 This forms hole 327 (see Figure 10(C)).

[0152] Next, the transparent conductive layer 310 and connecting electrode 320 are electrically connected to the drain electrode layer 206b. A transparent conductive layer 328 that is electrically connected and a transparent conductive layer that is electrically connected to the second terminal 322 Forms 329 (see Figures 10(D) and 14).

[0153] The transparent conductive layer 310 functions as a pixel electrode, and the transparent conductive layers 328 and 329 connect to the FPC. This will be the electrode or wiring used in the connection electrode 320. More specifically, a transparent The bright conductive layer 328 is used as a terminal electrode for connection that functions as an input terminal for gate wiring, The transparent conductive layer 329 formed on terminal 322 of the 2 is used as the input terminal for the source wiring. It can be used as a terminal electrode for connection.

[0154] Furthermore, the capacitive wiring 308, gate insulation layer 204, protective insulation layer 340 and transparent conductive layer 310 A greater retention capacity can be formed. In this case, the capacitance wiring 308 and the transparent conductive layer 310 The gate insulating layer 204 and the protective insulating layer 340 act as electrodes and dielectrics.

[0155] Transparent conductive layers 310, 328, and 329 are made of indium oxide (In2O3) and indium oxide. Tin oxide alloy (In2O3-SnO2, abbreviated as ITO), indium oxide zinc oxide alloy Gold (In2O3-ZnO) and other materials can be formed using sputtering, vacuum deposition, and other methods. For example, after forming a transparent conductive layer, a resist mask is formed on the transparent conductive layer, By removing unwanted parts through chipping, transparent conductive layers 310, 328, and 329 are formed. It is possible.

[0156] Through the above process, elements such as bottom-gate n-channel thin-film transistors and retaining capacitors are produced. This can be completed. Then, these elements are arranged in a matrix corresponding to individual pixels. By arranging it, one of the substrates for fabricating an active-matrix display device This can be done. For convenience in this specification, such a substrate is referred to as an active matrix substrate. Call.

[0157] When manufacturing an active-matrix liquid crystal display device, an active-matrix substrate is used. A liquid crystal layer is provided between the opposing substrate on which the opposing electrode is located, and the active matrix substrate and The opposing substrate should be fixed in place.

[0158] Furthermore, the configuration shown in this embodiment is not limited to the pixel configuration in Figure 14. An example of another configuration is shown in Figure 14. Figure 15 shows a transparent conductive layer 31 that functions as a pixel electrode, without capacitive wiring 308. 0 and the gate wiring 302 of the adjacent pixel are used as electrodes, and a protective insulating layer 340 and gate insulating This shows a configuration in which layer 204 is used as a dielectric to form a retaining capacitance.

[0159] This embodiment can be used in appropriate combination with other embodiments.

[0160] (Embodiment 6) In this embodiment, a thin-film transistor is fabricated, and the thin-film transistor is used as a pixel portion, and furthermore When manufacturing a semiconductor device (also called a display device) that has a display function and is used in a drive circuit, I will explain this. Also, I will explain that part or all of the drive circuit made with thin-film transistors is used in the pixel section. It can be integrally formed on the same substrate to create a system-on-panel.

[0161] A display device includes display elements. Display elements include liquid crystal elements (also called liquid crystal display elements) and light-emitting elements. A light-emitting element (also called a light-emitting display element) can be used. The light-emitting element is activated by current or voltage. This category includes elements whose brightness is controlled, specifically inorganic EL (Electrical LEDs). This includes Luminescence, organic EL, etc. Also, electronic inks, etc. Display media in which contrast changes due to the effect can also be applied.

[0162] Furthermore, the display device includes a panel in which the display elements are sealed, and a controller on the panel. The display device includes a module on which ICs and the like are mounted. With respect to an element substrate that corresponds to one form before the display element is completed in the process of manufacturing the element, The element substrate is provided with means for supplying current to the display element at each of the multiple pixels. Specifically, the display element may be in a state where only the pixel electrodes are formed, or the pixel electrodes and This is the state after a conductive layer has been formed, but before etching to form pixel electrodes. That's fine, and it applies to all forms.

[0163] In this specification, the term "display device" refers to an image display device, a display device, or an optical display device. This refers to the power source (including lighting equipment). It also refers to connectors, such as FPC (Flexible Printed Circuit). (inted circuit) or TAB (Tape Automated Bon) (ding) tape or TCP (Tape Carrier Package) Modules that have a printed circuit board attached to the end of the TAB tape or TCP. The display element or IC (integrated circuit board) is integrated using the COG (Chip On Glass) method. All modules in which the road is directly implemented are also included in the display device.

[0164] In this embodiment, an example of a liquid crystal display device is shown as a semiconductor device that is one embodiment of the present invention. Figure 16 shows the external appearance and cross-section of a liquid crystal display panel, which is a form of semiconductor device. Let me explain. Figures 16(A1)(A2) show the In-G formed on the first substrate 4001. Highly reliable thin-film transistor 4010 containing an a-Zn-O non-single-crystal film as a semiconductor layer. , 4011, and the liquid crystal element 4013 are placed between the second substrate 4006 and a sealing material 4005. Therefore, Figure 16(B) is a top view of the sealed panel, and Figure 16(A1)(A2) is M - This corresponds to a cross-sectional view in N.

[0165] The pixel section 4002 and the scanning line driving circuit 4004 are surrounded on the first substrate 4001. A sealing material 4005 is provided in this manner. Also, the pixel section 4002 and the scan line drive rotation A second substrate 4006 is provided on the path 4004. Therefore, the pixel section 4002 and the scanning The line drive circuit 4004 consists of the first substrate 4001, the sealing material 4005, and the second substrate 4006. It is sealed together with the liquid crystal layer 4008. Also, the seal on the first substrate 4001 A single crystal is placed on a separately prepared substrate in a region different from the area enclosed by material 4005. A signal line driving circuit 4003, formed from a semiconductor film or a polycrystalline semiconductor film, is mounted.

[0166] Furthermore, the method of connecting the separately formed drive circuit is not particularly limited, and COG method, Wire bonding methods or TAB methods can be used. Figure 16(A1) This is an example of implementing the signal line drive circuit 4003 using the COG method, and Figure 16(A2) shows, This is an example of implementing the signal line drive circuit 4003 using the TAB method.

[0167] Furthermore, the pixel section 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004 are It has multiple thin-film transistors, and in Figure 16(B), the thin film transistors included in the pixel section 4002 Thin film transistor 4010 and thin film transistor 401 included in scan line driving circuit 4004 1 is an example. On thin-film transistors 4010 and 4011 are insulating layers 4020 and 40 21 is provided.

[0168] Thin-film transistors 4010 and 4011 use an In-Ga-Zn-O non-single-crystal film as the semiconductor layer. A highly reliable thin-film transistor can be applied as such. Thin-film transistors 4010 and 4011 are n-channel thin-film transistors.

[0169] Furthermore, the pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin-film transistor 4010. They are electrically connected. And the counter electrode layer 4031 of the liquid crystal element 4013 is on the second substrate 40 Formed on 06. Pixel electrode layer 4030, counter electrode layer 4031, and liquid crystal layer 4008 The overlapping portion corresponds to the liquid crystal element 4013. Note that the pixel electrode layer 4030 and the opposite The electrode layer 4031 is provided with insulating layers 4032 and 4033, which function as alignment films. The liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033.

[0170] The first substrate 4001 and the second substrate 4006 are made of glass, metal (typically, glass). Stainless steel, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film Aluminum foil can be used with PVF film or polyester. It is also possible to use a sheet with a structure sandwiched between films.

[0171] Furthermore, 4035 is a columnar spacer obtained by selectively etching the insulating layer. The distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 is controlled. It is provided for this purpose. A spherical spacer may also be used. Also, the counter electrode layer 403 1 is electrically connected to a common potential line provided on the same substrate as the thin-film transistor 4010. It is possible to use a common connection part to connect the conductive particles placed between the pair of substrates to the counter electrode layer 4 031 and the common potential line can be electrically connected. Note that the conductive particles are sealing material 4 It is to be included in 005.

[0172] Alternatively, a liquid crystal exhibiting a blue phase without an alignment layer may be used. The blue phase is one of the liquid crystal phases. Yes, as the temperature of a cholesteric liquid crystal is increased, it transitions from the cholesteric phase to the isotropic phase. This is the phase that appears earlier. The blue phase only appears within a narrow temperature range, so improving the temperature range is necessary. To achieve this, a liquid crystal composition containing 5% or more by weight of a chiral agent is used in the liquid crystal layer 4008. It is used. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 10 μs~ With a short duration of 100 μs and optical isotropy, orientation processing is unnecessary, and it exhibits low field-of-view angle dependence. stomach.

[0173] The liquid crystal display device shown in this embodiment is an example of a transmissive liquid crystal display device, but the liquid crystal display device This method can be applied to both reflective and transflective liquid crystal displays.

[0174] Furthermore, in the liquid crystal display device shown in this embodiment, a polarizing plate is provided on the outside (viewing side) of the substrate, and the inside An example is shown where the coloring layer and the electrode layer used for the display element are arranged in that order, but the polarizing plate is on the inside of the substrate. It may also be provided in this embodiment. Furthermore, the laminated structure of the polarizing plate and the colored layer is not limited to this embodiment, and the polarizing plate The coloring layer can be set appropriately depending on the materials and manufacturing process conditions. A light-shielding film that functions as a shield may be provided.

[0175] Furthermore, in this embodiment, in order to reduce surface irregularities of the thin-film transistor, and thin-film transistor To improve the reliability of the transistor, thin-film transistors function as a protective layer or planarizing insulating layer. It is constructed to be covered with insulating layers (insulating layer 4020, insulating layer 4021). This is to prevent the entry of pollutants such as organic matter, metals, and water vapor suspended in the atmosphere. Therefore, a dense film is preferred. The protective layer is made by sputtering a silicon oxide film, nitride film Silicon oxide film, silicon nitride film, silicon nitride film, aluminum oxide film, aluminum nitride film Aluminum film, aluminum oxide nitride film, or aluminum nitride oxide film, in single or multilayer form This is sufficient. In this embodiment, an example is shown in which the protective layer is formed by sputtering, but it is not particularly limited. It can be formed using various methods.

[0176] Here, a laminated insulating layer 402 is formed as a protective layer. As the first layer of 0, a silicon oxide film is formed using the sputtering method. When using a recon film, the aluminum film used as the source electrode layer and drain electrode layer is It is effective in preventing lockout.

[0177] Furthermore, an insulating layer is formed as the second layer of the protective layer. Here, the second layer of the insulating layer 4020 is Then, a silicon nitride film is formed using the sputtering method. The silicon nitride film is used as a protective layer. This allows mobile ions such as sodium to penetrate the semiconductor region, altering the electrical properties of the TFT. It can suppress the process of causing the problem.

[0178] Alternatively, after forming the protective layer, the semiconductor layer may be annealed (300°C to 400°C). stomach.

[0179] Furthermore, an insulating layer 4021 is formed as a planar insulating layer. The insulating layer 4021 is made of poly Heat-resistant organic materials such as mids, acrylics, benzocyclobutenes, polyamides, and epoxys. Materials can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials) can also be used. Using siloxane-based resins, PSG (phosphorus glass), BPSG (phosphorus boron glass), etc. This can be achieved by laminating multiple insulating layers formed from these materials. 4021 may be formed.

[0180] Siloxane-based resins are formed using siloxane-based materials as the starting material for Si-OS. This corresponds to a resin containing i-bonds. Siloxane resins use organic groups (e.g., alkyl groups) as substituents. You may also use aryl groups or fluoro groups. Furthermore, organic groups may have fluoro groups. You can.

[0181] The method for forming the insulating layer 4021 is not particularly limited and can be sputtered or SOG depending on the material. Spin coating, dip coating, spray coating, droplet ejection (inkjet method, screen coating) Printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife A coater or the like can be used. When forming the insulating layer 4021 using a material liquid, The semiconductor layer may be annealed (300°C to 400°C) simultaneously with the machining process. By combining the firing process of the edge layer 4021 with the annealing of the semiconductor layer, semiconductor devices can be manufactured efficiently. It becomes possible to do so.

[0182] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Titanium oxide-containing indium tin oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide with added silicon dioxide. Conductive materials can be used.

[0183] Furthermore, conductive polymers are used as the pixel electrode layer 4030 and the counter electrode layer 4031. It can be formed using a conductive composition containing (also known as). The resulting pixel electrode preferably has a light transmittance of 70% or more at a wavelength of 550 nm. Furthermore, the resistivity of the conductive polymer contained in the conductive composition must be 0.1 Ω·cm or less. preferable.

[0184] As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. For example For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene Examples include derivatives thereof, or copolymers of two or more of these.

[0185] In addition, a separately formed signal line drive circuit 4003 and a scan line drive circuit 4004 or pixel unit 4 The various signals and potentials supplied to 002 are provided by the FPC4018.

[0186] In this embodiment, the connection terminal electrode 4015 is connected to the pixel electrode layer 40 of the liquid crystal element 4013. Formed from the same conductive layer as 30, the terminal electrode 4016 is made of thin-film transistor 4010, 40 The source electrode layer and drain electrode layer are formed of the same conductive layer.

[0187] The connecting terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. They are electrically connected.

[0188] Furthermore, in Figure 16, a signal line drive circuit 4003 is formed separately and implemented on the first substrate 4001. Although an example of the configuration is shown, this embodiment is not limited to this configuration. Scan line drive circuit Alternatively, it may be formed and implemented separately, or it may be part of the signal line drive circuit or part of the scan line drive circuit. It is also acceptable to form and implement the component separately.

[0189] Figure 17 shows a liquid crystal display module, which is a form of semiconductor device, using a TFT substrate 2600. This shows one example of how it can be constructed.

[0190] Figure 17 shows an example of a liquid crystal display module, in which the TFT substrate 2600 and the opposing substrate 2601 are The pixel portion 2603, which includes a TFT and the like, is fixed in place by a material 2602, and the liquid crystal layer is also included between them. A display element 2604 and a colored layer 2605 are provided to form a display area. Colored layer 2605 This is necessary for color display, and in the case of the RGB method, it corresponds to red, green, and blue. A colored layer is provided corresponding to each pixel. The TFT substrate 2600 and the opposing substrate 2601 Polarizing plates 2606, 2607, and 2613 are arranged on the outside. The light source is cold It consists of a cathode tube 2610 and a reflector 2611, and the circuit board 2612 is flexible The wiring circuit section 2608 of the TFT board 2600 is connected by the wire board 2609, and the control External circuits such as polarizing circuits and power supply circuits are incorporated. Also, between the polarizing plate and the liquid crystal layer The layers may be stacked with a phase difference plate in place.

[0191] The LCD display module has TN (Twisted Nematic) mode and IPS (I n-Plane-Switching) mode, FFS (Fringe Field Switching) (witching) mode, MVA (Multi-domain Vertical A) alignment) mode, PVA(Patterned Vertical Alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) irefringence) mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. You can use modes such as UID Crystal.

[0192] Through the above process, a highly reliable liquid crystal display device can be manufactured as a semiconductor device. .

[0193] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0194] (Embodiment 7) In this embodiment, electronic paper is shown as an example of a semiconductor device that is one embodiment of the present invention.

[0195] Figure 18 shows an active-matrix electronic paper as an example of a semiconductor device. The thin-film transistor 581 used in the device is the thin film shown in Embodiments 1 to 3 above. It can be fabricated in the same way as a transistor.

[0196] Figure 18 shows an example of an electronic paper display using a twist ball display method. The Toball display method is an electrode layer that uses spherical particles painted in white and black as display elements. It is placed between the first electrode layer and the second electrode layer, and a potential difference is applied between the first electrode layer and the second electrode layer. This method controls and displays the orientation of spherical particles by generating a specific phenomenon.

[0197] The thin-film transistor 581 provided on the substrate 580 is a thin-film transistor with a bottom gate structure. The source electrode layer or drain electrode layer is the first electrode layer 587 and the insulating layer 583, 5 The first electrode is electrically connected via contact holes formed at 84 and 585. Between layer 587 and the second electrode layer 588, there are black region 590a and white region 590b. And a spherical particle 589 is provided, which includes a cavity 594 filled with liquid around it. Furthermore, a filler material 595 such as resin is provided around the spherical particles 589 (see Figure 18). In 18, the first electrode layer 587 corresponds to the pixel electrode, and the second electrode layer 588 corresponds to the common electrode. This corresponds to a pole. The second electrode layer 588 is provided on the same substrate as the thin-film transistor 581. It is electrically connected to a common potential line. Using the common connection part shown in the above embodiment, a pair The conductive particles placed between the substrates allow the second electrode layer 588 provided on the substrate 596 to communicate with the substrate 596. It can be electrically connected to a common potential line.

[0198] Alternatively, an electrophoretic element can be used instead of a twist ball. In that case, A transparent liquid containing positively charged white particles and negatively charged black particles, with a diameter of 10 Microcapsules of approximately μm to 200 μm are used between the first electrode layer and the second electrode layer. The microcapsules provided are subjected to an electric field by a first electrode layer and a second electrode layer. When this happens, the white and black particles move in opposite directions, allowing for the display of either white or black. This principle is applied to display elements called electrophoretic display elements, and generally refers to electronic paper. It is called that. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lights It does not require a power supply, consumes little power, and allows the display to be seen even in dimly lit places. Yes. Furthermore, even if power is not supplied to the display unit, it can retain the image that has been displayed. Because this is possible, a semiconductor device with a display function (simply a display device, or a display) can be transmitted from the radio wave source. Even when the semiconductor device (also called a device equipped with the equipment) is moved away, the displayed image is saved. It becomes possible to do so.

[0199] As described above, highly reliable electronic paper can be manufactured as a semiconductor device.

[0200] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0201] (Embodiment 8) In this embodiment, an example of a light-emitting display device is shown as a semiconductor device that is one embodiment of the present invention. The display element of the display device is, in this case, a light-emitting element that utilizes electroluminescence. This is illustrated using the example. Electroluminescent light-emitting devices utilize organic compounds as their light-emitting material. They are distinguished by whether they are materials or inorganic compounds; generally, the former are organic EL elements, and the latter are inorganic compounds. These are called inorganic EL elements.

[0202] Organic EL elements emit electrons and holes from a pair of electrodes when a voltage is applied to the light-emitting element. Each of these is injected into a layer containing a luminescent organic compound, and an electric current flows through it. Then, these... The recombination of electrons and holes causes the luminescent organic compound to form an excited state. And when that excited state returns to the ground state, it emits light. From this mechanism, Such light-emitting devices are called current-excited light-emitting devices.

[0203] Inorganic electroluminescent (EL) elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements based on their element configuration. They are classified as such. Dispersive inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The luminescence mechanism utilizes donor and acceptor levels, and the donor-acceptor level is the key to this process. This is a receptor recombination type light emission. Thin-film inorganic EL elements sandwich the light-emitting layer between dielectric layers. Furthermore, it has a structure where it is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. This is a localized light emission. Here, we will explain using an organic EL element as the light-emitting element. ru.

[0204] Figure 19 shows an example of a semiconductor device that is one embodiment of the present invention to which digital time-gradation driving can be applied. This figure shows an example of a possible pixel configuration.

[0205] This section describes the pixel configuration and operation to which digital time-based gradation driving can be applied. This method uses an oxide semiconductor layer (In-Ga-Zn-O non-single crystal film) as the channel formation region. This example shows the use of two channel-type transistors in a single pixel.

[0206] Pixel 6400 consists of a switching transistor 6401, a driving transistor 6402, It has a light-emitting element 6404 and a capacitive element 6403. Switching transistor 64 01 has a gate connected to scan line 6406, and the first electrode (source electrode and drain electrode) The (side) is connected to signal line 6405, and the second electrode (the other of the source electrode and drain electrode) is driven It is connected to the gate of the drive transistor 6402. The drive transistor 6402 is The gate is connected to the power line 6407 via the capacitive element 6403, and the first electrode is connected to the power line 640 It is connected to 7, and the second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 6404. The second electrode of the light-emitting element 6404 corresponds to the common electrode 6408.

[0207] Furthermore, a low power supply potential is set for the second electrode (common electrode 6408) of the light-emitting element 6404. The low power supply potential is defined as the low power supply potential set on power line 6407 relative to the high power supply potential. The potential is the potential that satisfies the high power supply potential, and low power supply potentials include, for example, GND and 0V. It may be fixed. The potential difference between this high power supply potential and the low power supply potential is applied to the light-emitting element 6404. Then, in order to pass current through the light-emitting element 6404 and make the light-emitting element 6404 emit light, a high power supply potential is used. The potential difference between the low power supply potential and the light-emitting element 6404 is set to be greater than or equal to the forward threshold voltage of the light-emitting element 6404. Set the potential for each.

[0208] Note that the capacitive element 6403 is omitted by substituting the gate capacitance of the drive transistor 6402. This is also possible. Regarding the gate capacitance of the drive transistor 6402, the channel region A capacitance may be formed between the gate electrode and the gate electrode.

[0209] In the case of a voltage input / voltage drive method, the gate of the drive transistor 6402 is: The drive transistor 6402 is either fully on or completely off. The video signal is input. In other words, the driver transistor 6402 is operated in the linear region. The driver transistor 6402 operates in the linear region, therefore the voltage of the power line 6407 is higher than A high voltage is applied to the gate of the drive transistor 6402. The signal line 6405 is... Apply a voltage equal to or greater than (power line voltage + Vth of the drive transistor 6402).

[0210] Furthermore, when using analog gradation drive instead of digital time gradation drive, the signal input is different. By doing so, the same pixel configuration as in Figure 19 can be used.

[0211] When performing analog grayscale driving, the gate of the driving transistor 6402 is connected to the light-emitting element 6404 Apply a voltage equal to or greater than the forward voltage of the drive transistor 6402 + Vth. (Light-emitting element 64) The forward voltage of 04 refers to the voltage required to achieve the desired brightness, and at least the forward voltage is Includes key voltage. Note that the drive transistor 6402 operates in the saturation region. By inputting an O signal, current can be supplied to the light-emitting element 6404. The drive transistor... To operate the 6402 in the saturation region, the potential of the power line 6407 is set to the drive transistor The gate potential of the TA6402 is set higher. By making the video signal analog, the light-emitting element... By supplying current to the 6404 according to the video signal, analog grayscale driving can be performed.

[0212] Note that the pixel configuration shown in Figure 19 is not limited to this. For example, if new pixels are added to the pixels shown in Figure 19... Switches, resistors, capacitives, transistors, or logic circuits may be added to it.

[0213] Next, the configuration of the light-emitting element will be explained using Figure 20. Here, the driving TFT is n The cross-sectional structure of a pixel will be explained using the case of a type as an example. Figure 20(A)(B)(C) The TFT7001, 7011, and 7021, which are driver TFTs used in semiconductor devices, are above It can be fabricated in the same manner as the thin-film transistor shown in the embodiment described above, and is an In-Ga-Zn-O non-single-ended transistor. This is a highly reliable thin-film transistor that includes a crystal film as a semiconductor layer.

[0214] In order to extract light from a light-emitting element, it is sufficient that at least one of the anode or cathode is transparent. Then, a thin-film transistor and a light-emitting element are formed on the substrate, and light is emitted from the side opposite to the substrate. This includes top-side emission, bottom-side emission which extracts light from the substrate side, and on the substrate side and the opposite side of the substrate. There is a light-emitting element with a double-sided emission structure that extracts light from the side surface, and the pixel configuration is which emission structure It can also be applied to optical elements.

[0215] The light-emitting element with an upper surface injection structure will be explained using Figure 20(A).

[0216] Figure 20(A) shows that the driving TFT, TFT7001, is of n type, and the light-emitting element 7002 emits This shows a cross-sectional view of a pixel when the light being emitted passes through to the anode 7005 side. In Figure 20(A), The cathode 7003 of the light-emitting element 7002 and the driving TFT, TFT7001, are electrically connected. The cathode 7003 has a light-emitting layer 7004 and an anode 7005 stacked on top of it in that order. 7003 uses a variety of materials as long as the work function is small and the conductive film reflects light. This is possible. For example, Ca, Al, MgAg, AlLi, etc. are desirable. And the light-emitting layer 7 Whether 004 consists of a single layer or is configured with multiple layers stacked on top of each other Either is fine. If it consists of multiple layers, the electron injection layer is on the cathode 7003, and the electron transport layer is on top of the cathode 7003. The layers are stacked in the following order: transport layer, light-emitting layer, hole transport layer, and hole injection layer. There is no need to do so. The anode 7005 is formed using a conductive material that is translucent and transmits light. For example, indium oxide containing tungsten oxide, indium oxide containing tungsten oxide Lead oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, Indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, and silicon oxide are added. A transparent conductive layer, such as indium tin oxide, may also be used.

[0217] The region between the cathode 7003 and the anode 7005, which sandwiches the light-emitting layer 7004, is the light-emitting element 7002. It corresponds to the pixel shown in Figure 20(A), where the light emitted from the light-emitting element 7002 is the arrow. As indicated by the mark, inject towards the anode 7005 side.

[0218] Next, the light-emitting element with a bottom-extrusion structure will be explained using Figure 20(B). Driving TFT7 When 011 is of type n, and the light emitted from the light-emitting element 7012 is directed toward the cathode 7013 side, Figure 20(B) shows a cross-sectional view of the pixel. In Figure 20(B), the driving TFT7011 is electrically connected to the pixel. The cathode 7013 of the light-emitting element 7012 is formed on a light-transmitting conductive layer 7017. The light-emitting layer 7014 and the anode 7015 are stacked in order on the cathode 7013. If 015 is translucent, a shielding material to reflect or block light should be used to cover the anode. A film 7016 may be formed. The cathode 7013 is as in the case of Figure 20(A). Various materials can be used if the conductivity function is small. However, the film thickness is The film should be transparent enough to transmit light (preferably around 5 nm to 30 nm). For example, a 20 nm film. A thick aluminum film can be used as the cathode 7013. And the light-emitting layer 7 014, as in Figure 20(A), consists of a single layer, but multiple layers are stacked on top of each other. Either configuration is acceptable. The anode 7015 does not need to transmit light, but as shown in the diagram... Similar to 20(A), it can be formed using a light-transmitting conductive material. The shielding film 7016 can be made of, for example, a light-reflecting metal, but is not limited to a metal film. It's not possible. For example, a resin with black pigment added can be used.

[0219] The region between the cathode 7013 and anode 7015, sandwiching the light-emitting layer 7014, is the light-emitting element 7012. This corresponds to the pixel shown in Figure 20(B), where the light emitted from the light-emitting element 7012 is As indicated by the arrow, the material is injected towards the cathode 7013.

[0220] Next, a light-emitting element with a double-sided injection structure will be explained using Figure 20(C). Figure 20(C) Then, on the light-transmitting conductive layer 7027 electrically connected to the driving TFT 7021, The cathode 7023 of the light-emitting element 7022 is formed by depositing a film, and the light-emitting layer 7024 is on the cathode 7023. The anodes 7025 are stacked in order. The cathode 7023 is the same as in Figure 20(A). Various materials can be used if the conductivity function is small. However, the film thickness is ...to the extent that it transmits light. For example, Al with a film thickness of 20 nm is used as cathode 7023. It can be used. The light-emitting layer 7024 is composed of a single layer, as in Figure 20(A). It is acceptable whether it is configured as a single layer or as multiple layers stacked on top of each other. Anode 70 25 is formed using a light-transmitting conductive material, similar to Figure 20(A). It is possible.

[0221] The portion where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap is the light-emitting element 70 This corresponds to 22. In the case of the pixel shown in Figure 20(C), the light emitted from the light-emitting element 7022 As indicated by the arrows, the material is injected into both the anode 7025 side and the cathode 7023 side.

[0222] Here, we have discussed organic EL elements as light-emitting elements, but inorganic EL elements can also be used as light-emitting elements. It is also possible to incorporate an L element.

[0223] In this embodiment, a thin-film transistor (driving TFT) controls the driving of the light-emitting element, An example of electrically connected light-emitting elements was shown, but current is currently flowing between the driving TFT and the light-emitting element. A configuration in which a control TFT is connected is also acceptable.

[0224] The semiconductor device shown in this embodiment is not limited to the configuration shown in Figure 20. Various transformations are possible.

[0225] Next, the appearance of a light-emitting display panel (also called a light-emitting panel), which corresponds to a form of semiconductor device, and The cross-section will be explained using Figure 21. Figure 21(A) shows the formation on the first substrate 4501. A highly reliable thin-film transistor containing a processed In-Ga-Zn-O non-single-crystal film as a semiconductor layer. The zistas 4509, 4510 and the light-emitting element 4511 are sealed between them and the second substrate 4506. This is a top view of the panel sealed with material 4505, and Figure 21(B) is a top view of Figure 21(A). This corresponds to a cross-sectional view in HI.

[0226] Pixel section 4502, signal line driving circuit 4503a, 450 provided on the first substrate 4501 3b, and the scan line drive circuits 4504a and 4504b are surrounded by a sealing material 4505 A pixel unit 4502, signal line driving circuits 4503a, 4503b, and A second substrate 4506 is provided on top of the scan line driving circuits 4504a and 4504b. The pixel section 4502, signal line driving circuits 4503a, 4503b, and scan line driving circuit 45 04a and 4504b consist of a first substrate 4501, a sealing material 4505, and a second substrate 4506. It is sealed together with the filler 4507. Highly dense protective film with minimal degassing (laminated film, UV-curing resin film) It is preferable to package (seal) the product with a cover material such as a linoleum.

[0227] Also provided on the first substrate 4501 are the pixel section 4502, the signal line driving circuit 4503a, 4 503b, and the scan line driving circuits 4504a and 4504b have multiple thin-film transistors. In Figure 21(B), the thin-film transistor 4510 included in the pixel section 4502 and the signal The thin-film transistor 4509 included in the wire drive circuit 4503a is shown as an example.

[0228] Thin-film transistors 4509 and 4510 use an In-Ga-Zn-O non-single-crystal film as the semiconductor layer. A highly reliable thin-film transistor can be applied as such. Thin-film transistors 4509 and 4510 are n-channel thin-film transistors.

[0229] Furthermore, 4511 corresponds to a light-emitting element, and the first electrode is a pixel electrode of the light-emitting element 4511. Layer 4517 is electrically connected to the source electrode layer or drain electrode layer of the thin-film transistor 4510. It is connected to the following. The configuration of the light-emitting element 4511 is a first electrode layer 4517 and an electroluminescent layer The stacked structure consists of 4512 and a second electrode layer 4513, but is not limited to the configuration shown in this embodiment. It is not done. The direction of the light emitted from the light-emitting element 4511 is adjusted according to the direction of the light emitted from the light-emitting element 4511. The configuration can be changed as needed.

[0230] The partition wall 4520 is formed using an organic resin layer, an inorganic insulating layer, or an organic polysiloxane. In particular, using a photosensitive material, an opening is formed on the first electrode layer 4517, and the side wall of the opening It is preferable to form it so that it becomes an inclined surface with a continuous curvature.

[0231] Even if the electroluminescent layer 4512 consists of a single layer, it is configured to be stacked with multiple layers. It's fine either way.

[0232] To prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting element 4511, the second electrode layer A protective layer may be formed on 4513 and the partition wall 4520. The protective layer may be silicon nitride. It can form films, silicon nitride films, DLC films, and the like.

[0233] Also, signal line drive circuits 4503a, 4503b and scan line drive circuits 4504a, 4504b The various signals and potentials applied to the pixel section 4502 are FPC4518a, 4518 It is supplied by b.

[0234] In this embodiment, the connection terminal electrode 4515 is connected to the first electrode layer 4 of the light-emitting element 4511. Formed from the same conductive layer as 517, terminal electrode 4516 is thin-film transistor 4509, 4 The source electrode layer and drain electrode layer of 510 are formed from the same conductive layer.

[0235] The connecting terminal electrode 4515 is connected to the terminal of FPC4518a via the anisotropic conductive film 4519. They are electrically connected.

[0236] The second substrate 4506, located in the direction of light extraction from the light-emitting element 4511, must be translucent. It must be a glass plate, plastic plate, polyester film or A light-transmitting material, such as acrylic film, is used.

[0237] Furthermore, in addition to inert gases such as nitrogen and argon, UV-curable resin can also be used as the filler 4507. Oils or thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. This embodiment uses filler 4507 Nitrogen was used as the nitrogen.

[0238] Furthermore, if necessary, a polarizing plate or circular polarizing plate (including elliptical polarizing plate) may be placed on the emission surface of the light-emitting element. You may also appropriately incorporate optical films such as phase difference plates (λ / 4 plate, λ / 2 plate) and color filters. Furthermore, an anti-reflective coating may be provided on the polarizing plate or circular polarizing plate. For example, by the surface irregularities An anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0239] The signal line drive circuits 4503a and 4503b, and the scan line drive circuits 4504a and 4504b are Drive turns formed by a single-crystal semiconductor film or polycrystalline semiconductor film on a separately prepared substrate It may be implemented in the circuit. Also, only the signal line drive circuit, or part of it, or the scan line drive circuit The road may be formed separately or partially, and this embodiment is configured as shown in Figure 21. Not limited.

[0240] Through the above process, a highly reliable light-emitting display device (display panel) is manufactured as a semiconductor device. It is possible.

[0241] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0242] (Embodiment 9) One embodiment of the present invention, a semiconductor device, can be used as electronic paper. Super can be used in electronic devices in any field that display information. For example, using e-paper, e-books, posters, and trains. This can be applied to in-vehicle advertisements, displays on various cards such as credit cards, etc. Examples of electronic devices are shown in Figures 22 and 23.

[0243] Figure 22(A) shows poster 2631 made with electronic paper. In the case of printed materials, advertisements are changed manually, but with electronic paper... It allows you to change the ad display in a short amount of time. Furthermore, the display remains stable without any distortion. This can be obtained. Furthermore, the poster may be configured to transmit and receive information wirelessly.

[0244] Figure 22(B) also shows in-vehicle advertisements 2632 on trains and other vehicles. In the case of printed paper, advertisements are changed manually, but using electronic paper... This allows you to change the ad display quickly without requiring a lot of manpower. Also, the display will not break down. A stable image can be obtained without any issues. Furthermore, the in-car advertisements are configured to transmit and receive information wirelessly. That is also acceptable.

[0245] Figure 23 also shows an example of eBook 2700. For example, eBook 2700 is, It consists of two enclosures, enclosure 2701 and enclosure 2703. Enclosure 2701 and enclosure The body 2703 is integrated with the shaft portion 2711, and opens and closes around the shaft portion 2711 as an axis. It is possible to perform operations. This configuration makes it possible to operate like a paper book. This is the result.

[0246] The display unit 2705 is incorporated into the housing 2701, and the display unit 2707 is incorporated into the housing 2703. It is included. Display units 2705 and 2707 are configured to display a continuation screen. Alternatively, a configuration that displays different screens is also acceptable. For example, text is displayed on the right-hand display unit (display unit 2705 in Figure 23), and the left-hand display unit An image can be displayed on the display unit 2707 in Figure 23.

[0247] Furthermore, Figure 23 shows an example in which the housing 2701 is equipped with an operating unit, etc. For example, housing 2 Unit 701 is equipped with a power supply 2721, operation keys 2723, speaker 2725, and the like. The page can be turned using operation key 2723. Note that the key is located on the same side as the display unit of the casing. It may also be configured to include a board or pointing device. Furthermore, the back of the enclosure or On the side, there are external connection terminals (earphone jack, USB terminal, or AC adapter and USB A configuration that includes terminals that can connect to various cables such as cables, a recording medium insertion section, and so on. It may also be done this way. Furthermore, the eBook 2700 is configured to have the functionality of an electronic dictionary. That's fine.

[0248] Furthermore, the e-book 2700 may be configured to transmit and receive information wirelessly. By wireless means, The system will be configured to allow users to purchase and download desired book data from an e-book server. It is also possible.

[0249] (Embodiment 10) One embodiment of the present invention is a semiconductor device that can be applied to various electronic devices (including amusement machines). This can be done. As for electronic devices, for example, television equipment (television, or television) (Also called a receiver), computer monitors, digital cameras, digital video cameras Camera, digital photo frame, mobile phone (also called mobile phone or mobile phone device), mobile Examples include small game consoles, portable information terminals, sound playback devices, and large game machines such as pachinko machines. It can be done.

[0250] Figure 24(A) shows an example of the television equipment 9600. In the case of 00, the display unit 9603 is incorporated into the housing 9601. The display unit 9603 displays It is possible to display an image. Also, here, the stand 9605 is used to display the housing 9601 This shows a configuration that supports this.

[0251] The television unit 9600 is operated using the control switches on the housing 9601 and a separate remote control. This can be done using the control unit 9610. The remote control unit 9610 has control keys The 9609 allows you to control the channel and volume, and the information is displayed on the display unit 9603. The video can be controlled. Furthermore, the remote control unit 9610 can be controlled by the remote control unit. A display unit 9607 may be provided to display the information output from 9610.

[0252] The television system 9600 will consist of a receiver, modem, and other components. It can receive more general television broadcasts, and furthermore, it can connect via a modem, either wired or wirelessly. By connecting to the communication network, one-way (sender to receiver) or two-way communication is possible. It is also possible to communicate information (between a sender and a receiver, or between receivers, etc.).

[0253] Figure 24(B) shows an example of the digital photo frame 9700. For example, The photo frame 9700 has a display unit 9703 integrated into the housing 9701. Section 9703 is capable of displaying various images, such as those captured by a digital camera. By displaying the image data, it can function just like a regular photo frame.

[0254] The Digital Photo Frame 9700 includes an operating unit and external connection terminals (USB terminal, USB port). A structure that includes terminals that can connect to various cables such as B cables, a recording medium insertion section, etc. These components may be incorporated on the same surface as the display unit, but may also be on the sides or back. It is desirable to include it as it improves the design. For example, the recording medium of a digital photo frame. A memory device containing image data captured by a digital camera is inserted into the body insertion site. The system can capture data and display the captured image data on the display unit 9703.

[0255] Furthermore, the digital photo frame 9700 may be configured to send and receive information wirelessly. It is also possible to configure the system to acquire and display desired image data wirelessly.

[0256] Figure 25(A) shows a portable gaming machine, which consists of two casings, casing 9881 and casing 9891. It is connected by a connecting part 9893 so that it can be opened and closed. The housing 9881 has a display unit The 9882 is incorporated, and the display unit 9883 is incorporated into the housing 9891. The portable gaming machine shown in 25(A) also includes a speaker section 9884 and a recording medium insertion section 988 6. LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, electric current, voltage, power, radiation, flow rate, humidity, gradient, vibration Equipped with a function to measure motion, odor, or infrared radiation, a microphone (9889), etc. Of course, the configuration of portable gaming machines is not limited to those described above, and at least semiconductor equipment Any configuration that includes a storage unit is acceptable, and other auxiliary equipment may be provided as appropriate. The portable gaming machine shown in Figure 25(A) contains programs or data recorded on the recording medium. It has a function to read data and display it on the display unit, and it can also share information by wirelessly communicating with other portable gaming machines. It has the function of [doing something]. However, the functions of the portable gaming machine shown in Figure 25(A) are not limited to this. It can have various functions.

[0257] Figure 25(B) shows an example of a large-scale gaming machine, the slot machine 9900. The machine 9900 has a display unit 9903 integrated into the casing 9901. The Machine 9900 also features other operating mechanisms such as a start lever and stop switch, and coins. It is equipped with an input slot, speaker, etc. Of course, the configuration of the slot machine 9900 is as described above. Not limited to a specific object, but any configuration comprising a semiconductor device relating to at least one embodiment of the present invention Often, the system can be configured with other auxiliary equipment as appropriate.

[0258] Figure 26(A) shows an example of the mobile phone 1000. The mobile phone 1000 has a housing In addition to the display unit 1002 incorporated into 1001, there are also operation buttons 1003 and an external connection port 10 It is equipped with 04, speaker 1005, microphone 1006, etc.

[0259] The mobile phone 1000 shown in Figure 26(A) allows information to be conveyed by touching the display unit 1002 with a finger or the like. You can enter information. Also, operations such as making phone calls or sending emails are available. This can be done by touching the indicator part 1002 with a finger or the like.

[0260] The display unit 1002 has three main modes. The first is a display that primarily displays images. The first mode is display mode, the second is input mode which is mainly for inputting information such as characters. The third is display mode. This is a display + input mode, which is a combination of two modes: display mode and input mode.

[0261] For example, when making a phone call or composing an email, the display unit 1002 is used for text input. In this case, the primary text input mode should be used, and you should perform the input operation for the characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002. It seems so.

[0262] Furthermore, the mobile phone 1000 contains sensors that detect tilt, such as a gyroscope and an accelerometer. By providing a detection device, the orientation (vertical or horizontal) of the mobile phone 1000 can be determined, and the display The display on the display unit 1002 can be automatically switched.

[0263] Furthermore, the screen mode can be switched by touching the display unit 1002 or by operating the housing 1001. This is done by operating button 1003. Also, the type of image displayed on display unit 1002 Therefore, it is also possible to switch between them. For example, the image signal displayed on the display unit is a video signal. Switch to display mode if it's data, or to input mode if it's text data.

[0264] Furthermore, in input mode, the signal detected by the optical sensor of the display unit 1002 is detected and displayed If there is no input via touch operation on unit 1002 for a certain period of time, the screen mode will be changed to input mode. You may also control the system to switch from that display mode to a different mode.

[0265] The display unit 1002 can also function as an image sensor. For example, the display unit 10 By touching the palm or fingers to device 02, the device can capture palm prints, fingerprints, etc., to perform identity verification. It can also be used. In addition, the display unit has a backlight that emits near-infrared light or a sensor that emits near-infrared light. Using a light source designed for imaging, it is also possible to image finger veins, palmar veins, and other veins.

[0266] Figure 26(B) is also an example of a mobile phone. The mobile phone in Figure 26(B) has a housing 9411. The display device 9410 includes a display unit 9412 and an operation button 9413, and the housing 9401 Operation buttons 9402, external input terminal 9403, microphone 9404, speaker 9405, and It has a communication device 9400 which includes a light-emitting unit 9406 that emits light when an incoming call is received, and has a display function. The display device 9410 is detachable from the communication device 9400, which has telephone functionality, in two directions indicated by the arrows. Yes. Therefore, it is also possible to attach the short axes of the display device 9410 and the communication device 9400 together. The long axes of the display device 9410 and the communication device 9400 can also be attached together. If only the functionality is required, remove the display device 9410 from the communication device 9400, and the display device The 9410 can also be used independently. The communication device 9400 and the display device 9410 are connected wirelessly. Images or input information can be sent and received via wireless or wired communication, and each has a rechargeable battery. Close Terry. [Explanation of symbols]

[0267] 190 Chamber 191 Electrode 192 Electrode 193 Matching Box 194 Matching Box 195. Items to be processed 196 Inlet 197 RF power supply 198 RF power supply 199 DC power supply 200 circuit boards 202 Grid Layer 204 Gate Insulation Layer 206 Conductive layer 207 Recess 208 Plasma 209 Oxide semiconductor layer 210 Oxide semiconductor layer 213 Contact Holes 217 Oxide semiconductor layer 250 Thin-Film Transistors 251 Insulating layer 252 Insulating layer 260 Thin-Film Transistors 270 Thin-Film Transistors 271 Thin-film transistors 272 Thin-Film Transistors 280 Thin-Film Transistors 290 Thin-Film Transistors 302 Gate Wiring 308 Capacitance wiring 310 Transparent conductive layer 320 connecting electrodes 321 terminals 322 terminals 325 Contact Holes 326 Contact Holes 327 Contact Holes 328 Transparent conductive layer 329 Transparent conductive layer 340 Protective insulating layer 580 circuit boards 581 Thin-film transistor 583 Insulating layer 584 Insulating layer 585 Insulating layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 594 Cavity 595 Filling material 596 circuit boards 1000 mobile phones 1001 enclosure 1002 Display section 1003 Operation Buttons 1004 External connection port 1005 Speaker 1006 Mike 206a Source electrode layer 206b Drain electrode layer 217a Buffer layer 217b Buffer layer 2600 TFT substrate 2601 Opposing substrate 2602 Sealant 2603 pixel section 2604 display elements 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible Wiring Board 2610 cold cathode tube 2611 Reflector 2612 Circuit board 2613 Diffuser 2631 Poster 2632 In-car advertisement 2700 eBooks 2701 enclosure 2703 Casing 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation Keys 2725 Speaker 4001 circuit board 4002 pixel section 4003 Signal Line Drive Circuit 4004 Scan Line Drive Circuit 4005 Sealant 4006 circuit board 4008 Liquid Crystal Layer 4010 Thin-Film Transistor 4011 Thin-film transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulating layer 4021 Insulating layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulating layer 4033 Insulating layer 4501 circuit board 4502 pixel section 4505 Sealant 4506 circuit board 4507 Filling material 4509 Thin-film transistor 4510 Thin-Film Transistor 4511 Light-emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4519 Anisotropic conductive film 4520 Bulkhead 590a black area 590b White area 6400 pixels 6401 Switching Transistor 6402 drive transistor 6403 Capacitive element 6404 Light-emitting element 6405 signal line 6406 scan lines 6407 Power line 6408 Common electrode 7001 TFT 7002 Light-emitting element 7003 Cathode 7004 Emitting layer 7005 Anode 7011 Drive TFT 7012 Light-emitting element 7013 Cathode 7014 Emitting layer 7015 Anode 7016 Shielding membrane 7017 Conductive layer 7021 Drive TFT 7022 Light-emitting element 7023 Cathode 7024 Emitting layer 7025 Anode 7027 Conductive layer 9400 Communication equipment 9401 enclosure 9402 Operation Buttons 9403 External input terminal 9404 Microphone 9405 speaker 9406 Light-emitting part 9410 Display device 9411 enclosure 9412 Display section 9413 Operation Buttons 9600 Television equipment 9601 enclosure 9603 Display section 9605 Stand 9607 Display section 9609 Operation Keys 9610 Remote Control Unit 9700 Digital Photo Frame 9701 enclosure 9703 Display section 9881 cabinet 9882 Display section 9883 Display section 9884 Speaker section 9885 Operation Keys 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 cabinet 9893 Connection section 9900 slot machines 9901 cabinet 9903 Display section 4503a Signal Line Drive Circuit 4503b Signal line drive circuit 4504a Scan line drive circuit 4504b Scan line drive circuit 4518a FPC 4518b FPC

Claims

1. It comprises a first substrate, a second substrate, a liquid crystal, and a spacer. The liquid crystal and the spacer are liquid crystal display devices disposed between the first substrate and the second substrate, It comprises a first conductive layer, a first insulating layer, a second insulating layer, a second conductive layer, a third conductive layer, an oxide semiconductor layer, a third insulating layer, and a fourth conductive layer. The first conductive layer has the function of a gate electrode of a transistor and the function of gate wiring. The first insulating layer has a region in contact with the upper surface of the first conductive layer, The second insulating layer has a region in contact with the upper surface of the first insulating layer, The second conductive layer has a region in contact with the upper surface of the second insulating layer, The second conductive layer functions as either the source electrode or the drain electrode of the transistor. The third conductive layer has a region in contact with the upper surface of the second insulating layer, The third conductive layer functions as either the source electrode or the drain electrode of the transistor. The oxide semiconductor layer has a channel formation region for the transistor, The third insulating layer has a region in contact with the upper surface of the second conductive layer, a region in contact with the upper surface of the oxide semiconductor layer, and a region in contact with the upper surface of the third conductive layer. The fourth conductive layer functions as a pixel electrode and is electrically connected to the third conductive layer. The second insulating layer has a first region, a second region, and a third region. The first region does not overlap with the second conductive layer, does not overlap with the third conductive layer, and overlaps with the first conductive layer. The second region overlaps with the second conductive layer, The third region overlaps with the third conductive layer, The film thickness in the first region is thinner than the film thickness in the second region. The film thickness in the first region is thinner than the film thickness in the third region. The spacer overlaps with the oxide semiconductor layer in a liquid crystal display device.

2. It comprises a first substrate, a second substrate, a liquid crystal, and a spacer. The liquid crystal and the spacer are liquid crystal display devices disposed between the first substrate and the second substrate, It comprises a first conductive layer, a first insulating layer, a second insulating layer, a second conductive layer, a third conductive layer, an oxide semiconductor layer, a third insulating layer, and a fourth conductive layer. The first conductive layer has the function of a gate electrode of a transistor and the function of gate wiring. The first insulating layer has a region in contact with the upper surface of the first conductive layer, The second insulating layer has a region in contact with the upper surface of the first insulating layer, The dielectric constant of the first insulating layer is higher than that of the second insulating layer. The second conductive layer has a region in contact with the upper surface of the second insulating layer, The second conductive layer functions as either the source electrode or the drain electrode of the transistor. The third conductive layer has a region in contact with the upper surface of the second insulating layer, The third conductive layer functions as either the source electrode or the drain electrode of the transistor. The oxide semiconductor layer has a channel formation region for the transistor, The third insulating layer has a region in contact with the upper surface of the second conductive layer, a region in contact with the upper surface of the oxide semiconductor layer, and a region in contact with the upper surface of the third conductive layer. The fourth conductive layer functions as a pixel electrode and is electrically connected to the third conductive layer. The second insulating layer has a first region, a second region, and a third region. The first region does not overlap with the second conductive layer, does not overlap with the third conductive layer, and overlaps with the first conductive layer. The second region overlaps with the second conductive layer, The third region overlaps with the third conductive layer, The film thickness in the first region is thinner than the film thickness in the second region. The film thickness in the first region is thinner than the film thickness in the third region. The spacer overlaps with the oxide semiconductor layer in a liquid crystal display device.

3. It comprises a first substrate, a second substrate, a liquid crystal, and a spacer. The liquid crystal and the spacer are liquid crystal display devices disposed between the first substrate and the second substrate, It comprises a first conductive layer, a first insulating layer, a second insulating layer, a second conductive layer, a third conductive layer, an oxide semiconductor layer, a third insulating layer, and a fourth conductive layer. The first conductive layer has the function of a gate electrode of a transistor and the function of gate wiring. The first insulating layer has a region in contact with the upper surface of the first conductive layer, The second insulating layer has a region in contact with the upper surface of the first insulating layer, The second conductive layer has a region in contact with the upper surface of the second insulating layer, The second conductive layer functions as either the source electrode or the drain electrode of the transistor. The third conductive layer has a region in contact with the upper surface of the second insulating layer, The third conductive layer functions as either the source electrode or the drain electrode of the transistor. The oxide semiconductor layer has a channel formation region for the transistor, The third insulating layer has a region in contact with the upper surface of the second conductive layer, a region in contact with the upper surface of the oxide semiconductor layer, and a region in contact with the upper surface of the third conductive layer. The fourth conductive layer has the function of a pixel electrode, The second insulating layer has a first region, a second region, and a third region. The first region does not overlap with the second conductive layer, does not overlap with the third conductive layer, and overlaps with the first conductive layer. The second region overlaps with the second conductive layer, The third region overlaps with the third conductive layer, The film thickness in the first region is thinner than the film thickness in the second region. The film thickness in the first region is thinner than the film thickness in the third region. The fourth conductive layer is electrically connected to the third conductive layer via a contact hole provided in the third insulating layer. In a plan view, the contact hole does not overlap with the first conductive layer. The spacer overlaps with the oxide semiconductor layer in a liquid crystal display device.

4. It comprises a first substrate, a second substrate, a liquid crystal, and a spacer. The liquid crystal and the spacer are liquid crystal display devices disposed between the first substrate and the second substrate, It comprises a first conductive layer, a first insulating layer, a second insulating layer, a second conductive layer, a third conductive layer, an oxide semiconductor layer, a third insulating layer, and a fourth conductive layer. The first conductive layer has the function of a gate electrode of a transistor and the function of gate wiring. The first insulating layer has a region in contact with the upper surface of the first conductive layer, The second insulating layer has a region in contact with the upper surface of the first insulating layer, The dielectric constant of the first insulating layer is higher than that of the second insulating layer. The second conductive layer has a region in contact with the upper surface of the second insulating layer, The second conductive layer functions as either the source electrode or the drain electrode of the transistor. The third conductive layer has a region in contact with the upper surface of the second insulating layer, The third conductive layer functions as either the source electrode or the drain electrode of the transistor. The oxide semiconductor layer has a channel formation region for the transistor, The third insulating layer has a region in contact with the upper surface of the second conductive layer, a region in contact with the upper surface of the oxide semiconductor layer, and a region in contact with the upper surface of the third conductive layer. The fourth conductive layer has the function of a pixel electrode, The second insulating layer has a first region, a second region, and a third region. The first region does not overlap with the second conductive layer, does not overlap with the third conductive layer, and overlaps with the first conductive layer. The second region overlaps with the second conductive layer, The third region overlaps with the third conductive layer, The film thickness in the first region is thinner than the film thickness in the second region. The film thickness in the first region is thinner than the film thickness in the third region. The fourth conductive layer is electrically connected to the third conductive layer via a contact hole provided in the third insulating layer. In a plan view, the contact hole does not overlap with the first conductive layer. The spacer overlaps with the oxide semiconductor layer in a liquid crystal display device.

5. In any one of claims 1 to 4, The fourth conductive layer does not overlap with the oxide semiconductor layer in the liquid crystal display device.

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