Lamp generator

Abstract

This invention provides a lamp generator for generating lamp signals using an image sensor. [Solution] The lamp generator 10 includes a bias voltage generation unit 300 that generates a bias voltage and a plurality of lamp cells 410 that generate lamp signals based on the bias voltage, and each of the plurality of lamp cells 410 may include a local sampling unit 411 that adjusts the sampling timing of the bias voltage.

Description

Technical Field

[0001] The present invention relates to a ramp generator for generating a ramp signal with an image sensor.

Background Art

[0002] Generally, a CMOS (Complementary Metal Oxide Semiconductor) image sensor (CIS; CMOS Image Sensor) implemented in a CMOS process is rapidly expanding its market due to advantages such as low power consumption, low cost, and small size compared to other competing products. In particular, the CMOS image sensor is gradually expanding its application range to the video field that requires high resolution and high-speed frame rate through image quality improvement that was relatively lacking compared to competing products.

[0003] Unlike a solid-state imaging device, such a CMOS image sensor requires an operation to convert an analog signal (pixel signal) output from a pixel array into a digital signal. The CMOS image sensor uses a high-resolution analog-to-digital converter (ADC: Analog to Digital Converter) internally for the conversion from an analog signal to a digital signal.

[0004] The analog-to-digital converter can perform correlated double sampling (CDS: Correlated Double Sampling) on the analog output voltage, which is the output signal of the pixel array. Also, the analog-to-digital converter can provide a comparison signal for digital code generation by comparing the voltage stored in the correlated double sampling operation in response to the ramp signal generated by the ramp signal generator with a predetermined reference voltage (ramp signal).

[0005] However, since the lamp signal generator generates the lamp signal based on the power supply voltage, power noise or noise from the lamp signal generator itself may be directly included in the output lamp signal. Such noise can increase horizontal noise in CMOS image sensors (CIS). Therefore, in order to realize high-resolution and high-speed CMOS image sensors, a method for efficiently reducing horizontal noise is necessary. [Overview of the project] [Problems that the invention aims to solve]

[0006] Embodiments of the present invention provide an image sensing device that removes lamp noise and reduces horizontal noise. [Means for solving the problem]

[0007] An embodiment of the present invention includes a bias voltage generation unit that generates a bias voltage, and a plurality of lamp cells that generate a lamp signal based on the bias voltage, each of which may include a local sampling unit that adjusts the sampling timing of the bias voltage.

[0008] A lamp generator according to another embodiment of the present invention includes a first local sampling unit that samples a bias voltage based on a first control signal, and a first lamp cell that generates a lamp signal based on the sampling operation of the first local sampling unit; and a second local sampling unit that samples a bias voltage based on a second control signal, and a second lamp cell that generates a lamp signal based on the sampling operation of the second local sampling unit, wherein the first and second control signals may be activated at different timings. [Effects of the Invention]

[0009] Embodiments of the present invention can reduce horizontal noise and improve the noise characteristics of an image sensor.

[0010] Furthermore, the embodiments of the present invention are illustrative, and those skilled in the art can make various modifications, changes, substitutions, and additions through the technical idea and scope of the appended claims, and such modifications and changes should be considered to fall within the scope of the following claims. [Brief explanation of the drawing]

[0011] [Figure 1] This is a diagram illustrating the configuration of a lamp generator according to one embodiment of the present invention. [Figure 2] Figure 1 is an illustrative circuit diagram of the bias voltage generation unit. [Figure 3] Figure 1 is an illustrative circuit diagram relating to the lamp signal generation unit. [Figure 4] Figure 3 is a circuit diagram that specifically shows the multiple lamp cells. [Figure 5] Figure 4 is a diagram illustrating the noise reduction operation of the ramp cell shown. [Figure 6] Figure 4 is a waveform diagram illustrating the noise reduction operation in the ramp cell shown. [Figure 7] Figure 1 is a configuration diagram of an image sensing device including a lamp generator. [Modes for carrying out the invention]

[0012] Various embodiments will be described below with reference to the attached drawings. However, this disclosure should be understood not to be limited to any particular embodiment, but to include various modifications, equivalents, and / or alternatives of the embodiments. Embodiments of this disclosure can provide a variety of effects that can be directly or indirectly recognized through this disclosure.

[0013] Figure 1 is a diagram showing the configuration of a lamp generator according to one embodiment of the present invention.

[0014] Referring to Figure 1, the ramp generator 10 can generate a ramp signal (VRAMP) necessary for analog-to-digital conversion operation and supply it to the ADC (described later). For example, the ramp generator 10 can be implemented in a current steering digital-to-analog converting device for adjusting the gain of an image sensor by adjusting the current.

[0015] The lamp generator 10 may include a current generation unit 100, a current control unit 200, a bias voltage generation unit 300, a lamp signal generation unit 400, and a control signal generation unit 500.

[0016] Here, the current generation unit 100 can generate a reference current (IREF) based on a reference voltage (VREF). For example, the current generation unit 100 may correspond to a circuit that converts an input voltage to a current. For example, the current generation unit 100 may include an operational amplifier-based voltage-to-current converter, a transistor-based voltage-to-current converter, or an integrated circuit (IC)-based voltage-to-current converter, but the type of converter is not limited to these.

[0017] For example, a reference voltage (VREF) can be generated from a bandgap reference circuit (not shown). A bandgap reference circuit can generate a reference voltage (VREF) that has a constant level with little variation due to changes in the manufacturing process, electrical load, time, or ambient temperature.

[0018] And the current control unit 200 can control the value of the basic reference current (IREF) to adjust the gain of the image sensor. For example, the current control unit 200 receives the reference current (IREF) from the current generation unit 100 and can output a current (IDAC) corresponding to the adjusted gain by adjusting the gain of the input reference current (IREF).

[0019] For example, the current control unit 200 may include a current steering circuit and a current mirroring circuit. The current steering circuit can be connected to the current generation unit 100 in a current mirror structure, and the ratio of the copy of the reference current (IREF) can be determined by the current steering operation. The current mirroring circuit can mirror the current applied from the current steering circuit and provide the current (IDAC) to the bias voltage generation unit 300.

[0020] The bias voltage generation unit 300 can generate a bias voltage (VBIAS) based on the current (IDAC). The bias voltage (VBIAS) can determine the reference voltage level of the ramp signal (VRAMP). The bias voltage generation unit 300 can adjust the bias voltage (VBIAS) to regulate the average voltage level of the ramp signal (VRAMP).

[0021] For example, the bias voltage generation unit 300 may include a resistive element, an operational amplifier, a transistor, or an integrated circuit-based current-voltage converter, but the type of the converter is not limited thereto. As an example, a partial configuration of the bias voltage generation unit 300 can form a current mirroring circuit together with a partial configuration of the current control unit 200. The detailed configuration of the bias voltage generation unit 300 will be described later in FIG. 2.

[0022] The ramp signal generation unit 400 can generate a ramp signal (VRAMP) based on a bias voltage (VBIAS), a switch control signal (SWC), and a sampling control signal (SSC). The ramp signal generation unit 400 can control the waveform of the ramp signal (VRAMP), for example, its slope, based on the bias voltage (VBIAS) and the switch control signal (SWC). Furthermore, the ramp signal generation unit 400 can reduce noise in the ramp signal (VRAMP) based on the sampling control signal (SSC). The detailed configuration and operation of the ramp signal generation unit 400 will be described later in Figures 3 to 7.

[0023] In this disclosure, the ramp signal generation unit 400 may include a local sampling unit 411. The local sampling unit 411 can sample the bias voltage (VBIAS) applied from the bias voltage generation unit 300. The local sampling unit 411 can reduce correlation noise between ramp cells by controlling the operating timing of multiple ramp cells (described later) contained within the ramp signal generation unit 400 differently from each other. This reduces the noise in the ramp signal (VRAMP) generated by the ramp signal generation unit 400. The detailed configuration and operation of such a local sampling unit 411 will be described later in Figures 3 to 7.

[0024] The control signal generation unit 500 can generate a switch control signal (SWC) and a sampling control signal (SSC) for controlling the operation of the ramp signal generation unit 400 based on the control signal (CON). The control signal (CON) may be a signal generated by a timing controller, which will be described later. In this disclosure, the configuration of the control signal generation unit 500 is shown separately, but the control signal generation unit 500 may be a configuration included in the timing controller of the image sensor, which will be described later. A detailed explanation of the switch control signal (SWC) and sampling control signal (SSC) generated by the control signal generation unit 500 will be given later in Figures 3 to 7.

[0025] Figure 2 is an exemplary circuit diagram relating to the bias voltage generation unit shown in Figure 1.

[0026] Referring to Figure 2, the bias voltage generation unit 300 can convert the current (IDAC) applied from the current control unit 200 into a bias voltage (VBIAS).

[0027] The bias voltage generation unit 300 may include a transistor (P1). For example, the transistor (P1) may be a PMOS transistor.

[0028] A transistor (P1) may be connected between the terminal to which the power supply voltage (VDD) is applied and the terminal to which the current (IDAC) is applied. The gate terminal and drain terminal of transistor (P1) may be commonly connected, and a current (IDAC) may be applied.

[0029] Figure 3 is an exemplary circuit diagram relating to the lamp signal generation unit shown in Figure 1.

[0030] Referring to Figure 3, the lamp signal generation unit 400 may include a lamp cell 410 and a load unit 420.

[0031] The ramp cell 410 can generate a ramp signal (VRAMP) necessary for analog-to-digital conversion operation based on a bias voltage (VBIAS), a switch control signal (SWC), and a sampling control signal (SSC).

[0032] Depending on the embodiment, the ramp cell 410 can be embodied in multiple units and share a load unit 420. In this disclosure, it is described that one load unit 420 is shared by multiple ramp cells 410, but the present invention is not limited thereto. For example, the number of load units 420 may be more or less than the number of ramp cells 410, or they may be the same number.

[0033] The lamp cell 410 may include a transistor (P2), a switch (SW1), a local sampling unit 411, and a sampling control unit 412.

[0034] For example, transistor (P2) may be a PMOS transistor. Transistor (P2) may be connected between the terminal to which the power supply voltage (VDD) is applied and the node (ND2). A sampling voltage (VS) may be applied to transistor (P2) via its gate terminal. Transistor (P2) may selectively supply the power supply voltage (VDD) to the node (ND2) based on the sampling voltage (VS). Transistor (P2) may operate as a variable current source that adjusts the minute current supplied to the node (ND2) in response to the sampling voltage (VS).

[0035] A switch (SW) is connected between nodes (ND2) and (ND3), and its switching operation can be selectively controlled by a switch control signal (SWC). If there are multiple ramp cells 410, the ramp signal (VRAMP) can be controlled by adjusting the number of switches (SW) connected by multiple switch control signals (SWC).

[0036] The local sampling unit 411 can generate a sampling voltage (VS) by adjusting the sampling timing of the bias voltage (VBIAS) based on the sampling control signal (SSC). For example, the local sampling unit 411 can sample the bias voltage (VBIAS) during the ramping interval of the ramp signal (VRAMP). In this disclosure, if there are multiple ramp cells 410, each ramp cell 410 may contain a local sampling unit 411, hence the name "local".

[0037] Such a local sampling unit 411 may include a sampling switch (N1) and a sampling capacitor (C1).

[0038] Here, the sampling switch (N1) is connected between the bias voltage (VBIAS) application terminal and the node (ND1), and its switching operation can be controlled by a control signal (D). For example, the sampling switch (N1) may be a transistor connected between the bias voltage (VBIAS) application terminal and the node (ND1), to which the control signal (D) is applied via the gate terminal. For example, the sampling switch (N1) may be an NMOS transistor. The sampling capacitor (C1) may be connected between the power supply voltage (VDD) application terminal and the node (ND1).

[0039] When the sampling switch (N1) is turned on, the bias voltage (VBIAS) can be directly transmitted to the transistor (P2). That is, the bias voltage (VBIAS) can be applied to the sampling voltage (VS). On the other hand, when the sampling switch (N1) is turned off, a constant sampling voltage (VS) sampled and maintained by the sampling capacitor (C1) can be transmitted to the transistor (P2). As an example, it is preferable that the sampling switch (N1) be controlled within a row time interval in response to a control signal (D) from the sampling control unit 412.

[0040] Thus, the ramp signal generation unit 400 according to this disclosure includes a local sampling unit 411 within each ramp cell 410 and samples the bias voltage (VBIAS) transmitted to the transistor (P2) within each ramp cell 410, thereby blocking temporally transmitted ramp noise and reducing horizontal noise.

[0041] The sampling control unit 412 can adjust the operating timing of the local sampling unit 411 in each ramp cell 410 based on the sampling control signal (SSC) applied from the control signal generation unit 500. For example, if there are multiple ramp cells 410, the operating timing of the local sampling unit 411 contained within each ramp cell 410 can be controlled differently from one another. In such a case, correlation noise between ramp cells 410 can be reduced. The detailed configuration and operation of the sampling control unit 412 will be described later in Figure 4.

[0042] The load unit 420 can control the loading of the ramp signal (VRAMP) generated by the ramp cell 410. Such a load unit 420 may include, but is not limited to, a variable resistor (R1) whose resistance value can be changed to perform offset adjustment. The variable resistor (R1) is connected between the node (ND3) and the ground voltage terminal and its resistance level can be adjusted. As an example, the resistance level of the variable resistor (R1) may be adjusted based on a control signal (not shown) applied from the control signal generation unit 500.

[0043] As the resistance of the load section 420 decreases, the interval between the maximum and minimum voltage levels of the ramp signal (VRAMP), i.e., the swing range, may decrease. For example, if the swing range of the ramp signal (VRAMP) is relatively small, image data corresponding to a relatively large value may be generated for the same pixel signal. In other words, the analog gain may increase. Conversely, as the resistance of the load section 420 increases, the swing range of the ramp signal (VRAMP) may increase. For example, if the swing range of the ramp signal (VRAMP) is relatively large, image data corresponding to a relatively small value may be generated for the same pixel signal. In other words, the analog gain may decrease.

[0044] Figure 4 is a circuit diagram that specifically shows the multiple lamp cells shown in Figure 3.

[0045] Referring to Figure 4, the lamp signal generation unit 400 according to this disclosure may include m lamp cells (410<0:m-1>).

[0046] For example, lamp cell (410 <0> ) consists of a transistor (P2), a switch (SW1), and a local sampling unit (411 <0> ), and a sampling control unit (412_1) may be included. The sampling control unit (412_1) delays the sampling control signal (SSC) by a certain amount of time and controls the control signal (D <1> A control signal (D) can be generated. For example, the sampling control unit (412_1) may include a plurality of inverters (IV1, IV2) that non-invert the sampling control signal (SSC). The sampling control unit (412_1) can bypass the sampling control signal (SSC) without delay operation. <0> The signal (D) output by the sampling control unit (412_1) can be output to the gate terminal of the sampling switch (N1). <1> This can be transmitted to the gate terminal of the sampling switch (N2) at the rear end.

[0047] Lamp cell (410 <1> ) consists of a transistor (P3), a switch (SW2), and a local sampling section (411 <1> ), and a sampling control unit (412_2) may be included. The sampling control unit (412_2) is a control signal (D <1> ) delays the control signal (D <m-2>) can be generated. For example, the sampling control unit (412_2) can generate a control signal (D <1> It may include multiple inverters (IV3, IV4) that control the non-inverting signal (D) output by the sampling control unit (412_2). <m-2>This can be transmitted to the gate terminal of the sampling switch (N3) at the rear end.

[0048] Lamp cell (410 <m-2>) consists of a transistor (P4), a switch (SW3), and a local sampling section (411 <m-2>), and a sampling control unit (412_3) may be included. The sampling control unit (412_3) is a control signal (D <m-2>) delays the control signal (D <m-1>) can be generated. For example, the sampling control unit (412_3) can generate a control signal (D <m-2>It may include multiple inverters (IV5, IV6) that control the non-inverting signal (D) output by the sampling control unit (412_3). <m-1>This can be transmitted to the gate terminal of the sampling switch (N4) at the rear end.

[0049] Lamp cell (410 <m-1>) consists of a transistor (P5), a switch (SW4), and a local sampling unit (411 <m-1>) may be included. If the number of lamp cells is m, the last lamp cell (410 <m-1>The ) does not necessarily have to include a sampling control unit, but if the number of ramp cells is changed depending on the embodiment, a sampling control unit may be included. The configuration and operation for each of the m ramp cells (410<0:m-1>) are the same as in Figure 3, so the explanation of the redundant connection structure and operation is omitted.

[0050] m ramp cells (410<0:m-1>) can perform sampling operations at different timings according to control signals (D<0:m-1>) which are obtained by delaying the sampling control signal (SSC) by different times from each other. That is, local sampling unit (411 <0> ) is a sampling control signal (SSC), that is, a control signal with no delay time (D <0> It can be operated by the local sampling unit (411 <1> ) is a control signal (D) delayed by the sampling control unit (412_1). <1> ) operates by the local sampling unit (411 <0> It can operate slower than the local sampling unit (411 <m-2>) is a control signal (D) delayed by the sampling control unit (412_2). <m-2>) operates by the local sampling unit (411 <1> It can operate slower than the local sampling unit (411 <m-1>) is a control signal (D) delayed by the sampling control unit (412_3). <m-1>) operates by the local sampling unit (411 <m-2>It can operate at a slower rate than ).

[0051] In this disclosure, m ramp cells (410<0:m-1>) are described as performing sequential sampling operations with different delay times. However, this disclosure is not limited to this, and by adjusting the configuration of the sampling control units (412_1~412_3) and the delay times, m ramp cells (410<0:m-1>) can also perform selective sampling operations.

[0052] When m ramp cells (410<0:m-1>) share a single local sampling unit, a single sampling voltage (VS) allows the m ramp cells (410<0:m-1>) to perform sampling operations. In such a case, the correlation noise of the m ramp cells (410<0:m-1>) can be increased.

[0053] Therefore, in this disclosure, a separate local sampling unit (411<0:m-1>) is included for each m ramp cell (410<0:m-1>), allowing each ramp cell (410<0:m-1>) to perform sampling operations individually. This allows the m ramp cells (410<0:m-1>) to perform sampling operations at different timings, thereby reducing correlation noise between each ramp cell. A detailed explanation of this operation will be given later in Figures 5 and 6.

[0054] Figure 5 is a diagram illustrating the noise reduction operation of the ramp cell shown in Figure 4. And Figure 6 is a waveform diagram illustrating the noise reduction operation of the ramp cell shown in Figure 4.

[0055] Referring to Figures 5 and 6, the voltage applied from the bias voltage generation unit 300 is V SIG We define the noise applied from the bias voltage generation unit 300 as N(t). Therefore, the bias voltage (VBIAS) is the voltage V SIG The x(t) value can be obtained by adding the noise and N(t).

[0056] A bias voltage (VBIAS) can be input to the ramp signal generation unit 400. m local sampling units (411<0:m-1>) can perform sampling operations using m control signals (D<0:m-1>). In Figure 5, since the m control signals (D<0:m-1>) are activated at different timings, the m control signals (D<0:m-1>) may be defined as δ(tT), δ(t-2T), δ(t-(m-1)T), and δ(t-mT), respectively. Here, "T" may represent the multiplier of the delay time.

[0057] As an example, as shown in Figure 6, m control signals (D<0:m-1>) can be activated by transitioning at logically low levels at different timings. <0> ) is activated, and after a certain period of time the control signal (D <1> ) may be activated. Control signal (D <1> ) is activated, and after a certain period of time the control signal (D <2> ) may be activated. Control signal (D <2> ) is activated, and after a certain period of time the control signal (D <m-2>) may be activated. Control signal (D <m-2>) is activated, and after a certain period of time the control signal (D <m-1>) may be activated.

[0058] When m control signals (D<0:m-1>) are activated sequentially, the sampling transistors (N1~N4) can be turned off sequentially. That is, the turn-off timing of the sampling transistors (N1~N4) can be controlled differently from each other by the m control signals (D<0:m-1>).

[0059] When sampling is performed sequentially by the sampling capacitors (C1 to C4), the sampling voltage (VS<0:m-1>) can maintain the sampling voltage level. When sampling is performed, not only the bias voltage (VBIAS) for generating the ramp signal (VRAMP) but also noise may be sampled. The noise in the sampling voltage (VS<0:m-1>) generated by sampling by the voltage local sampling unit (411<0:m-1>) can be defined as n1(t), n2(t), nm-1(t), and nm(t), respectively.

[0060] Lamp cell (410 <0> The noise sampled with ) (i.e., error term) is ET <0> It may have the value of Lamp Cell (410 <1> The noise sampled with ) is ET <1> It may have the value of Lamp Cell (410 <m-2>The noise sampled with ) is ET <m-2>It may have the value of Lamp Cell (410 <m-1>The noise sampled with ) is ET <m-1>It may have a value of .

[0061] The voltage values ​​generated by the m ramp cells (410<0:m-1>) may be denoted as h(t). The ramp signal (VRAMP), which is obtained by adding the h(t) value output by each ramp cell (410<0:m-1>) to the voltage value of the load unit 410, may have a value of y2(t).

[0062] Based on the above-described operation, the operation by which noise is reduced in the lamp signal generation unit 400 can be expressed mathematically as follows [Mathematical Equation 1].

[0063] [Mathematical formula 1]

number

[0064] The noise generated by m ramp cells (410<0:m-1>) may have a value of ET<0:m-1>. However, the noise of the ramp signal generation unit 400 is noise generated and transmitted when the reference voltage is generated in the current generation unit 100 and / or when the gain is adjusted in the current control unit 200, so it may be thermal noise, i.e., white noise. In this disclosure, the noise of the ramp signal (VRAMP) can be reduced by spreading the noise offset of each ramp cell (410<0:m-1>) and removing correlation noise. Therefore, looking at [Equation 1] above, the more sampling operations are performed, the more the average noise value can converge to "0".

[0065] Figure 7 is a configuration diagram of an image sensing device including the lamp generator shown in Figure 1.

[0066] Referring to Figure 7, the image sensing device (IS) may include a lamp generator 10, pixels (PX), an analog-to-digital converter (ADC) 600, and a timing controller 700.

[0067] The image sensing device (IS) in Figure 7 may include the ramp generator 10 described in the embodiments of Figures 1 to 6 above. The ramp generator 10 can generate and supply a ramp signal (VRAMP) necessary for the analog-to-digital conversion operation of the ADC 600 in response to a control signal (CON) from the timing controller 700.

[0068] A pixel array may include multiple pixels (PX) arranged in multiple rows and multiple columns. In one embodiment, the multiple pixels (PX) may be arranged in a two-dimensional pixel array including rows and columns. In another embodiment, the multiple unit image pixels may be arranged in a three-dimensional pixel array. The multiple pixels (PX) can convert optical signals into electrical signals on a pixel-by-pixel or pixel-group basis to output a pixel signal (PS). Pixels (PX) within a pixel group may share at least one internal circuit. The pixel array can receive drive signals from a row driver (not shown), including a row selection signal, a pixel reset signal, and a transmission signal, and the drive signals can activate the pixels (PX) in the pixel array to perform operations corresponding to the row selection signal, pixel reset signal, and transmission signal.

[0069] The ADC600 can sequentially sample and hold reference signals and video signals provided from each of the multiple column lines of a pixel array, convert them into digital signals, and output them. The ADC600 can receive a ramp signal (VRAMP) from the ramp generator 10 and a pixel signal (PS) from a pixel (PX), and generate and output ADC data (ADC_OUT) based on the ramp signal (VRAMP) and the pixel signal (PS). In one embodiment, the ADC600 can be embodied as a ramp-compare type ADC that uses the ramp signal (VRAMP) from the ramp generator 10.

[0070] According to one embodiment, the ADC600 may include a first capacitor (C10), a second capacitor (C11), a comparator 610, and a counter 620.

[0071] The first capacitor (C10) can receive the ramp signal (VRAMP) and transmit it to the comparator 610. The second capacitor (C11) can receive the pixel signal (PS) and transmit it to the comparator 610.

[0072] The comparator 610 compares the ramp signal (VRAMP) and the pixel signal (PS), and generates comparison data (CMP_OUT) according to the comparison result, which it then transmits to the counter 620. In one embodiment, if the ramp signal (VRAMP) is greater than the pixel signal (PS), the comparator 610 can generate logically high-level comparison data (CMP_OUT). Conversely, if the ramp signal (VRAMP) is less than the pixel signal (PS), the comparator 610 can generate logically low-level comparison data (CMP_OUT). In other words, the comparison data (CMP_OUT) can indicate the magnitude relationship between the ramp signal (VRAMP) and the pixel signal (PS).

[0073] According to one embodiment, the counter 620 can be activated in response to a counter enable signal (CNT_EN) applied from the timing controller 700. The counter 620 can perform counting operations until the ramp signal (VRAMP) is matched to the analog pixel signal (PS). The activated counter 620 can then perform counting in response to a logical high-level comparison data (CMP_OUT) and output the counting result to ADC data (ADC_OUT).

[0074] The timing controller 700 can control at least one of the ramp generator 10 and the ADC 600. The timing controller 700 can generate a control signal (CON) to control the operation of the ramp generator 10. The timing controller 700 can generate a counter enable signal (CNT_EN) to control the operation of the counter 620. [Explanation of Symbols]

[0075] 10 Lamp Generators 100 Current generation section 200 Current Control Unit 300 Bias voltage generation unit 400 Lamp signal generation unit 410 Lamp Cell 411 Local Sampling Section 412 Sampling Control Unit 420 Road Section 500 Control signal generation unit 610 comparator 620 counter 700 Timing Controller

Claims

1. A bias voltage generation unit that generates a bias voltage, Includes a plurality of lamp cells that generate a lamp signal based on the bias voltage, Each of the aforementioned plurality of lamp cells is A ramp generator including a local sampling unit for adjusting the sampling timing of the bias voltage.

2. The local sampling unit described above is A sampling switch is connected between the bias voltage application terminal and the first node, and its switching operation is controlled by a control signal. The lamp generator according to claim 1, further comprising a sampling capacitor connected between a power supply voltage application terminal and the first node.

3. The local sampling unit described above is When the sampling switch is turned on, the sampling voltage is controlled in accordance with the bias voltage. The lamp generator according to claim 2, wherein when the sampling switch is turned off, the sampling voltage is controlled by the sampling capacitor.

4. The lamp generator according to claim 1, further comprising a sampling control unit that generates a plurality of control signals for adjusting the sampling operation timing of local sampling units included in the plurality of lamp cells in different ways based on a sampling control signal.

5. The sampling control unit, The lamp generator according to claim 4, further comprising a plurality of inverters for controlling the delay time of the plurality of control signals.

6. Each of the aforementioned plurality of lamp cells is A transistor that selectively supplies a power supply voltage to the second node based on the output of the local sampling unit, The lamp generator according to claim 1, further comprising a switch connected between the second node and the output terminal of the lamp signal, the switching operation of which is controlled by a switch control signal.

7. The lamp generator according to claim 1, further comprising a load unit for controlling the loading of the lamp signal.

8. The aforementioned load section is The lamp generator according to claim 7, which is shared by the plurality of lamp cells.

9. The aforementioned multiple lamp cells are The lamp generator according to claim 1, wherein the lamps are activated at different timings by the local sampling unit.

10. The aforementioned multiple lamp cells are The lamp generator according to claim 1, which is sequentially activated by the local sampling unit.

11. The aforementioned multiple lamp cells are The lamp generator according to claim 1, which is selectively activated by the local sampling unit.

12. A first ramp cell includes a first local sampling unit that samples a bias voltage based on a first control signal, and generates a ramp signal based on the sampling operation of the first local sampling unit, The system includes a second local sampling unit that samples the bias voltage based on a second control signal, and a second ramp cell that generates the ramp signal based on the sampling operation of the second local sampling unit, A ramp generator in which the first control signal and the second control signal are activated at different timings.

13. The lamp generator according to claim 12, further comprising a sampling control unit that generates the first control signal and the second control signal based on a sampling control signal.

14. The lamp generator according to claim 12, wherein a second control signal is activated after a certain period of time has elapsed since the activation of the first control signal.

15. The first local sampling unit and the second local sampling unit are each: A sampling switch is connected between the bias voltage application terminal and the first node, and its switching operation is controlled by a control signal. The lamp generator according to claim 12, further comprising a sampling capacitor connected between the power supply voltage application terminal and the first node.

16. The first local sampling unit and the second local sampling unit are each: When the sampling switch is turned on, the sampling voltage is controlled in accordance with the bias voltage. The lamp generator according to claim 15, wherein when the sampling switch is turned off, the sampling voltage is controlled by the sampling capacitor.

17. Each of the first lamp cell and the second lamp cell is, A transistor that selectively supplies power voltage to the second node based on the output of the local sampling unit, The lamp generator according to claim 12, further comprising a switch connected between the second node and the output terminal of the lamp signal, the switching operation of which is controlled by a switch control signal.

18. The lamp generator according to claim 12, further comprising a load unit for controlling the loading of the lamp signal.

19. The aforementioned load section is The lamp generator according to claim 18, shared by the first lamp cell and the second lamp cell.

20. The lamp generator according to claim 12, further comprising a bias voltage generation unit that generates the bias voltage.

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