Wiring board
The wiring board design with parallel via portions addresses the issue of crack-prone stacked via conductors by distributing stress, ensuring reliable connections through parallel via conductor arrangements.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- IBIDEN CO LTD
- Filing Date
- 2024-11-11
- Publication Date
- 2026-05-21
AI Technical Summary
Conventional wiring boards with stacked via portions are prone to cracks in the via conductors, leading to connection failures.
A wiring board design featuring a plurality of conductive and insulating layers with parallel via portions connecting land sections in the stacking direction, enhancing connection reliability by distributing tensile stress and maintaining connectivity even if cracks occur.
The design effectively suppresses crack formation and maintains reliable connections under thermal stress, improving the connection reliability of the stacked via portions.
Smart Images
Figure 2026084208000001_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a wiring board having a plurality of via conductors.
Background Art
[0002] Conventionally, as this type of wiring board, one having a stacked via portion in which a plurality of via conductors and a plurality of lands are alternately laminated is known (see, for example, Patent Document 1).
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] In the above-described conventional wiring board, cracks may occur in the via conductors of the stacked via portion, causing connection failures. Therefore, the present application discloses a technology capable of improving the connection reliability of the stacked via portion.
Means for Solving the Problems
[0005] A wiring board according to an aspect of the present disclosure includes a plurality of conductive layers and a plurality of insulating layers alternately laminated, a plane portion provided in each of the plurality of conductive layers, a land portion provided in each of the plurality of conductive layers and surrounded by the plane portion, and a stacked via portion in which a plurality of via conductors connecting the land portions are arranged in the stacking direction of the wiring board. The stacked via portion includes a parallel via portion in which a plurality of the via conductors are connected in parallel between adjacent lands in the stacking direction of the wiring board.
Brief Description of the Drawings
[0006] [Figure 1] FIG. 1 is a cross-sectional view of a wiring board according to the first embodiment [Figure 2] Figure 2 is a plan view of the first stack via section. [Figure 3] Figures 3A and 3B are cross-sectional views showing the manufacturing process of a wiring board. [Figure 4] Figures 4A and 4B are cross-sectional views showing the manufacturing process of a wiring board. [Figure 5] Figures 5A and 5B are cross-sectional views showing the manufacturing process of a wiring board. [Figure 6] Figure 6 is a cross-sectional view showing the manufacturing process of a wiring board. [Figure 7] Figure 7 is a cross-sectional view of the wiring board according to the second embodiment. [Figure 8] Figures 8A to 8D are cross-sectional views of the first stack via section according to a modified example. [Modes for carrying out the invention]
[0007] [First Embodiment] This embodiment will be described with reference to Figures 1 to 6. The wiring board 10A of this embodiment includes a first build-up layer 20F and a second build-up layer 20B that are laminated on both the front and back surfaces of the core board 11.
[0008] The first build-up layer 20F and the second build-up layer 20B are constructed by alternately laminating a plurality of insulating layers 15 and a plurality of conductive layers 30, with each of the conductive layers 30 having a plain portion 31. The plurality of insulating layers 15 are, for example, insulating films for build-up substrates (thermosetting resins containing inorganic fillers), and the plurality of conductive layers 30 are mainly electroplated.
[0009] Solder resist layers 40 having multiple openings (not shown) are laminated on the outermost surfaces of the first build-up layer 20F and the second build-up layer 20B. Solder balls are fixed to some or all of the multiple openings, for example, to form multiple solder bumps (not shown). On the surface of the first build-up layer 20F, a mounting area (not shown) for mounting electronic components is formed by multiple solder bumps arranged in a grid.
[0010] In this embodiment, the first build-up layer 20F is provided with a first stack via section 51, and the second build-up layer 20B is provided with a second stack via section 52. The first stack via section 51 and the second stack via section 52 are connected via a through-hole conductor 14 that penetrates the core substrate 11.
[0011] The second stacked via section 52 comprises a plurality of alternately stacked land sections 32 and a plurality of via conductors 33. The plurality of land sections 32 are formed in each of the plurality of conductive layers 30 of the second build-up layer 20B and are arranged within openings 31B formed in the plain section 31 of each conductive layer 30. Furthermore, the plurality of land sections 32 are arranged such that, for example, they form a circle when viewed from the stacking direction and their central axes overlap. The via conductors 33 are formed such that their central axes overlap with the center of each land section 32.
[0012] The first stacked via section 51 comprises a plurality of alternately stacked land sections 34 and a plurality of via conductors 33. The plurality of land sections 34 are formed on each of the plurality of conductive layers 30 of the first build-up layer 20F and are arranged within openings 31F formed in the plain section 31 of each conductive layer 30. As shown in Figure 2, the plurality of land sections 34 have a shape, for example, of two circular parts overlapping each other. Furthermore, the plurality of land sections 34 are formed at positions that overlap each other in the stacking direction. In the first stacked via section 51, all the spaces between adjacent land sections 34 in the stacking direction are parallel via sections 35, which are connected in parallel by a plurality (for example, two) of via conductors 33. The plurality of parallel via sections 35 have the same number of via conductors 33 in each parallel via section 35 and are arranged at positions that overlap each other when viewed from the stacking direction. Furthermore, the planar shape of the land 34 connected to the parallel via section 35 can be described as arranging the concentric circles of multiple via conductors 33 so that some of them overlap.
[0013] Figure 1 shows wiring extending from the innermost land portion 34 of the first stack via portion 51 towards the through-hole conductor 14, but this land portion 34 is surrounded by a plane portion 31, which is not shown.
[0014] The plurality of openings 31F and 31B in the plurality of plane portions 31 correspond to the shapes of the land portions 32 and 34. Specifically, for example, the opening 31F on the side of the first build-up layer 20F has a shape in which a part of two circles overlap each other when viewed from the stacking direction, and the opening 31B on the side of the second build-up layer 20B is circular. And in both cases, they are formed so that the centers of the land portions 32 and 24 coincide with the centers of the openings 31F and 31B. Further, the longest part of the plurality of openings 31F and 31B has a size, for example, 2 to 3 times the size of the longest part of the corresponding land portions 32 and 34, and the distance between the inner surface of the openings 31F and 31B and the outer surface of the corresponding land portions 32 and 34 is, for example, 300 to 700 μm.
[0015] The wiring board 10A of the present disclosure is manufactured as follows. (1) A copper-clad laminate in which metal foils are laminated on both sides of an insulating layer is prepared. Then, from the copper-clad laminate, by a known method, as shown in FIG. 3A, a core substrate 11 is formed in which the conductive layers 13 on the front and back of the insulating layer 12 are connected by through-hole conductors 14.
[0016] (2) Next, an insulating film for a build-up substrate as the insulating layer 15 is laminated and heat-pressed. Further, a laser is irradiated to form a plurality of via holes 33H, and a desmear treatment is performed (see FIG. 3B).
[0017] (3) After electroless plating treatment, a plating resist is formed in a predetermined pattern, and further electroplating treatment is performed. Then, the plating resist is peeled off, and the electroless plating exposed from the plating resist is removed. As a result, as shown in FIG. 4A, conductive layers 30 each having land portions 32 and 34 included in the plane portion 31 are formed.
[0018] (4) By the same process as in (2) above, an insulating layer 15 having a plurality of via holes 33H is formed on the land portions 32 and 34, and a desmear treatment is performed (see FIG. 4B).
[0019] (5) Next, electroless plating is performed. After a plating resist 80 with a predetermined pattern is formed on the electroless plating film, electrolytic plating is performed. Then, as shown in FIG. 5A, electrolytic plating fills the plurality of via holes 33H to form a plurality of via conductors 33, and an electrolytic plating film 30D is formed on the portion exposed from the plating resist 80.
[0020] (6) Next, the plating resist 80 is peeled off and the electroless plating film below the plating resist 80 is removed. As shown in FIG. 5B, a conductive layer 30 including a plane portion 31, land portions 32, 34 is formed by the remaining electroless plating film and electrolytic plating film 30D. Thereby, the land portions 32 are connected by the via conductors 33, and the land portions 34 are connected by the parallel via portions 35.
[0021] (7) The steps (4) to (6) are repeatedly performed, and as shown in FIG. 6, the outermost conductive layer 30 is laminated. Thereby, a first build-up layer 20F and a second build-up layer 20B are formed on both surfaces of the core substrate 11, and a first stack via portion 51 and a second stack via portion 52 are obtained.
[0022] (8) A solder resist layer 40 having a plurality of openings is laminated (see FIG. 1).
[0023] (9) Next, a plurality of solder bumps (not shown) are formed. Thus, the wiring board 10A is completed.
[0024] Next, the effects of the wiring board 10A will be explained. When the temperature of a wiring board rises above room temperature, for example, the resin constituting the insulating layer expands, generating tensile stress in the via conductors penetrating the insulating layer in the direction of stacking, which can cause cracks. In contrast, in the first stack via section 51 of the wiring board 10A of this embodiment, the land sections 34 are connected in parallel by multiple via conductors 33, so it can withstand greater tensile stress than before, and the occurrence of cracks is suppressed. Furthermore, in this embodiment, even if a crack occurs in one of the multiple via conductors 33, the remaining via conductors 33 maintain the connection between the land sections 34. As a result, the connection reliability of the first stack via section 51 is improved compared to conventional wiring boards.
[0025] In particular, the insulating layer 15 sandwiched between the two land portions 34 closest to the core substrate 11 in the first stack via portion 51 is less permeable to heat dissipation compared to the insulating layer 15 further out, making the resin of the insulating layer 15 more prone to expansion. In this embodiment, the land portions 34 closest to the core substrate 11 in the first stack via portion 51 are connected by a parallel via portion 35, which allows it to withstand greater tensile stress than conventional designs and suppresses the occurrence of cracks.
[0026] Furthermore, in the wiring board 10A of this embodiment, in order to suppress the generation of stray capacitance between the opening 31F of the plane portion 31 and the land portion 34 included in the same conductive layer 30, each land portion 34 of the first stack via portion 51 and the plane portion 31 of each conductive layer 30 are relatively far apart. However, as a result, the amount of resin in the insulating layer 15 sandwiched between the plane portion 31 and the land portion 34 increases, making it more susceptible to the effects of thermal expansion, thus making it easier to enjoy the above effect. Moreover, in this embodiment, since all of the first stack via portion 51 are parallel via portions 35, the occurrence of cracks is suppressed in all layers. In addition, in the first stack via portion 51 of this embodiment, the number of via conductors 33 in all parallel via portions 35 is the same, and they are arranged so as to overlap each other when viewed from the stacking direction, so that the outermost land portion 34 and the innermost land portion 34 can be connected by the shortest distance.
[0027] Furthermore, the first build-up layer 20F, on which electronic components are mounted, is more susceptible to thermal influence from the electronic components than the second build-up layer 20B, and the resin of the insulating layer 15 is more prone to thermal expansion. In this embodiment, the first build-up layer 20F is provided with a first stack via section 51 having parallel via sections 35, making it easier to enjoy the above effects.
[0028] Furthermore, in the first stack via section 51, the multiple land sections 34 are arranged so that the concentric circles of the multiple via conductors 33 arranged in parallel overlap, allowing multiple via conductors 33 to be connected in parallel in a small area.
[0029] [Second Embodiment] Figure 7 shows a wiring board 10B according to the second embodiment. The wiring board 10B of this embodiment differs from the first embodiment only in the second stack via section 52B. In the second stack via section 52B, the two land sections 34 closest to the core substrate 11 have the same shape as the land sections 34 of the first stack via section 51, and a parallel via section 35 is provided between these land sections 34. The centers of these two land sections 34 and the centers of the outermost land section 32 are arranged to overlap each other.
[0030] In Figure 7, only a portion of the second stack via section 52B is a parallel via section 35, but it is also possible for the entire section to be a parallel via section 35. Furthermore, in the example in Figure 7, the first stack via section 51 of the first build-up layer 20F has more parallel via sections 35 than the second stack via section 52B of the second build-up layer 20B, but this is not limited to this case; the number of parallel via sections 35 may be the same, or the second stack via section 52B may have more.
[0031] [Other embodiments] In the above embodiment, the first stacked via section 51 and the second stacked via sections 52, 52B are shown as examples where three via conductors 33 are stacked, but it is sufficient for two or more via conductors 33 to be stacked. Furthermore, the number of via conductors 33 included in the parallel via section 35 is not limited to two, but may be three or more. Moreover, the number of via conductors 33 may differ among the multiple parallel via sections 35 included in the first stacked via section 51.
[0032] The number of first stack via sections 51 and second stack via sections 52, 52B included in the wiring boards 10A and 10B is not limited to one, but may be two or more. Furthermore, if there are multiple first stack via sections 51, all of the first stack via sections 51 may be provided on a common layer, or only some of them may be provided on a common layer. The same applies to the second stack via sections 52, 52B. Moreover, the first stack via sections 51 and second stack via sections 52, 52B may be provided on only one of the first build-up layer 20F and the second build-up layer 20B.
[0033] The positions in which the first stack via section 51 and the second stack via sections 52, 52B are arranged may be on either the inner or outer layer side if they are the first build-up layer 20F or the second build-up layer 20B. Furthermore, the first stack via section 51 and the second stack via sections 52, 52B may be connected to the conductive layer 13 included in the core substrate 11.
[0034] Furthermore, in the above embodiment, as shown in Figure 1, the first stack via section 51 and the second stack via section 52 are connected via the through-hole conductor 14, but they do not necessarily have to be connected.
[0035] The stack via section including the first stack via section 51 and the second stack via sections 52, 52B in the above embodiment is not limited to a configuration where all of them are parallel via sections 35 or where only the side closest to the core substrate 11 is a parallel via section 35. For example, as shown in Figures 8A to 8D, the parallel via sections 35 may be provided at any position.
[0036] While this specification and drawings disclose specific examples of the technology included in the claims, the technology described in the claims is not limited to these specific examples, but also includes various modifications and changes to these examples, as well as parts of the examples taken individually. [Explanation of Symbols]
[0037] 10A, 10B Wiring Board 11 Core board 15. Insulating layer 20F First Build-Up Layer 20B Second build-up layer 30 Conductive layer 31 Plain section 31B,31F opening 32,34 Land section 33 via conductors 35 Parallel via section 51. First Stack Via Section 52, 52B Second Stack Via Section
Claims
1. Multiple conductive layers and multiple insulating layers are stacked alternately, Each of the plurality of conductive layers has a plain portion provided therein, Each of the plurality of conductive layers is provided with a land portion surrounded by the plain portion, A wiring board comprising a stack via section in which multiple via conductors connecting the aforementioned land sections are arranged in the stacking direction of the wiring board, The stacked via section includes a parallel via section in which adjacent land sections in the stacking direction of the wiring board are connected in parallel by a plurality of via conductors.
2. A wiring board according to claim 1, All of the land portions of the stack via portion are connected to each other by the parallel via portion.
3. A wiring board according to claim 2, All of the parallel via sections have the same number of via conductors and are arranged to overlap each other when viewed from the stacking direction.
4. A wiring board according to claim 1, The plurality of conductive layers and the plurality of insulating layers are formed on a core substrate. The two land portions closest to the core substrate within the stacked via portion are connected by the parallel via portion.
5. A wiring board according to claim 4, A build-up layer including the plurality of conductive layers and the plurality of insulating layers is formed on both the front and back surfaces of the core substrate. Of the two build-up layers on the front and back sides, the stack via portion of the first build-up layer on the side where the electronic components are mounted has more parallel via portions than the stack via portion of the second build-up layer on the opposite side.
6. A wiring board according to any one of claims 1 to 5, The planar shape of the land portion connected to the parallel via portion is such that the concentric circles of the multiple via conductors overlap.
7. A wiring board according to any one of claims 1 to 5, The shortest distance between the land portion and the plane portion is 300 to 700 μm.
8. A wiring board according to any one of claims 1 to 5, The plain portion has an opening that encloses the land portion. The longest part of the opening in the plain section is two to three times the size of the longest part of the land section.