Power conversion device and control method

Abstract

To provide a power conversion device and control method that can be operated stably. [Solution] The power converter provides a dead time between turning off one of the two sets of switching elements and short-circuiting the clamp circuit, and between leaving the clamp circuit unshort-circuited and turning on one set of switching elements. Outside of the dead time, the control unit short-circuits the clamp circuit when turning off both sets of switching elements, and in a first predetermined period including a zero-crossing where the polarity of the AC voltage output from the output terminal changes, it disconnects the clamp circuit for at least a second predetermined period within the dead time included in the first predetermined period. During the dead time included in periods other than the first predetermined period, the control unit controls the clamp circuit so that it is in a rectified state where current flows due to the reverse voltage of the output voltage of the inverter circuit.

Description

Technical Field

[0001] The present disclosure relates to a power conversion device and a control method.

Background Art

[0002] A power conversion device that switches DC power to convert it into AC power is known. Patent Document 1 below discloses an inverter device as a power conversion device. This inverter device includes a full-bridge inverter circuit and a clamp circuit composed of two switching elements. In the inverter device described in Patent Document 1, when one set of switching elements included in the inverter circuit is turned on, any one of the two switching elements of the clamp circuit is turned on. In this case, the other switching element of the two switching elements of the clamp circuit is turned off.

[0003] This inverter device also provides a dead time between turning off one set of switching elements included in the inverter circuit and short-circuiting the clamp circuit, and between turning the clamp circuit from short-circuited to non-short-circuited and turning on one set of switching elements. During the dead time, all the switching elements constituting the inverter circuit are off, and the clamp circuit is in a non-short-circuited state.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the inverter device described in Patent Document 1, even near the zero-crossing point where the polarity of the AC voltage switches, control is performed to turn on one of the two switching elements of the clamp circuit during the dead time. The control device that controls the switching elements determines the control signal based on the detected output voltage. Near the zero-crossing point where the output voltage is small, voltage detection errors or voltage polarity determination errors may occur due to the influence of noise and other factors. Therefore, depending on the control device, the control signal for the switching element may not be output correctly near the zero-crossing point. In this case, the stability of the inverter device during operation may decrease.

[0006] Therefore, the purpose of this disclosure is to provide a power conversion device and control method that can be operated stably. [Means for solving the problem]

[0007] A power conversion device according to one aspect of the present disclosure includes an inverter circuit that converts DC power supplied from a DC power source to AC power, which includes two sets of switching elements; a clamp circuit connected between the output terminals of the inverter circuit and which includes at least one switching element; and a control unit that controls the on and off of the switching elements included in the inverter circuit and the clamp circuit. A dead time is provided between the time when one of the two sets of switching elements is turned off and the clamp circuit is short-circuited, and between the time the clamp circuit is not short-circuited and one set of switching elements is turned on. Outside of the dead time, when both sets of switching elements are turned off, the control unit short-circuits the clamp circuit, and in a first predetermined period including a zero-crossing in which the polarity of the AC voltage output from the output terminal changes, the control unit shuts off the clamp circuit for at least a second predetermined period within the dead time included in the first predetermined period. During the dead time included in periods other than the first predetermined period, the control unit controls the clamp circuit so that it is in a rectified state in which current flows due to the reverse voltage of the output voltage of the inverter circuit. [Effects of the Invention]

[0008] This disclosure provides a power conversion device and control method that can be operated stably. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a circuit diagram showing the configuration of a power conversion device according to an embodiment of this disclosure. [Figure 2] Figure 2 is a circuit diagram showing the operation of the power converter shown in Figure 1, specifically when the output voltage is positive. [Figure 3] Figure 3 is a circuit diagram showing the operation of the power converter shown in Figure 1 during periods other than near the zero-crossing, and the operation during the dead time following Figure 2. [Figure 4] Figure 4 is a circuit diagram showing the operation of the power converter shown in Figure 1 during the commutation period. [Figure 5] Figure 5 is a circuit diagram showing the operation of the power converter shown in Figure 1, specifically when the output voltage is negative. [Figure 6] Figure 6 is a circuit diagram showing the operation of the power converter shown in Figure 1, specifically the operation during the dead time following Figure 5. [Figure 7] Figure 7 is a circuit diagram showing the operation of the power converter shown in Figure 1, specifically the operation during the dead time included in the vicinity of the zero-crossing where the output voltage is positive. [Figure 8] Figure 8 is a circuit diagram showing the operation of the power converter shown in Figure 1, specifically the operation during the dead time included in the vicinity of the zero-crossing where the output voltage is negative. [Figure 9] Figure 9 is a circuit diagram illustrating the occurrence of a short circuit in the DC bus. [Figure 10] Figure 10 is a graph showing a method for generating control signals during periods other than those near zero-crossing. [Figure 11] Figure 11 is a graph showing a different method from Figure 10 for generating control signals during periods other than near the zero crossing. [Figure 12]FIG. 12 is a graph showing a method of generating a control signal over the entire period including the vicinity of the zero crossing. [Figure 13] FIG. 13 is a graph showing the graph shown in FIG. 12 with an enlarged time axis. [Figure 14] FIG. 14 is a graph showing the period A shown in FIG. 13 with an enlarged time axis. [Figure 15] FIG. 15 is a graph showing the period B shown in FIG. 13 with an enlarged time axis. [Figure 16] FIG. 16 is a graph showing the period C shown in FIG. 13 with an enlarged time axis. [Figure 17] FIG. 17 is a graph showing the period D shown in FIG. 13 with an enlarged time axis. [Figure 18] FIG. 18 is a graph showing a different method from FIG. 12 for generating a control signal over the entire period including the vicinity of the zero crossing. [Figure 19] FIG. 19 is a circuit diagram showing the configuration of a power conversion device according to a modification example. [Figure 20] FIG. 20 is a circuit diagram redrawn by corresponding the circuit of FIG. 19 to the circuit of FIG. 1. [Figure 21] FIG. 21 is a circuit diagram showing the operation of the power conversion device shown in FIG. 20 when the output voltage is positive. [Figure 22] FIG. 22 is a circuit diagram showing the operation of the power conversion device shown in FIG. 20 during the dead time following FIG. 21. [Figure 23] FIG. 23 is a circuit diagram showing the operation of the power conversion device shown in FIG. 20 during the commutation period. [Figure 24] FIG. 24 is a circuit diagram showing the operation of the power conversion device shown in FIG. 20 during a part of the dead time included in the vicinity of the zero crossing where the output voltage is positive. [Figure 25] FIG. 25 is a circuit diagram showing the operation of the power conversion device shown in FIG. 20 during a part of the dead time included in the vicinity of the zero crossing where the output voltage is negative. [Modes for carrying out the invention]

[0010] [Description of Embodiments in this Disclosure] The embodiments of this disclosure are listed and described below. At least some of the embodiments described below may be combined in any way.

[0011] (1) The power converter according to the first aspect of the present disclosure includes an inverter circuit that converts DC power supplied from a DC power source to AC power, which includes two sets of switching elements; a clamp circuit connected between the output terminals of the inverter circuit and which includes at least one switching element; and a control unit that controls the on and off of the switching elements included in the inverter circuit and the clamp circuit. A dead time is provided between the time when one of the two sets of switching elements is turned off and the clamp circuit is short-circuited, and between the time the clamp circuit is not short-circuited and one set of switching elements is turned on. Outside of the dead time, when both sets of switching elements are turned off, the control unit short-circuits the clamp circuit, and in a first predetermined period including a zero-crossing in which the polarity of the AC voltage output from the output terminal changes, the control unit shuts off the clamp circuit for at least a second predetermined period in the dead time included in the first predetermined period. During the dead time included in periods other than the first predetermined period, the control unit controls the clamp circuit so that it is in a rectified state in which current flows due to the reverse voltage of the output voltage of the inverter circuit. This makes it possible to operate the power converter stably.

[0012] (2) In (1) above, the clamp circuit may include two switching elements, and the clamp circuit may be short-circuited when both switching elements are turned on, and interrupted when both switching elements are turned off. This makes it possible to operate the power converter more stably.

[0013] (3) In (1) or (2) above, the control unit may perform PWM control using a carrier signal in which the same voltage waveform is periodically repeated in the positive voltage region, a first command signal having the same frequency as the frequency of AC power and changing sinusoidally alternately in the positive and negative voltage regions, a second command signal obtained by inverting the first command signal, a third command signal generated by adding a predetermined value corresponding to the dead time to the first command signal in the positive voltage region, and a fourth command signal generated by adding a predetermined value to the second command signal in the positive voltage region, and during the period excluding the dead time, the control unit may, during the period in which the value of the first command signal is greater than the value of the carrier signal, The inverter circuit may be configured to turn on the first set of switching elements of the two sets of switching elements, turn off the first set of switching elements during the period when the value of the first command signal is less than or equal to the value of the carrier signal, and short-circuit the clamp circuit during the period when the value of the third command signal is a positive value less than or equal to the value of the carrier signal, turn on the second set of switching elements of the two sets of switching elements of the inverter circuit during the period when the value of the second command signal is greater than the value of the carrier signal, turn off the second set of switching elements during the period when the value of the second command signal is less than or equal to the value of the carrier signal, and short-circuit the clamp circuit during the period when the value of the fourth command signal is a positive value less than or equal to the value of the carrier signal. This allows DC power to be converted to AC power.

[0014] (4) In (1) or (2) above, a first command signal is set to have the same frequency as the frequency of the AC power and whose voltage alternately changes sinusoidally in the positive and negative regions, and a second command signal is set to be During the specified period, the control unit may turn on the first set of switching elements among the two sets of switching elements included in the inverter circuit when the value of the third command signal is less than the value of the carrier signal, turn off the first set of switching elements when the value of the third command signal is greater than or equal to the value of the carrier signal, and short-circuit the clamp circuit when the value of the first command signal is positive and the value of the fifth command signal is greater than or equal to the value of the carrier signal, turn on the second set of switching elements among the two sets of switching elements included in the inverter circuit when the value of the fourth command signal is less than the value of the carrier signal, turn off the second set of switching elements when the value of the fourth command signal is greater than or equal to the value of the carrier signal, and short-circuit the clamp circuit when the value of the first command signal is negative and the value of the sixth command signal is greater than or equal to the value of the carrier signal. This allows DC power to be converted to AC power.

[0015] (5) In (1) above, the clamp circuit may include a first switching element and a second switching element, and the control unit may perform PWM control using a carrier wave signal in which the same voltage waveform periodically repeats in the positive voltage region, the first command signal, the second command signal, a third command signal generated by adding a predetermined value corresponding to the dead time to the first command signal, and a fourth command signal generated by adding a predetermined value to the second command signal, and during the period when the value of the first command signal is greater than the value of the carrier wave signal, the control unit may switch the first set of switching elements of the two sets of switching elements included in the inverter circuit The first set of switching elements may be turned on, and during the period when the value of the first command signal is less than or equal to the value of the carrier signal, the first set of switching elements may be turned off. During the period when the value of the second command signal is greater than the value of the carrier signal, the second set of switching elements of the two sets of switching elements included in the inverter circuit may be turned on, and during the period when the value of the second command signal is less than or equal to the value of the carrier signal, the second set of switching elements may be turned off. During the period when the value of the third command signal is less than the value of the carrier signal, the first switching element may be turned on, and during the period when the value of the fourth command signal is less than the value of the carrier signal, the first switching element may be turned off.

[0016] (6) In (1) above, the clamp circuit may include a first switching element and a second switching element, and the control unit may use a first command signal which has the same frequency as the frequency of the AC power and whose voltage alternately changes sinusoidally in the positive and negative regions, and a second command signal which is generated by inverting the first command signal, and a carrier wave signal in which the same voltage waveform repeats periodically in the positive voltage region, a third command signal generated by subtracting the first command signal from the maximum value of the carrier wave signal, a fourth command signal generated by subtracting the second command signal from the maximum value of the carrier wave signal, a fifth command signal generated by subtracting a predetermined value corresponding to the dead time from the third command signal, and a sixth command signal generated by subtracting a predetermined value from the fourth command signal to perform PWM control, and the control unit may use a carrier wave signal in which the same voltage waveform repeats periodically in the positive voltage region, a third command signal generated by subtracting the first command signal from the maximum value of the carrier wave signal, a fourth command signal generated by subtracting the second command signal from the maximum value of the carrier wave signal, a fifth command signal generated by subtracting a predetermined value from the third command signal, and a sixth command signal generated by subtracting a predetermined value from the fourth command signal, and the control unit may use a carrier wave signal in which the value of the third command signal is smaller than the value of the carrier wave The first set of switching elements in the pair may be turned on, and during the period when the value of the third command signal is greater than or equal to the value of the carrier signal, the first set of switching elements may be turned off. During the period when the value of the fourth command signal is less than the value of the carrier signal, the second set of switching elements in the inverter circuit may be turned on, and during the period when the value of the fourth command signal is greater than or equal to the value of the carrier signal, the second set of switching elements may be turned off. During the period when the value of the fifth command signal is greater than the value of the carrier signal, the first switching element may be turned on, and during the period when the value of the fifth command signal is less than or equal to the value of the carrier signal, the first switching element may be turned off. During the period when the value of the sixth command signal is greater than the value of the carrier signal, the second switching element may be turned on, and during the period when the value of the sixth command signal is less than or equal to the value of the carrier signal, the second switching element may be turned off. This enables control during dead time and prevents short circuits of the DC bus during dead time near zero crossing.

[0017] (7) A control method relating to a second aspect of the present disclosure is a control method for a power converter including an inverter circuit that converts DC power supplied from a DC power source into AC power, which includes two sets of switching elements; a clamp circuit that includes at least one switching element and is connected between the output terminals of the inverter circuit; and a control unit that controls the on and off of the switching elements included in the inverter circuit and the clamp circuit, the method comprising: providing a dead time between the time when one of the two sets of switching elements is turned off and the clamp circuit is short-circuited, and between the time when the clamp circuit is not short-circuited and one set of switching elements is turned on, and the control unit short-circuits the clamp circuit when it turns off all two sets of switching elements outside of the dead time; the control unit interrupts the clamp circuit for at least a second predetermined period in the dead time included in a first predetermined period which includes a zero-crossing in which the polarity of the AC voltage output from the output terminal changes; and the control unit controls the clamp circuit during the dead time included in a period other than the first predetermined period such that the clamp circuit is in a rectified state in which current flows due to the reverse voltage of the output voltage of the inverter circuit. This makes it possible to operate the power conversion device stably.

[0018] [Details of the embodiments of this disclosure] In the following embodiments, identical parts are assigned the same reference numeral. Their names and functions are also identical. Therefore, detailed descriptions of them will not be repeated.

[0019] (Overall structure) Referring to Figure 1, the power converter 100 according to the embodiment of this disclosure includes an inverter circuit 102, a clamp circuit 104, and a control unit 110. The inverter circuit 102 includes switching elements Q1 to Q4 and diodes D1 to D4. Switching elements Q1 to Q4 are switched on and off by external electrical control. Four sets of parallel-connected switching elements and diodes are connected in series in pairs. Furthermore, they are connected in parallel to form a full bridge circuit. Diodes D1 and D2 are connected in series, with the anode of diode D1 connected to the cathode of diode D2. Diodes D3 and D4 are connected in series, with the anode of diode D3 connected to the cathode of diode D4.

[0020] The connection nodes of switching elements Q1 and Q3 are connected to input terminal IN1, and the connection nodes of switching elements Q2 and Q4 are connected to input terminal IN2. Capacitor C1 is connected between input terminals IN1 and IN2. Wiring 106 is connected to the connection nodes of the series-connected switching elements Q1 and Q2. Wiring 106 is connected to output terminal OUT1 via reactor L1. Wiring 108 is connected to the connection nodes of the series-connected switching elements Q3 and Q4. Wiring 108 is connected to output terminal OUT2 via reactor L2.

[0021] DC power (input voltage V1) is input between input terminals IN1 and IN2. Switching elements Q1 to Q4 included in the inverter circuit 102 are controlled by a control signal from the control unit 110 (for example, PWM (Pulse Width Modulation) control). As a result, the power converter 100 converts the DC power into AC power (output voltage V2) and outputs it from output terminals OUT1 and OUT2.

[0022] The clamp circuit 104 includes a switching element Q5 and a diode D5 connected in parallel, and a switching element Q6 and a diode D6 connected in parallel. Switching elements Q5 and Q6 are switched on and off by external electrical control. The anode of diode D5 is connected to the anode of diode D6. The clamp circuit 104 is connected between wiring 106 and wiring 108. That is, the connection node between switching element Q5 and the cathode of diode D5 is connected to wiring 106, and the connection node between switching element Q6 and the cathode of diode D6 is connected to wiring 108.

[0023] Switching elements Q5 and Q6 included in the inverter circuit 102 are controlled by a control signal from the control unit 110, allowing them to short-circuit or disconnect (open) wiring 106 and wiring 108. As a result, the clamp circuit 104 functions as a commutation path when the inverter circuit 102 converts DC power to AC power, as will be described later. Furthermore, the clamp circuit 104 can prevent malfunctions that may occur in the inverter circuit 102 during power conversion.

[0024] The control unit 110 includes a CPU (Central Processing Unit) 112, a memory 114, and an IF unit (interface unit) 116. The CPU 112 executes a predetermined program to realize the power conversion function of the power converter 100. The memory 114 stores the program executed by the CPU 112. The IF unit 116, under the control of the CPU 112, outputs signals (gate voltages of each switching element) to control the on and off states of each switching element included in the inverter circuit 102 and the clamp circuit 104. The IF unit 116 also receives voltages and currents between output terminals OUT1 and OUT2 (detection signals from sensors (not shown), etc.). The IF unit 116 converts the analog detection signals into digital data using AD conversion and stores them in the memory 114. The stored detection values ​​are used by the CPU 112 to adjust the timing of the on / off control of each switching element.

[0025] Switching elements Q1 to Q6 are, for example, FETs (Field Effect Transistors) or IGBTs (Insulated Gate Bipolar Transistors). When FETs are used for switching elements Q1 to Q6, the parasitic diodes (body diodes) of the FETs can be used for diodes D1 to D6. When IGBTs are used for switching elements Q1 to Q6, external diodes D1 to D6 are provided.

[0026] (operation) The power conversion operation of the power converter 100 will be explained with reference to Figures 2 to 8. A DC input voltage V1 is applied between input terminals IN1 and IN2, and the control unit 110 controls switching elements Q1 to Q4 by PWM control. The control unit 110 is not shown in the following figures.

[0027] 1. Periods other than those near zero crossings 1.1 Period when output voltage V2 > 0 (Mode 1) Figure 2 shows the state of switching elements Q1 through Q6 during a period when the output voltage V2 > 0 and not near zero crossing. This state is called the first mode. Note that the first mode represents the direction of current, and even if switching element Q6 is off in Figure 2, the direction of the current does not change, so the state in Figure 2 where switching element Q6 is off is also included in the first mode. Near zero crossing means a predetermined period including zero crossing (i.e., output voltage V2 = 0), which is the timing when the polarity of the output voltage V2 switches. Switching elements Q1, Q4, and Q6 are on, and switching elements Q2, Q3, and Q5 are off. As a result, current flows as shown by the dashed arrows, and the output voltage V2, which is a positive voltage (see the upward arrow on the far right), is output from output terminals OUT1 and OUT2.

[0028] (Dead time) Figure 3 shows the state of switching elements Q1 to Q6 following Figure 2. Switching elements Q1 and Q4 are turned off, but the other switching elements remain in the same state as in Figure 2. As a result, current flows as indicated by the dashed arrows. That is, the clamp circuit 104 is in a rectified state in which current flows due to the reverse voltage of the output voltage (output voltage V2) of the inverter circuit 102. The dead time refers to the period from when one pair of switching elements in the inverter circuit is turned off until the clamp circuit is short-circuited, and the period from when the clamp circuit is not short-circuited until one pair of switching elements in the inverter circuit is turned on.

[0029] (Translocation) Figure 4 shows the state of switching elements Q1 through Q6, following Figure 3. This state is called commutation. Switching element Q5 is turned on, but the other switching elements remain in the same state as in Figure 3. As a result, current flows as indicated by the dashed arrows.

[0030] When the output voltage V2 > 0, and except near the zero-crossing period, the system repeats in the following order: first mode (Figure 2), dead time (Figure 3), commutation (Figure 4), dead time (Figure 3), and first mode (Figure 2). By keeping the repetition period constant and controlling the duration of the first mode, a sinusoidal output voltage V2 can be generated. By providing the dead time described above, a short circuit in the DC bus (i.e., a short circuit between input terminals IN1 and IN2) that may occur when controlling the system to transition immediately from the first mode to commutation, or from commutation to the first mode, can be avoided.

[0031] 1.2 Period when output voltage V2 < 0 (Second mode) Figure 5 shows the state of switching elements Q1 through Q6 during periods other than near zero crossing, when the output voltage V2 < 0. This state is called the second mode. Switching elements Q2, Q3, and Q5 are on, while switching elements Q1, Q4, and Q6 are off. As a result, current flows as indicated by the dashed arrows, and a negative voltage output voltage V2 is output from output terminals OUT1 and OUT2. The fact that the output voltage V2 is negative is indicated by the downward arrow on the far right. Note that the second mode represents the direction of current, and even if switching element Q5 is off in Figure 5, the direction of the current does not change, so the state in Figure 5 where switching element Q5 is off is also included in the second mode.

[0032] (Dead time) Figure 6 shows the state of switching elements Q1 through Q6, following Figure 5. Switching elements Q2 and Q3 are turned off, but the other switching elements remain in the same state as in Figure 5. As a result, current flows as indicated by the dashed arrows.

[0033] (Translocation) Following Figure 6, switching elements Q1 through Q6 are controlled to the state shown in Figure 4. Since the output voltage V2 < 0, the current direction is opposite to the dashed arrow in Figure 4.

[0034] When the output voltage V2 < 0, and except near the zero-crossing period, the system repeats in the following order: second mode (Figure 5), dead time (Figure 6), commutation (as described above, with the current direction reversed in Figure 4), dead time (Figure 6), and second mode (Figure 5). By keeping the repetition period constant and controlling the duration of the second mode, a sinusoidal output voltage V2 can be generated. By providing the dead time (Figure 6) described above, it is possible to avoid short circuits in the DC bus that may occur when controlling the system to transition immediately from the second mode to commutation, or when controlling the system to transition immediately from commutation to the second mode.

[0035] 2. Zero-crossing neighborhood 2.1 Period when output voltage V2 > 0 Even near zero crossing, during the period when the output voltage V2 > 0, the first mode described above (switching element Q6 is off in Figure 2), dead time (Figure 3), and commutation (Figure 4) are performed.

[0036] (Off-time) Figure 7 shows the state of switching elements Q1 through Q6 between the first mode (switching element Q6 is off in Figure 2) and the dead time (Figure 3). Switching elements Q5 and Q6 are all off, and the clamp circuit 104 is disconnected. The period during which the clamp circuit 104 is disconnected, other than the first and second modes, is called the off time. As mentioned above, the state in Figure 2 where switching element Q6 is off, i.e., the state where both switching elements Q5 and Q6 are off, is included in the first mode, so this state is not included in the off time. The same applies to the second mode. In Figure 7, switching elements Q1 through Q6 are all off, and current flows as indicated by the dashed arrows.

[0037] During the period when the output voltage V2 > 0 near the zero-crossing, the control cycles through the following stages: first mode (switching element Q6 is off in Figure 2), off-time (Figure 7), dead time (Figure 3), commutation (Figure 4), dead time (Figure 3), off-time (Figure 7), and back to the first mode (switching element Q6 is off in Figure 2). The off-time (cutting off the clamp circuit 104) occurs only during the short period near the zero-crossing and not during periods other than near the zero-crossing. Therefore, there is no interference with the control of the power converter 100.

[0038] 2.2 Period when output voltage V2 < 0 (Off-time) Figure 8 shows the state of switching elements Q1 to Q6 during the off-time, which is provided between the second mode (switching element Q5 is off in Figure 5) and the dead time (Figure 6). During the off-time, switching elements Q5 and Q6 are all off, and the clamp circuit 104 is disconnected. Since the output voltage V2 < 0, the current indicated by the dashed arrow is different from that in Figure 7.

[0039] During the period when the output voltage V2 < 0 near the zero crossing, the control cycles through the following modes in order: second mode (switching element Q5 is off in Figure 5), off time (Figure 8), dead time (Figure 6), commutation (current direction reversed in Figure 4), dead time (Figure 6), off time (Figure 8), and second mode (switching element Q5 is off in Figure 5).

[0040] Near the zero-crossing point, the detection signal is susceptible to noise due to the low voltage. Therefore, the control unit 110 is less likely to generate a correct PWM control signal that takes the detection signal into account. If the control unit 110 does not output a correct PWM control signal, for example, as shown in Figure 9, switching element Q5 may turn on before switching elements Q1 and Q4 turn off. When a short circuit (current indicated by the dashed arrow) occurs in the DC bus in this way, the operation of the power supply providing the input voltage V1 can become unstable. By providing an off-time during the dead time between the transition from the first mode to commutation and between the transition from commutation to the first mode, a DC bus short circuit that could occur can be avoided. Therefore, the power converter 100 can be operated stably.

[0041] As described above, the clamp circuit 104 includes two switching elements Q5 and Q6. The clamp circuit 104 is short-circuited when both switching elements Q5 and Q6 are turned on, and disconnected when both switching elements Q5 and Q6 are turned off. This allows the power converter 100 to operate more stably.

[0042] (Control signal waveform) The control signals required to achieve the above-described operation will now be explained. Figure 10 shows an example of a PWM control signal for achieving operation during periods other than near the zero-crossing.

[0043] In Figure 10, the horizontal axis represents time. The top row shows the AC voltage control command signal S0, which corresponds to one period of the output voltage V2, the output of the power converter 100. The AC voltage control command signal S0 is a sine wave that takes positive and negative values ​​centered around 0. The second row from the top shows the PWM-controlled triangular wave carrier signal SH, the first command signal S1 (see solid line), and the second command signal S2 (see dashed line). The carrier signal SH is normalized, with a minimum value of 0 and a maximum value of 1. The first command signal S1 and the second command signal S2 are sine waves generated by multiplying the AC voltage control command signal S0 by a predetermined number.

[0044] The third and fourth rows from the top show pulse signals for controlling switching elements Q1 through Q4 included in the inverter circuit 102, which are generated by the carrier signal SH, the first command signal S1, and the second command signal S2. The carrier signal SH and the first command signal S1 generate control signals for switching elements Q1 and Q4, and the carrier signal SH and the second command signal S2 generate control signals for switching elements Q2 and Q3.

[0045] Specifically, if the value of the first command signal S1 is greater than the value of the carrier signal SH, the control signals for switching elements Q1 and Q4 become high-level to turn them on. If the value of the first command signal S1 is less than or equal to the value of the carrier signal SH, the control signals for switching elements Q1 and Q4 become low-level to turn them off. In the latter half of the cycle, the value of the first command signal S1 is negative and less than the value of the carrier signal SH, so the control signals for switching elements Q1 and Q4 remain low-level.

[0046] If the value of the second command signal S2 is greater than the value of the carrier signal SH, the control signals for switching elements Q2 and Q3 become high to turn them on. If the value of the second command signal S2 is less than or equal to the value of the carrier signal SH, the control signals for switching elements Q2 and Q3 become low to turn them off. In the first half of the cycle, the value of the second command signal S2 is negative and less than the value of the carrier signal SH, so the control signals for switching elements Q2 and Q3 are kept low.

[0047] The fifth row from the top shows the waveforms for generating pulse signals to control switching elements Q5 and Q6 included in the clamp circuit 104. The third command signal S3 is obtained by adding a predetermined value d1 (d1>0) to the signal of the first half-cycle (voltage>0) of the first command signal S1. The second half-cycle (voltage<0) of the third command signal S3 is the same as that of the first command signal S1. The fourth command signal S4 is obtained by adding a predetermined value d1 to the signal of the second half-cycle (voltage>0) of the second command signal S2. The first half-cycle (voltage<0) of the fourth command signal S4 is the same as that of the second command signal S2. For reference, the fifth row from the top shows the signal of the first half-cycle of the first command signal S1 and the signal of the second half-cycle of the second command signal S2, as shown in the second row from the top. The sixth and seventh rows from the top show pulse signals for controlling switching elements Q5 and Q6, which are generated by the carrier signal SH, the third command signal S3, and the fourth command signal S4 shown in the fifth row from the top. The carrier signal SH and the third command signal S3 generate a control signal for switching element Q5, and the carrier signal SH and the fourth command signal S4 generate a control signal for switching element Q6.

[0048] Specifically, if the value of the third command signal S3 is less than or equal to the value of the carrier signal SH, the control signal for the switching element Q5 becomes high-level, turning the switching element Q5 on. If the value of the third command signal S3 is greater than the value of the carrier signal SH, the control signal for the switching element Q5 becomes low-level, turning the switching element Q5 off. In the latter half of the cycle, the value of the third command signal S3 is negative and less than the value of the carrier signal SH, so the control signal for the switching element Q5 is maintained at a high level.

[0049] If the value of the fourth command signal S4 is less than or equal to the value of the carrier signal SH, the control signal for the switching element Q6 becomes high-level, turning the switching element Q6 on. If the value of the fourth command signal S4 is greater than the value of the carrier signal SH, the control signal for the switching element Q6 becomes low-level, turning the switching element Q6 off. In the first half of the cycle, the value of the fourth command signal S4 is negative and less than the value of the carrier signal SH, so the control signal for the switching element Q6 is maintained at a high level.

[0050] During periods other than near the zero-crossing, a control signal for switching element Q6 is supplied from the switching element Q1 generated in this manner to the corresponding switching element, thereby enabling the operation of the power converter 100 during periods other than near the zero-crossing, as described above. That is, during periods when the output voltage V2 > 0, the first mode (Figure 2), zero-crossing (Figure 3), commutation (Figure 4), zero-crossing (Figure 3), and the first mode (Figure 2) are repeated. During periods when the output voltage V2 < 0, the second mode (Figure 5), zero-crossing (Figure 6), commutation (with the current direction reversed in Figure 4), zero-crossing (Figure 6), and the second mode (Figure 5) are repeated. As a result, the power converter 100 can convert DC power to AC power. The length of the off-periods for switching elements Q5 and Q6 is determined by the magnitude of a predetermined value d1, and the length of the dead time (time) is determined. Therefore, the predetermined value d1 should be set according to the required dead time length.

[0051] The PWM control signal used to achieve operation outside the vicinity of the zero crossing is not limited to the control signal shown in Figure 10. It may be generated as shown in Figure 11. The signal waveforms shown in each row of Figure 11 correspond to the signal waveforms shown in each row of Figure 10. The signal in the top row of Figure 11 is the same as the signal in the top row of Figure 10. In the second row from the top of Figure 11, the carrier signal SH is the same as in Figure 10. The third command signal S3a is a signal generated by subtracting the first command signal S1 (see Figure 10) from the maximum value of the carrier signal SH. The fourth command signal S4a is a signal generated by subtracting the second command signal S2 (see Figure 10) from the maximum value of the carrier signal SH.

[0052] The third and fourth rows from the top show pulse signals for controlling switching elements Q1 through Q4 included in the inverter circuit 102, which are generated by the carrier signal SH, the third command signal S3a, and the fourth command signal S4a. The carrier signal SH and the third command signal S3a generate control signals for switching elements Q1 and Q4, and the carrier signal SH and the fourth command signal S4a generate control signals for switching elements Q2 and Q3.

[0053] Specifically, if the value of the third command signal S3a is less than the value of the carrier signal SH, the control signals for switching elements Q1 and Q4 become high to turn them on. If the value of the third command signal S3a is greater than or equal to the value of the carrier signal SH, the control signals for switching elements Q1 and Q4 become low to turn them off. In the latter half of the cycle, the value of the third command signal S3a is greater than the value of the carrier signal SH, so the control signals for switching elements Q1 and Q4 are maintained at a low level.

[0054] If the value of the fourth command signal S4a is less than the value of the carrier signal SH, the control signals for switching elements Q2 and Q3 become high to turn them on. If the value of the fourth command signal S4a is less than or equal to the value of the carrier signal SH, the control signals for switching elements Q2 and Q3 become low to turn them off. In the first half of the cycle, the value of the fourth command signal S4a is greater than the value of the carrier signal SH, so the control signals for switching elements Q2 and Q3 are kept low.

[0055] The fifth row from the top shows the waveforms used to generate pulse signals for controlling switching elements Q5 and Q6 included in the clamp circuit 104. The fifth command signal S5 is obtained by subtracting a predetermined value d2 (d2>0) from the signal of the first half-period in the third command signal S3a. The second half-period of the fifth command signal S5 is the same as that of the third command signal S3a. The sixth command signal S6 is obtained by subtracting a predetermined value d2 from the signal of the second half-period in the fourth command signal S4a. The first half-period of the sixth command signal S6 is the same as that of the fourth command signal S4a. For reference, the fifth row from the top shows the signal of the first half-period of the third command signal S3a and the signal of the second half-period of the fourth command signal S4a. The sixth and seventh rows from the top show the pulse signals for controlling switching elements Q5 and Q6, which are generated by the carrier signal SH, the fifth command signal S5, and the sixth command signal S6 shown in the fifth row from the top. The carrier signal SH and the fifth command signal S5 generate a control signal for the switching element Q5, and the carrier signal SH and the sixth command signal S6 generate a control signal for the switching element Q6.

[0056] Specifically, if the value of the fifth command signal S5 is greater than or equal to the value of the carrier signal SH, the control signal for the switching element Q5 becomes high-level, turning the switching element Q5 on. If the value of the fifth command signal S5 is less than the value of the carrier signal SH, the control signal for the switching element Q5 becomes low-level, turning the switching element Q5 off. In the latter half of the cycle, the value of the fifth command signal S5 is greater than the value of the carrier signal SH, so the control signal for the switching element Q5 is maintained at a high level.

[0057] If the value of the sixth command signal S6 is greater than or equal to the value of the carrier signal SH, the control signal for the switching element Q6 becomes high-level, turning the switching element Q6 on. If the value of the sixth command signal S6 is less than the value of the carrier signal SH, the control signal for the switching element Q6 becomes low-level, turning the switching element Q6 off. In the first half of the cycle, the value of the sixth command signal S6 is greater than the value of the carrier signal SH, so the control signal for the switching element Q6 is maintained at a high level.

[0058] During periods other than near the zero-crossing, a control signal for switching element Q6 is supplied from the switching element Q1 generated in this manner to the corresponding switching element, thereby enabling operation during periods other than near the zero-crossing, as described above. That is, during periods when the output voltage V2 > 0, the first mode (Figure 2), zero-crossing (Figure 3), commutation (Figure 4), zero-crossing (Figure 3), and the first mode (Figure 2) are repeated. During periods when the output voltage V2 < 0, the second mode (Figure 5), zero-crossing (Figure 6), commutation (with the current direction reversed in Figure 4), zero-crossing (Figure 6), and the second mode (Figure 5) are repeated. As a result, the power converter 100 can convert DC power to AC power. Similar to the predetermined value d1 described above, the predetermined value d2 should be set according to the required dead time length.

[0059] (Near zero crossing) Figure 12 shows an example of a PWM control signal for achieving operation near zero crossing. The signal waveforms shown in each row of Figure 12 correspond to the signal waveforms shown in each row of Figure 10. In Figure 12, signals with the same reference numerals as in Figure 10 represent the same signals as in Figure 10. Therefore, in the following, we will mainly explain the differences without repeating explanations. The carrier signal SH is a triangular wave, similar to that in Figure 10, but its frequency is higher than that of the carrier signal SH in Figure 10, so the carrier signal SH is shown as a solid black in Figure 12. The control signals for switching elements Q1 to Q4 are also pulse signals similar to those in Figure 10, although they are partially distorted due to the higher frequency of the carrier signal SH.

[0060] The third command signal S3b and the fourth command signal S4b, shown in the fifth row from the top, are generated by adding a predetermined value d1 (d1>0) to the first command signal S1 and the second command signal S2, shown in the second row from the top. The length of the dead time (time) is determined by the magnitude of the predetermined value d1. Therefore, the predetermined value d1 should be set according to the required dead time length. The carrier signal SH and the third command signal S3b generate a control signal for the switching element Q5, and the carrier signal SH and the fourth command signal S4b generate a control signal for the switching element Q6.

[0061] Specifically, if the value of the third command signal S3b is less than or equal to the value of the carrier signal SH, the control signal for the switching element Q5 becomes high-level, turning the switching element Q5 on. If the value of the third command signal S3b is greater than the value of the carrier signal SH, the control signal for the switching element Q5 becomes low-level, turning the switching element Q5 off. During the latter half of the half-cycle, excluding the period near the zero-crossing, the value of the third command signal S3b is negative and less than the value of the carrier signal SH, so the control signal for the switching element Q5 is maintained at a high level.

[0062] If the value of the fourth command signal S4b is less than or equal to the value of the carrier signal SH, the control signal for switching element Q6 becomes high-level, turning on the switching element Q6. If the value of the fourth command signal S4b is greater than the value of the carrier signal SH, the control signal for switching element Q6 becomes low-level, turning off the switching element Q6. During the first half-cycle, excluding the period near the zero-crossing, the value of the fourth command signal S4b is negative and less than the value of the carrier signal SH, so the control signal for switching element Q6 is maintained at a high level.

[0063] Figure 13 shows the periods containing zero crossings by zooming in on the horizontal axis (time axis) of each graph shown in Figure 12. Figures 14 to 17 show each of the periods A to D in Figure 13, zoomed in on. Period A is not included near the zero crossing. Periods B and D are included near the zero crossing. In period B, the output voltage V2 > 0 (AC voltage control command signal S0 > 0), and in period C, the output voltage V2 < 0 (AC voltage control command signal S0 < 0). Period D contains the zero crossing.

[0064] Referring to Figure 14, as described above, the control signal for switching element Q5, generated from the relative magnitudes of the third command signal S3b and the carrier signal SH, changes from high level to low level to high level. As described above, the control signal for switching element Q6, generated from the relative magnitudes of the fourth command signal S4b and the carrier signal SH, is maintained at a high level. Therefore, considering the control signals for switching elements Q1 to Q4, as described above, the state of the power converter 100 transitions from commutation (Figure 4), dead time (Figure 3), first mode (Figure 2), dead time (Figure 3), and commutation (Figure 4).

[0065] Period B is included near the zero-crossing but does not include the zero-crossing. Referring to Figure 15, as described above, the control signal for switching element Q5, generated from the relative magnitudes of the third command signal S3b and the carrier signal SH, changes from high level to low level to high level. As described above, the control signal for switching element Q6, generated from the relative magnitudes of the fourth command signal S4b and the carrier signal SH, also changes from high level to low level to high level. However, switching element Q6 turns off after switching element Q5 and turns on before switching element Q5. Therefore, considering the control signals for switching elements Q1 to Q4, as described above, the state of the power converter 100 transitions as follows: commutation (Figure 4), dead time (Figure 3), off time (Figure 7), first mode (see Figure 2), off time (Figure 7), dead time (Figure 3), and commutation (Figure 4). Periods t1 and t2 represent the off time. However, in the first mode shown in Figure 2, the switching element Q6 is on, but here the switching element Q6 is off. As mentioned above, even when the switching element Q6 is off, the current flows as shown by the dashed arrow in Figure 2, so that state is also included in the first mode.

[0066] Period C is included near the zero crossing but does not include the zero crossing. Referring to Figure 16, as described above, the control signal for switching element Q5, generated from the relative magnitudes of the third command signal S3b and the carrier signal SH, changes from high level to low level to high level. As described above, the control signal for switching element Q6, generated from the relative magnitudes of the fourth command signal S4b and the carrier signal SH, also changes from high level to low level to high level. However, switching element Q6 turns off before switching element Q5 and turns on after switching element Q5. Therefore, considering the control signals for switching elements Q1 to Q4, as described above, the state of the power converter 100 transitions as follows: commutation (state with the current direction reversed in Figure 4), dead time (Figure 6), off time (Figure 8), second mode (see Figure 5), off time (Figure 8), dead time (Figure 6), and commutation (state with the current direction reversed in Figure 4). However, in the second mode shown in Figure 5, the switching element Q5 is on, whereas here the switching element Q5 is off. As mentioned above, even when the switching element Q5 is off, the current flows as shown by the dashed arrow in Figure 5, so that state is also included in the second mode.

[0067] Referring to Figure 17, period D is included near the zero crossing and includes the zero crossing. As described above, the control signal for switching element Q5, generated from the relative magnitudes of the third command signal S3b and the carrier signal SH, changes from high level to low level to high level. As described above, the control signal for switching element Q6, generated from the relative magnitudes of the fourth command signal S4b and the carrier signal SH, also changes from high level to low level to high level at almost the same timing as switching element Q5. Since the control signals for switching elements Q1 to Q4 are all off, as described above, the state of the power converter 100 transitions from commutation (output voltage V2>0), off time, and commutation (output voltage V2<0). In this state, it can be said that all dead time is replaced by off time.

[0068] Thus, by using the carrier signal SH and the third command signal S3b to generate the control signal for switching element Q5, and the carrier signal SH and the fourth command signal S4b to generate the control signal for switching element Q6, a dead time can be realized. At least a portion of the dead time (for example, from period t1 to period t4) is the off time, and switching elements Q5 and Q6 are turned off (i.e., the clamp circuit 104 is shut off), as described above, a short circuit in the DC bus can be avoided.

[0069] The method for generating the PWM control signal to achieve operation near zero crossing is not limited to that shown in Figure 12. For example, it may be generated as shown in Figure 18. The signal waveforms shown in each stage of Figure 18 correspond to the signal waveforms shown in each stage of Figure 11. In Figure 18, signals with the same reference numerals as in Figure 11 represent the same signals as in Figure 11. Therefore, in the following, we will mainly explain the differences without repeating redundant explanations.

[0070] The fifth command signal S5a and the sixth command signal S6a, shown in the fifth row from the top, are generated by subtracting a predetermined value d2 (d2>0) from the third command signal S3a and the fourth command signal S4a, shown in the second row from the top. The magnitude of the predetermined value d2 determines the dead time. Therefore, the predetermined value d2 should be set according to the required dead time length. The carrier signal SH and the fifth command signal S5a generate a control signal for the switching element Q5, and the carrier signal SH and the sixth command signal S6a generate a control signal for the switching element Q6.

[0071] During the period when the output voltage V2 > 0 near the zero crossing, the state of the power converter 100 transitions as follows, similar to Figure 15: commutation (Figure 4), dead time (Figure 3), off time (Figure 7), first mode (switching element Q6 is off in Figure 2), off time (Figure 7), dead time (Figure 3), and commutation (Figure 4). During the period when the output voltage V2 < 0 near the zero crossing, the state of the power converter 100 transitions as follows, similar to Figure 16: commutation (current direction reversed in Figure 4), dead time (Figure 6), off time (Figure 8), second mode (switching element Q5 is off in Figure 5), off time (Figure 8), dead time (Figure 6), and commutation (current direction reversed in Figure 4).

[0072] In this way, a dead time can be realized by using the carrier signal SH and the fifth command signal S5a to generate the control signal for switching element Q5, and the carrier signal SH and the sixth command signal S6a to generate the control signal for switching element Q6. Furthermore, an off time can be formed during a portion of the dead time, and by turning off switching elements Q5 and Q6 (i.e., the clamp circuit 104 is shut off), a short circuit of the DC bus can be avoided as described above.

[0073] (modified version) The inverter circuit and clamp circuit included in the power converter are not limited to the inverter circuit 102 and clamp circuit 104 shown in Figure 1. Referring to Figure 19, a modified power converter 200 includes an inverter circuit 202, a clamp circuit 204, a diode D9, and a control unit (not shown). The control unit is the same as the control unit 110 shown in Figure 1. The inverter circuit 202 includes switching elements Q1 to Q4, and diodes D2 and D4. The clamp circuit 204 includes switching elements Q5 and Q6, and diodes D7 and D8.

[0074] Figure 20 is a circuit diagram redrawn from Figure 19 to facilitate comparison with Figure 1. Referring to Figure 20, the power converter 200 is the same as the power converter 100 in Figure 1, but with diodes D1 and D2 removed, diodes D5 and D6 replaced by diodes D7 and D8 respectively, and diode D9 added. In Figure 20, elements with the same reference numerals as in Figure 1 are the same as in Figure 1. Therefore, to avoid repeating explanations, the following will mainly focus on the differences.

[0075] The clamp circuit 204 includes a switching element Q5 and a diode D7 connected in parallel, and a switching element Q6 and a diode D8 connected in parallel. The cathode of diode D7 is connected to the cathode of diode D8. The anode of diode D9 is connected to the connection node between the cathodes of diode D7 and diode D8. The cathode of diode D9 is connected to the connection node between switching elements Q1 and Q3, i.e., the input terminal IN1.

[0076] The power converter 200 operates in the same manner as the power converter 100 described above. Referring to Figure 21, during periods other than near the zero crossing, when the output voltage V2 > 0, switching elements Q1, Q4, and Q5 are turned on, and switching elements Q2, Q3, and Q6 are turned off. As a result, current flows as in Figure 2, as indicated by the dashed arrows, and the first mode is realized. Referring to Figure 22, during periods other than near the zero crossing, when the output voltage V2 > 0, switching element Q5 is turned on, and switching elements Q1 through Q4 and Q6 are turned off. As a result, current flows as in Figure 3, as indicated by the dashed arrows, and a dead time is realized. Referring to Figure 23, during periods other than near the zero crossing, when the output voltage V2 > 0, switching elements Q1 through Q4 are turned off, and switching elements Q5 and Q6 are turned on. As a result, current flows as in Figure 4, as indicated by the dashed arrows, and commutation is realized. During periods other than near zero crossing, when the output voltage V2 > 0, the first mode (Figure 21), dead time (Figure 22), commutation (Figure 23), dead time (Figure 22), and the first mode (Figure 21) are repeatedly executed.

[0077] During periods other than near the zero-crossing, when the output voltage V2 < 0, the second mode is realized, similar to Figure 5, by reversing the on / off states of each switching element shown in Figure 21. Also, during periods other than near the zero-crossing, when the output voltage V2 < 0, the dead time corresponding to Figure 6 is realized by reversing the on / off states of switching elements Q5 and Q6 shown in Figure 22. During periods other than near the zero-crossing, when the output voltage V2 < 0, the cycle of second mode, dead time, commutation, dead time, and second mode is repeatedly executed.

[0078] Referring to Figure 24, during the period when the output voltage V2 > 0 near the zero-crossing, all switching elements Q1 through Q6 are turned off, and an off-time is realized. At this time, the current flows along a path similar to that in Figure 7, as indicated by the dashed arrow. Referring to Figure 25, during the period when the output voltage V2 < 0 near the zero-crossing, all switching elements Q1 through Q6 are turned off, and an off-time is realized. At this time, the current flows along a path similar to that in Figure 8, as indicated by the dashed arrow.

[0079] Therefore, during the period when the output voltage V2 > 0 near the zero-crossing, the first mode (Figure 21), off-time (Figure 24), dead time (Figure 22), commutation (Figure 23), dead time (Figure 22), off-time (Figure 24), and the first mode (Figure 21) can be repeatedly executed. Also, during the period when the output voltage V2 < 0 near the zero-crossing, the second mode, off-time (Figure 25), dead time, commutation, dead time, off-time (Figure 25), and the second mode can be repeatedly executed.

[0080] Thus, similar to the power converter 100, the power converter 200 can provide off-times during the dead time between the transition from the first mode to commutation and between the transition from commutation to the first mode near zero crossing. Furthermore, similar to the power converter 100, the power converter 200 can also provide off-times during the dead time between the transition from the second mode to commutation and between the transition from commutation to the second mode near zero crossing. Therefore, the power converter 200 can avoid short circuits of the DC bus that may occur near zero crossing. Consequently, the power converter 200 can be operated stably.

[0081] The above describes a case where a portion of the dead time is off-time (i.e., the clamp circuit is shut off) near the zero-crossing, but it is not limited to this. It is sufficient that a portion of the dead time includes off-time. As the control signals for switching elements Q5 and Q6 near the zero-crossing, a control signal may be used that turns off both switching elements Q5 and Q6 for the entire dead time.

[0082] The vicinity of the zero crossing can be any predetermined period that includes the zero crossing. For example, a period of 2 cycles or less, 3 cycles or less, 4 cycles or less, or 5 cycles or less of the carrier signal SH can be considered the vicinity of the zero crossing. In environments with significant noise, a longer period may be considered the vicinity of the zero crossing.

[0083] The above describes a case where the clamp circuit includes two switching elements, but it is not limited to this. The clamp circuit only needs to include at least one switching element. For example, the clamp circuit may include one bidirectional switching element such as GaN / AlGaN. When using one bidirectional switching element in the clamp circuit, as described above, the bidirectional switching element should be controlled so that during the dead time the clamp circuit is in a rectified state where current flows due to the reverse voltage of the output voltage of the inverter circuit. A GaN / AlGaN bidirectional switching element has two electrodes and two gate electrodes for controlling the current flow between the two electrodes. The two electrodes can be source electrodes or drain electrodes depending on the direction of the current flowing through the element. In a GaN / AlGaN bidirectional switching element, an AlGaN layer is formed on top of a GaN layer, the two gate electrodes are formed on the AlGaN layer, and the two electrodes are formed so as to reach the GaN layer with the two gate electrodes in between. When a voltage is applied between two electrodes, if the voltage applied to either gate electrode is not greater than the threshold voltage, depletion occurs in the two-dimensional electron gas layer at the AlGaN / GaN heterointerface formed beneath the gate electrode, and no current flows between the two electrodes. When a voltage greater than the threshold voltage is applied to both gate electrodes, current flows between the two electrodes in accordance with the voltage applied to the two electrodes (the direction of the current depends on the direction of the voltage applied between the two electrodes). Therefore, a GaN / AlGaN bidirectional switching element can conduct current in both directions, and one GaN / AlGaN bidirectional switching element can replace the two switching elements in the clamp circuit 104 shown in Figure 1. Furthermore, in a GaN / AlGaN bidirectional switching element, if a voltage greater than the threshold voltage is applied to only one of the two gate electrodes, it functions as a diode. Therefore, a rectified state can be achieved in which current flows due to the reverse voltage of the output voltage of the inverter circuit.

[0084] The present disclosure has been described above by describing embodiments, but the embodiments described above are illustrative and the present disclosure is not limited to the embodiments described above. The scope of the present disclosure is as indicated by each claim of the claims, with reference to the description of the detailed description of the invention, and includes all modifications within the meaning and scope equivalent to the wording contained herein. [Explanation of symbols]

[0085] 100, 200 Power Converters 102, 202 Inverter Circuit 104, 204 clamp circuit 106, 108 Wiring 110 Control Unit 112 CPU 114 memory 116 IF section A, B, C, D, t1, t2, t3, t4 period C1 Capacitor D1, D2, D3, D4, D5, D6, D7, D8, D9 diodes d1, d2 predetermined values IN1, IN2 Input Terminals L1, L2 Reactors OUT1, OUT2 output terminals Q1, Q2, Q3, Q4, Q5, Q6 switching elements S0 AC voltage control command signal S1 1st command signal S2 2nd command signal S3, S3a, S3b 3rd command signal S4, S4a, S4b 4th command signal S5, S5a 5th command signal S6, S6a 6th command signal SH carrier signal V1 Input Voltage V2 Output Voltage

Claims

1. An inverter circuit including two sets of switching elements that converts DC power supplied from a DC power source into AC power, A clamp circuit, which includes at least one switching element, is connected between the output terminals of the inverter circuit. The inverter circuit and the clamp circuit include a control unit that controls the on and off states of the switching elements, A dead time is provided between the time when one of the two sets of switching elements is turned off and the clamp circuit is short-circuited, and between the time the clamp circuit is not short-circuited and the time when one set of switching elements is turned on. The control unit, Outside of the aforementioned dead time, when all two sets of switching elements are turned off, the clamp circuit is short-circuited. During a first predetermined period that includes a zero-crossing in which the polarity of the AC voltage output from the output terminal changes, the clamp circuit is shut off for at least a second predetermined period in the dead time included in the first predetermined period. A power conversion device that controls the clamp circuit so that, during the dead time included in a period other than the first predetermined period, the clamp circuit enters a rectified state in which current flows due to the reverse voltage of the output voltage of the inverter circuit.

2. The clamp circuit includes two switching elements, The clamping circuit is When both of the aforementioned switching elements are turned on, a short circuit occurs. The power conversion device according to claim 1, wherein the power is interrupted when both of the aforementioned switching elements are turned off.

3. The control unit, A carrier signal in which the same voltage waveform periodically repeats in the positive voltage region, A first command signal having the same frequency as the AC power, and whose voltage alternately changes sinusoidally in the positive and negative regions, The second command signal is obtained by inverting the positive and negative signs of the first command signal, In the first command signal, a third command signal is generated by adding a predetermined value corresponding to the dead time to the first command signal in the positive voltage region, In the second command signal, PWM control is performed using the second command signal in the positive voltage region and the fourth command signal generated by adding the predetermined value to the second command signal. During the period excluding the aforementioned dead time, the control unit shall During the period when the value of the first command signal is greater than the value of the carrier signal, the first set of switching elements among the two sets of switching elements included in the inverter circuit is turned on. During the period when the value of the first command signal is less than or equal to the value of the carrier signal, the first set of switching elements is turned off, and during the period when the value of the third command signal is a positive value less than or equal to the value of the carrier signal, the clamp circuit is short-circuited. During the period when the value of the second command signal is greater than the value of the carrier signal, the second set of switching elements among the two sets of switching elements included in the inverter circuit is turned on. The power conversion device according to claim 1 or 2, wherein the second set of switching elements is turned off during a period when the value of the second command signal is less than or equal to the value of the carrier signal, and the clamp circuit is short-circuited during a period when the value of the fourth command signal is a positive value less than or equal to the value of the carrier signal.

4. A signal having the same frequency as the AC power and whose voltage alternately changes sinusoidally between the positive and negative regions is defined as the first command signal, and a signal generated by inverting the positive and negative values ​​of the first command signal is defined as the second command signal. The control unit, A carrier signal in which the same voltage waveform periodically repeats in the positive voltage region, A third command signal generated by subtracting the first command signal from the maximum value of the carrier signal, A fourth command signal generated by subtracting the second command signal from the maximum value of the carrier signal, A fifth command signal is generated by subtracting a predetermined value corresponding to the dead time from the third command signal in the region where the voltage is smaller than the maximum value, PWM control is performed using the fourth command signal and a sixth command signal generated by subtracting a predetermined value from the fourth command signal in a region where the voltage is smaller than the maximum value. During the period excluding the aforementioned dead time, the control unit shall During the period when the value of the third command signal is smaller than the value of the carrier signal, the first set of switching elements among the two sets of switching elements included in the inverter circuit is turned on. During the period when the value of the third command signal is greater than or equal to the value of the carrier signal, the first set of switching elements is turned off, and during the period when the value of the first command signal is positive and the value of the fifth command signal is greater than or equal to the value of the carrier signal, the clamp circuit is short-circuited. During the period when the value of the fourth command signal is smaller than the value of the carrier signal, the second set of switching elements among the two sets of switching elements that include the inverter circuit is turned on. The power conversion device according to claim 1 or 2, wherein the second set of switching elements is turned off during a period when the value of the fourth command signal is equal to or greater than the value of the carrier signal, and the clamp circuit is short-circuited during a period when the value of the first command signal is negative and the value of the sixth command signal is equal to or greater than the value of the carrier signal.

5. The clamp circuit includes a first switching element and a second switching element, A signal having the same frequency as the AC power and whose voltage alternately changes sinusoidally between the positive and negative regions is defined as the first command signal, and a signal generated by inverting the positive and negative values ​​of the first command signal is defined as the second command signal. The control unit, A carrier signal in which the same voltage waveform periodically repeats in the positive voltage region, The first command signal and, The second command signal and, A third command signal is generated by adding a predetermined value corresponding to the dead time to the first command signal, PWM control is performed using the second command signal and the fourth command signal generated by adding the predetermined value to the second command signal. The control unit, During the period when the value of the first command signal is greater than the value of the carrier signal, the first set of switching elements among the two sets of switching elements included in the inverter circuit is turned on. During the period when the value of the first command signal is less than or equal to the value of the carrier signal, the first set of switching elements is turned off. During the period when the value of the second command signal is greater than the value of the carrier signal, the second set of switching elements among the two sets of switching elements included in the inverter circuit is turned on. During the period when the value of the second command signal is less than or equal to the value of the carrier signal, the second set of switching elements is turned off. During the period when the value of the third command signal is smaller than the value of the carrier signal, the first switching element is turned on. During the period in which the value of the third command signal is equal to or greater than the value of the carrier signal, the first switching element is turned off. During the period when the value of the fourth command signal is smaller than the value of the carrier signal, the second switching element is turned on. The power conversion device according to claim 1, wherein the second switching element is turned off during a period in which the value of the fourth command signal is equal to or greater than the value of the carrier signal.

6. The clamp circuit includes a first switching element and a second switching element, A signal having the same frequency as the AC power and whose voltage alternately changes sinusoidally between the positive and negative regions is defined as the first command signal, and a signal generated by inverting the positive and negative values ​​of the first command signal is defined as the second command signal. The control unit, A carrier signal in which the same voltage waveform periodically repeats in the positive voltage region, A third command signal generated by subtracting the first command signal from the maximum value of the carrier signal, A fourth command signal generated by subtracting the second command signal from the maximum value of the carrier signal, A fifth command signal is generated by subtracting a predetermined value corresponding to the dead time from the third command signal, PWM control is performed using the sixth command signal generated by subtracting the predetermined value from the fourth command signal. The control unit, During the period when the value of the third command signal is smaller than the value of the carrier signal, the first set of switching elements among the two sets of switching elements included in the inverter circuit is turned on. During the period in which the value of the third command signal is equal to or greater than the value of the carrier signal, the first set of switching elements is turned off. During the period when the value of the fourth command signal is smaller than the value of the carrier signal, the second set of switching elements among the two sets of switching elements included in the inverter circuit is turned on. During the period in which the value of the fourth command signal is equal to or greater than the value of the carrier signal, the second set of switching elements is turned off. During the period when the value of the fifth command signal is greater than the value of the carrier signal, the first switching element is turned on. During the period when the value of the fifth command signal is less than or equal to the value of the carrier signal, the first switching element is turned off. During the period when the value of the sixth command signal is greater than the value of the carrier signal, the second switching element is turned on. The power conversion device according to claim 1, wherein the second switching element is turned off during a period when the value of the sixth command signal is less than or equal to the value of the carrier signal.

7. An inverter circuit including two sets of switching elements that converts DC power supplied from a DC power source into AC power, A clamp circuit, which includes at least one switching element, is connected between the output terminals of the inverter circuit. A control method for a power converter, comprising a control unit that controls the on and off states of the switching elements included in the inverter circuit and the clamp circuit, A dead time is provided between the time when one of the two sets of switching elements is turned off and the clamp circuit is short-circuited, and between the time the clamp circuit is not short-circuited and the time when one set of switching elements is turned on. The control unit, when turning off all two sets of switching elements outside of the dead time, short-circuits the clamp circuit. The control unit performs the steps of shutting off the clamp circuit for at least a second predetermined period within the dead time included in the first predetermined period, during a first predetermined period that includes a zero-crossing in which the polarity of the AC voltage output from the output terminal changes, A control method comprising the step of the control unit controlling the clamp circuit such that, during the dead time included in a period other than the first predetermined period, the clamp circuit enters a rectified state in which current flows due to the reverse voltage of the output voltage of the inverter circuit.

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