semiconductor element

Abstract

To provide semiconductor devices with improved integration density and electrical characteristics. [Solution] The device comprises a base structure extending in a first direction, a plurality of gate electrodes extending in a second direction perpendicular to the first direction on the base structure and spaced apart from each other in the first and second directions, a plurality of channel layers spaced apart from each other along a third direction perpendicular to the upper surface of the base structure and surrounded by each of the gate electrodes, source / drain regions connected to the plurality of channel layers on both sides of the gate electrodes, a separation structure extending in a first direction that separates each of the plurality of adjacent gate electrodes, the plurality of channel layers, and the source / drain regions along the second direction, and a gate connection layer that electrically connects the first gate electrode and the second gate electrode, which are spaced apart from each other in a fourth direction intersecting the first and second directions among the plurality of gate electrodes, and is on the separation structure and in contact with the upper surface of the separation structure.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device with improved integration density and electrical characteristics. [Background technology]

[0002] As the demand for higher performance, faster speeds, and / or more functionality in semiconductor devices increases, the integration density of semiconductor devices is also increasing. In manufacturing semiconductor devices with fine patterns to accommodate the trend towards high integration of semiconductor devices, it is required to realize patterns with fine widths or fine spacing distances. Furthermore, in order to overcome the limitations in operating characteristics due to the reduction in size of planar MOSFETs (metal oxide semiconductor FETs), efforts are underway to develop semiconductor devices, including transistors with three-dimensional channel structures, and this remains a daily challenge. [Overview of the project] [Problems that the invention aims to solve]

[0003] The present invention has been made in view of the problems with the above-mentioned conventional semiconductor devices, and the object of the present invention is to provide a semiconductor device with improved integration density and electrical characteristics. [Means for solving the problem]

[0004] To achieve the above objective, the semiconductor device according to the present invention is characterized by comprising: a base structure extending in a first direction; a plurality of gate electrodes extending on the base structure in a second direction perpendicular to the first direction and spaced apart from each other in the first and second directions; a plurality of channel layers extending on the base structure, spaced apart from each other along a third direction perpendicular to the upper surface of the base structure and surrounded by each of the gate electrodes; source / drain regions connected to the plurality of channel layers on both sides of the gate electrodes; a separation structure extending in a first direction that separates each of the plurality of gate electrodes, the plurality of channel layers, and the source / drain regions adjacent to each other along the second direction; and a gate connection layer that electrically connects a first gate electrode and a second gate electrode that are spaced apart from each other in a fourth direction intersecting the first and second directions among the plurality of gate electrodes, and that contacts the upper surface of the separation structure on the separation structure.

[0005] Furthermore, the semiconductor element according to the present invention, made to achieve the above objective, is characterized by comprising: a first gate electrode and a second gate electrode that are separated from each other in a first direction; a third gate electrode and a fourth gate electrode that are separated from each other in the first direction and separated from the first and second gate electrodes, respectively, in a second direction perpendicular to the first direction; a separation structure that extends in the first direction between the first and third gate electrodes and between the second and fourth gate electrodes; source / drain regions arranged on both sides of each of the first to fourth gate electrodes along the first direction and separated from each other in the second direction by the separation structure; and a gate connection layer on the separation structure that contacts the second and third gate electrodes via its side surface and electrically connects the second gate electrode and the third gate electrode.

[0006] Furthermore, the semiconductor device according to the present invention, made to achieve the above objective, is characterized by comprising: a plurality of gate structures including a gate dielectric layer, a gate electrode, and a gate capping layer, which are separated from each other in a first direction and a second direction orthogonal to the first direction and stacked sequentially; a plurality of channel layers separated from each other along a third direction perpendicular to the first and second directions and surrounded by each of the gate structures; source / drain regions on both sides of the gate structure that are connected to the plurality of channel layers; isolation structures that are adjacent to each other along the second direction, separating each of the gate structures, the plurality of channel layers, and the source / drain regions from each other and extending along the first direction; and a gate connection layer on the isolation structure that is in contact with the gate capping layer and electrically connects a first gate electrode and a second gate electrode, which are separated from each other in a fourth direction intersecting the first and second directions within the gate electrode. [Effects of the Invention]

[0007] According to the semiconductor device of the present invention, a semiconductor device with improved integration density and electrical characteristics can be provided by including a gate connection layer on an isolation structure. [Brief explanation of the drawing]

[0008] [Figure 1] This is a plan view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 2a] This is a cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 2b] This is a cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 2c] This is a cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 3a] This is a layout diagram showing the schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 3b] This is a layout diagram showing the schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 4a]It is a cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 4b] It is a cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 5] It is a circuit diagram of a semiconductor device according to an embodiment of the present invention. [Figure 6a] It is a plan view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 6b] It is a plan view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 7a] It is a cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 7b] It is a cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 7c] It is a cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 7d] It is a cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 8a] It is a diagram showing the process sequence for explaining the manufacturing method of a semiconductor device according to an embodiment of the present invention. [Figure 8b] It is a diagram showing the process sequence for explaining the manufacturing method of a semiconductor device according to an embodiment of the present invention. [Figure 8c] It is a diagram showing the process sequence for explaining the manufacturing method of a semiconductor device according to an embodiment of the present invention. [Figure 8d] It is a diagram showing the process sequence for explaining the manufacturing method of a semiconductor device according to an embodiment of the present invention. [Figure 8e] It is a diagram showing the process sequence for explaining the manufacturing method of a semiconductor device according to an embodiment of the present invention. [Figure 8f] It is a diagram showing the process sequence for explaining the manufacturing method of a semiconductor device according to an embodiment of the present invention. [Figure 8g] It is a diagram showing the process sequence for explaining the manufacturing method of a semiconductor device according to an embodiment of the present invention.

Best Mode for Carrying Out the Invention

[0009] Next, a specific example of a form for implementing the semiconductor device according to the present invention will be described while referring to the drawings.

[0010] In the following, terms such as "upper", "upper part", "upper surface", "lower", "lower part", "lower surface", "side surface", etc. can be understood to be referred to based on the drawings unless otherwise explained. The exemplary embodiments described below can also be described as one exemplary embodiment in combination with each other.

[0011] FIG. 1 is a plan view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention, and FIGS. 2A to 2C are cross-sectional views showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. FIG. 2A shows a cross-section obtained by cutting the semiconductor device of FIG. 1 along lines I-I', II-II', and III-III', FIG. 2B shows a cross-section obtained by cutting the semiconductor device of FIG. 1 along line IV-IV', and FIG. 2C shows a cross-section obtained by cutting the semiconductor device of FIG. 1 along line V-V'.

[0012] Referring to FIGS. 1 to 2C, the semiconductor device 100 includes an active region ACT on a substrate 101, a channel structure 140 disposed on the active region ACT and spaced apart from each other perpendicularly, including first to fourth channel layers (141, 142, 143, 144), first to fourth gate electrodes (GE1, GE2, GE3, GE4) extending intersecting the active region ACT, a source / drain region 150 in contact with the channel structure 140, a separation structure DWS between adjacent source / drain regions 150, a gate connection layer GL connecting the second and third gate electrodes (GE2, GE3), a source contact plug CA connected to the source / drain region 150, and a gate contact plug CB connected to the first to fourth gate electrodes (GE1, GE2, GE3, GE4). The semiconductor device 100 further includes an element isolation layer 110, an insulating liner layer 155, an upper via VA, a first wiring line M1, and first to third interlayer insulating layers (190, 192, 194).

[0013] In the semiconductor device 100, the active region ACT has a fin structure or a protruding structure, and the first to fourth gate electrodes (GE1, GE2, GE3, GE4) are arranged between the active region ACT and the channel structure 140, between the first to fourth channel layers (141, 142, 143, 144) of the channel structure 140, and on the channel structure 140. As a result, the semiconductor device 100 includes a transistor with an MBCFET (registered trademark) (Multi Bridge Channel FET) structure, which is a gate-all-around type field-effect transistor. The substrate 101 has an upper surface that extends in the X and Y directions. The substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, Group IV semiconductors may include silicon, germanium, or silicon-germanium. The substrate 101 is provided as a bulk wafer, an epitaxial layer, an SOI (Silicon On Insulator) layer, or an SeOI (Semiconductor On Insulator) layer, etc.

[0014] The active region ACT is defined on the substrate 101 by the element isolation layer 110 and the isolation structure DWS, and is arranged to extend in a first direction, for example, in the X direction. Between adjacent active regions ACT in the Y direction, the element isolation layer 110 or the lower isolation structure (DWS_L) of the isolation structure DWS is positioned. Depending on the explanation method, it is also possible to describe the active region ACT as part of the substrate 101. In this specification, the active region ACT is also referred to as the base structure together with the substrate 101. The active region ACT protrudes partially above the device isolation layer 110 below the first to fourth gate electrodes (GE1, GE2, GE3, GE4), and a portion of the upper surface of the active region ACT is located at a higher level than the upper surface of the device isolation layer 110. The active region ACT is composed of a portion of the substrate 101 and includes an epitaxial layer grown from the substrate 101. However, on both sides of the first to fourth gate electrodes (GE1, GE2, GE3, GE4), the active region ACT is partially recessed, and the source / drain region 150 is positioned on the active region ACT.

[0015] The active region (ACT) contains well regions that contain impurities. For example, the well region may contain p-type impurities such as boron (B), gallium (Ga), or aluminum (Al), or n-type impurities such as phosphorus (P), arsenic (As), or antimony (Sb). The well regions are positioned, for example, at a predetermined depth from each of the upper surfaces of the active region ACT. The element isolation layer 110 defines the active region ACT on the substrate 101. The element isolation layer 110 is formed, for example, by a shallow trench isolation (STI) process. The element isolation layer 110 exposes at least the upper surface of the active region ACT, and partially exposes the upper part. In this embodiment, the element isolation layer 110 has a curved upper surface that is higher the closer it is to the active region ACT. The element isolation layer 110 is made of an insulating material. The element isolation layer 110 may be, for example, an oxide, a nitride, or a combination thereof.

[0016] The first to fourth gate electrodes (GE1, GE2, GE3, GE4) are arranged on the active region ACT so as to extend in one direction, for example, in the Y direction. The first to fourth gate electrodes (GE1, GE2, GE3, GE4) are arranged spaced apart from each other along the X and Y directions. Between the first to fourth gate electrodes (GE1, GE2, GE3, GE4) adjacent in the Y direction, the lower separation structure (DWS_L) of the separation structure DWS is interposed. The channel region of the transistor is formed in the channel structure 140 that intersects with the first to fourth gate electrodes (GE1, GE2, GE3, GE4). Each of the first to fourth gate electrodes (GE1, GE2, GE3, GE4) forms a gate structure together with the gate dielectric layer 162, the gate spacer layer 164, and the gate capping layer 167.

[0017] The gate dielectric layer 162 is positioned between the active region ACT and the first to fourth gate electrodes (GE1, GE2, GE3, GE4), and between the channel structure 140 and the first to fourth gate electrodes (GE1, GE2, GE3, GE4), and is positioned to cover at least a portion of the surface of the first to fourth gate electrodes (GE1, GE2, GE3, GE4). For example, the gate dielectric layer 162 is positioned to surround all surfaces of the first to fourth gate electrodes (GE1, GE2, GE3, GE4) except for their uppermost surfaces. The gate dielectric layer 162 extends between the first to fourth gate electrodes (GE1, GE2, GE3, GE4) and the gate spacer layer 164, but is not limited to this. The gate dielectric layer 162 may also be extended onto the side surface of the lower isolation structure (DWS_L).

[0018] The gate dielectric layer 162 contains an oxide, nitride, or high-dielectric constant (high-k) material. High dielectric constant materials refer to dielectric materials that have a higher dielectric constant than silicon oxide (SiO2). High dielectric constant materials include, for example, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), and zirconium silicon oxide (ZrSi x O y ), hafnium oxide (HfO2), hafnium silicon oxide (HfSi x O y ), lanthanum oxide (La2O3), aluminum lanthanum oxide (LaAl x O y)、Lanthanum hafnium oxide (LaHf x O y )、hafnium aluminum oxide (HfAl x O y ), or one of praseodymium oxide (Pr2O3). According to an embodiment, the gate dielectric layer 162 can have a multilayer structure.

[0019] The first to fourth gate electrodes (GE1, GE2, GE3, GE4) contain a conductive material, for example, metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and / or metal materials such as aluminum (Al), tungsten (W), or molybdenum (Mo), or semiconductor materials such as doped polysilicon. According to an embodiment, the first to fourth gate electrodes (GE1, GE2, GE3, GE4) can also have a multilayer structure. The first, third, and fourth gate electrodes (GE1, GE3, GE4) are connected to the upper gate contact plug CB.

[0020] The gate spacer layer 164 is disposed on both side surfaces of each of the first to fourth gate electrodes (GE1, GE2, GE3, GE4) on the channel structure 140. The gate spacer layer 164 insulates the source / drain region 150 from the first to fourth gate electrodes (GE1, GE2, GE3, GE4). According to an embodiment, the shape of the upper end of the gate spacer layer 164 can be variously changed, and the gate spacer layer 164 can also have a multilayer structure. The gate spacer layer 164 can contain at least one of an oxide, a nitride, and an oxynitride, and can be made of, for example, a low dielectric constant film. The gate capping layer 167 is disposed on each of the first to fourth gate electrodes (GE1, GE2, GE3, GE4). In one embodiment, the lower surface of the gate capping layer 167 has a convex shape downward. The gate capping layer 167 contains an insulating material, which may include, for example, at least one of oxides, nitrides, and oxynitrides.

[0021] The channel structure 140 is positioned on each of the active regions ACT, in the region where the active region ACT intersects with the first to fourth gate electrodes (GE1, GE2, GE3, GE4). The channel structure 140 includes first to fourth channel layers (141, 142, 143, 144), which are two or more channel layers spaced apart from each other in a direction perpendicular to the upper surface of each active region ACT, for example, in the Z direction. The first to fourth channel layers (141, 142, 143, 144) are connected to the source / drain region 150, while being separated from the upper surface of the active region ACT. The first to fourth channel layers (141, 142, 143, 144) have the same or similar width as the active region ACT in the Y direction and the same or similar width as the gate structure in the X direction. The width in the Y direction of the first to fourth channel layers (141, 142, 143, 144) increases toward the lower channel layers, but is not limited to this. The number and shape of each channel layer (141, 142, 143, 144) of the channel structure 140 can be varied in various ways depending on the embodiment.

[0022] A lower separation structure (DWS_L) is interposed between adjacent channel structures 140 in the Y direction. One side of the channel layer (141, 142, 143, 144) in the Y direction is in contact with the lower separation structure (DWS_L) and is coplanar with the side of the lower separation structure (DWS_L), while the other side protrudes into the first to fourth gate electrodes (GE1, GE2, GE3, GE4). The first to fourth channel layers (141, 142, 143, 144) are made of a semiconductor material and may include at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). The first to fourth channel layers (141, 142, 143, 144) are made of the same material as the substrate 101, for example.

[0023] The source / drain regions 150 are positioned on both sides of the gate structure so as to be in contact with the channel structure 140. The source / drain region 150 is positioned to cover the sides of the first to fourth channel layers (141, 142, 143, 144) of the channel structure 140, along the X direction. The upper surface of the source / drain region 150 is located at the same level as or higher than the lower surface of the gate electrode 165 on the channel structure 140, and this level can be varied in various embodiments. The source / drain region 150, outside the gate structure, includes a polygonal upper region in a cross-section along the Y direction. However, in the embodiment, the shape of the upper region is not limited to the shape shown in Figure 2a, and may have a curved polygon, ellipse, or circular shape. In the source / drain region 150, at least the upper region may be covered with an insulating liner 155. In one embodiment, an insulating spacer layer is further arranged on the side surface in the Y direction of the lower region of the source / drain area 150. The source / drain regions 150 are connected to the upper source contact plug CA, respectively.

[0024] The source / drain region 150 contains at least one of semiconductor materials, such as silicon (Si) and germanium (Ge), and further contains impurities. Each of the source / drain regions 150 includes multiple epitaxial layers having different compositions from each other. In one embodiment, the semiconductor element 100 further includes an internal spacer layer disposed between the side surface of the source / drain region 150 along the X direction and the gate dielectric layer 162. The internal spacer layer contains an insulating material. The insulating liner 155 covers the surface of the source / drain region 150 and extends over the upper surface of the element isolation layer 110 and the side surface of the gate structure. The insulating liner 155 contains an insulating material, which may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. In one embodiment, the insulating liner 155 may constitute or omit a portion of the first interlayer insulating layer 190.

[0025] As shown in Figure 1, the separation structure DWS has a linear shape that extends in the X direction and is interposed in the Y direction between adjacent first to fourth gate electrodes (GE1, GE2, GE3, GE4), between active regions ACT, between channel structures 140, and between source / drain regions 150. The separation structure DWS includes a lower separation structure (DWS_L) and an upper separation structure (DWS_U) on the lower separation structure (DWS_L). The lower separation structure (DWS_L) extends continuously in the X direction, while the upper separation structure (DWS_U) is positioned only outside the gate structure. Although the width of the upper separation structure (DWS_U) is shown as being smaller than the width of the lower separation structure (DWS_L), it is not limited to this and may be the same as or larger than the width of the lower separation structure (DWS_L).

[0026] The upper surface of the lower separation structure (DWS_L) is at substantially the same level as the upper surfaces of the first to fourth gate electrodes (GE1, GE2, GE3, GE4) between the gate structures. However, in one embodiment, the upper surface of the lower separation structure (DWS_L) may be located at the same or similar level as the upper surface of the uppermost fourth channel layer 144. In this case, a separate gate separation structure is further positioned on the lower separation structure (DWS_L) to separate the first to fourth gate electrodes (GE1, GE2, GE3, GE4). The lower separation structure (DWS_L) has inclined sides that decrease in width toward the substrate 101, but the shape of the sides of the lower separation structure (DWS_L) is not limited to this. The lower separation structure (DWS_L) is positioned at a relatively low height outside the gate structure. As a result, the upper surface of the lower separation structure (DWS_L) is located at a relatively low level, within the height of the source / drain area 150.

[0027] The upper separation structure (DWS_U) is located outside the gate structure, between the source / drain regions 150, and is connected to the lower separation structure (DWS_L). The upper separation structure (DWS_U) extends upward along the Y-direction between adjacent source contact plugs CA. In this embodiment, the upper surface of the upper separation structure (DWS_U) is located at a lower level than the upper surface of the source contact plug CA. For example, the upper surface of the upper separation structure (DWS_U) is at substantially the same level as the lower surface of the gate capping layer 167, and is at substantially the same level as the upper surface of the lower separation structure (DWS_L) between the gate structures. For example, the height of the DWS (Dispersion Welding Station) is constant. The upper separation structure (DWS_U) is positioned in a configuration in which a portion of the region, including the upper region, is removed in the area where the gate connection layer GL is located. The isolation structure DWS contains an insulating material, which may include a material different from that of the element isolation layer 110, for example. The separation structure DWS may include, for example, at least one of silicon nitride and silicon oxynitride. For example, the lower separation structure (DWS_L) and the upper separation structure (DWS_U) contain the same material.

[0028] The gate connection layer GL physically and electrically connects the second and third gate electrodes (GE2, GE3), which are gate electrodes spaced diagonally apart from each other, for example in the D1 direction. The D1 direction intersects with the X and Y directions and is parallel to the upper surface of the substrate 101. The gate connection layer GL is separated from the first and fourth gate electrodes (GE1, GE4), for example, in the Y direction. In this embodiment, the first and fourth gate electrodes (GE1, GE4) are either electrically connected to each other or not electrically connected to each other. When electrically connected to each other, the first and fourth gate electrodes (GE1, GE4) can be connected via an upper wiring structure not shown in the figure.

[0029] The gate connection layer GL has a shape in which lines or patterns extending in the X and Y directions are connected, and the entire structure extends in the D1 direction. For example, the gate connection layer GL includes a pattern that extends in the Y direction and a pattern that connects to it and extends in the X direction. In the gate connection layer GL, the second width W2 of the pattern connected to the second and third gate electrodes (GE2, GE3) and extending in the Y direction is greater than the first width W1 of the second and third gate electrodes (GE2, GE3). In the gate connection layer GL, the third width W3 of the pattern connecting the pattern extending in the Y direction and the pattern extending in the X direction is greater than, but not limited to, the second width W2. The maximum width of the gate connection layer GL, for example, the third width W3, is smaller than the width of the separation structure DWS. In this specification, unless otherwise specified, "width" refers to the length in the direction perpendicular to the direction of extension.

[0030] In the plan view of Figure 1, the gate connection layer GL is entirely superimposed on the separation structure DWS. The gate connection layer GL is entirely superimposed on the separation structure DWS in the Z direction. As shown in Figures 2a and 2b, the gate connection layer GL is positioned on the separation structure DWS in a configuration in which the separation structure DWS is partially removed. For example, the gate connection layer GL is positioned such that, along the Y direction, in a region aligned with the second and third gate electrodes (GE2, GE3), the lower separation structure (DWS_L) is recessed from the top surface to a predetermined depth. Outside the linear region, the gate connection layer GL is positioned with the upper separation structure (DWS_U) recessed from the top surface to a predetermined depth. The gate connection layer GL is positioned by partially removing the adjacent gate dielectric layer 162.

[0031] A portion of the side surface of the gate connection layer GL is in contact with the sides of the second and third gate electrodes (GE2, GE3), while another portion is in contact with the separation structure DWS. In this embodiment, the upper surface of the gate connection layer GL is coplane with the upper surfaces of the second and third gate electrodes (GE2, GE3) and the lower separation structure (DWS_L), but the level of the upper surface of the gate connection layer GL is not limited to this. In this embodiment, the entire upper surface of the gate connection layer GL is covered with the gate capping layer 167. However, in one embodiment, a gate contact plug CB may also be placed on the gate connection layer GL. The lower surface of the gate connection layer GL is located at a level lower than the upper surface of the second and third gate electrodes (GE2, GE3) but higher than the lower surface. The entire lower surface of the gate connection layer GL is covered by the lower separation structure (DWS_L) and the gate dielectric layer 162.

[0032] The thickness of the gate connection layer GL is less than the thickness of the second and third gate electrodes (GE2, GE3) on the uppermost channel layer 144. In this embodiment, the gate connection layer GL is located at a level corresponding to a portion of the second and third gate electrodes (GE2, GE3). The gate connection layer GL contains a conductive material, which may include, for example, aluminum (Al), tungsten (W), or molybdenum (Mo). The gate connection layer GL contains the same material as or different from the first to fourth gate electrodes (GE1, GE2, GE3, GE4). For example, the first to fourth gate electrodes (GE1, GE2, GE3, GE4) contain tungsten (W), and the gate connection layer GL contains molybdenum (Mo). In one embodiment, the gate connection layer GL may further include barrier layers forming the bottom and side surfaces. The semiconductor element 100 includes a gate connection layer GL that connects diagonal gate electrodes, which simplifies the wiring structure, simplifies the manufacturing process, and reduces coupling capacitance and routing resistance compared to connecting via an upper wiring structure.

[0033] The first interlayer insulating layer 190 covers the source / drain region 150. The second interlayer insulating layer 192 covers the gate structure and the source contact plug CA. The third interlayer insulating layer 194 is placed on the second interlayer insulating layer 192. The first to third interlayer insulating layers (190, 192, 194) may contain at least one insulating material, such as oxides, nitrides, and oxynitrides, and may include, for example, a low dielectric constant material. Depending on the embodiment, at least one of the first to third interlayer insulating layers (190, 192, 194) may include multiple insulating layers.

[0034] The source contact plug CA is connected to the upper region of the source / drain region 150 and applies an electrical signal to the source / drain region 150. The source contact plug CA penetrates the first interlayer insulating layer 190 and the insulating liner 155. The source contact plug CA has, but is not limited to, a sloping side where the width at the bottom is narrower than the width at the top, depending on the aspect ratio. The source contact plug CA is positioned with the source / drain region 150 recessed from the top surface. The source contact plug CA extends from the top, for example, below the lower surface of the uppermost fourth channel layer 144 of the channel structure 140, but is not limited to this. The gate contact plug CB is connected to the first, third, and fourth gate electrodes (GE1, GE3, GE4) by penetrating the second interlayer insulating layer 192 and the gate capping layer 167. Since the second and third gate electrodes (GE2 and GE3) are directly connected by the gate connection layer GL, the gate contact plug CB does not need to be connected to all of the second and third gate electrodes (GE2 and GE3), but only to one of them.

[0035] The source contact plug CA and gate contact plug CB may contain conductive materials, such as metallic materials like aluminum (Al), tungsten (W), or molybdenum (Mo). Depending on the embodiment, the source contact plug CA may further include a barrier layer that comprises a metal-semiconductor compound layer located at the interface with the source / drain region 150, for example, a metal silicide layer, forming the side surface of the source contact plug CA and extending onto the upper surface of the metal-semiconductor compound layer. Similarly, the gate contact plug CB may further include a barrier layer that comprises a metal-semiconductor compound layer, such as a metal silicide layer, located at the interface with the first, third, and fourth gate electrodes (GE1, GE3, GE4), forming the side surface of the gate contact plug CB and extending onto the upper surface of the metal-semiconductor compound layer. The barrier layer may include, for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN).

[0036] The upper via VA electrically connects the source contact plug CA to the first wiring line M1. The upper via VA and the first wiring line M1 may contain at least one of the following conductive materials: tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), ruthenium (Ru), titanium (Ti), and molybdenum (Mo). Additional vias and wiring lines can be placed on the upper via VA and the first wiring line M1. In exemplary embodiments, the connection configurations of the gate contact plug CB, source contact plug CA, upper via VA, and first wiring line M1 can be varied in various ways.

[0037] In the following descriptions of embodiments, explanations that overlap with the above explanation will be omitted with reference to Figures 1 to 2c. Figures 3a and 3b are layout diagrams showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. Figure 3b further shows some of the components that make up the wiring structure in the layout diagram of Figure 3a. Figures 4a and 4b are cross-sectional views showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. Figures 4a and 4b show cross-sections of the semiconductor device shown in Figures 3a and 3b, obtained by cutting along the VI-VI' line and the VII-VII' line. Figure 5 is a circuit diagram of a semiconductor device according to an embodiment of the present invention.

[0038] Referring to Figures 3a to 5, semiconductor element 100a includes a standard cell of the multiplexer (MUX) circuit shown in Figure 5. As shown in Figure 5, the semiconductor device 100a includes first to sixth NMOS transistors (NM1, NM2, NM3, NM4, NM5, NM6) and first to sixth PMOS transistors (PM1, PM2, PM3, PM4, PM5, PM6).

[0039] The first NMOS transistor NM1 and the first PMOS transistor PM1 constitute an inverter, and a selection signal S0 is input via the gate electrode to output a complementary selection signal (S0_B). The third PMOS transistor PM3 and the fifth NMOS transistor NM5 receive the first selection signal A via their gate electrodes, while the fourth PMOS transistor PM4 and the sixth NMOS transistor NM6 receive the second selection signal B via their gate electrodes. The fifth and sixth PMOS transistors (PM5, PM6) and the third and fourth NMOS transistors (NM3, NM4) form a cross-couple circuit XC, with the source / drain regions of the third and fourth PMOS transistors (PM3, PM4) and the fifth and sixth NMOS transistors (NM5, ​​NM6) respectively connected to each other. The second NMOS transistor NM2 and the second PMOS transistor PM2 constitute an inverter, and a signal is input to the gate electrode from the cross-coupled circuit XC, outputting one of the first and second selection signals (A, B) as the output signal Y.

[0040] Unlike the embodiments shown in Figures 1 to 2c, the semiconductor element 100a does not include the substrate 101 and the active region ACT, but further includes a substrate insulating layer 103, a back insulating layer 196, a second gate connection layer GL2, a backside contact plug BCA, and a backside wiring line 180. The semiconductor element 100a further includes a gate isolation layer CT, a contact connection layer GC, first and second vias (V1, V2), and second and third wiring lines (M2, M3). The substrate insulating layer 103 is a layer formed during the manufacturing process by removing and / or oxidizing the substrate 101 and the active region ACT, which are made of semiconductor material. In this specification, the substrate insulating layer 103 is also referred to as the base structure. The rear insulating layer 196 is positioned on the underside of the substrate insulating layer 103. The substrate insulating layer 103 and the back insulating layer 196 are made of insulating material, which may include, for example, oxides, nitrides, or combinations thereof. Depending on the embodiment, at least one of the substrate insulating layer 103 and the back insulating layer 196 may include multiple insulating layers.

[0041] The first gate connection layer GL1 electrically connects the second and third gate electrodes (GE2, GE3) to each other, and the same explanation for the gate connection layer GL described above applies to this layer with reference to Figures 1 to 2c. As shown in Figures 3a and 3b, the second gate connection layer GL2 connects adjacent gate electrodes GE in a straight line from the gate electrode GE along the Y direction. In this embodiment, the second gate connection layer GL2 connects the outer gate electrodes GE of the first to fourth gate electrodes (GE1, GE2, GE3, GE4) to each other in the Y direction. The second gate connection layer GL2 is formed together with the first gate connection layer GL1, is positioned on the separation structure DWS at the same level as the first gate connection layer GL1, and contains the same material as the first gate connection layer GL1.

[0042] The backside contact plug BCA penetrates the substrate insulating layer 103 and connects to the lower surface of at least one of the source / drain regions 150. The backside contact plug BCA is positioned with a portion of the source / drain region 150 recessed from the bottom. The backside wiring line 180 is located within the backside insulation layer 196 and connects to the backside contact plug BCA. In an exemplary embodiment, additional contact plugs and wiring lines may be further arranged between the backside contact plug BCA and the backside wiring line 180. The backside wiring line 180, together with the backside contact plug (BCA), forms a backside power delivery network (BSPDN) to which power or ground voltage is applied. For example, power and ground signals are transmitted to the backside contact plug BCA in Figure 4a, and power and ground signals are also transmitted to the backside contact plug BCA located symmetrically on the left side in Figures 3a and 3b. The backside contact plugs BCA between the first to fourth gate electrodes (GE1, GE2, GE3, GE4) forming the cross-coupled circuit XC are electrically connected to each other along the Y direction. The backside contact plug BCA and backside wiring line 180 may contain conductive material, such as metallic material such as aluminum (Al), tungsten (W), or molybdenum (Mo).

[0043] The gate isolation layer (CT) is positioned at both ends of the standard cell along the Y direction to isolate the gate electrode (GE). The gate isolation layer (CT) contains insulating material and, unlike the isolation structure (DWS), is positioned at the end of a standard cell to separate only the gate electrode (GE) or gate structure from each other in the Y direction between standard cells. The contact connection layer GC connects adjacent source contact plugs CA to each other along the Y direction. The contact connection layer GC is placed on the separation structure DWS and contains a conductive material. The first via V1 connects the first wiring line M1 and the second wiring line M2, and the second via V2 connects the second wiring line M2 and the third wiring line M3. The first and second vias (V1, V2) and the second and third wiring lines (M2, M3) contain a conductive material, such as a metallic material.

[0044] The fifth and sixth PMOS transistors (PM5, PM6) and the third and fourth NMOS transistors (NM3, NM4) that form the cross-coupled circuit XC each include the first to fourth gate electrodes (GE1, GE2, GE3, GE4). The second and third gate electrodes (GE2, GE3) are directly connected via the first gate connection layer GL1, and the first and fourth gate electrodes (GE1, GE4) are electrically connected to each other via a wiring structure. Specifically, as shown in Figure 3b, the first gate electrode GE1 is electrically connected to the fourth gate electrode GE4 via the gate contact plug CB, the first wiring line M1, the first via V1, the second wiring line M2, the second via V2, the third wiring line M3, the second via V2, the second wiring line M2, the first via V1, the first wiring line M1, and the gate contact plug CB.

[0045] Unlike the first and fourth gate electrodes (GE1, GE4), semiconductor element 100a has a structure in which the connection of the second and third gate electrodes (GE2, GE3) is simplified. The semiconductor element 100a has a cross-coupled configuration within 2CPP (Contacted Poly Pitch) corresponding to the pitch of the two gate electrodes, and includes a first gate connection layer GL1 that connects the diagonally opposite gate electrodes. This simplifies the wiring structure, simplifies the manufacturing process, and reduces coupling capacitance and routing resistance. This structure of the first gate connection layer GL1 can be applied to a variety of circuits, including not only multiplexers (MUX) but also circuits with cross-coupled structures, such as flip-flop circuits.

[0046] Figures 6a and 6b are plan views showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. Figures 6a and 6b show the regions corresponding to Figure 1, respectively. Referring to Figure 6a, in semiconductor device 100b, the gate connection layer GL includes a single line pattern that connects the second gate electrode GE2 and the third gate electrode GE3 and extends in the direction of D1. The second width W2b of the gate connection layer GL is the same as, or similar to, the first width W1 of the second and third gate electrodes (GE2, GE3), but is not limited to this and can be changed in various ways depending on the embodiment.

[0047] In the gate connection layer GL, a portion of the region, including the central region along at least the X and Y directions, overlaps with the separation structure DWS in the plan view. A portion of the gate connection layer GL is located outside the separation structure DWS, without overlapping with it. The gate connection layer GL is positioned so that a portion of it overlaps with the second and third gate electrodes (GE2, GE3) in the plan view, in which case the second and third gate electrodes (GE2, GE3) are positioned in a form that is partially recessed. However, in one embodiment, the gate connection layer GL is not located in the region that overlaps with the second and third gate electrodes (GE2, GE3).

[0048] Referring to Figure 6b, in semiconductor device 100c, the gate connection layer GL includes a plurality of line patterns connecting the second gate electrode GE2 and the third gate electrode GE3 in the D1 direction. However, unlike the embodiment shown in Figure 1, in the gate connection layer GL of this embodiment, the second width W2c of the pattern connected to the second and third gate electrodes (GE2, GE3) and extended in the Y direction is smaller than the first width W1 of the second and third gate electrodes (GE2, GE3). In the gate connection layer GL, the third width W3c of the pattern extended in the X direction by connecting patterns extended in the Y direction is the same as, but not limited to, the second width W2c. As shown in the embodiments of Figures 6a and 6b, the shape, width, and placement range of the gate connection layer GL on the plan view can be varied in various ways depending on the embodiment.

[0049] Figures 7a to 7d are cross-sectional views showing the schematic configuration of a semiconductor device according to an embodiment of the present invention. Figures 7a to 7d show the regions corresponding to Figure 2b, respectively. Referring to Figure 7a, in the semiconductor device 100d, the gate connection layer GL has a shape that extends horizontally with a first length L1 toward at least one of the second and third gate electrodes (GE2, GE3). As a result, the gate connection layer GL protrudes into the second and third gate electrodes (GE2, GE3). The first length L1 can be varied in various ways depending on the embodiment.

[0050] Referring to Figure 7b, in the semiconductor device 100e, the gate connection layer GL extends upward through the gate capping layer 167. As a result, the upper surface of the gate connection layer GL is located at a higher level than the upper surfaces of the second and third gate electrodes (GE2, GE3). The upper surface of the gate connection layer GL is coplane with the upper surface of the gate capping layer 167. However, even in this case, the upper surface of the gate connection layer GL is located at a lower level than the upper surface of the gate contact plug CB. In this embodiment, the gate connection layer GL is formed after the gate capping layer 167 is formed. As a result, in this embodiment, the upper surface of the upper separation structure (DWS_U) (see Figure 2a) is located at the same level as the upper surface of the gate capping layer 167.

[0051] In one embodiment, the height H1 of the gate connection layer GL can be varied by changing the level of the upper surface of the gate connection layer GL to be the same as or lower than the level of the upper surface of the gate capping layer 167. In one embodiment, the gate connection layer GL may be in contact with or integrated with the gate contact plug CB, which is connected to the second and third gate electrodes (GE2, GE3).

[0052] Referring to Figure 7c, in semiconductor device 100f, the gate connection layer GL protrudes into the gate capping layer 167 and is positioned extending from the upper surface of the isolation structure DWS onto the upper surfaces of the second and third gate electrodes (GE2, GE3). This allows the gate connection layer GL to also be in contact with the upper surfaces of the second and third gate electrodes (GE2, GE3). Referring to Figure 7d, in semiconductor device 100g, the upper isolation structure (DWS_U) is not located below the gate connection layer GL. As a result, the gate connection layer GL includes a region that protrudes downward from the central region along the D1 direction, depending on the level of the upper surface of the lower separation structure (DWS_L). In this embodiment, the upper separation structure (DWS_U) can be manufactured without forming it in the region where the gate connection layer GL is located.

[0053] Figures 8a to 8g are diagrams illustrating the process sequence for explaining the method for manufacturing a semiconductor device according to an embodiment of the present invention. Figures 8a to 8g illustrate one embodiment of a manufacturing method for producing the semiconductor devices shown in Figures 2a to 2c. Figures 8a to 8g show cross-sections corresponding to Figure 2a, respectively.

[0054] Referring to Figure 8a, an active structure is formed on the substrate 101 in which a sacrificial layer 120 and the first to fourth channel layers (141, 142, 143, 144) are alternately stacked, and a lower separation structure (DWS_L) is formed between the active structures. The substrate 101 may contain silicon (Si), germanium (Ge), or silicon germanium (SiGe). The substrate 101 may include a bulk wafer, an epitaxial layer, an SOI (Silicon On Insulator) layer, or an SeOI (Semiconductor On Insulator) layer.

[0055] The active structure includes sacrificial layers 120 and first to fourth channel layers (141, 142, 143, 144) that are alternately stacked with respect to each other, and further includes an active region ACT formed by removing a portion of the substrate 101 so as to protrude from the substrate 101. The active structure is formed using a mask layer ML. The mask layer ML is, for example, a hard mask layer. The active structures are formed in a linear form that extends in one direction, for example, in the X direction, and are separated from each other in the Y direction. The active region (ACT) may contain further impurities. However, impurities can also be introduced in a later stage of the process.

[0056] The sacrificial layer 120 is a layer that replaces the gate dielectric layer 162 and the first to fourth gate electrodes (GE1, GE2, GE3, GE4) through subsequent processes, as shown in Figure 2a. The sacrificial layer 120 is made of a material that has etching selectivity for each of the first to fourth channel layers (141, 142, 143, and 144). The first to fourth channel layers (141, 142, 143, 144) contain a different substance from the sacrificial layer 120. The sacrificial layer 120 and the first to fourth channel layers (141, 142, 143, 144) contain a semiconductor material that includes, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge), but may also contain different materials and may or may not contain impurities. For example, the sacrificial layer 120 contains silicon germanium (SiGe), and the first to fourth channel layers (141, 142, 143, 144) contain silicon (Si). The sacrificial layer 120 and the first to fourth channel layers (141, 142, 143, 144) are formed by performing an epitaxial growth process from the substrate 101.

[0057] The lower separation structure (DWS_L) is first formed by conformally depositing an insulating material to cover the active structure, and then partially removing it, for example, by an etch-back process, so that it remains only between the active structures.

[0058] Referring to Figure 8b, the element isolation layer 110 and the sacrificial gate structure 200 are formed. The element isolation layer 110 is formed by depositing an insulating material to fill the space between the active structures, and then partially removing the deposited insulating material from the top so that at least the upper surface of the active region ACT is exposed. At this stage, the level and shape of the upper surface of the element isolation layer 110 can be changed in various ways.

[0059] The sacrificial gate structure 200 is a sacrificial structure formed on the channel structure 140 through a subsequent process, as shown in Figure 2a, in the region where the gate dielectric layer 162, the first to fourth gate electrodes (GE1, GE2, GE3, GE4), and the gate capping layer 167 are arranged. The sacrificial gate structure 200 has a linear shape that intersects with the active structure and extends in one direction. The sacrificial gate structure 200 extends, for example, in the Y direction. Each of the sacrificial gate structures 200 includes sequentially stacked first and second sacrificial gate layers (202, 205) and a mask pattern layer 206. The first and second sacrificial gate layers (202, 205) are patterned using the mask pattern layer 206.

[0060] The first and second sacrificial gate layers (202, 205) are an insulating layer and a conductive layer, respectively, but are not limited to this, and the first and second sacrificial gate layers (202, 205) may also consist of a single layer. For example, the first sacrificial gate layer 202 may contain silicon oxide, and the second sacrificial gate layer 205 may contain polysilicon. The mask pattern layer 206 may contain silicon oxide and / or silicon nitride. Outside the sacrificial gate structure 200, a portion of the mask layer ML and the lower separation structure (DWS_L) are removed during the formation of the sacrificial gate structure 200.

[0061] Referring to Figure 8c, a portion of the active structure is removed from the outside of the sacrificial gate structure 200. The sacrificial layer 120 exposed from the sacrificial gate structure 200, and the first to fourth channel layers (141, 142, 143, 144) are removed. In this stage, the active region ACT, which is exposed after the removal of the sacrificial layer 120 and the first to fourth channel layers (141, 142, 143, 144), is also partially recessed from the top surface, but is not limited to this. In this stage, the first to fourth channel layers (141, 142, 143, 144) form a channel structure 140 having a limited length along the X direction.

[0062] Referring to Figure 8d, the upper separation structure (DWS_U) is formed. A separate mask layer is formed on the overall structure under construction, and this is patterned to create an opening in the region corresponding to the upper separation structure (DWS_U) in Figure 2a. Then, the opening is filled with an insulating material, and the mask layer is removed to form the upper separation structure (DWS_U).

[0063] Referring to Figure 8e, the source / drain region 150 and the insulating liner layer 155 are formed. The source / drain region 150 is formed by growing it from the active region ACT, for example, by a selective epitaxial process. The source / drain region 150 contains impurities due to in-situ doping. The insulating liner layer 155 is conformally formed to cover the surface of the source / drain region 150 and is further formed on the upper surface of the sacrificial gate structure 200. In the embodiments shown in Figures 3a to 4b, at this stage, before forming the source / drain region 150, the placeholder layer is formed first after partially removing the active region ACT. The placeholder layer contains a semiconductor material and may have a different composition from the source / drain region 150.

[0064] Referring to Figure 8f, the first interlayer insulating layer 190 is formed, and the sacrificial layer 120 and sacrificial gate structure 200 are removed. The sacrificial layer 120 and the sacrificial gate structure 200 are selectively removed from the gate spacer layer 164, the first interlayer insulating layer 190, the source / drain region 150, and the channel structure 140. For example, if the sacrificial layer 120 contains silicon germanium (SiGe) and the channel structure 140 contains silicon (Si), the sacrificial layer 120 can be selectively removed by a wet etching process. At this stage, the mask layer ML is also removed.

[0065] Referring to Figure 8g, the gate dielectric layer 162 and the first to fourth gate electrodes (GE1, GE2, GE3, GE4) are formed, and the gate connection layer GL is formed. The gate dielectric layer 162 and the first to fourth gate electrodes (GE1, GE2, GE3, GE4) are formed in the region where the sacrificial layer 120 and the sacrificial gate structure 200 have been removed. The gate dielectric layer 162 is formed to conformally cover the surface within the above region. The first to fourth gate electrodes (GE1, GE2, GE3, GE4) are formed to completely fill the above region, and then, together with the gate dielectric layer 162 and the gate spacer layer 164, are removed from the top down to a predetermined depth by a planarization process or the like. At this stage, a portion of the upper separation structure (DWS_U) is also removed, reducing its height. The gate connection layer GL is formed by partially removing the separation structure DWS and the gate dielectric layer 162 from the top surface, and then filling the area with a conductive material.

[0066] Next, referring to Figures 2a to 2c together, a gate capping layer 167 is formed on the first to fourth gate electrodes (GE1, GE2, GE3, GE4), the gate connection layer GL, and the upper isolation structure (DWS_U), forming the source contact plug CA, gate contact plug CB, upper via VA, and the first wiring line M1. First, a source contact plug CA is formed that penetrates the gate capping layer 167 and the first interlayer insulating layer 190. After forming the second interlayer insulating layer 192, a gate contact plug CB is formed that penetrates the second interlayer insulating layer 192 and the gate capping layer 167. The upper via VA is formed on the source contact plug CA, and the first wiring line M1 is formed on the source contact plug CA and the gate contact plug CB. If there are further wiring structures to be placed on the first wiring line M1, these wiring structures are further formed at this stage. This allows for the manufacture of the semiconductor device 100 shown in Figures 1 to 2c.

[0067] In the embodiments shown in Figures 3a and 4b, the rear surface of the substrate 101 is further manufactured by performing the following steps after the above process has been completed. First, the substrate 101 and the active region ACT are removed, and the substrate insulating layer 103 is formed. Next, after removing a portion of the substrate insulating layer 103 and the placeholder layer, a conductive material is deposited to form the backside contact plug BCA. Next, a rear insulating layer 196 is formed, creating a backside wiring line 180 that connects to the backside contact plug BCA.

[0068] Furthermore, the present invention is not limited to the embodiments described above. It can be modified and implemented in various ways without departing from the technical scope of the present invention. [Explanation of Symbols]

[0069] 101 circuit board 105 Active region 110-element isolation layer 140 Channel Structures Channel layers 141, 142, 143, and 144 (1st to 4th) 150 Source / Drain Area 155 Insulating Liner 162 Gate Dielectric Layer 164 Gate Spacer Layer 167 Gate capping layer 190, 192, 194 (1st to 3rd) Interlayer Insulation Layers ACT active region CA Source Contact Plug CB Gate Contact Plug DWS separation structure DWS_L Lower separation structure DWS_U Upper separation structure GE1, GE2, GE3, GE4 (1st to 4th) Gate GL gate connection layer M1 First Wiring Line VA upper via

Claims

1. A base structure extending in the first direction, On the base structure, a plurality of gate electrodes are provided, extending in a second direction perpendicular to the first direction and spaced apart from each other in the first and second directions, On the base structure, there are a plurality of channel layers spaced apart from each other along a third direction perpendicular to the upper surface of the base structure and surrounded by each of the gate electrodes, On both sides of the gate electrode, there are source / drain regions connected to the plurality of channel layers, A separation structure extending along the first direction separates each of the plurality of gate electrodes, the plurality of channel layers, and the source / drain regions that are adjacent to each other along the second direction, A semiconductor element characterized by electrically connecting a first gate electrode and a second gate electrode, which are separated from each other in a fourth direction intersecting the first and second directions among the plurality of gate electrodes, and having a gate connection layer that contacts the upper surface of the separation structure on the separation structure.

2. The semiconductor element according to claim 1, characterized in that the lower surface of the gate connection layer is located at a level lower than the upper surface of the gate electrode and higher than the lower surface.

3. The gate electrode further comprises a gate contact plug electrically connected to the gate electrode, The semiconductor element according to claim 1, characterized in that the upper surface of the gate connection layer is located at a lower level than the upper surface of the gate contact plug.

4. The aforementioned terminal is, The first and second gate electrodes, The invention further includes a third gate electrode and a fourth gate electrode, which are separated by the separation structure along the second direction, The semiconductor element according to claim 1, characterized in that the gate connection layer is separated from the third and fourth gate electrodes in the second direction.

5. The gate electrode further comprises a gate contact plug, a first wiring line, a via, and a second wiring line, which are sequentially arranged on the gate electrode. The semiconductor element according to claim 4, characterized in that the third and fourth gate electrodes are electrically connected to each other via the gate contact plug, the first wiring line, the via, and the second wiring line.

6. The semiconductor element according to claim 1, characterized in that the upper surface of the gate connection layer is coplane with the upper surface of the gate electrode.

7. A first gate electrode and a second gate electrode that are separated from each other in a first direction, A third gate electrode and a fourth gate electrode that are separated from each other in the first direction and separated from the first and second gate electrodes, respectively, in a second direction perpendicular to the first direction, A separation structure extending in the first direction between the first and third gate electrodes and between the second and fourth gate electrodes, Source / drain regions are arranged on both sides of the first gate electrodes along the first direction and are separated from each other in the second direction by the separation structure, A semiconductor element characterized by having a gate connection layer on the separation structure that contacts the second and third gate electrodes via their sides and electrically connects the second gate electrode and the third gate electrode.

8. The aforementioned separation structure is A lower separation structure provided between the first and third gate electrodes and between the second and fourth gate electrodes, The semiconductor element according to claim 7, further comprising an upper separation structure extending between the source / drain regions on the lower separation structure.

9. A plurality of gate structures including a gate dielectric layer, a gate electrode, and a gate capping layer, which are spaced apart from each other in a first direction and a second direction perpendicular to the first direction, and are stacked sequentially, A plurality of channel layers, separated from each other along a third direction perpendicular to the first and second directions and surrounded by each of the gate structures, On both sides of the gate structure, source / drain regions connected to the plurality of channel layers, A separation structure extending along the first direction separates each of the gate structures, the plurality of channel layers, and the source / drain regions that are adjacent to each other along the second direction, A semiconductor element characterized by having a gate connection layer on the separation structure that contacts the gate capping layer and electrically connects a first gate electrode and a second gate electrode that are separated from each other in a fourth direction that intersects the first and second directions of the gate electrode.

10. The semiconductor element according to claim 9, characterized in that the upper surface of the gate connection layer is located at the same level as, or lower than, the upper surface of the gate capping layer.

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