Multilayer ceramic capacitor

Abstract

One embodiment of the present invention aims to provide a multilayer ceramic capacitor that can prevent a decrease in insulation resistance. [Solution] A multilayer ceramic capacitor according to one embodiment of the present invention includes a body containing a plurality of internal electrodes stacked with a dielectric layer in between, and an external electrode disposed outside the body and connected to the plurality of internal electrodes, wherein the external electrode includes a first plating layer, the average ratio of the major axis to the minor axis of the crystal grains of the first plating layer is 1:1 or more and 3:1 or less, and the coefficient of variation of the thickness of the first plating layer may be 11.7% or more and 15.9% or less.

Description

[Technical Field]

[0001] This disclosure relates to multilayer ceramic capacitors. [Background technology]

[0002] Electronic components that use ceramic materials include capacitors, inductors, piezoelectric elements, varistors, and thermistors. Among these ceramic electronic components, multilayer ceramic capacitors (MLCCs) can be used in a wide variety of electronic devices due to their advantages of being small, having guaranteed high capacitance, and being easy to mount.

[0003] A multilayer ceramic capacitor may include a body containing multiple dielectric layers and multiple internal electrodes, and external electrodes positioned outside the body and connected to the internal electrodes. If hydrogen generated during the plating process penetrates into the interior of the multilayer ceramic capacitor, the insulation resistance may decrease. Furthermore, techniques are required to improve the thickness variations and surface roughness of the plating layers. [Overview of the project] [Problems that the invention aims to solve]

[0004] One embodiment of the present invention aims to provide a multilayer ceramic capacitor that can prevent a decrease in insulation resistance.

[0005] Another embodiment of the present invention aims to provide a multilayer ceramic capacitor that can improve the thickness variation and surface roughness of the plating layer. [Means for solving the problem]

[0006] A multilayer ceramic capacitor according to one embodiment of the present invention includes a body containing a plurality of internal electrodes stacked with a dielectric layer in between, and an external electrode disposed outside the body and connected to the plurality of internal electrodes, wherein the external electrode includes a first plating layer, the average ratio of the major axis to the minor axis of the crystal grains of the first plating layer is 1:1 to 3:1, and the coefficient of variation of the thickness of the first plating layer may be 11.7% or more and 15.9% or less.

[0007] The average thickness of the first plating layer may be between 1.806 μm and 2.2362 μm.

[0008] The standard deviation of the thickness of the first plating layer may be 0.24 or more and 0.35 or less.

[0009] The first plating layer may contain nickel (Ni).

[0010] The major axis may indicate the maximum diameter of the crystal grain, and the minor axis may indicate the maximum diameter measured in a direction perpendicular to the measurement direction of the major axis.

[0011] The external electrode may further include a second plating layer disposed on the first plating layer.

[0012] The second plating layer may contain tin (Sn).

[0013] The external electrode may further include an electrode layer disposed between the body and the first plating layer and connected to the internal electrode.

[0014] A multilayer ceramic capacitor according to an embodiment of the present invention includes a body including a plurality of internal electrodes laminated with a dielectric layer interposed therebetween, and an external electrode disposed outside the body and connected to the plurality of internal electrodes. The external electrode includes a first plating layer, the average ratio of the major diameter to the minor diameter of the crystal grains of the first plating layer is from 1:1 to 3:1, and the surface roughness Ra of the first plating layer may be 1.51 μm or more and 1.86 μm or less.

[0015] The first plating layer may contain nickel (Ni).

[0016] The major diameter indicates the maximum diameter of the crystal grains, and the minor diameter may indicate the maximum diameter measured in a direction perpendicular to the measurement direction of the major diameter.

[0017] The external electrode may further include a second plating layer disposed on the first plating layer.

[0018] The second plating layer may contain tin (Sn).

[0019] The external electrode may further include an electrode layer disposed between the body and the first plating layer and connected to the internal electrode.

[0020] According to the multilayer ceramic capacitor according to the embodiment of the present invention, it is possible to prevent a decrease in insulation resistance by adjusting the ratio of the major diameter to the minor diameter of the crystal grains of the plating layer of the external electrode.

[0021] Further, according to the multilayer ceramic capacitor according to the embodiment, it is possible to improve the thickness variation and surface roughness of the plating layer by adjusting the ratio of the major diameter to the minor diameter of the crystal grains of the plating layer of the external electrode.

Brief Description of the Drawings

[0022] [Figure 1] FIG. 1 is a perspective view schematically showing a multilayer ceramic capacitor according to an embodiment. [Figure 2]FIG. 2 is a separated perspective view schematically showing the laminated structure of the internal electrodes of the multilayer ceramic capacitor of FIG. 1. [Figure 3] FIG. 3 is a plan view schematically showing the first internal electrode of the multilayer ceramic capacitor of FIG. 1. [Figure 4] FIG. 4 is a plan view schematically showing the second internal electrode of the multilayer ceramic capacitor of FIG. 1. [Figure 5] FIG. 5 is a cross-sectional view taken along the line I-I' of FIG. 1. [Figure 6] FIG. 6 is a cross-sectional view taken along the line II-II' of FIG. 1. [Figure 7] FIG. 7 is an enlarged partial cross-sectional view of the region A of FIG. 5. [Figure 8] FIG. 8 is a schematic diagram showing a current application profile by a direct current (DC) plating method. [Figure 9] FIG. 9 is a schematic diagram showing a current application profile by a periodic pulse reverse (PPR) plating method. [Figure 10] FIG. 10 is an electron micrograph of the first plating layer formed by the PPR plating method. [Figure 11] FIG. 11 is an electron micrograph of the first plating layer formed by the DC plating method. [Figure 12] FIG. 12 is a schematic diagram showing a plating layer smoothing process by the PPR plating method. [Figure 13] FIG. 13 is a graph showing the results of evaluating the insulation resistance reliability at high temperature for the multilayer ceramic capacitors according to the examples and comparative examples. [Figure 14] FIG. 14 is a graph showing the results of evaluating the thickness uniformity of the plating layer for the multilayer ceramic capacitors according to the examples and comparative examples.

MODE FOR CARRYING OUT THE INVENTION

[0023] Embodiments of the present invention will be described in detail below with reference to the attached drawings, so that they can be easily implemented by a person with ordinary skill in the art to which the present invention pertains. In the drawings, unnecessary parts have been omitted in order to clearly illustrate the present invention, and the same or similar components are denoted by the same reference numerals throughout the specification. In addition, some components in the attached drawings are exaggerated, omitted, or shown schematically, and the size of each component does not fully reflect its actual size.

[0024] The accompanying drawings are provided solely to facilitate understanding of the embodiments disclosed herein, and should not be understood as limiting the technical ideas disclosed herein, and should be understood to include any modifications, equivalents, or substitutions that fall within the concept and scope of the invention.

[0025] Terms including ordinal numbers, such as "first," "second," etc., can be used to describe a variety of components, but the components are not limited by such terms. These terms are used solely for the purpose of distinguishing one component from another.

[0026] Furthermore, when we say that a layer, membrane, region, plate, or other part is "on top of" another part, this includes not only the case where it is "directly above" the other part, but also the case where the other part is in between. Conversely, when we say that one part is "directly above" another part, it means that there is no other part in between. Also, being "on top of" a reference part means being located above or below the reference part, and does not necessarily mean being located "above" in the opposite direction of gravity.

[0027] Throughout the specification, terms such as “includes” or “have” are intended to specify the presence of features, figures, steps, actions, components, parts, or combinations thereof described in the specification, and should not be understood to preemptively exclude the presence or possibility of adding one or more other features, figures, steps, actions, components, parts, or combinations thereof. Therefore, when a part “includes” a component, this means that, unless otherwise stated, it does not exclude other components and may further include other components.

[0028] Furthermore, throughout the specification, "on a plane" refers to the view of the part in question from above, and "on a cross-section" refers to the view of the cross-section of the part in question, obtained by cutting it perpendicularly, from the side.

[0029] Furthermore, throughout the specification, the term "connected" does not only mean that two or more components are directly connected, but may also mean that two or more components are indirectly connected through other components, that they are not only physically connected but also electrically connected, or that they are a single unit, even though they are referred to by different names depending on their location or function.

[0030] Figure 1 is a schematic perspective view showing a multilayer ceramic capacitor according to one embodiment.

[0031] Referring to Figure 1, the multilayer ceramic capacitor 1000 according to this embodiment includes a body 110, a first external electrode 200, and a second external electrode 300.

[0032] First, to clearly explain this embodiment, the directions are defined as follows: the L-axis, W-axis, and T-axis shown in the drawing represent the first, second, and third directions of the multilayer ceramic capacitor 1000, respectively.

[0033] The first direction (L-axis direction) is a direction parallel to the broad surface (main surface) of the sheet-shaped component and may intersect (or be perpendicular to) the third direction (T-axis direction). For example, the first direction (L-axis direction) may be the direction in which the first external electrode 200 and the second external electrode 300 face each other. Hereafter, for the sake of explanation, the "first direction" will be referred to as the "length direction".

[0034] The second direction (W-axis direction) is a direction parallel to the wide surface (main surface) of the sheet-shaped component, and may intersect (or be perpendicular to) the first direction (L-axis direction) and the third direction (T-axis direction) simultaneously. For the sake of explanation, the "second direction" will be referred to as the "width direction" below.

[0035] The third direction (T-axis direction) may be perpendicular to the broad surface (main surface) of the sheet-shaped component. For example, the third direction (T-axis direction) can be used with the same concept as the direction in which the dielectric layer 140 is stacked. Hereafter, for the sake of explanation, the "third direction" will be referred to as the "thickness direction".

[0036] The body 110 may be approximately hexahedral in shape, but this embodiment is not limited to this. Due to shrinkage during sintering, the body 110 may not be a perfect hexahedron, but may have a substantially hexahedral shape. For example, the body 110 may be approximately a right hexahedron, but the corners and vertices may have a rounded shape.

[0037] In this embodiment, for the sake of explanation, the surfaces of the body 110 that face each other in the longitudinal direction (L-axis direction) are defined as the first surface S1 and the second surface S2, the surfaces of the body 110 that face each other in the width direction (W-axis direction) and connect the first surface S1 and the second surface S2 are defined as the third surface S3 and the fourth surface S4, and the surfaces of the body 110 that face each other in the thickness direction (T-axis direction) and connect the first surface S1 and the second surface S2 are defined as the fifth surface S5 and the sixth surface S6.

[0038] Therefore, the first direction, which is the direction in which the first surface S1 and the second surface S2 face each other, may be the length direction (L-axis direction), and the second and third directions, which are perpendicular to the first direction and perpendicular to each other, may be the thickness direction (T-axis direction) and the width direction (W-axis direction) or the width direction (W-axis direction) and the thickness direction (T-axis direction), respectively.

[0039] The length of body 110 may represent the maximum length of a plurality of line segments parallel to the length direction (L-axis direction), based on an optical microscope or scanning electron microscope (SEM) photograph of the cross section of body 110 in the length direction (L-axis direction) - thickness direction (T-axis direction) at the center of the width direction (W-axis direction) of body 110, by connecting the two outermost boundary lines facing each other in the length direction (L-axis direction) as shown in the aforementioned cross section photograph. On the other hand, the length of body 110 may represent the minimum length of a plurality of line segments parallel to the length direction (L-axis direction), by connecting the two outermost boundary lines facing each other in the length direction (L-axis direction) as shown in the aforementioned cross section photograph.

[0040] On the other hand, the length of body 110 may mean the arithmetic mean of the lengths of at least two line segments parallel to the length direction (L-axis direction) of body 110, which connects the two outermost boundary lines facing each other in the length direction (L-axis direction) of body 110 as shown in the aforementioned cross-sectional photograph.

[0041] The thickness of body 110 may represent the maximum length of a plurality of line segments parallel to the thickness direction (T-axis direction), obtained by connecting the two outermost boundary lines opposite to the thickness direction (T-axis direction) of body 110 as shown in the aforementioned cross-sectional photograph of body 110 in the length direction (L-axis direction) - thickness direction (T-axis direction), based on an optical microscope or scanning electron microscope (SEM) photograph of the cross-section of body 110 in the width direction (W-axis direction). On the other hand, the thickness of body 110 may represent the minimum length of a plurality of line segments parallel to the thickness direction (T-axis direction), obtained by connecting the two outermost boundary lines opposite to the thickness direction (T-axis direction) of body 110 as shown in the aforementioned cross-sectional photograph.

[0042] On the other hand, the thickness of body 110 can mean the arithmetic mean of the lengths of at least two line segments that connect the two outermost boundary lines of body 110 that are opposite to each other in the thickness direction (T-axis direction) as shown in the aforementioned cross-sectional photograph, and are parallel to the thickness direction (T-axis direction).

[0043] The width of body 110 may represent the maximum length of a plurality of line segments parallel to the width direction (W-axis direction), obtained by connecting the two outermost boundary lines of body 110 facing each other in the width direction (W-axis direction) as shown in the aforementioned cross-sectional photograph of body 110 in the length direction (L-axis direction) - width direction (W-axis direction), based on an optical microscope or scanning electron microscope (SEM) photograph of the cross-section of body 110 in the length direction (L-axis direction) - width direction (W-axis direction), as shown in the aforementioned cross-sectional photograph. On the other hand, the width of body 110 may represent the minimum length of a plurality of line segments parallel to the width direction (W-axis direction), obtained by connecting the two outermost boundary lines of body 110 facing each other in the width direction (W-axis direction), as shown in the aforementioned cross-sectional photograph. On the other hand, the width of body 110 may represent the arithmetic mean of the lengths of at least two line segments parallel to the width direction (W-axis direction), obtained by connecting the two outermost boundary lines of body 110 facing each other in the width direction (W-axis direction), as shown in the aforementioned cross-sectional photograph.

[0044] FIG. 2 is a separated perspective view schematically showing the laminated structure of the internal electrodes of the multilayer ceramic capacitor of FIG. 1, FIG. 3 is a plan view schematically showing the first internal electrode of the multilayer ceramic capacitor of FIG. 1, and FIG. 4 is a plan view schematically showing the second internal electrode of the multilayer ceramic capacitor of FIG. 1. FIG. 5 is a cross-sectional view taken along the line I-I' of FIG. 1, and FIG. 6 is a cross-sectional view taken along the line II-II' of FIG. 1.

[0045] Referring to FIGS. 2, 3, 4, 5, and 6, the body 110 can include a plurality of dielectric layers 140, a first internal electrode 150, and a second internal electrode 160.

[0046] The plurality of dielectric layers 140 are laminated in the thickness direction (T-axis direction) of the body 110. The boundaries between the dielectric layers 140 may be unclear. For example, the boundaries between the dielectric layers 140 are difficult to confirm without using a scanning electron microscope (SEM), and the plurality of dielectric layers 140 may appear as an integral structure.

[0047] The dielectric layer 140 can include a ceramic material. For example, the ceramic material can include a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Further, these components can further include auxiliary components such as manganese (Mn) compounds, iron (Fe) compounds, chromium (Cr) compounds, cobalt (Co) compounds, nickel (Ni) compounds, etc. For example, the dielectric layer is (Ba 1-y , 1-y , y , x , y Ca x )TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1) or Ba(Ti 1-y Zr y)There are O3 (0 < y < 1), etc., but the present invention is not limited thereto.

[0048] The dielectric layer 140 can further contain one or more of a ceramic additive, an organic solvent, a plasticizer, a binder, and a dispersant. The ceramic additive may be, for example, a transition metal oxide or carbide, a rare earth element, magnesium (Mg), aluminum (Al), or the like.

[0049] The first internal electrode 150 and the second internal electrode 160 may be alternately laminated with the dielectric layer 140 interposed therebetween. Such a laminated structure may be repeated within the body 110, and the internal electrode closest to the fifth surface S5 of the body 110 may be the first internal electrode 150 or the second internal electrode 160. Similarly, the internal electrode closest to the sixth surface S6 of the body 110 may be the first internal electrode 150 or the second internal electrode 160.

[0050] The first internal electrode 150 and the second internal electrode 160 have different polarities from each other, but can be electrically insulated from each other by the dielectric layer 140 disposed therebetween.

[0051] The first internal electrode 150 and the second internal electrode 160 may be formed by printing a conductive paste containing a metal on the surface of the dielectric layer 140. For example, a conductive paste containing nickel (Ni) or a nickel (Ni) alloy can be printed on the surface of the dielectric layer by a screen printing method or a gravure printing method to form an internal electrode. However, the present embodiment is not limited thereto.

[0052] When a voltage is applied to the first external electrode 200 and the second external electrode 300, charge accumulates between the first internal electrode 150 and the second internal electrode 160. In other words, capacitance can be obtained between the first internal electrode 150, which is electrically connected to the first external electrode 200, and the second internal electrode 160, which is electrically connected to the second external electrode 300. The capacitance of the multilayer ceramic capacitor 1000 is proportional to the overlapping area of ​​the first internal electrode 150 and the second internal electrode 160, which overlap each other along the thickness direction (T-axis direction).

[0053] Referring to Figures 5 and 6, a first cover layer 143 and a second cover layer 145 may be arranged on the outermost part of the body 110 in the thickness direction (T-axis direction).

[0054] The first cover layer 143 is positioned between the fifth surface S5 of the body 110 and the closest internal electrode. The second cover layer 145 is positioned between the sixth surface S6 of the body 110 and the closest internal electrode.

[0055] In other words, the first cover layer 143 may be placed on top of the uppermost internal electrode within the body 110, and the second cover layer 145 may be placed on top of the lowermost internal electrode. The first cover layer 143 and the second cover layer 145 may have the same composition as the dielectric layer 140. The first cover layer 143 and the second cover layer 145 can be formed by laminating one or more dielectric layers on the outer surface of the uppermost internal electrode and the outer surface of the lowermost internal electrode, respectively. On the other hand, the first cover layer 143 and the second cover layer 145 may have a different composition from the dielectric layer 140.

[0056] The first cover layer 143 and the second cover layer 145 can serve to prevent damage to the first internal electrode 150 and the second internal electrode 160 due to physical or chemical stress.

[0057] The first external electrode 200 and the second external electrode 300 are positioned outside the body 110.

[0058] The first external electrode 200 is positioned on the first surface S1 of the body 110 and may extend to the third surface S3, fourth surface S4, fifth surface S5, and sixth surface S6. The second external electrode 300 is positioned on the second surface S2 of the body 110 and may extend to the third surface S3, fourth surface S4, fifth surface S5, and sixth surface S6. In other embodiments, the first external electrode 200 and the second external electrode 300 may extend to a portion of at least one surface of the fifth surface S5 and sixth surface S6.

[0059] The first external electrode 200 may include a first electrode layer 120, a first plating layer 180, and a second plating layer 182.

[0060] The first electrode layer 120 includes a first connecting portion 121, a first band portion 123, and a first corner portion 125.

[0061] The first connection portion 121 covers the first surface S1 of the body 110 and is connected to a plurality of first internal electrodes 150, thereby being electrically coupled.

[0062] In other embodiments, the first connecting portion 121 can cover a portion of the first surface S1 of the body 110.

[0063] The first band portion 123 extends from the first connecting portion 121 and covers at least a portion of the third surface S3, fourth surface S4, fifth surface S5, and sixth surface S6 of the body 110. The first band portion 123 can be used to further secure the first electrode layer 120 to the body 110.

[0064] The first corner portion 125 may be the portion that connects the first connecting portion 121 and the first band portion 123.

[0065] The second external electrode 300 may include a second electrode layer 130, a third plating layer 190, and a fourth plating layer 192.

[0066] The second electrode layer 130 includes a second connecting portion 131, a second band portion 133, and a second corner portion 135.

[0067] The second connection portion 131 covers the second surface S2 of the body 110 and is connected to a plurality of second internal electrodes 160, thereby being electrically connected.

[0068] In other embodiments, the second connecting portion 131 can cover a portion of the second surface S2 of the body 110.

[0069] The second band portion 133 extends from the second connecting portion 131 and covers at least a portion of the third surface S3, fourth surface S4, fifth surface S5, and sixth surface S6 of the body 110. The second band portion 133 can be used to further secure the second electrode layer 130 to the body 110.

[0070] The second corner portion 135 may be the portion that connects the second connecting portion 131 and the second band portion 133.

[0071] Based on an optical microscope or scanning electron microscope (SEM) photograph of the cross section of the multilayer ceramic capacitor 1000 in the length direction (L-axis direction) - thickness direction (T-axis direction) at the center in the width direction (W-axis direction), the first connection portion 121 and the second connection portion 131 of the multilayer ceramic capacitor 1000 shown in the aforementioned cross section photograph may have a shape approximately parallel to the thickness direction (T-axis direction), the first band portion 123 and the second band portion 133 may have a shape approximately parallel to the length direction (L-axis direction), and the first corner portion 125 and the second corner portion 135 may have a curved shape. The aforementioned curved shape may also be a curved shape having a tangent whose slope changes in the direction parallel to the thickness direction (T-axis direction) in the direction parallel to the length direction (L-axis direction) (or in the opposite direction).

[0072] The first electrode layer 120 and the second electrode layer 130 are formed on conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), chromium (Cr), titanium (Ti), or alloys thereof, but are not limited to these.

[0073] As another example, the first electrode layer 120 and the second electrode layer 130 may include metal and glass. The metal may be a conductive metal including, for example, copper (Cu), nickel (Ni), tin (Sn), palladium (Pd), platinum (Pt), gold (Au), silver (Ag), tungsten (W), titanium (Ti), lead (Pb), or alloys thereof. The glass component included in the electrode layer may be a composition of mixed oxides. The glass component may include, for example, silicon oxide, boron oxide, aluminum oxide, transition metal oxide, alkali metal oxide, alkaline earth metal oxide, or combinations thereof. Here, the transition metal may be selected from zinc (Zn), titanium (Ti), copper (Cu), vanadium (V), manganese (Mn), iron (Fe), or nickel (Ni); the alkali metal may be selected from lithium (Li), sodium (Na), or potassium (K); and the alkaline earth metal may be selected from magnesium (Mg), calcium (Ca), strontium (Sr), or barium (Ba). The method for forming such an electrode layer is not particularly limited. For example, it can be formed by dipping the body into a conductive paste containing metal and glass, or by printing the conductive paste onto the surface of the body using screen printing or gravure printing. In addition, various methods can be used, such as coating the surface of the body with the conductive paste, or transferring a dried film of the conductive paste to a laminate.

[0074] The first plating layer 180 can cover the first electrode layer 120, and the second plating layer 182 can cover the first plating layer 180. The first plating layer 180 may contain nickel (Ni), and the second plating layer 182 may contain tin (Sn).

[0075] The third plating layer 190 can cover the second electrode layer 130, and the fourth plating layer 192 can cover the third plating layer 190. The third plating layer 190 may contain nickel (Ni), and the fourth plating layer 192 may contain tin (Sn). The third plating layer 190 and the fourth plating layer 192 correspond to the first plating layer 180 and the second plating layer 182, except for their positions, so the following description will focus on the first plating layer 180 and the second plating layer 182.

[0076] The average ratio of the major axis to the minor axis of the crystal grains in the first plating layer 180 may be between 1:1 and 3:1. In this case, the effect of hydrogen, which is inevitably generated during the plating process, can be minimized, thereby improving the insulation resistance.

[0077] If the average ratio of the major axis to the minor axis of the crystal grains in the first plating layer 180 exceeds 3:1, the hydrogen penetration suppression effect of the first plating layer 180 may be insufficient. On the other hand, since the major axis of the crystal grains represents the maximum diameter of the crystal grains, the minimum value (i.e., lower limit) of the average ratio of the major axis to the minor axis of the crystal grains is 1:1.

[0078] The major axis of a crystal grain refers to the maximum diameter that penetrates the interior of the crystal grain, while the minor axis refers to the maximum diameter measured perpendicular to the direction in which the major axis is measured. However, if there are two or more maximum diameters of the same length that penetrate the interior of a crystal grain, one of them can be considered the major axis, and the minor axis can be measured in the same way as described above.

[0079] Figure 7 is an enlarged partial cross-sectional view of region A in Figure 5.

[0080] Referring to Figure 7, the average ratio L1:L2 of the major axis to minor axis of the crystal grain G can be determined by measuring the major axis L1, which is the maximum diameter penetrating the interior of the crystal grain G of the first plating layer 180, and the minor axis L2, which is the maximum diameter measured in a direction perpendicular to the measurement direction of the major axis L1.

[0081] Here, the major and minor axes of the crystal grains can be determined by scanning a cross-section of the multilayer ceramic capacitor in the length direction (L-axis direction) - thickness direction (T-axis direction) at the center of the width direction (W-axis direction) using a scanning electron microscope (SEM). After taking 10 crystal grains in order from the largest crystal grain of the first plating layer shown in the aforementioned cross-sectional photograph and measuring their major and minor axes, the average ratio of the major and minor axes of the crystal grains can be determined by calculating the arithmetic mean of the ratio of the major and minor axes.

[0082] Figure 8 is a schematic diagram showing the current application profile of the DC (direct current) plating method.

[0083] Referring to Figure 8, during the manufacturing process of a multilayer ceramic capacitor, when nickel (Ni) and / or tin (Sn) plating is applied to the external electrodes, a constant current is applied for a predetermined time. In this case, hydrogen generated during the plating reaction continuously penetrates the interior of the multilayer ceramic capacitor for the duration of the plating, which leads to a problem of deterioration in insulation resistance.

[0084] Figure 9 is a schematic diagram showing the current application profile for a pulse periodic reverse current (PPR) plating process, which is a current generated by repeatedly performing forward and reverse electrolysis in a short period of time so that the direction of the current periodically changes to a pulsed waveform.

[0085] Referring to Figure 9, hydrogen can be adsorbed during the forward current application time when plating is performed, but the adsorbed hydrogen is desorbed during the reverse current application time, preventing hydrogen from easily penetrating the interior of the multilayer ceramic capacitor during the plating process. Therefore, hydrogen accumulation may be reduced compared to when the DC plating method is applied.

[0086] Figure 10 is an electron microscope image of the first plating layer formed by the PPR plating method, and Figure 11 is an electron microscope image of the first plating layer formed by the DC plating method.

[0087] Referring to Figure 10, the first plating layer 180 formed by applying the PPR plating method has round crystal grains. Referring to Figure 11, the first plating layer 180' formed by applying the DC plating method has pointed, needle-shaped crystal grains. In other words, the ratio of the major axis L1 to the minor axis L2 of the crystal grains shown in Figure 10 is smaller than the ratio of the major axis L1' to the minor axis L2' of the crystal grains shown in Figure 11.

[0088] The following describes the conditions for PPR plating. As shown in Figure 9, PPR plating involves forward current and reverse current, and the waveform may include one or more reverse currents. Since the PPR plating method includes one or more reverse currents, it always includes a hydrogen desorption process. Therefore, the PPR plating method can suppress hydrogen accumulation during the plating process more effectively than the DC plating method.

[0089] The process of forming the first plating layer may be barrel plating, and the barrel rotation speed may be between 5 rpm and 30 rpm. If the barrel rotation speed is less than 5 rpm or more than 30 rpm, the tips may stick together or problems may arise with variations in the thickness of the plating layer. The forward current density may be between 0.5 ASD and 20 ASD, and the reverse current density may be between 0.1 ASD and 20 ASD.

[0090] The ratio Tf / Tr, which is the ratio of the application time Tf of the forward current to the application time Tr of the reverse current, may be between 2 and 50. If the ratio Tf / Tr is less than 2, the problem of external electrode disappearance may occur, and if the ratio Tf / Tr exceeds 50, the effect of suppressing hydrogen turbulence may be insufficient.

[0091] On the other hand, the strength of the reverse current may be greater than the strength of the forward current.

[0092] In this embodiment, by forming the first plating layer in a manner that satisfies the aforementioned conditions, the crystal grain shape of the first plating layer can be controlled, thereby ensuring high-temperature reliability by suppressing hydrogen penetration.

[0093] Referring to Figure 9, PPR plating may be performed continuously until the plating is complete, or without a separate off-time during which the current is set to "0" until the plating is complete.

[0094] The average thickness of the first plating layer 180 may be between 1.806 μm and 2.2362 μm.

[0095] If the average thickness of the first plating layer 180 is less than 1.806 μm, the plating layer may break, leading to a deterioration in reliability. If it exceeds 2.2362 μm, the size of the multilayer ceramic capacitor may exceed the specified limit.

[0096] Here, the average thickness of the first plating layer can be determined by scanning an image of the cross-section of the multilayer ceramic capacitor in the length direction (L-axis direction) - thickness direction (T-axis direction) at the center in the width direction (W-axis direction) using a scanning electron microscope (SEM). The average thickness of the first plating layer can be measured by calculating the arithmetic mean of the thickness measured at 10 equally spaced points in the first plating layer shown in the aforementioned cross-sectional photograph.

[0097] The standard deviation of the thickness of the first plating layer 180 may be between 0.24 and 0.35. The standard deviation of the thickness of the first plating layer 180 can be derived from the average thickness of the first plating layer as described above.

[0098] If the standard deviation of the thickness of the first plating layer 180 exceeds 0.35, the size deviation of the multilayer ceramic capacitor will increase, resulting in insufficient quality consistency, or the size of the multilayer ceramic capacitor may exceed the specified limit.

[0099] The coefficient of variation (CV) of the thickness of the first plating layer 180 may be between 11.7% and 15.9%. Here, the coefficient of variation of thickness means the value obtained by dividing the standard deviation of thickness by the arithmetic mean of thickness.

[0100] If the coefficient of variation of the thickness of the first plating layer 180 exceeds 15.9%, the size deviation of the multilayer ceramic capacitor will increase, resulting in insufficient quality consistency, or the size of the multilayer ceramic capacitor may exceed the specified limit.

[0101] On the other hand, the surface roughness Ra of the first plating layer 180 may be 1.51 μm or more and 1.86 μm or less.

[0102] If the surface roughness of the first plating layer 180 is less than 1.51 μm, the bonding strength between the plating layers may be insufficient, and if it exceeds 1.86 μm, non-uniformity of the plating layers may occur when additional plating layers are formed.

[0103] Here, the surface roughness of the first plating layer can be determined by scanning an image of the cross-section of the multilayer ceramic capacitor in the length direction (L-axis direction) - thickness direction (T-axis direction) at the center of the width direction (W-axis direction) using a scanning electron microscope (SEM). The value may include the minimum and maximum surface roughness measured at 10 equally spaced points on the first plating layer shown in the aforementioned cross-sectional photograph.

[0104] Figure 12 is a schematic diagram showing the process of smoothing the plating layer by PPR plating.

[0105] Referring to Figure 12, the protrusions P generated by the forward current (Forward(+)) on the first plating layer 180 covering the first electrode layer 120 are etched by the reverse current (Reverse(-)) and changed into smaller protrusions P', thereby smoothing the surface of the first plating layer 180.

[0106] The following are specific embodiments of this disclosure. However, the embodiments described below are merely illustrative or explanatory of the invention and should not limit the scope of the invention.

[0107] [Manufacturing example: Manufacturing of multilayer ceramic capacitors] (Examples) A paste containing barium titanate (BaTiO3) powder was applied to a carrier film and then dried to produce multiple dielectric green sheets.

[0108] A conductive paste containing nickel (Ni) was applied onto a dielectric green sheet using screen printing to form a conductive paste layer.

[0109] A dielectric green sheet laminate was manufactured by stacking multiple dielectric green sheets so that at least a portion of the conductive paste layer overlapped.

[0110] After cutting the dielectric green sheet laminate into individual chips, the binder was removed by maintaining the chips at 350°C for 66 hours in an air atmosphere, and then the bodies were manufactured by firing at 1165°C.

[0111] A paste containing glass frit and copper (Cu) was applied to the outer surface of the body by dipping, dried, and then sintered to form an electrode layer.

[0112] A first plating layer was formed by nickel (Ni) plating on the electrode layer using PPR plating. Subsequently, the multilayer ceramic capacitor was manufactured by heat treatment at 160°C for 2 hours.

[0113] To confirm the crystal grain shape of the first plating layer of the multilayer ceramic capacitor according to an embodiment of the present invention, specimens were prepared so that the cross-section in the length direction (L-axis direction) and thickness direction (T-axis direction) was exposed. Next, the surface of the specimens was etched with a Focused Ion Beam (FIB), and then the major and minor axes of the crystal grains of the first plating layer were measured using a scanning electron microscope (SEM) with 30KV, 50,000x magnification, and SE MODE. Ten crystal grains were selected in descending order of size, and the major and minor axes of these ten crystal grains were measured. The arithmetic mean of the ratio of major to minor axes was then taken and is shown in Table 1.

[0114] [Table 1]

[0115] Referring to Table 1, the average major axis of the crystal grains in the first plating layer of the multilayer ceramic capacitor according to the example was 0.59 μm, the average minor axis was 0.32 μm, and the average ratio of major axis to minor axis was 1.97:1. Thus, because the difference between the major axis and minor axis of the crystal grains in the first plating layer of the multilayer ceramic capacitor according to the example was relatively small, the crystal grains exhibited a rounded shape.

[0116] (Comparative example) The procedure was identical to the example, except that a first plating layer was formed on the electrode layer by nickel (Ni) plating using DC plating.

[0117] To confirm the crystal grain shape of the first plating layer of the comparative example multilayer ceramic capacitor, specimens were prepared so that the cross-section in the length direction (L-axis direction) and thickness direction (T-axis direction) was exposed. Next, the surface of the specimens was etched with a Focused Ion Beam (FIB), and then the major and minor axes of the crystal grains of the first plating layer were measured using a scanning electron microscope (SEM) at 30KV, 50,000x magnification, and SE MODE. Ten crystal grains were selected in descending order of size, and the major and minor axes of these ten crystal grains were measured. The arithmetic mean of the ratio of major to minor axes was then taken and is shown in Table 2.

[0118] [Table 2]

[0119] Referring to Table 2, the average major axis of the crystal grains in the first plating layer of the comparative example multilayer ceramic capacitor was 1.18 μm, the average minor axis was 0.25 μm, and the average ratio of major axis to minor axis was 5.58:1. Thus, because the difference between the major axis and minor axis of the crystal grains in the first plating layer of the comparative example multilayer ceramic capacitor was relatively large, the crystal grains exhibited a pointed shape.

[0120] (Experimental Example 1: Evaluation of insulation resistance reliability at high temperatures) After immersing the substrates on which the multilayer ceramic capacitors according to the examples and comparative examples were mounted in a 0.01M NaOH solution, the DC plating conditions for the comparative example were set to satisfy 0.03A, and the PPR plating conditions for the examples were set to satisfy a forward current (Fwd.) of 0.03A and 450ms, and a reverse current (Rev.) of 0.09A and 50ms, thereby inducing only the hydrogen reaction.

[0121] When the PPR plating waveform was applied to the substrate on which the multilayer ceramic capacitor according to the example was mounted, all 50 samples showed normal insulation resistance.

[0122] When the DC plating waveform was applied to the substrate on which the multilayer ceramic capacitors in the comparative example were mounted, a decrease in insulation resistance (IR drop) was observed in most of the 50 samples.

[0123] (Experimental Example 2: Evaluation of Reproducibility) On the other hand, to evaluate reproducibility, the plating time in Experimental Example 1 was further extended, and the results of this experiment are shown in Figure 13. In the case of the comparative example and the example, the same results (right side of Figure 13) as the results of the primary evaluation (left side of Figure 13) were obtained.

[0124] (Experimental Example 3: Thickness of the Plating Layer) The thickness of the first plating layer was measured for five representative samples of multilayer ceramic capacitors according to the examples and comparative examples, and the mean, standard deviation, and coefficient of variation were derived. The results are shown in Tables 3 and 4, respectively. Table 3 pertains to the examples, and Table 4 pertains to the comparative examples.

[0125] [Table 3]

[0126] [Table 4]

[0127] Referring to Table 3, the coefficient of variation of the thickness of the first plating layer of the multilayer ceramic capacitor according to the example was shown to be between 11.7% and 15.9%. Referring to Table 4, the coefficient of variation of the thickness of the first plating layer of the multilayer ceramic capacitor according to the comparative example was shown to be between 13.5% and 28.3%. Since the coefficient of variation of the thickness of the first plating layer of the multilayer ceramic capacitor according to the example has a smaller range, it can be seen that the variation in plating thickness has been improved.

[0128] (Experimental Example 4: Surface Roughness of Plating Layer) The surface roughness of the first plating layer of five representative samples of multilayer ceramic capacitors according to the examples and comparative examples was measured, and the results are shown in Tables 5 and 6, respectively. Table 5 relates to the examples, and Table 6 relates to the comparative examples.

[0129] [Table 5]

[0130] [Table 6]

[0131] Referring to Table 5, the surface roughness of the first plating layer of the multilayer ceramic capacitor according to the example was 1.51 μm to 1.86 μm. Referring to Table 6, the surface roughness of the first plating layer of the multilayer ceramic capacitor according to the comparative example was 2.46 μm to 3.06 μm. Since the surface roughness of the first plating layer of the multilayer ceramic capacitor according to the example has a smaller range, it can be seen that the smoothness of the plating layer was improved in the example.

[0132] As described above, embodiments of the present invention have been explained, but the present invention is not limited thereto, and can be implemented in various ways within the scope of the claims, description of the invention, and attached drawings, and these also naturally fall within the scope of the present invention. [Explanation of Symbols]

[0133] 1000: Multilayer ceramic capacitor 110: Body 200: 1st external electrode 300: 2nd external electrode 120: 1st electrode layer 130: Second electrode layer 140: Dielectric layer 143: First Cover Layer 145: Second Cover Layer 150: 1st internal electrode 160:Second internal electrode 180: First plating layer 182: Second plating layer 190: Third plating layer 192: Fourth plating layer

Claims

1. A body containing multiple internal electrodes stacked with a dielectric layer in between, An external electrode is positioned outside the body and connected to the plurality of internal electrodes, Includes, The external electrode includes a first plating layer, The average ratio of the major axis to the minor axis of the crystal grains in the first plating layer is 1:1 to 3:

1. A multilayer ceramic capacitor wherein the coefficient of variation of the thickness of the first plating layer is 11.7% or more and 15.9% or less.

2. The multilayer ceramic capacitor according to claim 1, wherein the average thickness of the first plating layer is 1.806 μm or more and 2.2362 μm or less.

3. The multilayer ceramic capacitor according to claim 2, wherein the standard deviation of the thickness of the first plating layer is 0.24 or more and 0.35 or less.

4. The multilayer ceramic capacitor according to claim 1, wherein the first plating layer contains nickel (Ni).

5. The aforementioned major axis is the maximum diameter of the crystal grain. The multilayer ceramic capacitor according to claim 1, wherein the minor axis is the maximum diameter measured in a direction perpendicular to the measurement direction of the major axis.

6. The multilayer ceramic capacitor according to claim 1, wherein the external electrode further comprises a second plating layer disposed on the first plating layer.

7. The multilayer ceramic capacitor according to claim 6, wherein the second plating layer contains tin (Sn).

8. The multilayer ceramic capacitor according to claim 1, wherein the external electrode further includes an electrode layer disposed between the body and the first plating layer and connected to the internal electrode.

9. A body containing multiple internal electrodes stacked with a dielectric layer in between, An external electrode is positioned outside the body and connected to the plurality of internal electrodes, Includes, The external electrode includes a first plating layer, The average ratio of the major axis to the minor axis of the crystal grains in the first plating layer is 1:1 to 3:

1. A multilayer ceramic capacitor wherein the surface roughness Ra of the first plating layer is 1.51 μm or more and 1.86 μm or less.

10. The multilayer ceramic capacitor according to claim 9, wherein the first plating layer contains nickel (Ni).

11. The aforementioned major axis is the maximum diameter of the crystal grain. The multilayer ceramic capacitor according to claim 9, wherein the minor axis is the maximum diameter measured in a direction perpendicular to the measurement direction of the major axis.

12. The multilayer ceramic capacitor according to claim 9, wherein the external electrode further comprises a second plating layer disposed on the first plating layer.

13. The multilayer ceramic capacitor according to claim 12, wherein the second plating layer contains tin (Sn).

14. The multilayer ceramic capacitor according to claim 9, wherein the external electrode further includes an electrode layer disposed between the body and the first plating layer and connected to the internal electrode.

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