Press-fit terminals for isolated power semiconductor devices

Abstract

The present invention provides a method for forming an insulated semiconductor device package that improves reliability and performance while reducing manufacturing and packaging costs, as well as a semiconductor package assembly apparatus and a semiconductor substrate assembly. [Solution] A method for forming a lead frame assembly 400 to which a semiconductor substrate assembly 402 is attached, comprising the step of performing a lead attachment step, which includes directly attaching at least one lead to a substrate 403 supporting one or more semiconductor dies 404. At least one lead is attached to the substrate in an individualized manner. A post-shaping step is performed to attach the trimmed and individualized leads to a semiconductor substrate package 412 for bending. This gives the semiconductor substrate package 412 an overall gull-wing shape, which is suitable for surface-mount power device applications.

Description

Technical Field

[0001] Embodiments relate to the field of semiconductor devices, and more particularly, to packages for power semiconductor chips.

Background Art

[0002] Semiconductor device packages (or simply "semiconductor packages"), such as power modules or discrete packages, may include components such as semiconductor chips, substrates, and connectors, the latter of which may include wires, clips, and other connectors. In particular, power semiconductor packages may include power chips, such as thyristors, field effect transistors (FETs), insulated gate bipolar transistors (IGBTs), and auxiliary chips including diodes. The main purpose of the clips is to electrically connect these chips to each other or to the substrate.

[0003] In the manufacture of discrete semiconductor device packages, it is common to have a lead frame structure to form the so-called backbone of the semiconductor package. During the assembly of the semiconductor package, the lead frame can be connected to, for example, a metallized substrate that supports the semiconductor die. The structure of the lead frame can be characterized by a metal frame or support portion, and lead portions that may be defined within the frame. To create electrical connections that deliver control and power signals to the semiconductor device supported by the substrate, the lead frame can be assembled to the substrate such that different lead portions are aligned with and contact metal features within the substrate. The lead portions and the frame portion can form a continuous structure that is monolithic and electrically interconnected, such that the individual leads are not electrically insulated from each other.

[0004] After assembly onto the circuit board, the trimmed frame portion of the lead frame is removed, and the electrical leads are individualized. This is intended to make each lead a standalone structure by removing the portion of the lead frame that originally connected the leads to each other. This individualization is particularly necessary to electrically isolate specific leads from one another, for example, when different leads should be electrically coupled to different terminals of a semiconductor device.

[0005] Considering the above, it can be understood that this involves a process of connecting electrical leads to a semiconductor package using a lead frame structure.

[0006] This embodiment is provided with the above in mind. [Overview of the project]

[0007] In one embodiment, a method for forming a semiconductor package is provided. The method may include a step of performing a lead attachment step, which involves directly attaching at least one lead to a substrate configured to support one or more semiconductor dies, wherein the at least one lead is attached to the substrate in an individualized manner.

[0008] In another embodiment, a semiconductor package assembly apparatus is provided. The apparatus may include a substrate clamp assembly and a mold structure that at least partially covers the substrate clamp assembly, the mold structure including an upper lead guide block arranged to prevent mold bleeding during the molding process.

[0009] In a further embodiment, a semiconductor substrate assembly for forming a semiconductor device package is provided. The semiconductor substrate assembly may include a substrate comprising a ceramic body and a set of metal layers attached to the ceramic body, and a set of leads attached to the substrate, the set of leads being adjacent to the substrate through laser welding. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1A shows a top view of a semiconductor substrate assembly according to an embodiment of the present disclosure. Figure 1B shows a top view of another semiconductor substrate assembly according to an embodiment of the present disclosure. Figure 1C shows a top isometric view of a lead according to an embodiment of the present disclosure. Figure 1D shows a top view of the lead in Figure 1C. Figure 1E shows a side view of the lead in Figure 1C. Figure 1F shows a top isometric view of another lead according to an embodiment of the present disclosure. Figure 1G shows a top view of the lead in Figure 1F. Figure 1H shows a side view of the lead in Figure 1F.

[0011]

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[0016]

[0017]

[0018] [Figure 2] Figure 2A shows a top view of the semiconductor substrate assembly. Figure 2B shows a top view of the semiconductor substrate assembly of Figure 2A after the assembly of the lead set according to an embodiment of the present disclosure. Figure 2C shows a top view of the semiconductor device assembly of Figure 2B after wire bonding. Figure 2D shows a top view of the semiconductor device assembly of Figure 2C after the formation of the molded housing. Figure 2E shows a top view of the semiconductor device assembly of Figure 2D after the plating treatment of the lead set.

[0019]

[0020]

[0021]

[0022]

[0023] [Figure 3-1] Figures 3A, 3B, 3C, 3D, and 3E show various stages during the assembly of a semiconductor device package assembly according to an embodiment of the present disclosure. [Figure 3-2] Figures 3F, 3G, 3H, 3I, 3J, and 3K show various stages during the assembly of a semiconductor device package assembly according to an embodiment of the present disclosure.

[0024] [Figure 4] A side cross-sectional view of a transfer mold design according to an embodiment of the present disclosure is shown.

[0025] [Figure 5] Figure 5A shows a top perspective view of a portion of the structure of FIG. 4. Figure - 5B shows an enlarged view of the pinch bar section of the structure of FIG. 5A.

[0026]

[0027] [Figure 6] Figure 6A shows a top isometric view of a semiconductor device package according to some embodiments. Figure 6B shows an enlarged view of the lead portion of the semiconductor device package of FIG. 6A.

[0028]

[0029] [Figure 7] Figure 7A shows a photographic image diagram of a test process. Figure 7B shows a photographic image diagram of another test process. Figure 7C shows a photographic image diagram of another test process.

[0030] < /

[0031] [[ID= - 42]]

[0032] [Figure 8] Figure 8A shows a lead frame assembly to which a semiconductor substrate assembly is attached. Figure 8B shows the semiconductor substrate assembly of FIG. 8A after trimming and singulation. [[ID=^48]]

[0033]

[0034] [Figure 9] Figure 9A is a composite diagram showing a top view and a side view of an assembly having a semiconductor substrate package and mounted leads, as well as a diagram of a single lead, according to an embodiment of the present disclosure. Figure 9B shows the assembly of Figure 9A after the molding process. Figure 9C shows a top isometric view of the assembly of Figure 9B in the final stage.

[0035]

[0036]

[0037] [Figure 10] A side cross-sectional view of a mold tool layout according to an embodiment of the present disclosure is shown.

[0038] [Figure 11] An illustrative process flow is presented. [Modes for carrying out the invention]

[0039] Hereafter, the embodiments will be described in more detail with reference to the accompanying drawings illustrating exemplary embodiments. These embodiments should not be construed as limiting the embodiments described herein. Rather, these embodiments are provided so that the disclosure may be complete and the scope of the embodiments may be fully conveyed to those skilled in the art. Throughout the drawings, similar numbers refer to similar elements.

[0040] In the following description and / or claims, the terms “on,” “overlying,” “disposed on,” and “over” may be used in the following description and claims. “On,” “overlying,” “disposed on,” and “over” may be used to indicate that two or more elements are in direct physical contact with each other. Alternatively, the terms “on,” “overlying,” “disposed on,” and “over” may mean that two or more elements are not in direct contact with each other. For example, “over” may mean that one element is on another element but is not in contact with each other, and there may be one or more other elements between these two elements. Furthermore, the term "and / or" can mean "and," "or," "exclusive-or," "one," "some, but not all," "neither," and / or "both," but the scope of the claimed subject matter is not limited in this respect.

[0041] In various embodiments, novel semiconductor device packages and assembly methods are provided. As detailed below, leaded semiconductor device packages may be assembled through a leadless process, which allows for fewer process steps, lower manufacturing and packaging costs than existing designs, and better performance, including reliability, particularly for package types including insulated semiconductor device packages.

[0042] As will be further detailed below, a combination of features including press-fit terminal leads, laser welding for direct bonding of leads to an AMB / DCB substrate, and the use of lead-free die bonding material can be used to realize a suitable package for power semiconductor devices, including in cases of wide-bandgap semiconductor requirements to address high voltage, high current, high thermal conductivity, and higher operating temperature applications exceeding 175°C.

[0043] Figure 1A shows a top view of a semiconductor substrate assembly 100 according to an embodiment of the present disclosure. The semiconductor substrate assembly 100 includes a substrate section 104 and a set of leads, indicated as leads 102. In this case, leads 102 represent general-purpose standard terminals. Figure 1B shows a top view of another semiconductor substrate assembly 110 according to an embodiment of the present disclosure. In this case, leads 112 represent general-purpose press-fit terminals. Figure 1C shows a top isometric view of leads 102 according to an embodiment of the present disclosure; Figure 1D shows a top view of the leads in Figure 1C; and Figure 1E shows a side view of the leads in Figure 1C.

[0044] Figure 1F shows a top isometric view of lead 112 according to an embodiment of the present disclosure; Figure 1G shows a top view of the lead in Figure 1F; while Figure 1H shows a side view of the lead in Figure 1F. As will be detailed in the following description, these semiconductor package assemblies may be formed by welding processes, in particular, without a lead frame structure. For example, the “general-purpose standard terminal” structure in Figure 1C or the “general-purpose press-fit terminal” structure in Figure 1F may be precisely fabricated for use as individual leads in semiconductor packages such as isolated power device packages. In other words, the leads are attached in an “individually” manner, where any given lead is not attached to any other lead.

[0045] As will be further detailed in the following embodiments, the combination of press-fit terminal leads directly bonded by laser welding to substrates such as active metal brazing (AMB), direct copper bonded (DCB), or direct aluminum bonded (DAB) substrates, along with lead-free die adhesive materials, may be suitable for broadband gap semiconductor requirements to address applications at high voltage, high current, high thermal conductivity, and higher operating temperatures above 175°C. In particular, the advantages provided by this embodiment using press-fit connections without lead frames include low thermal load on components; assembly of power modules at the bottom of printed circuit boards (PCBs); prevention of solder bridges, splashes, and flux residues; connections may be lead-free and halogen-free; excellent current carrying capability; high long-term reliability; high cost-effectiveness; and low assembly costs.

[0046] Figure 2A shows a top view of a semiconductor substrate assembly 120 including a substrate 121, which may be a DCB substrate or a DAB substrate of other substrates known in the art. The substrate 121 may have a ceramic body and a metallization pattern 124 for forming contact with the semiconductor die 122.

[0047] Figure 2B shows a top view of the semiconductor substrate assembly of Figure 2A after assembly of the lead set, in this case lead 112, according to an embodiment of the present disclosure. Figure 2C shows a top view of the semiconductor device assembly of Figure 2B after the formation of the wire bond 125. In one non-limiting embodiment, the semiconductor die 122 may be a SiC chip, while the substrate 121 is a Si3N4 substrate having a metallization formed by bonding a metal layer to a Si3N4 substrate using an active metal brazing (AMB) process, the chip-to-substrate bonding is achieved by Ag sintering, the lead 112 is a general-purpose press-fit structure, and the bonding wire is formed of aluminum wire. In other embodiments, standard high-Pb content metallization may be used to bond the substrate and the chip. In one embodiment, the lead 112 may be bonded to the substrate using laser welding. In some embodiments, the wire bond 125 may use Al wire.

[0048] Figure 2D shows a top view of the semiconductor device assembly of Figure 2C after the formation of the molded housing 126. Figure 2E shows a top view of the semiconductor device assembly of Figure 2D after the plating of the lead set. In particular, after the molding process, the leads may be treated to present a bare copper surface for better solderability during mounting on the PCB board. The lead plating may then be carried out using a known plating process such as tin plating.

[0049] In various embodiments, for long-lead embodiments of semiconductor device assemblies, a skew tool assembly for lead adjustment may be provided after the lead plating process, at a final testing (FT) station, or with an offline tool for straightening bent leads. Since the semiconductor packages of this disclosure do not have a lead frame, the terminal leads are prone to bending during processing, such as during the plating process. Therefore, additional lead adjustment may be performed at an FT station, or using a special adjustment tool, or offline before final electrical testing.

[0050] Figures 3A to 3L illustrate various stages in the assembly of a semiconductor device package assembly according to embodiments of the present disclosure. In Figure 3A, an assembly holder 302 is provided for holding and aligning substrates, such as DCB substrates, during the assembly of a semiconductor package or an array of packages. The assembly holder 302 includes a terminal aligner slot 305 for housing a terminal aligner insert 304, and a substrate slot 307 in particular for housing the substrates. Note that the terminal aligner insert 304 may include embedded magnets to facilitate coupling to a clamp, as described below with respect to Figure 3D. In Figure 3B, the terminal aligner insert 304 is positioned within the terminal aligner slot 305. Note that, as shown in Figure 3C, with a substrate 121 having leads 112 positioned within the assembly holder 302, the terminal aligner insert 304 functions to align and space out sets of leads connected to each substrate. It should be noted that in other embodiments, the assembly holder 302 may alternatively accommodate a substrate assembly 110 or a similar substrate assembly. Briefly, also referring to Figures 2B and 2C, in the stage of Figure 3C, a set of substrates 121 is placed in the substrate slot 307. The leads 112 are placed in lead recesses provided in the terminal aligner insert 304 and are aligned with each substrate in the substrate slot 307. The semiconductor dies 122 are placed and mounted on each substrate as shown.

[0051] Figure 3D shows a subsequent instance of assembly, where the clamp 306 is placed on the terminal aligner insert 304. The clamp 306 may be a magnetic weighting fixture or any suitable structure for clamping the lead 112 during an assembly process such as a vacuum reflow process. In particular, the clamp 306 may be magnetic to magnetically clamp onto the terminal aligner insert 304. Figure 3E shows a subsequent instance after wire bonding has been performed to form wire bonds between various components, such as semiconductor dies, and the substrate, as shown in Figure 2C. Note that the wire bonding is performed while the components are held in the assembly holder 302.

[0052] Figure 3F is a composite diagram including perspective and cross-sectional views showing a subsequent instance in which the terminal aligner insert 304 and clamp 306 are removed together from the assembly holder 302. Note that, as shown in the cross-sectional view of Figure 3F, the terminal aligner insert 304 and clamp 306 together hold the substrate 121 and the attached leads, i.e., leads 112. The terminal aligner insert 304 and clamp 306 form a substrate clamp assembly 308 for holding the leads 112 and the substrate 121, thereby allowing the clamped leads and substrate to be subsequently placed into a mold structure for forming the housing of the fabricated semiconductor package.

[0053] Figure 3G shows a subsequent instance in which the substrate clamp assembly 308 is arranged in the mold structure 316 for molding. In particular, the set of substrates 121 is arranged within the bottom mold frame 312, while the top mold frame 310 is placed on top of the substrates 121. Note that the bottom mold frame 312 extends below the substrates 121 and below the terminal aligner inserts 304.

[0054] Figure 3H shows a subsequent instance in which the bottom mold frame 312 and the upper mold frame 310 are combined to cover the substrate 121 and a portion of the leads 112 adjacent to the substrate 121. Note that the upper mold frame 310 includes an upper lead guide block 314 with pinch bars to prevent mold bleeding, as will be detailed below.

[0055] Figure 3I is a composite diagram, including perspective and cross-sectional views, showing a subsequent instance in which the molding process is performed, in which the molding material, such as a known polymer material, is poured into a cavity defined within the bottom mold frame 312 and the upper mold frame 310. Note that, as shown in the cross-sectional view, a clamp 306 and alignment pins 318 extending through terminal aligner inserts 304 may be provided.

[0056] Figure 3J, a composite diagram including perspective and cross-sectional views, shows a subsequent instance in which the bottom mold frame 312 and the top mold frame 310 have been removed, leaving the semiconductor device package assembly, indicated as package 320, still held between the clamp 306 and the terminal aligner insert 304.

[0057] Figure 3K shows a subsequent instance in which the clamp 306 and terminal aligner insert 304 have been removed, leaving the semiconductor device package assembly, indicated as package 320.

[0058] A key feature of the assembly process shown in Figures 3A to 3K is that the lead 112 is assembled into the package 320 without the use of a lead frame.

[0059] To illustrate a notable feature of this embodiment that enables a process without a lead frame, Figure 4 shows a side section view of a transfer mold design according to an embodiment of the present disclosure. In addition to the components described above, the design includes a bottom lead guide 340, which may form part of a bottom mold frame 312. The design in Figure 4 further shows an upper cavity 334 and a bottom cavity 336 into which the molding material will be flowed during the molding process. The design in Figure 4 further includes an upper gate block 309, a bottom gate block 311, and an upper gate entry 338. The design in Figure 4 further includes an upper lead guide block 314 with a pinch bar.

[0060] Figure 5A shows a top perspective view of the structure in Figure 4. Note that a set of embedded magnets, indicated as magnet 342, is shown. Figure 5B shows a magnified view of the pinch bar section of the structure in Figure 5A. Note that the pinch bar of the upper lead guide block 314 abuts against the top of the lead 112, as shown in Figure 4. In this way, mold bleeding outside the upper mold frame 310 and bottom mold frame 312 is prevented as the mold material flows into the structure in Figure 4. In particular, the mold material is not excessively extruded onto the lead 112.

[0061] Figure 6A shows a top perspective view of a semiconductor device package 350 according to several embodiments, while Figure 6B shows a magnified view of the lead portion of the semiconductor device package 350 in Figure 6A. A structural feature of the semiconductor device package 350 is the presence of pinch bar marks 352, which are brought about by part of the assembly process described above, as outlined in Figures 3A to 3K.

[0062] Figure 7A shows a photographic diagram of the test process according to this embodiment. In this instance, the lead is clamped and moved laterally within the plane defined by the lead 112. In particular, a lifting tool 360 is provided together with a movable clamp 362 and a sample unit 364.

[0063] Figure 7B shows a photographic diagram of another test process. In particular, at this stage, the lead is tightened and moved up and down in a direction perpendicular to the plane defined by the lead 112.

[0064] Figure 7C shows a top perspective view of another test step in which a visual system check 366 is performed to detect a bent lead.

[0065] By reference, Figure 8A shows a lead frame assembly 400 with a semiconductor substrate assembly 402 attached. Figure 8B shows the semiconductor substrate assembly 402 of Figure 8A after lead trimming and individualization. The semiconductor substrate assembly 402 may include a substrate 403, as well as a semiconductor die 404 and wire bonds 405.

[0066] Figure 9A shows an assembly having a semiconductor substrate package 412 with leads attached, according to an embodiment of the present disclosure, and Figure 9B shows the assembly of Figure 9A after a molding process for bending the leads, which are highlighted in the cross-sectional view. Figure 9C shows a top perspective view of the assembly of Figure 9B in the final stage.

[0067] The difference between the semiconductor substrate package 412 and the semiconductor substrate assembly 402 is that the semiconductor substrate package 412 is not formed using a lead frame. In this example, the semiconductor substrate package 412 has an overall gull-wing shape, which is suitable for surface-mount power device applications.

[0068] Figure 10 shows a side section view of a mold tool layout 500 according to an embodiment of the present disclosure. In this example, the mold tool layout 500 may generally include components organized according to the aforementioned embodiments described particularly with respect to Figures 3A to 5B. As shown, the mold tool layout 500 includes an upper clamp structure 502 and a lower clamp structure 504 arranged on both sides of the upper cavity bar 506 and the lower cavity bar 508. The mold tool layout 500 also includes a set of alignment pins 318 arranged on both sides of the upper cavity bar 506 and the lower cavity bar 508. The mold tool layout 500 further includes a set of upper lead guide blocks 510 and a set of lower lead guide blocks 512 having pinch bars, arranged on both sides of the upper cavity bar 506 and the lower cavity bar 508, respectively. In this embodiment, the set of leads 514 extends from the left side of the mold tool layout 500 and is attached to the substrate 520, while the set of leads 516 extends from the right side of the mold tool layout 500 and is also attached to the substrate 520, thereby making this arrangement suitable for forming the gullwing package shown in Figure 9C.

[0069] Figure 11 shows process flows 1100 according to some embodiments of the present disclosure. In block 1102, a semiconductor die is mounted on a substrate such as a DCB, DAB, or AMB substrate.

[0070] In block 1104, terminals (leads) are attached to the substrate. In various embodiments, the leads may be attached to each substrate by a laser welding process.

[0071] In various embodiments, the mounting of semiconductor dies and leads is performed within an assembly holder as detailed in the above embodiments. In various embodiments, to form a substrate assembly including substrates with attached leads, the assembly holder may accommodate multiple substrates such that the mounting of leads and semiconductor dies is applied to multiple substrates arranged simultaneously within the assembly holder.

[0072] In certain embodiments, as detailed above, the leads are secured using terminal aligner inserts and clamps.

[0073] In block 1106, a reflow process, such as vacuum reflow, is performed. In particular, during the solder reflow process, a vacuum is applied before high temperatures are applied inside the chamber to remove gas and ensure that no voids are formed in the solder.

[0074] In block 1108, a wire bonding process is performed to attach various components, including a substrate and a semiconductor die, to each other while these components are held within an assembly holder.

[0075] In block 1110, molding and post-mold curing (PMC) processes are performed. The PMC process involves annealing to release package stress before plating. According to this embodiment, the substrate assembly is removed from the assembly holder after block 1108 and before the molding process is performed. After removal from the assembly holder, the substrate assembly may remain clamped between the terminal aligner insert and the clamp. In some embodiments, the molding process may use an upper mold frame and a bottom mold frame, the bottom mold frame extending below the substrate and terminal aligner insert.

[0076] In various embodiments, the upper mold frame may include a lead guide block having pinch bars that contact the leads of the substrate assembly. During the molding process, mold material can be injected into the cavities provided by the upper and lower mold frames. The pinch bars can prevent excess mold material from flowing over the leads during the molding process.

[0077] In block 1112, the lead plating process is performed. In this instance, a housing formed from the molding material extends over the substrate and a portion of the leads adjacent to the substrate. In this instance, the leads are plated with a plating material such as a known metallization. Note that after the process in block 1110, once molding is complete, the substrate assembly is removed from the upper and lower mold frames. The substrate assembly is further unclamped and removed from the terminal aligner inserts and clamps before the plating process is performed.

[0078] In block 1114, a lead forming process is performed to properly shape and space the leads. In block 1116, an FT process is performed, particularly in the case of long lead embodiments of semiconductor device assemblies, by using a skew tool assembly for lead adjustment in an FT station or offline tool to straighten bent leads.

[0079] In summary, this embodiment provides a leadframe-less assembly structure and process for semiconductor packages, such as discrete power semiconductor packages. Advantages of this method include reduced manufacturing and packaging costs due to the elimination of leadframes and trimming and individualization processes. In some embodiments of this embodiment, an AMB Si3N4 substrate is provided, achieving higher current capacity compared to known Al2O3 or AlN DCB type substrates due to a thicker Cu layer (e.g., approximately 0.4 mm to 0.8 mm) in the AMB method. In addition, ceramic cracking problems are reduced due to the higher flexural strength and toughness of the Si3N4 substrate. Furthermore, the wire bonding capability of the AMB Si3N4 substrate is improved due to its smaller grain structure. Moreover, the laser welding process in this embodiment avoids soldering, resulting in higher device reliability by avoiding solder in the final package. Embodiments of this disclosure using an AMB substrate exhibit reduced warping and superior thermal performance compared to known DCB packages. In particular, an AMB substrate with a coefficient of thermal expansion (CTE) of 2.5 ppm / K will experience lower thermal stress compared to a DCB substrate with a CTE of 7 ppm / K.

[0080] Various embodiments of this disclosure further provide Ag sintered die bonding, thereby resulting in a package suitable for higher operating temperatures, having lead-free components, being solder void-free, and exhibiting higher reliability performance. These features provided in power semiconductor packages can maximize device performance for power devices such as SiC.

[0081] Further advantages provided by this embodiment include the ability to rapidly prototype new products, stemming from the elimination of the need for embossing tools, which would otherwise be required for leadframe-based packages. Therefore, since the leads are individualized before being bonded to the substrate, the package lead count can be easily adjusted from 2, 3, 4, 5, 6, 7, etc., depending on product requirements. This embodiment also covers implementations in gullwing-type package architectures with adapted lead counts (e.g., SMPD 9L, 15L, 21L, etc.).

[0082] Although this embodiment is disclosed with reference to a specific embodiment, numerous modifications, alterations, and changes are possible to the embodiment described without departing from the scope and realm of this disclosure, as set forth in the appended claims. Therefore, this embodiment should not be limited to the embodiment described, but may encompass the entire scope as defined by the following claims and their equivalents.

Claims

1. A method for forming a semiconductor package: A step of performing a lead attachment process, which includes directly attaching at least one lead to a substrate configured to support one or more semiconductor dies, wherein the at least one lead is attached to the substrate in an individualized manner. A method that includes [a certain feature].

2. The aforementioned substrate is Si ３ N ４ The ceramic body and the Si by an activated metal brazing process ３ N ４ The method according to claim 1, comprising a set of metal layers attached to a ceramic body.

3. The method according to claim 1, wherein the substrate comprises a set of a ceramic body and a metal layer attached to the ceramic body, and the step of attaching the at least one lead comprises a step of performing a laser welding step to bond the at least one lead to the metal layer of the substrate.

4. The method according to claim 1, wherein the step of performing the lead attachment process includes the steps of arranging a plurality of substrates in an assembly holder, arranging a terminal aligner insert in the assembly holder, and arranging a plurality of leads in slots provided in the terminal aligner insert.

5. The method according to claim 4, further comprising the steps of connecting a clamp to the terminal aligner insert and performing a reflow process when the clamp is connected to the terminal aligner insert.

6. The method according to claim 4, further comprising the steps of arranging the plurality of substrates between an upper mold frame and a bottom mold frame, and performing a molding process when the upper mold frame and the bottom mold frame are joined together to form a mold tool.

7. The method according to claim 6, wherein the upper mold frame includes an upper lead guide having a pinch bar, the pinch bar preventing the mold material from flowing out of the mold tool during the molding process.

8. The method according to any one of claims 1 to 7, further comprising the step of attaching the one or more semiconductor dies to the substrate using an Ag sintering process.

9. The method according to any one of claims 1 to 7, wherein the one or more semiconductor dies include a SiC die.

10. The aforementioned molding tool; Upper cavity bar; Bottom cavity bar; and A pair of upper lead guide blocks, each with a pinch bar arranged on it; and Includes a pair of bottom lead guide blocks, The pair of upper lead guide blocks and the pair of lower lead guide blocks are arranged on both sides of the upper cavity bar and the lower cavity bar. The method according to claim 6.

11. PCB clamp assembly; and A mold structure that at least partially covers the substrate clamp assembly, wherein the mold structure includes an upper lead guide block arranged to prevent mold bleeding during the molding process. A semiconductor package assembly apparatus equipped with the following features.

12. The aforementioned substrate clamp assembly: Terminal aligner inserts for aligning a set of leads to be attached to a set of substrates to be arranged within the mold structure; and A clamp for coupling with the terminal aligner insert and holding the lead in place. A semiconductor package assembly apparatus according to claim 11, including the following:

13. The aforementioned mold structure is: A bottom mold frame for holding the set of substrates; and An upper mold frame, wherein the upper mold frame includes the upper lead guide block, and the upper lead guide block includes pinch bars arranged to contact the set of leads when the upper mold frame and the bottom mold frame are assembled together. A semiconductor package assembly apparatus according to claim 12, including the following:

14. The semiconductor package assembly apparatus according to any one of claims 11 to 13, further comprising the substrate clamp assembly and a set of alignment pins extending through the mold structure.

15. The aforementioned mold structure is; Upper cavity bar; Bottom cavity bar; and A pair of upper lead guide blocks, each with a pinch bar arranged on it; and Includes a pair of bottom lead guide blocks, The pair of upper lead guide blocks and the pair of lower lead guide blocks are arranged on both sides of the upper cavity bar and the lower cavity bar. The semiconductor package assembly apparatus according to claim 13.

16. A semiconductor substrate assembly for forming a semiconductor device package, A substrate, the substrate includes a ceramic body and a set of metal layers attached to the ceramic body; and A set of leads attached to the substrate, the set of leads adjacent to the substrate through laser welding A semiconductor substrate assembly comprising the above features.

17. The aforementioned substrate is Si ３ N ４ A semiconductor substrate assembly according to claim 16, comprising a ceramic body and a set of metal layers attached to the ceramic body by an activated metal brazing process.

18. The semiconductor substrate assembly according to claim 16, wherein the set of leads includes general-purpose press-fit leads.

19. The semiconductor substrate assembly according to any one of claims 16 to 18, wherein the set of leads is attached to the substrate in a gull-wing configuration.

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