Stacked memory device having folded bit lines and staggered channels and method of operation thereof

Abstract

The present invention provides a stacked memory device based on folded bit lines and staggered semiconductor channels, and a method for operating the same. [Solution] The operating method of the stacked memory device of the present invention includes the steps of: offsetting the position of a first isolation trench group with respect to the position of a second isolation trench group; forming a first local bit line at a first angle with respect to the orientation of the first and second isolation trench groups; offsetting the position of a third isolation trench group with respect to the position of a fourth isolation trench group; and forming a second local bit line at a second angle different from the first angle with respect to the orientation of the third and fourth isolation trench groups.

Description

Technical Field

[0005] ,

[0001] The present invention relates to a memory system, and more particularly, to a stacked memory device based on folded bit lines and staggered semiconductor channels and an operating method thereof.

Background Art

[0002] This background section is only intended to provide context, and the disclosure of any concepts described in this section does not admit that such concepts are prior art.

[0003] A memory chip includes an integrated circuit that stores and reads data in digital devices such as computers and mobile devices. The memory chip stores data temporarily or permanently. Memory chips include random access memory (RAM), dynamic random access memory (DRAM), read only memory (ROM), flash memory, etc. The memory chip includes output lines connected to the system data bus. Some memory chips are cut out from wafers and placed in individual housings. Memory chips are mounted on a printed circuit board (PCB), incorporated into a system on a chip (SoC), or stacked vertically.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention has been made in view of the above prior art, and an object of the present invention is to provide a stacked memory device based on folded bit lines and staggered semiconductor channels and an operating method thereof.

Means for Solving the Problems

[0005] A stacked memory device according to one aspect of the present invention, made to achieve the above objective, comprises a first isolation trench group and a second isolation trench group, a first local bit line formed at a first angle with respect to the orientation of the first isolation trench group and the second isolation trench group, a third isolation trench group and a fourth isolation trench group, and a second local bit line formed at a second angle different from the first angle with respect to the orientation of the third isolation trench group and the fourth isolation trench group, wherein the position of the first isolation trench group is offset with respect to the position of the second isolation trench group, and the position of the third isolation trench group is offset with respect to the position of the fourth isolation trench group.

[0006] The first angle of the first local bit line may be in the range of 10 to 80 degrees with respect to the orientation of the first and second isolation trench groups, which are oriented at zero angle. The first connector connects the first local bit line to the first global bit line, the first global bit line connects the first local bit line to the first sense amplifier, and the first global bit line may be positioned at zero angle. The second angle of the second local bit line may be in the range of 100 to 170 degrees with respect to the orientation of the third and fourth isolation trench groups, which are oriented at zero angle. A second connector connects the second local bit line to a second global bit line, the second global bit line connects the second local bit line to a second sense amplifier, and the second global bit line may be positioned at zero angle. The first portion of the first local bit line may be formed between the first isolation trench and the second isolation trench of the first group of isolation trenches. The second portion of the first local bit line may be formed between the third isolation trench and the fourth isolation trench of the second group of isolation trenches. The first local bit line may be connected to the first memory cell array and the second memory cell array.

[0007] To achieve the above objective, another stacked memory device according to the present invention comprises a first isolation trench group and a second isolation trench group, a first local bit line formed between the first isolation trench and the second isolation trench of the first isolation trench group, and a second local bit line formed between the third isolation trench and the fourth isolation trench of the second isolation trench group, wherein the position of the first isolation trench group is offset with respect to the position of the second isolation trench group.

[0008] The position of the first local bit line may be offset with respect to the position of the second local bit line. The angle between the first local bit line and the second local bit line may be in the range of 10 to 80 degrees with respect to the orientation of the first and second isolation trench groups, which are oriented at zero angle. The first connector connects the first local bit line to the first global bit line, and the first global bit line may connect the first local bit line to the first sense amplifier. The first global bit line is positioned at least partially between the first isolation trench and the second isolation trench, and the first global bit line may be positioned at zero angle. A second connector connects the second local bit line to a second global bit line, and the second global bit line may connect the second local bit line to a second sense amplifier. The second global bit line is positioned at least partially between the third isolation trench and the fourth isolation trench, and the second global bit line may be positioned at zero angle. The first local bit line may be connected to a first memory cell array, and the second local bit line may be connected to a second memory cell array.

[0009] To achieve the above objective, an operating method for a stacked memory device according to one aspect of the present invention includes the steps of: offsetting the position of a first isolation trench group with respect to the position of a second isolation trench group; forming a first local bit line at a first angle with respect to the orientation of the first and second isolation trench groups; offsetting the position of a third isolation trench group with respect to the position of a fourth isolation trench group; and forming a second local bit line at a second angle different from the first angle with respect to the orientation of the third and fourth isolation trench groups.

[0010] The first angle of the first local bit line may be in the range of 10 to 80 degrees with respect to the orientation of the first and second isolation trench groups, which are oriented at zero angle. The first connector connects the first local bit line to the first global bit line, the first global bit line connects the first local bit line to the first sense amplifier, and the first global bit line may be positioned at zero angle. The second angle of the second local bit line may be in the range of 100 to 170 degrees with respect to the orientation of the third and fourth isolation trench groups, which are oriented at zero angle.

[0011] Computer-readable media can store instructions that, when executed by a computer, cause the computer to perform operations substantially identical or similar to those described herein. Similarly, non-transient computer-readable media, devices, and systems for performing operations substantially identical or similar to those described herein are further disclosed. [Effects of the Invention]

[0012] The memory device of the present invention may include a sense amplifier (SA) with an expanded pitch margin, which is realized based on a folded bit line architecture. Furthermore, the operating method of the memory device of the present invention allows for greater leeway in the physical layout of the sense amplifier within the constraints of the memory cell array based on the bit line pitch or spacing.

[0013] Here, the bit line pitch is due to the folded bit line architecture. Furthermore, the memory device can be configured to bond and integrate with core and peripheral transistors based on the folded bit line systems and methods described herein.

[0014] These and other features and advantages of the present invention will be understood and recognized by reference to this specification, the claims, and the drawings. [Brief explanation of the drawing]

[0015] [Figure 1] This figure shows an example architecture according to one embodiment of the present invention. [Figure 2] This figure shows the details of an example architecture according to one embodiment of the present invention. [Figure 3] This figure shows another example architecture according to one embodiment of the present invention. [Figure 4] This figure shows the architectural details of another example according to one embodiment of the present invention. [Figure 5]A flowchart showing an example of an operation method related to a system according to an embodiment of the present invention. [Figure 6] A flowchart showing another example of an operation method related to a system according to an embodiment of the present invention. **DETAILED DESCRIPTION OF THE INVENTION**

[0016] The above aspects and other aspects of the present system and method will be more clearly understood by reading this specification together with the following drawings. In the drawings, the same reference numerals denote similar or identical elements. Furthermore, the drawings shown in this specification are for illustrating specific embodiments, and other embodiments not shown are not excluded from the scope of the present invention.

[0017] The systems and methods described in this specification can be subject to various changes and alternative forms. For the purpose of illustrating specific embodiments, they are shown in the drawings and will be described below. The drawings are not necessarily drawn to scale. However, the drawings and their detailed description are not intended to limit the present systems and methods to the specific forms disclosed, but rather are intended to cover all changes, equivalents, and alternatives that fall within the spirit and scope of the present systems and methods defined by the claims.

[0018] Details of embodiments of the present invention are shown in the drawings and the following description. Other features, aspects, and advantages of the present invention will become apparent from this specification, the drawings, and the claims.

[0019] Hereinafter, specific examples of embodiments for implementing the present invention will be described in detail while referring to the drawings.

[0020] However, the drawings show only some, and not all, embodiments. In fact, the present invention can be embodied in many forms and should not be construed as being limited to the embodiments described herein. Rather, these embodiments are provided to satisfy the legal requirements to which the present invention applies. The term "or" is used herein in both an alternative and a conjunctive sense unless otherwise specified. The terms "exemplary" and "example" are used simply as examples and do not indicate a level of quality. The same numbers refer to the same elements throughout. Arrows in each figure indicate bidirectional data flow and / or bidirectional data flow functionality. The terms "path," "pathway," and "route" are used interchangeably herein.

[0021] Embodiments of the present invention can be implemented in various forms, such as computer program products including manufactured articles. Computer program products may include non-temporary computer-readable storage media that store applications, programs, program components, scripts, source code, program code, object code, byte code, compiled code, interpreter code, machine code, executable instructions, and / or similar (also referred herein as executable instructions, execution instructions, computer program products, program code, and / or similar terms used interchangeably herein). Such non-temporary computer-readable storage media encompass all computer-readable media, including volatile and non-volatile media.

[0022] In one embodiment, non-volatile computer-readable storage media include floppy disks, flexible disks, hard disks, solid-state storage (SSS) (e.g., solid-state drives (SSDs)), solid-state cards (SSCs), solid-state modules (SSMs), enterprise flash drives, magnetic tapes, or other non-temporary magnetic media. Non-volatile computer-readable storage media also include punch cards, paper tapes, optical mark sheets (or any other physical media having hole patterns or other optically recognizable markings), compact disk read-only memory (CD-ROM), compact disk rewriteable (CD-RW), digital purpose discs (DVDs), Blu-ray discs (BDs), other non-temporary optical media, and / or similar media. Such non-volatile computer-readable storage media include read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory (e.g., serial, NAND, NOR, etc.), multimedia memory cards (MMC), secure digital (SD) memory cards, SmartMedia cards, CompactFlash® (CF) cards, Memory Stick®, and other similar media. Furthermore, non-volatile computer-readable storage media include conductive bridge random access memory (CBRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FeRAM), non-volatile random access memory (NVRAM), magnetoresistive random access memory (MRAM), resistive random access memory (ReRAM), silicon-oxide-nitride-oxide-silicon structure memory (SONOS), floating junction gate random access memory (FJG RAM), millipede memory, racetrack memory, and other similar storage media.

[0023] In one embodiment, the volatile computer-readable storage medium includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), fast page-mode dynamic random access memory (FPM DRAM), extended data output dynamic random access memory (EDO DRAM), synchronous dynamic random access memory (SDRAM), double data-rate synchronous dynamic random access memory (DDR SDRAM), double data-rate type 2 synchronous dynamic random access memory (DDR2 SDRAM), double data-rate type 3 synchronous dynamic random access memory (DDR3 SDRAM), Rambus dynamic random access memory (RDRAM), twin-transistor RAM (TTRAM), thyristor RAM (T-RAM), zero-capacitor RAM (Z-RAM), Rambus in-line memory component (RIMM), dual in-line memory component (DIMM), single in-line memory component (SIMM), video random access memory (VRAM), cache memory (including various levels), flash memory, register memory, and other similar storage media. Where an embodiment is described as using a computer-readable storage medium, it will be understood that other types of computer-readable storage medium may be used in place of or in addition to the computer-readable storage medium described above.

[0024] As will be naturally understood, various embodiments of the present invention are implemented as methods, apparatus, systems, computing devices, computing entities, and / or similar. Thus, embodiments of the present invention are implemented in the form of apparatus, systems, computing devices, computing entities, and other similar entities that execute instructions stored in a computer-readable storage medium to perform specific steps or operations. Accordingly, embodiments of the present invention are embodied as hardware embodiments, computer program product embodiments, and / or embodiments that combine a computer program product and hardware to perform specific steps or operations.

[0025] Embodiments of the present invention will be described below with reference to block diagrams and flowcharts. Accordingly, it will be understood by those skilled in the art that each block in the block diagrams and flowcharts is implemented in the form of a computer program product, a hardware embodiment, a combination of hardware and a computer program product, and / or a device, system, computing device, computing entity, or similar entity that executes instructions, operations, steps, or words used interchangeably therewith (e.g., executable instructions, instructions for execution, program code, etc.) stored on a computer-readable storage medium for execution. For example, code reading, loading, and execution are configured so that instructions are read, loaded, and executed sequentially, one instruction at a time. In some examples, reading, loading, and / or execution are performed in parallel so that multiple instructions are read, loaded, and / or executed simultaneously. Thus, such embodiments realize a machine specifically configured to perform the steps or operations described in the block diagrams and flowcharts. Accordingly, block diagrams and flowcharts support various combinations of embodiments for performing a given instruction, operation, or step.

[0026] Throughout this specification, the phrase "one embodiment" or "an embodiment" means that any particular feature, structure, or characteristic described in relation to that embodiment is included in at least one embodiment disclosed herein. Therefore, throughout this specification, phrases such as "in one embodiment," "in an embodiment," or "according to one embodiment" (or other expressions of similar intent) may appear, but these do not necessarily refer to the same embodiment. Furthermore, particular features, structures, or characteristics can be combined in any suitable way in one or more embodiments. In this regard, the term "exemplary" as used herein means "serving as an example, illustration, or descriptive element." Embodiments described as "exemplary" herein are not necessarily construed as being preferable or advantageous to other embodiments. Furthermore, particular features, structures, or characteristics can be combined in any suitable way in one or more embodiments. Also, depending on the context of the discussion herein, singular terms may include their corresponding plural forms, and plural terms may include their corresponding singular forms. Similarly, hyphenated terms (e.g., "two-dimensional," "pre-determined," "pixel-specific") may be used interchangeably with their corresponding non-hyphenated terms (e.g., "two-dimensional," "predetermined," "pixel specific"), and capitalized terms (e.g., "counter clock," "row select," "pixout") may be used interchangeably with their corresponding non-capsulated terms (e.g., "counter clock," "row select," "pixout").Such occasional, interchangeable usages are not considered contradictory.

[0027] Furthermore, depending on the context of the discussion in this specification, singular terms may include their corresponding plural forms, and plural terms may include their corresponding singular forms. It should also be noted that the various figures (including component diagrams) shown and discussed herein are for illustrative purposes only and are not drawn to scale. Similarly, the various waveform and timing diagrams are shown for illustrative purposes only. For example, the dimensions of some elements may be exaggerated relative to others for clarity. Furthermore, where appropriate, reference numerals are repeated between figures to indicate corresponding and / or similar elements.

[0028] The terms used herein are for the purpose of describing certain embodiments and are not intended to limit the scope of the claims. In this specification, the singular terms “a,” “an,” and “the” are intended to include the plural unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and / or “comprising,” when used herein, identify the presence of the described features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0029] When an element or layer is referred to as being on another element or layer, or “connected to” or “coupled to” another element or layer, it will be understood that the element or layer may be directly on the other element or layer, or connected to or coupled to the other element or layer, or that there may be an intervening element or layer. In contrast, when an element is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there is no intervening element or layer. The same number refers to the same element throughout. As used herein, the term “and / or” includes any combination of one or more of the related enumerated items.

[0030] As used herein, terms such as “first,” “second,” etc., are used as labels for nouns preceding them and do not imply any kind of order (e.g., spatial, temporal, logical, etc.) unless explicitly defined as such. Furthermore, the same reference numerals may be used across two or more figures to refer to parts, components, blocks, circuits, units, or modules having the same or similar function. However, such usage is solely for the purpose of simplifying the illustration and facilitating discussion, and does not imply that the structural or architectural details of such components or units are the same across all embodiments, or that such commonly referenced parts / modules are the only way to implement some of the embodiments disclosed herein.

[0031] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as those generally understood by those skilled in the art in which the present invention pertains. Furthermore, terms as defined in commonly used dictionaries should be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and it will be understood that they should not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0032] As used herein, the term “module” means any combination of software, firmware, and / or hardware configured to provide the functions described herein in relation to the module. For example, software may be embodied as a software package, code, and / or instruction set, or instructions, and the term “hardware” as used in any implementation described herein may include, for example, assemblies, hardwired circuits, programmable circuits, state machine circuits, and / or firmware that stores instructions executed by programmable circuits, either alone or in any combination. Modules may be embodied collectively or individually as circuits that form part of a larger system, but are not limited to, integrated circuits (ICs), system-on-a-chip (SoCs), assemblies, etc.

[0033] The descriptions provided are intended to enable those skilled in the art to implement and utilize the present invention and incorporate it into the context of a particular application. While the following describes specific embodiments, other further embodiments can be devised by those skilled in the art without departing from their basic scope.

[0034] Various modifications, along with diverse uses in different applications, will be readily understood by those skilled in the art, and the general principles defined herein apply to a wide range of embodiments. Therefore, the present invention is not intended to be limited to the embodiments described herein, but should be interpreted in the broadest sense, insofar as it is consistent with the principles and novel features disclosed herein.

[0035] Numerous specific details are described to provide a more complete understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be implemented without being limited to these specific details. In other examples, well-known structures and apparatus are shown in block diagrams rather than in detail, so as not to obscure the present invention.

[0036] All features disclosed herein (including, for example, the claims, abstract, and drawings) may be replaced by alternative features serving the same, equivalent, or similar purpose unless expressly stated otherwise. Thus, unless expressly stated otherwise, each disclosed feature is merely an example of a general set of equivalent or similar features.

[0037] This specification describes various features with reference to the drawings. It should be noted that the drawings are provided solely to facilitate the description of the features. The various features described are not intended to be exhaustive or to limit the scope of the invention. Furthermore, the illustrated embodiments do not necessarily encompass all the embodiments or advantages shown in the figures. Embodiments or advantages described in relation to a particular embodiment are not necessarily limited to that embodiment and may be implemented in other embodiments even if not illustrated or explicitly described.

[0038] Furthermore, any element in a claim that is not explicitly described as a “means for” or a “step for” performing a particular function shall not be construed as a “means” or “step” clause as defined in 35 U.S.C. Section 112, Paragraph 6. In particular, the use of “step of” or “act of” in a claim is not intended to apply the provisions of 35 U.S.C. 112, Paragraph 6.

[0039] Please note that the terms left, right, front, back, up, down, forward, backward, clockwise, and counterclockwise are used for convenience and do not imply any specific fixed direction. Instead, these terms are used to indicate the relative position and / or direction between different parts of an object.

[0040] Data processing includes data buffering, alignment of received data from multiple communication lanes, and forward error correction (FEC). For example, data is received by an analog front end (AFE), which can prepare the received data for digital processing. The digital portion of the transceiver (e.g., a digital signal processor (DSP)) provides skew management, equalization, reflection cancellation, and / or other functions. It should be understood that the processes described herein offer various advantages, including power and cost savings.

[0041] Furthermore, the terms “system,” “component,” “module,” “interface,” “model,” and other similar terms are generally intended to refer to any computer-related entity, whether hardware, a combination of hardware and software, software, or software in operation. For example, a component includes, but is not limited to, processes running on a processor, processors, objects, executable programs, threads (units of execution), programs, and / or computers. As an example, both an application running on a controller and the controller itself are components. One or more components may reside within a process and / or thread, but a component may reside on a single computer and / or be distributed across two or more computers.

[0042] Unless explicitly stated otherwise, each numerical value and range should be interpreted as an approximation, as if preceded by the words "approximately" or "about." Signals and their corresponding nodes or ports may be referred to by the same name and are used interchangeably for the purposes of this specification.

[0043] While embodiments will be described in relation to circuit functions, the embodiments of the present invention are not limited thereto. Possible implementations include a single integrated circuit, a multi-chip module, a single card, a SoC, or a multi-card circuit pack. As will be obvious to those skilled in the art, various embodiments are implemented as part of a larger system. Such embodiments are used in combination, for example, with a digital signal processor, a microcontroller, a field-programmable gate array, an application-specific integrated circuit, or a general-purpose computer.

[0044] As will be obvious to those skilled in the art, the various functions of circuit elements are implemented as processing blocks within software programs. Such software is used, for example, in digital signal processors, microcontrollers, or general-purpose computers. Such software can be represented in the form of program code embodied on tangible media such as magnetic recording media, optical recording media, solid-state memory, floppy disks, CD-ROMs, hard drives, or any other non-temporary machine-readable storage medium, and when the program code is loaded and executed on a machine such as a computer, the machine becomes an apparatus for carrying out the present invention. When implemented on a general-purpose processor, the program code segment is coupled with the processor to constitute its own device that operates similarly to a specific logic circuit. Embodiments described herein are also embodied in the form of bitstreams or other sequences of signal values ​​transmitted electrically or optically through a medium generated using the methods and / or apparatus described herein, or magnetic field fluctuations recorded in a magnetic recording medium.

[0045] Stacked memory includes three-dimensional dynamic random access memory (3D-DRAM) and vertical stacked DRAM (VS-DRAM). Stacked memory addresses the growing demand for high-density, high-performance memory in modern computing systems. By vertically stacking memory cells, 3D-DRAM offers the potential for greater storage capacity and improved energy efficiency compared to conventional planar DRAM architectures.

[0046] However, as 3D-DRAM structures become more complex and denser, maintaining signal integrity and reducing noise during read and write operations presents challenges. The placement and arrangement of bit lines, word lines, and other components significantly impacts the overall performance and reliability of the memory device.

[0047] One of the key considerations in 3D-DRAM design is the bit line configuration. Open bit line structures have been used in some 3D-DRAM designs due to local bit line placement constraints. In this configuration, each bit line typically uses an adjacent die to define a reference signal during device operation. While functional, this approach presents challenges related to noise coupling and sense margins.

[0048] As 3D-DRAM density increases, there is growing interest in exploring alternative bit-line architectures that may offer advantages in terms of signal quality, noise reduction, and overall device performance. Furthermore, considering process margins and integration with other components such as core transistors and peripheral transistors will drive the evolution of 3D-DRAM design.

[0049] Efforts to enhance 3D-DRAM technology often involve balancing multiple factors such as cell density, power consumption, reliability, and manufacturability. Thus, innovation in memory cell structure, interconnect design, and manufacturing technology remains an area of ​​active research and development in the field of 3D-DRAM.

[0050] According to one aspect of the present invention, a three-dimensional dynamic random access memory (3D-DRAM) device is provided having folded bit lines that improve the sense margin of the associated sense amplifier. For example, the device includes a staggered channel structure (e.g., a staggered trench isolation structure, a staggered semiconductor channel structure, a staggered silicon (Si) channel structure). Optionally, the device may include a folded bit line (BL) architecture realized by the staggered channel structure. The folded bit line architecture is implemented to improve the sense margin (compared to, for example, an open bit line structure).

[0051] In some examples, staggered channel structures are based on staggered or offset trench isolation structures (e.g., staggered capacitive deep trench isolation (CDTI) structures). Based on staggered channel structures, devices include local bit lines (LBLs) that are angled or inclined (e.g., with respect to the orientation of the staggered channel structure), enabling folded bit line architectures.

[0052] According to one aspect of the present invention, a method for manufacturing a 3D-DRAM device is provided. This method includes forming a staggered channel structure (e.g., a staggered CDTI, a staggered semiconductor channel structure). This method includes implementing a folded bit line BL architecture realized by the staggered channel structure. The folded bit line architecture can improve sense margin (compared to, for example, an open bit line structure). This method includes tilting the LBL to enable the folded bit line architecture. For example, the method of the present invention includes forming the LBL at an angle to the staggered channel structure and / or to the direction of extension of the global bit line.

[0053] The above general description of exemplary embodiments and the following detailed description are merely illustrative and not limiting to the teachings of the present invention.

[0054] Figure 1 shows an example architecture 100 according to one embodiment of the present invention.

[0055] Architecture 100 shows a perspective or oblique view of a stacked memory module. For example, Architecture 100 shows a top view of a stacked memory module. In some configurations, one or more aspects of Architecture 100 are carried out by, or in combination with, a manufacturing apparatus configured to form semiconductor manufacturing patterns and components (e.g., based on removal, etching, formation, deposition, etc.).

[0056] In the illustrated example, architecture 100 includes a substrate 105, a plurality of trench isolation structures (e.g., isolation trench 120, isolation trench 125, isolation trench 130, isolation trench 135), local bit lines (e.g., local bit lines LBL140, LBL145), global bit lines (e.g., global bit lines GBL160, GBL165, GBL170, GBL175), sense amplifiers (e.g., sense amplifier 110, sense amplifier 115), one or more first connectors (e.g., connector 150), and one or more second connectors (e.g., connector 155).

[0057] The substrate 105 serves as the base for the 3D-DRAM structure of architecture 100. The substrate 105 may be composed of one or more semiconductor materials (e.g., silicon). Isolation trenches (e.g., isolation trench 120, isolation trench 125, isolation trench 130, isolation trench 135) are formed in or on the substrate 105 to electrically isolate different components of the memory structure.

[0058] Local bit lines (e.g., LBL140, LBL145) are formed to connect individual memory cells to global bit lines. Global bit lines (e.g., GBL160, GBL165, GBL170, GBL175) are used to transmit data signals between the memory cells and sense amplifiers in the 3D-DRAM structure.

[0059] Sense amplifiers (e.g., sense amplifier 110, sense amplifier 115) are used to detect and amplify relatively small voltage differences on the bit line during readout operations. Thus, sense amplifiers are placed at both ends of the global bit line.

[0060] Connectors (e.g., connector 150, connector 155) are used to establish electrical connections between different layers or components of a 3D-DRAM structure. For example, connectors connect local bit lines to global bit lines and establish connections between memory cells connected to local bit lines and sense amplifiers.

[0061] In the illustrated example, the trench isolation structures (e.g., isolation trench 120, isolation trench 125, isolation trench 130, isolation trench 135) are arranged in a staggered pattern. For simplicity, from a top view in Figure 1, since one isolation trench is formed above another, the group of isolation trenches drawn perpendicularly in Figure 1 is called a "row" of isolation trenches. For example, isolation trench 120 forms the top of the first row of isolation trenches, isolation trench 125 forms the top of the second row, isolation trench 130 forms the top of the third row, and isolation trench 135 forms the top of the fourth row. As illustrated, the first row of isolation trenches is formed offset from the second row of isolation trenches (for example, isolation trench 120 is formed offset from isolation trench 125, and isolation trench 125 is shifted upward from isolation trench 120). Similarly, the third row of isolation trenches is formed offset from the fourth row (for example, isolation trench 130 is formed offset from isolation trench 135, and isolation trench 135 is shifted upward from isolation trench 130). Based on the offset, at least a portion of isolation trench 120 (e.g., in the width direction) is aligned with the space between isolation trench 125 and the next isolation trench below isolation trench 125. Similarly, based on the offset, at least a portion of isolation trench 130 (e.g., in the width direction) is aligned with the space between isolation trench 135 and the next isolation trench below isolation trench 135.

[0062] As shown in the figure, a given isolation trench is formed to have a width and a length, but the width is smaller than the length. Similarly, a given local bit line is formed to have a width and a length, but the width is smaller than the length. From a top view in Figure 1, the global bit line extends in the X direction. Also, as shown in the figure, the arrangement of the rows of isolation trenches extends in the Y direction. Similarly, based on Figure 1, the arrangement of the local bit lines is arranged in "rows" in the Y direction (for example, LBL140 at the top of the first row of the illustrated bit lines, LBL145 at the top of the second row of the illustrated bit lines, etc.).

[0063] The methods described herein include tilting the LBL. For example, the method includes forming the LBL at an angle with respect to the staggered channel structure and / or the direction of extension of the global bit line.

[0064] In the illustrated embodiment, at least a portion of the left end of LBL140 is formed within the gap between isolation trench 120 and the next isolation trench below isolation trench 120. Similarly, at least a portion of the right end of LBL140 is formed within the gap between isolation trench 125 and the next isolation trench below isolation trench 120. As illustrated, the LBLs of architecture 100 are formed at an angle during formation. For example, the first row of LBLs shown (e.g., LBL140) is formed at an angle to a given GBL or isolation trench (e.g., according to the illustrated viewpoint). As illustrated, the longitudinal orientation of isolation trench 120 is formed at an angle of zero or near zero degrees with respect to the x-direction of the illustrated GBL, while the first row of LBLs shown (e.g., LBL140) is formed at an angle in the range of 10 to 80 degrees.

[0065] In the illustrated embodiment, at least a portion of the left end of LBL145 is formed within the gap between isolation trench 130 and the next isolation trench below isolation trench 130. Similarly, at least a portion of the right end of LBL145 is formed within the gap between isolation trench 135 and the next isolation trench below isolation trench 135. As illustrated, the LBLs of architecture 100 are formed at an angle during formation. For example, the illustrated second row of LBLs (e.g., L145) is formed at an angle to a given GBL or isolation trench. As illustrated, the longitudinal orientation of isolation trench 130 is formed at an angle of zero or near zero degrees with respect to the x-direction of the illustrated GBL, while the illustrated second row of LBLs (e.g., LBL145) is formed at an angle in the range of 100 to 170 degrees (e.g., -10 to -80 degrees).

[0066] In the illustrated example, the LBLs (e.g., LBL140, LBL145) extend in the z direction relative to the x direction of the GBLs (e.g., GBL160, GBL165, GBL170, GBL175) (for example, into the page from the viewpoint shown in Figure 1). The illustrated connectors (e.g., connector 150, connector 155) are placed on top of the illustrated LBLs, but the GBLs extend laterally above the connectors.

[0067] The illustrated staggered trench isolation structure enables a folded bit-line structure, which can improve sense margin and noise immunity compared to an open bit-line structure. This arrangement allows for more efficient use of space and can improve overall memory performance.

[0068] Figure 2 shows details of an example architecture 200 according to one embodiment of the present invention.

[0069] Architecture 200 shows a perspective or oblique view of a stacked memory module. For example, Architecture 200 shows a cross-sectional or side view of a stacked memory module. In particular, Architecture 200 shows a cross-sectional view of folded bit lines based on staggered trench isolation (e.g., staggered capacitive deep trench isolation CDTI). For example, Architecture 200 shows a cross-sectional view of Architecture 100 in Figure 1. In some configurations, one or more aspects of Architecture 200 are carried out by, or in combination with, a manufacturing apparatus configured to form semiconductor manufacturing patterns and components (e.g., based on removal, etching, formation, deposition, etc.).

[0070] In the illustrated example, architecture 200 includes a substrate 205, an LBL 210, at least one connector (e.g., connector 150, connector 155), a capping material (e.g., capping 220, capping 225, dielectric capping, semiconductor capping, metal capping, etc.), and a semiconductor 230. As illustrated, architecture 200 also includes one or more capacitors (e.g., capacitor 235).

[0071] In the illustrated example, the transistor includes a semiconductor (e.g., semiconductor 230), a gate (e.g., gate 240), a gate oxide (e.g., gate oxide 245), and a dielectric (e.g., dielectric 250). The semiconductor 230 and capacitor 235 form a memory cell of architecture 200. As shown, a given semiconductor is formed adjacent to a gate (e.g., gate metal) such that the gate oxide separates the semiconductor from the gate. For example, semiconductor 230 is formed adjacent to a gate 240 (e.g., gate metal) such that the gate oxide 245 separates the semiconductor 230 from the gate 240. As shown, the gate 240 is formed adjacent to a dielectric (e.g., dielectric 250). In some cases, the gate 240 may surround the dielectric 250. As shown, the depicted capacitor (e.g., capacitor 235) is connected to each transistor (e.g., semiconductor 230 connected to capacitor 235).

[0072] As shown in the figure, the architecture 200 includes a first semiconductor stack (e.g., semiconductor 230, capacitor 235) formed on the substrate 205 and under the capping 220, and a second semiconductor stack formed on the substrate 205 and under the capping 225. As shown in the figure, LBL 210 connects the first group of memory cells (e.g., under the capping 225, including semiconductor 230 and capacitor 235) to the connector (CC) 215. Similarly, LBL 210 connects the second group of memory cells (e.g., under the capping 225) to the connector 215. The connector 215 connects LBL 210 to the global bit line. The global bit line is connected to the sense amplifier.

[0073] Figure 3 shows another example architecture 300 according to one embodiment of the present invention.

[0074] Architecture 300 shows a perspective or oblique view of a stacked memory module. For example, Architecture 300 shows a top view of a stacked memory module. In some configurations, one or more aspects of Architecture 300 are carried out by, or in combination with, a manufacturing apparatus configured to form semiconductor manufacturing patterns and components (e.g., based on removal, etching, formation, deposition, etc.).

[0075] Architecture 300 includes a substrate 305, a plurality of sense amplifiers (e.g., SA310, SA315), and a plurality of isolation trenches (e.g., isolation trench 320, isolation trench 325, isolation trench 330, isolation trench 335).

[0076] Architecture 300 also includes one or more local bit line (LBL) conductors. For example, architecture 300 includes LBL conductors 340 and 345. These LBL conductors are formed from conductive materials such as polysilicon, metal, or semiconductor materials.

[0077] Depending on the configuration, architecture 300 may include multiple connectors. For example, architecture 300 may include connectors 350 and 355. These connectors serve to establish electrical connections between different components and layers within the memory structure. As shown in the illustration, connector 350 is connected to LBL conductor 340 (e.g., the top of LBL conductor 340 in the illustrated top view), while connector 355 is connected to LBL conductor 345 (e.g., the top of LBL conductor 345 in the illustrated top view).

[0078] Architecture 300 further includes multiple global bit lines (GBLs). As shown in the illustration, architecture 300 includes GBL360, GBL365, GBL370, and GBL375. In the illustrated example, GBL360 and GBL365 are connected to SA310, while GBL370 and GBL375 are connected to SA315. These global bit lines are used for data signal transmission between memory cells and sense amplifiers. In the illustrated top view, the illustrated LBL conductors extend downward within the page. Memory cells also extend within the page adjacent to the LBL conductors and are connected to the LBL conductors.

[0079] The component arrangement of Architecture 300 contributes to a folded bit-line structure. For example, GBL360 and GBL365 are connected to SA310, while GBL370 and GBL375 are connected to SA315. This configuration improves noise immunity and sense margin compared to an open bit-line structure. This configuration also allows for more effective noise cancellation during read operations. For example, SA310 can use GBL365 as a voltage reference when reading a signal on GBL360, and vice versa. Similarly, GBL375 is used as a voltage reference when SA315 reads a signal on GBL370, and vice versa.

[0080] In some cases, the local bit lines of architecture 300 may be formed with an inclination. For example, connector 350 is connected to a local bit line formed with an inclination. Such an inclined configuration of local bit lines contributes to a folded bit line structure, enabling more efficient use of space within the memory architecture.

[0081] In the illustrated example, the LBL conductor is formed within the gap between isolation trenches. For example, the LBL conductor 340 (including, for example, the connector 350) is formed within the gap between isolation trench 320 and the next isolation trench below isolation trench 320. For example, the LBL conductor 340 (including, for example, the connector 350) is formed within the gap between isolation trench 320 and the next isolation trench below isolation trench 320. As shown in the illustration, the LBL conductor and connector are formed within the gap between isolation trench 330 and the next isolation trench below isolation trench 330. Similarly, the LBL conductor and connector are formed within the gap between isolation trench 335 and the next isolation trench below isolation trench 335.

[0082] In some embodiments, based on offset isolation trenches, at least a portion of the GBL is at least partially aligned with some isolation trenches, or passes over them and further at least partially between isolation trenches (e.g., at least partially aligned with or passing over the spacing between isolation trenches). For example, GBL 360 is at least aligned with the spacing between isolation trench 325 and the next isolation trench below isolation trench 325, and at least partially aligned with the spacing between isolation trench 335 and the next isolation trench below isolation trench 335. Also, GBL 360 is at least partially aligned with or passes over isolation trenches 320 and 330. Similarly, GBL365 is aligned at least to the space between isolation trench 320 and the next isolation trench below isolation trench 320, and at least partially to the space between isolation trench 330 and the next isolation trench below isolation trench 330. Also, GBL365 is at least partially aligned to or passes over the next isolation trench below isolation trench 325 and the next isolation trench below isolation trench 335.

[0083] The staggered arrangement of isolation trenches (e.g., isolation trench 325, isolation trench 330, isolation trench 335) facilitates the formation of a folded bit-line structure. This staggered arrangement makes it possible to arrange memory cells and bit lines in a way that supports a folded bit-line architecture.

[0084] Figure 4 shows details of architecture 400, another example according to one embodiment of the present invention.

[0085] Architecture 400 shows a perspective or oblique view of a stacked memory module. For example, Architecture 400 shows a cross-sectional or side view of a stacked memory module. In particular, Architecture 400 shows a cross-sectional view of folded bit lines based on staggered trench isolation (e.g., staggered capacitive deep trench isolation CDTI). For example, Architecture 400 shows a cross-sectional view of Architecture 300 in Figure 3. In some configurations, one or more aspects of Architecture 400 are carried out by, or in combination with, a manufacturing apparatus configured to form semiconductor manufacturing patterns and components (e.g., based on removal, etching, formation, deposition, etc.).

[0086] In the illustrated example, architecture 400 includes a substrate 405, local bit lines (LBL) 410, connectors (CC) 415 (e.g., a first connector), and capping 420 (e.g., capping material, dielectric capping, semiconductor capping, metal capping, etc.). Architecture 400 also includes connectors (CC) 425 (e.g., a second connector) and LBL 455. As shown, connector 415 is connected to LBL 410. Connector 425 is connected to LBL 455.

[0087] Architecture 400 includes multiple stacks of memory cells formed on top of the substrate 405. A first stack of memory cells is formed on the left side of architecture 400, while a second stack of memory cells is formed on the right side. Each stack contains one or more memory cells.

[0088] The memory cell of architecture 400 includes a semiconductor 430 connected to a capacitor 435. For example, the semiconductor 430 is electrically coupled to the capacitor 435 to form a single memory cell in the first stack.

[0089] In some cases, the semiconductor 430 may be formed adjacent to the gate 440. The gate oxide film 445 separates the semiconductor 430 from the gate 440. The gate 440 is positioned adjacent to the dielectric 450. In some embodiments, the gate 440 may surround the dielectric 450.

[0090] The LBL of architecture 400 includes LBL 410, LBL 455, and LBL conductor 460. The LBL conductor 460 is formed of a conductive material such as metal, semiconductor, or polysilicon. Optionally, LBL 410 may connect a first stack of memory cells (e.g., the left-hand stack including semiconductor 430 and capacitor 435) to connector 415. Similarly, LBL 455 may connect a second stack of memory cells (e.g., the right-hand stack) to connector 425. As shown, the first portion of LBL conductor 460 connects the first stack of memory cells to LBL 410. Similarly, the second portion of LBL conductor 460 connects the second stack of memory cells to LBL 455.

[0091] Architecture 400 is based on a staggered arrangement of capacitive deep trench isolation CDTI, which facilitates the formation of a folded bit-line structure. This staggered arrangement allows for the placement of memory cells and bit lines in a manner that supports the folded bit-line architecture. Staggered CDTI can improve sense margin and noise immunity compared to open bit-line structures. The improvement in sense margin is due to the arrangement of local and global bit lines in the folded configuration. This configuration allows for more efficient routing of signals within the memory array, thereby improving the overall performance of the memory.

[0092] By staggering the placement of isolation trenches, space within the memory architecture can be used more efficiently, improving overall memory performance. Staggered placement of isolation trenches allows for more efficient use of space within the memory architecture, leading to higher density memory designs. In some cases, staggered placement of isolation trenches can relax the process margin at the sense amplifier pitch. Relaxing the process margin improves manufacturing flexibility and yield. In some cases, relaxing the process margin at the sense amplifier pitch can improve integration with core and peripheral transistors. For example, providing more headroom at the sense amplifier pitch allows for a more efficient bonding process when integrating the memory array with other components in a system-on-chip design.

[0093] In some cases, combining a staggered arrangement of isolation trenches with a folded bit line architecture can achieve a memory design that balances performance, density, and manufacturability. These design features interact with each other to address challenges in 3D-DRAM design and improve memory solutions for various applications.

[0094] Figure 5 is a flowchart showing an example of operation method 500 related to a system according to one embodiment of the present invention.

[0095] In some configurations, one or more aspects of the system operation method 500 are carried out by, or in combination with, a manufacturing apparatus configured to form semiconductor manufacturing patterns and components (for example, based on removal, etching, formation, deposition, etc.). The illustrated method 500 is only one embodiment, and one or more operations of method 500 are possible in other embodiments, and rearrangement, reordering, omission, and / or other modifications are intended to encompass such embodiments.

[0096] In step 505, method 500 includes offsetting the isolation trenches. For example, the manufacturing apparatus offsets the position of a first group of isolation trenches relative to the position of a second group of isolation trenches based on a predetermined viewpoint (e.g., a top view) of the stacked memory system. Optionally, the manufacturing apparatus may offset the position of a third group of isolation trenches relative to the position of a fourth group of isolation trenches from the viewpoint of the stacked memory system.

[0097] In step 510, method 500 includes forming a first local bit line at a first angle. For example, the manufacturing apparatus forms a first local bit line at a first angle with respect to a first group of isolation trenches and a second group of isolation trenches.

[0098] In step 515, method 500 includes forming a second local bit line at a second angle. For example, the manufacturing apparatus forms a second local bit line at a second angle different from the first angle with respect to the third and fourth isolation trench groups.

[0099] Figure 6 is a flowchart illustrating the operation method 600 of another example related to the system according to one embodiment of the present invention.

[0100] In some configurations, one or more aspects of the system operation method 600 are carried out by, or in combination with, a manufacturing apparatus configured to form semiconductor manufacturing patterns and components (for example, based on removal, etching, formation, deposition, etc.). The illustrated method 600 is only one embodiment, and one or more operations of method 600 can be rearranged, reordered, omitted, and / or otherwise modified so that other embodiments are possible and such embodiments are intended to be included.

[0101] In step 605, method 600 includes offsetting the isolation trenches. For example, the manufacturing apparatus offsets the position of a first group of isolation trenches relative to the position of a second group of isolation trenches based on a predetermined viewpoint (e.g., a top view) of the stacked memory system.

[0102] In step 610, method 600 includes forming a first local bit line between isolation trenches. For example, the manufacturing apparatus forms a first local bit line between a first isolation trench and a second isolation trench.

[0103] In step 615, method 600 includes forming a second local bit line between isolation trenches. For example, the manufacturing apparatus forms a second local bit line between the third isolation trench and the fourth isolation trench of the second group of isolation trenches.

[0104] In the embodiments described herein, the configurations and operations are exemplary and may include various additional configurations and operations not explicitly illustrated. In some examples, one or more aspects of the illustrated configurations and / or operations may be omitted. In some embodiments, one or more operations may be performed by components other than those illustrated herein. Furthermore, the order and / or temporal order of operations may be changed instead.

[0105] Certain embodiments may be implemented using hardware, firmware, software, or a combination thereof. Other embodiments may be implemented as instructions stored in a computer-readable storage device, which can be read and executed by at least one processor to achieve the operations described herein. A computer-readable storage device may include any non-temporary storage mechanism that stores information in a format that can be read by a machine (e.g., a computer). For example, computer-readable storage devices include read-only memory (ROM), random-access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, and various other storage devices or storage media.

[0106] In this specification, “exemplary” means “an example, a practical example, or an illustrative example.” Embodiments described as “exemplary” in this specification are not necessarily construed as being preferable or advantageous to other embodiments. As used herein, the terms “computing device,” “user device,” “communication station,” “station,” “handheld device,” “mobile device,” “wireless device,” and “user equipment” (UE) refer to wired and / or wireless communication devices such as switches, routers, network interface controllers, mobile phones, smartphones, tablets, netbooks, wireless terminals, laptop computers, femtocells, high data rate (HDR) subscriber stations, access points, printers, POS devices, access terminals, or other personal communication system (PCS) devices. Devices are wireless, wired, mobile, and / or fixed.

[0107] As used herein, the term “communication” means transmission, reception, or both transmission and reception. Similarly, bidirectional data exchange between two devices (in which both devices transmit and receive) is described as “communicating” when only the functionality of one of those devices is requested. As used herein with respect to wired and / or wireless signals, the term “communicating” includes the transmission of such wired and / or wireless signals and / or the reception of such wired and / or wireless signals. For example, a communication unit capable of communicating wired and / or wireless signals includes a wired / wireless transmitter for transmitting communication signals to at least one other communication unit and / or a wired / wireless receiver for receiving communication signals from at least one other communication unit.

[0108] Some embodiments can be used with a variety of devices and systems, such as personal computers (PCs), desktop computers, mobile computers, laptop computers, notebook computers, tablet computers, server computers, handheld computers, handheld devices, personal digital assistant (PDA) devices, handheld PDA devices, onboard devices, offboard devices, hybrid devices, automotive devices, non-automotive devices, mobile or portable devices, consumer devices, non-mobile or non-portable devices, wireless communication stations, wireless communication devices, wireless access points (APs), wired or wireless routers, wired or wireless modems, video devices, audio devices, audio-video (A / V) devices, wired or wireless networks, wireless area networks, wireless video area networks (WVANs), local area networks (LANs), wireless LANs (WLANs), personal area networks (PANs), and wireless PANs (WPANs).

[0109] Some embodiments can be used in combination with, for example, one-way and / or two-way wireless communication systems, cellular radiotelephone communication systems, mobile phones, cellular phones, radiotelephones, personal communication system (PCS) devices, PDA devices incorporating wireless communication devices, mobile or portable Global Positioning System (GPS) devices, GPS receivers, devices incorporating transceivers or chips, devices incorporating RFID elements or chips, multiple input multiple output (MIMO) transceivers or devices, single input multiple output (SIMO) transceivers or devices, multiple input single output (MISO) transceivers or devices, devices having one or more internal and / or external antennas, digital video broadcast (DVB) devices or systems, multistandard wireless devices or systems, wired or wireless handheld devices (e.g., smartphones), wireless application protocol (WAP) devices, etc.

[0110] Some embodiments can be used in combination with one or more types of radio communication signals and / or systems that comply with one or more radio communication protocols. For example, radio frequency (RF), infrared (IR), frequency division multiplexing (FDM), quadrature FDM (OFDM), time division multiplexing (TDM), time division multiple access (TDMA), extended TDMA (E-TDMA), general packet radio service (GPRS), extended GPRS, code division multiple access (CDMA®), broadband CDMA® (WCDMA®), CDMA® 2000, single-carrier CDMA®, and multi-carrier CDMA®. Examples include multi-carrier modulation (MDM), discrete multitone (DMT), Bluetooth®, Global Positioning System (GPS), Wi-Fi, Wi-Max, ZigBee®, ultra-wideband (UWB), Global Mobile Communications System (GSM®), 2G, 2.5G, 3G, 3.5G, 4G, fifth-generation (5G) mobile networks, 3GPP®, Long-Term Evolution (LTE), LTE-Advanced, EDGE (Enhanced Data rates for GSM® Evolution), etc. Other embodiments can be used in various other devices, systems, and / or networks.

[0111] In addition to the exemplary processing systems described above, embodiments and functional operations of the present invention can be implemented in other types of digital electronic circuits, including the structures and structural equivalents disclosed herein, or in computer software, firmware, hardware, or a combination of one or more thereof.

[0112] Embodiments and operations of the present invention can be implemented in digital electronic circuits, computer software, firmware, hardware, or one or more combinations thereof, including structures and structural equivalents thereof disclosed herein. Embodiments of the present invention can be implemented as one or more computer programs, that is, the computer programs can be implemented as one or more components of computer program instructions encoded on a computer storage medium to be executed by an information / data processing device or to control the operation of such device. Alternatively, the program instructions can be encoded into artificially generated propagating signals, such as mechanically generated electrical, optical, or electromagnetic signals, which are generated to encode information / data to be transmitted to a suitable receiving device for execution by an information / data processing device. The computer storage medium is a computer-readable storage device, a computer-readable storage board, a random-access or serial-access memory array or device, or one or more combinations thereof, or includes them. Furthermore, the computer storage medium is not a propagating signal itself, but can be a source or destination of computer program instructions encoded into artificially generated propagating signals. Furthermore, computer storage media may consist of one or more separate physical components or media (e.g., multiple CDs, disks, or other storage devices), or be contained within them.

[0113] The operations described herein can be performed by an information / data processing device on information / data stored in one or more computer-readable storage devices, or on information / data received from other sources.

[0114] The term "data processing device" encompasses all types of devices, machines, and equipment for processing data, including, for example, programmable processors, computers, systems on a chip, or a combination thereof. Such devices may include, for example, special-purpose logic circuits such as FPGAs and ASICs. In addition to hardware, such devices may include code that constitutes the execution environment for the computer program. This may include, for example, code that constitutes processor firmware, protocol stacks, database management systems, operating systems, cross-platform execution environments, virtual machines, or a combination of one or more of these. Such devices and execution environments realize various computing model foundations, such as web services, distributed computing, and grid computing infrastructure.

[0115] Computer programs (also known as programs, software, software applications, scripts, or code) are written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and are deployed in any form, such as standalone programs or as components, subroutines, objects, or other units suitable for use in a computing environment. Computer programs correspond to, but do not necessarily correspond to, files in a file system. Programs are stored in part of files that hold other programs or information / data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program, or in multiple related files (e.g., files containing one or more components, subprograms, or parts of code). Computer programs are deployed to run on one computer, on multiple computers located in the same location, or on multiple computers distributed across multiple locations and interconnected by a communication network.

[0116] The processes and logical flows described herein can be executed by one or more programmable processors running one or more computer programs, processing input information / data and producing output. Processors suitable for executing computer programs include, for example, general-purpose microprocessors and special-purpose microprocessors, as well as one or more processors in any type of digital computer. Generally, a processor receives instructions and information / data from read-only memory, random-access memory, or both. Essential elements of a computer include a processor for performing operations according to instructions and one or more memory devices for storing instructions and data. Generally, a computer includes one or more mass storage devices for storing data, such as magnetic disks, magneto-optical disks, or optical disks. Alternatively, the computer may be operablely coupled to receive information / data from these mass storage devices, transfer information / data, or both. However, a computer does not necessarily have to have such devices. Devices suitable for storing computer program instructions and information / data include all forms of non-volatile memory, media, and memory devices, such as semiconductor memory devices like EPROMs, EEPROMs, and flash memory devices; magnetic disks like internal hard disks or removable disks; magneto-optical disks; and CD-ROMs and DVD-ROMs. Processors and memory are complemented by or incorporated into special-purpose logic circuits.

[0117] To provide user interaction, embodiments of the present invention are implemented on a computer having a display device for displaying information / data to the user, such as a CRT (cathode ray tube) or LCD (liquid crystal display) monitor, and a keyboard and pointing device for the user to input into the computer, such as a mouse or trackball. Other types of devices may be used to provide user interaction. For example, the feedback provided to the user may be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback. Input from the user may be received in any form, including acoustic input, voice input, or tactile input. Furthermore, the computer interacts with the user by sending documents to and receiving documents from a device used by the user. For example, it interacts with the user by sending a web page to a web browser on the user's client device in response to a request received from a web browser.

[0118] Embodiments of the present invention are implemented in a computing system. The computing system includes, for example, a backend component as an information / data server; or, for example, a middleware component as an application server; and further includes a frontend component such as a client computer having a graphical user interface or a web browser on which a user can interact with the embodiment of the present invention; or includes one or more combinations of these backend, middleware, or frontend components. The components of the system are interconnected by any form or medium of digital information / data communication, such as a communication network. Examples of communication networks include local area networks (LANs), wide area networks (WANs), internetworks (e.g., the Internet), and peer-to-peer networks (e.g., ad-hoc peer-to-peer networks).

[0119] A computing system includes a client and a server. The client and server are generally located in separate locations and typically interact with each other via a communication network. The client-server relationship is based on the fact that computer programs running on each computer have a client-server relationship with each other. In some embodiments, the server transmits information / data (e.g., an HTML page) to the client device. (For example, this is for the purpose of displaying information / data to a user interacting with the client device and receiving input from that user.) Information / data generated by the client device (e.g., the result of interaction with the user) is received by the server from the client device.

[0120] While this specification provides details of many specific embodiments, these should not be interpreted as limitations on the scope of any embodiment or claims, but rather as descriptions of features specific to particular embodiments. Certain features described herein in the context of separate embodiments may be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may be implemented individually or in any suitable subcombination in multiple embodiments. Furthermore, features are described above as acting in certain combinations, and may even be initially claimed as such; however, one or more features from a claimed combination may, in some cases, be removed from that combination, and the claimed combination may relate to a subcombination or a variation of a subcombination.

[0121] Similarly, although the operations are depicted in a specific order in the diagrams, this should not be understood as requiring that such operations be performed in a specific or sequential order as shown, or that all illustrated operations be performed, in order to achieve a favorable result. In some situations, multitasking or parallel processing may be advantageous. Furthermore, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated in a single software product or packaged in multiple software products.

[0122] In this manner, specific embodiments of the present invention have been described. Other embodiments are within the scope of the claims. In some cases, the operations described in the claims may be performed in a different order to obtain the desired results. Furthermore, the steps shown in the drawings do not necessarily have to be performed in the specific illustrated order or sequential order to obtain the desired results. In certain embodiments, multitasking and parallel processing may be advantageous.

[0123] Many of the modifications and other examples described herein can be readily conceived by those skilled in the art relating to these embodiments who benefit from the teachings presented in the above description and the accompanying drawings. Therefore, the embodiments should not be limited to any particular embodiment disclosed, and variations and other embodiments should be understood as being intended to be included within the claims. Certain terms are used herein, but these are used in a general and descriptive sense only and are not intended to be limiting. Numerous examples have been described; however, it should be understood that various modifications may be made without departing from the spirit and scope of the invention. Therefore, additional embodiments are included within the claims. [Explanation of symbols]

[0124] 100, 200, 300 Architectures 105, 205, 305, 405 substrates 110, 115, 310, 315 Sense Amplifier (SA) 120, 125, 130, 135, 320, 325, 330, 335 Isolation Trench 140, 145, 210, 410, 455 Local Bit Lines (LBL) 150, 350 First connector 155, 355 Second connector 160, 165, 170, 175, 360, 365, 370, 375 Global Bit Lines (GBL) 215, 415, 425 connectors (CC) 220, 225, 420 capping 230, 430 Semiconductors 235, 435 Capacitors 240, 440 gates 245, 445 gate oxides 250, 450 dielectric 340, 345, 460 LBL conductors CC0, CC1 CDTI Staggered Capacitive Deep Trench Isolation CM1, CM2

Claims

1. A stacked memory device, The first isolation trench group and the second isolation trench group, A first local bit line formed at a first angle with respect to the orientation of the first isolation trench group and the second isolation trench group, The third isolation trench group and the fourth isolation trench group, The system comprises a second local bit line formed at a second angle different from the first angle with respect to the orientation of the third isolation trench group and the fourth isolation trench group, The position of the first isolation trench group is offset from the position of the second isolation trench group. A stacked memory device characterized in that the position of the third isolation trench group is offset from the position of the fourth isolation trench group.

2. The stacked memory device according to claim 1, characterized in that the first angle of the first local bit line is in the range of 10 to 80 degrees with respect to the orientation of the first isolation trench group and the second isolation trench group which are oriented at zero angle.

3. The first connector connects the first local bit line to the first global bit line. The first global bit line connects the first local bit line to the first sense amplifier. The stacked memory device according to claim 2, characterized in that the first global bit line is arranged at zero angle.

4. The stacked memory device according to claim 1, characterized in that the second angle of the second local bit line is in the range of 100 to 170 degrees with respect to the orientation of the third isolation trench group and the fourth isolation trench group which are oriented at zero angle.

5. The second connector connects the second local bit line to the second global bit line. The second global bit line connects the second local bit line to the second sense amplifier. The stacked memory device according to claim 4, characterized in that the second global bit line is arranged at zero angle.

6. The stacked memory device according to claim 1, characterized in that the first portion of the first local bit line is formed between the first isolation trench and the second isolation trench of the first isolation trench group.

7. The stacked memory device according to claim 1, characterized in that the second portion of the first local bit line is formed between the third isolation trench and the fourth isolation trench of the second isolation trench group.

8. The stacked memory device according to claim 1, characterized in that the first local bit line is connected to the first memory cell array and the second memory cell array.

9. A stacked memory device, The first isolation trench group and the second isolation trench group, A first local bit line formed between the first isolation trench and the second isolation trench of the first isolation trench group, The second local bit line is formed between the third isolation trench and the fourth isolation trench of the second isolation trench group, A stacked memory device characterized in that the position of the first isolation trench group is offset from the position of the second isolation trench group.

10. The stacked memory device according to claim 9, characterized in that the position of the first local bit line is offset with respect to the position of the second local bit line.

11. The stacked memory device according to claim 9, characterized in that the angle between the first local bit line and the second local bit line is in the range of 10 to 80 degrees with respect to the orientation of the first isolation trench group and the second isolation trench group which are oriented at zero angle.

12. The first connector connects the first local bit line to the first global bit line. The stacked memory device according to claim 9, characterized in that the first global bit line connects the first local bit line to the first sense amplifier.

13. The first global bit line is at least partially located between the first isolation trench and the second isolation trench. The stacked memory device according to claim 12, characterized in that the first global bit line is arranged at zero angle.

14. The second connector connects the second local bit line to the second global bit line. The stacked memory device according to claim 9, characterized in that the second global bit line connects the second local bit line to the second sense amplifier.

15. The second global bit line is at least partially located between the third isolation trench and the fourth isolation trench. The stacked memory device according to claim 14, characterized in that the second global bit line is arranged at zero angle.

16. The first local bit line is connected to the first memory cell array, The stacked memory device according to claim 9, characterized in that the second local bit line is connected to the second memory cell array.

17. A method for operating a stacked memory device, The steps include offsetting the position of the first isolation trench group relative to the position of the second isolation trench group, The steps include forming a first local bit line at a first angle with respect to the orientation of the first isolation trench group and the second isolation trench group, The steps include offsetting the position of the third isolation trench group relative to the position of the fourth isolation trench group, A method characterized by comprising the step of forming a second local bit line at a second angle different from the first angle with respect to the orientation of the third isolation trench group and the fourth isolation trench group.

18. The method according to 17, characterized in that the first angle of the first local bit line is in the range of 10 to 80 degrees with respect to the orientation of the first isolation trench group and the second isolation trench group which are oriented at zero angle.

19. The first connector connects the first local bit line to the first global bit line. The first global bit line connects the first local bit line to the first sense amplifier. The method according to 17, characterized in that the first global bit line is positioned at zero angle.

20. The method according to 17, characterized in that the second angle of the second local bit line is in the range of 100 to 170 degrees with respect to the orientation of the third isolation trench group and the fourth isolation trench group which are oriented at zero angle.

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