Semiconductor equipment

Abstract

To provide a semiconductor device capable of suppressing the decrease in dielectric breakdown voltage. [Solution] The semiconductor device of the embodiment comprises an element region and a termination region surrounding the element region. The element region includes a first electrode, a second electrode, a silicon carbide layer having a first surface and a second surface, and a gate electrode. The terminal region includes a silicon carbide layer comprising: a first silicon carbide region of a first conductivity type including a first region and a second region; a fifth silicon carbide region of a second conductivity type between the second region and the first surface; a plurality of sixth silicon carbide regions of a second conductivity type located in a first direction toward the terminal region from the element region relative to the fifth silicon carbide region and spaced apart from each other; a seventh silicon carbide region of a second conductivity type between the first region and the second region; an eighth silicon carbide region of a second conductivity type located in a first direction relative to the seventh silicon carbide region; and a ninth silicon carbide region of a second conductivity type located in a first direction relative to the sixth silicon carbide region between the second region and the first surface.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] In a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) using silicon carbide, for example, a termination region is provided around the element region containing the transistor. The termination region reduces the intensity of the electric field applied to the termination of the pn junction of the element region when the MOSFET is in the off state. The termination region also has the function of improving the dielectric breakdown voltage of the MOSFET.

[0003] During MOSFET operation, charges may be trapped, for example, in the insulating layer above the termination region. These charges may be, for example, electrons or holes injected from within the silicon carbide, or mobile ions entering from outside the MOSFET.

[0004] If charges are trapped in the insulating layer above the termination region, the electric field distribution in the termination region changes, which can reduce the dielectric breakdown voltage of the MOSFET. A decrease in the dielectric breakdown voltage of the MOSFET reduces its reliability. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2023-140891 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] The problem that this invention aims to solve is to provide a semiconductor device that can suppress the decrease in dielectric breakdown voltage. [Means for solving the problem]

[0007] The semiconductor device of the embodiment comprises an element region and a termination region surrounding the element region, the element region comprising a first electrode, a second electrode, and a silicon carbide layer provided between the first electrode and the second electrode, having a first surface on the side of the first electrode and a second surface on the side of the second electrode, the first silicon carbide region having a first conductivity type including a first region and a second region provided between the first region and the first surface, the second silicon carbide region having a second conductivity type provided between the second region and the first surface and electrically connected to the first electrode, and the second silicon carbide A silicon carbide layer comprising: a third silicon carbide region of a first conductivity type provided between the silicon carbide region and the first surface and electrically connected to the first electrode; a fourth silicon carbide region of a second conductivity type provided between the first region and the second region; a gate electrode provided within the silicon carbide layer and facing the fourth silicon carbide region, the second region, the second silicon carbide region, and the third silicon carbide region; and a gate insulating layer provided between the gate electrode and the silicon carbide layer, wherein the termination region comprises the second electrode and the first region and the second region The first silicon carbide region comprising the first silicon carbide region, a fifth silicon carbide region of second conductivity type provided between the second region and the first surface and electrically connected to the first electrode, a plurality of sixth silicon carbide regions of second conductivity type provided between the second region and the first surface, located in a first direction toward the terminal region from the element region relative to the fifth silicon carbide region, separated from the fifth silicon carbide region, and separated from each other in the first direction, and a seventh silicon carbide region of second conductivity type provided between the first region and the second region and electrically connected to the first electrode The silicon carbide layer includes a silicon region, at least one eighth silicon carbide region of a second conductivity type provided between the first region and the second region, located in the first direction relative to the seventh silicon carbide region and separated from the seventh silicon carbide region, and at least one ninth silicon carbide region of a second conductivity type provided between the second region and the first surface, located in the first direction relative to the sixth silicon carbide region and separated from the sixth silicon carbide region, wherein the first position of the end of the seventh silicon carbide region in the first direction opposite to the element region isThe third position of the end of the fifth silicon carbide region in the first direction opposite to the element region is located closer to the element region than the second position of the end of the fifth silicon carbide region in the first direction opposite to the element region, and the third position of the end of the eighth silicon carbide region in the first direction opposite to the element region, which is the furthest from the element region in the first direction among the at least one eight silicon carbide region, is located closer to the element region than the fourth position of the end of the sixth silicon carbide region in the first direction opposite to the element region, which is the furthest from the element region in the first direction among the sixth silicon carbide region, and the third position is the second furthest from the element region in the first direction among the sixth silicon carbide region The silicon region is located further from the element region in the first direction than the fifth position of the end of the silicon region in the first direction opposite to the element region, and the first distance between the 9th silicon carbide region, which is closest to the element region in the first direction among the at least one 9th silicon carbide region, and the 6th silicon carbide region, which is furthest from the element region in the first direction among the 6th silicon carbide region, is smaller than the second distance between the 6th silicon carbide region, which is furthest from the element region in the first direction among the 6th silicon carbide region, and the 6th silicon carbide region, which is second furthest from the element region in the first direction among the 6th silicon carbide region. [Brief explanation of the drawing]

[0008] [Figure 1] A schematic top view of the semiconductor device according to the first embodiment. [Figure 2] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 3] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 4] A schematic cross-sectional view of the semiconductor device of the first comparative example. [Figure 5] A schematic cross-sectional view of the semiconductor device of the second comparative example. [Figure 6] A schematic cross-sectional view of the semiconductor device according to the second embodiment. [Figure 7] A schematic cross-sectional view of a semiconductor device according to the third embodiment.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members are denoted by the same reference numerals, and the description of the members once described may be omitted as appropriate.

[0010] Also, in the following description, n + 、n、n - and, p + 、p、p - If there is such notation, those notations represent the relative high and low of the impurity concentration in each conductivity type. That is, n + has a relatively higher n-type impurity concentration than n, and n - has a relatively lower n-type impurity concentration than n. Also, p + has a relatively higher p-type impurity concentration than p, and p - has a relatively lower p-type impurity concentration than p. Note that n + type, n - type may be simply described as n-type, p + type, p - type may be simply described as p-type.

[0011] In this specification, unless otherwise specified, "impurity concentration" means the concentration obtained by compensating for the concentration of impurities of the opposite conductivity type. That is, the n-type impurity concentration in the n-type silicon carbide region means the concentration obtained by subtracting the p-type impurity concentration from the n-type impurity concentration. Also, the p-type impurity concentration in the p-type silicon carbide region means the concentration obtained by subtracting the n-type impurity concentration from the p-type impurity concentration. In this specification, unless otherwise specified, the "impurity concentration in the silicon carbide region" is the maximum impurity concentration in the corresponding silicon carbide region.

[0012] Impurity concentrations can be measured, for example, by Secondary Ion Mass Spectrometry (SIMS). The relative levels of impurity concentrations can also be determined, for example, from the carrier concentrations obtained by Scanning Capacitance Microscopy (SCM). Furthermore, distances such as depth and thickness of impurity regions can be determined, for example, by SIMS or Scanning Electron Microscope (SEM). Additionally, distances such as depth, thickness, width, and spacing of impurity regions can be determined, for example, from a composite image of SCM and Atomic Force Microscope (AFM) images.

[0013] (First embodiment) The semiconductor device of the first embodiment comprises an element region and a termination region surrounding the element region. The element region comprises a first electrode, a second electrode, and a silicon carbide layer provided between the first electrode and the second electrode, having a first surface on the side of the first electrode and a second surface on the side of the second electrode, comprising a first silicon carbide region of a first conductivity type including the first region and a second region provided between the first region and the first surface, a second silicon carbide region of a second conductivity type provided between the second region and the first surface and electrically connected to the first electrode, and a second silicon carbide layer The silicon carbide layer includes a third silicon carbide region of a first conductivity type provided between an elementary region and a first surface and electrically connected to a first electrode, and a fourth silicon carbide region of a second conductivity type provided between the first region and a second region; a gate electrode provided within the silicon carbide layer and facing the fourth silicon carbide region, the second region, the second silicon carbide region, and the third silicon carbide region; and a gate insulating layer provided between the gate electrode and the silicon carbide layer. The termination region comprises a second electrode, a first silicon carbide region including the first region and the second region, a fifth silicon carbide region of second conductivity type provided between the second region and the first surface and electrically connected to the first electrode, a plurality of sixth silicon carbide regions of second conductivity type provided between the second region and the first surface, located in a first direction toward the termination region from the element region relative to the fifth silicon carbide region, separated from the fifth silicon carbide region, and separated from each other in the first direction, and provided between the first region and the second region. The silicon carbide layer includes: a seventh silicon carbide region of a second conductivity type electrically connected to a first electrode; at least one eighth silicon carbide region of a second conductivity type provided between the first region and the second region, located in a first direction relative to the seventh silicon carbide region and separated from the seventh silicon carbide region; and at least one ninth silicon carbide region of a second conductivity type provided between the second region and the first surface, located in a first direction relative to the sixth silicon carbide region and separated from the sixth silicon carbide region.The first position of the end of the seventh silicon carbide region in the first direction opposite to the element region is located closer to the element region than the second position of the end of the fifth silicon carbide region in the first direction opposite to the element region, and the third position of the end of the eighth silicon carbide region in the first direction opposite to the element region, which is furthest from the element region in the first direction among at least one eighth silicon carbide region, is located closer to the element region than the fourth position of the end of the sixth silicon carbide region in the first direction opposite to the element region, which is furthest from the element region in the first direction among the sixth silicon carbide region, and the third position is the second in the first direction among the sixth silicon carbide region The 6th silicon carbide region is located further from the element region in the first direction than the 5th position at the end of the 6th silicon carbide region in the first direction opposite to the element region, and the 1st distance between the 9th silicon carbide region that is closest to the element region in the first direction among at least one of the 9th silicon carbide regions and the 6th silicon carbide region that is furthest from the element region in the first direction among the 6th silicon carbide regions is smaller than the 2nd distance between the 6th silicon carbide region that is furthest from the element region in the first direction among the 6th silicon carbide regions and the 6th silicon carbide region that is second furthest from the element region in the first direction among the 6th silicon carbide regions.

[0014] Figure 1 is a schematic top view of a semiconductor device according to the first embodiment. Figure 1 shows the layout patterns of the element region and the termination region.

[0015] Figures 2 and 3 are schematic cross-sectional views of the semiconductor device according to the first embodiment. Figure 2 is the AA' cross-section shown in Figure 1. Figure 3 is the BB' cross-section shown in Figure 1.

[0016] The semiconductor device of the first embodiment is a vertical MOSFET 100 using silicon carbide. The MOSFET 100 is a Double Implantation MOSFET (DIMOSFET) in which the base region and source region are formed by ion implantation, for example. The MOSFET 100 is a trench-gate type MOSFET in which the gate electrode is provided in a trench.

[0017] The following explanation will use the case where the first conductivity type is n-type and the second conductivity type is p-type as an example. MOSFET100 is a vertical n-channel MOSFET that uses electrons as carriers.

[0018] The MOSFET 100 comprises a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate electrode 16, a gate insulating layer 18, a conductive layer 20, a trench insulating layer 22 (insulating layer), a field insulating layer 24, and an interlayer insulating layer 26.

[0019] The silicon carbide layer 10 is n + Drain region 30 of type n, drift region 32 of type n (first silicon carbide region), cell base region 34 of type p (second silicon carbide region), n + Source region 36 of the shape (third silicon carbide region), p + Shaped cell contact area 38, p + The cell bottom region 40 of the p-shape (fourth silicon carbide region), the terminal base region 42 of the p-shape (fifth silicon carbide region), the upper guard ring region 44 of the p-shape (sixth silicon carbide region), p + The terminal bottom region 46 of the shape (the 7th silicon carbide region), p + Lower guard ring region 48 of the shape (8th silicon carbide region), outer guard ring region 50 of the p shape (9th silicon carbide region), p + Shaped terminal contact region 52, p + The structure includes a connection region 54 (the 10th silicon carbide region), a gate trench 56, and a terminal trench 58.

[0020] The drift region 32 includes a lower region 32a (first region) and an upper region 32b (second region). The upper guard ring region 44 includes a first upper guard ring region 44a, a second upper guard ring region 44b, a third upper guard ring region 44c, and a fourth upper guard ring region 44d. The lower guard ring region 48 includes a first lower guard ring region 48a, a second lower guard ring region 48b, a third lower guard ring region 48c, a fourth lower guard ring region 48d, and a fifth lower guard ring region 48e. The outer perimeter guard ring region 50 includes a first outer perimeter guard ring region 50a, a second outer perimeter guard ring region 50b, and a third outer perimeter guard ring region 50c.

[0021] The MOSFET 100 comprises an element region 101 and a termination region 102. The termination region 102 surrounds the element region 101. The termination region 102 is located outside the element region 101. The element region 101 is located inside the termination region 102.

[0022] The element region 101 includes multiple transistors. The termination region 102 reduces the intensity of the electric field applied to the termination of the pn junction of the element region 101 when the transistors are in the off state. The termination region 102 has the function of improving the dielectric breakdown voltage of the MOSFET 100.

[0023] The element region 101 comprises a silicon carbide layer 10, a source electrode 12, a drain electrode 14, a gate electrode 16, a gate insulating layer 18, and an interlayer insulating layer 26.

[0024] The silicon carbide layer 10 of the element region 101 is n + Drain region 30 of type n, drift region 32 of type n (first silicon carbide region), cell base region 34 of type p (second silicon carbide region), n + Source region 36 of the shape (third silicon carbide region), p + Shaped cell contact area 38, p + The cell bottom region 40 (fourth silicon carbide region) includes a gate trench 56.

[0025] The terminal region 102 comprises a silicon carbide layer 10, a source electrode 12, a drain electrode 14, a conductive layer 20, a trench insulating layer 22, a field insulating layer 24, and an interlayer insulating layer 26.

[0026] The silicon carbide layer 10 in the terminal region 102 is n + Drain region 30 of type n, drift region 32 of type n (first silicon carbide region), terminal base region 42 of type p (fifth silicon carbide region), upper guard ring region 44 of type p (sixth silicon carbide region), p + The terminal bottom region 46 of the shape (the 7th silicon carbide region), p + Lower guard ring region 48 of the shape (8th silicon carbide region), outer guard ring region 50 of the p shape (9th silicon carbide region), p + Shaped terminal contact region 52, p + The shape includes a connection region 54 (the 10th silicon carbide region) and a terminal trench 58.

[0027] The silicon carbide layer 10 is provided between the source electrode 12 and the drain electrode 14. The silicon carbide layer 10 is single-crystal SiC. For example, the silicon carbide layer 10 is 4H-SiC.

[0028] The silicon carbide layer 10 comprises a first surface ("F1" in Figures 2 and 3) and a second surface ("F2" in Figures 2 and 3). The first surface F1 is the surface of the silicon carbide layer. The second surface F2 is the back surface of the silicon carbide layer. Hereinafter, the first surface F1 may be referred to as the surface and the second surface F2 as the back surface. The first surface F1 is located on the source electrode 12 side of the silicon carbide layer 10. The second surface F2 is located on the drain electrode 14 side of the silicon carbide layer 10. The first surface F1 and the second surface F2 face each other. Hereinafter, "depth" refers to the depth in the direction toward the second surface with respect to the first surface. The "surfaces" of the first surface F1 and the second surface F2 refer to, for example, the interface between the silicon carbide layer and the insulating film, or between the silicon carbide layer and the metal.

[0029] A direction parallel to the first plane is defined as the first direction. The first direction is the direction from the element region 101 toward the termination region 102. A direction parallel to the first plane and perpendicular to the first direction is defined as the second direction.

[0030] The first surface F1 is, for example, a surface inclined at an angle of 0 to 8 degrees relative to the (0001) surface. The second surface F2 is, for example, a surface inclined at an angle of 0 to 8 degrees relative to the (000-1) surface. The (0001) surface is referred to as the silicon surface. The (000-1) surface is referred to as the carbon surface.

[0031] The thickness of the silicon carbide layer 10 is, for example, 5 μm to 350 μm.

[0032] n + The drain region 30 is provided on the back side of the silicon carbide layer 10. The drain region 30 contains, for example, nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the drain region 30 is, for example, 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0033] An n-shaped drift region 32 is provided between the drain region 30 and the first surface F1. An n-shaped drift region 32 is provided between the source electrode 12 and the drain electrode 14. An n-shaped drift region 32 is provided between the gate electrode 16 and the drain electrode 14. An n-shaped drift region 32 is provided on the drain region 30.

[0034] The drift region 32 functions as a current path, for example, when the MOSFET 100 is ON. Furthermore, the drift region 32 has the function of forming a depletion layer and maintaining the dielectric breakdown voltage when the MOSFET 100 is OFF.

[0035] The drift region 32 contains, for example, nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the drift region 32 is lower than the concentration of n-type impurities in the drain region 30. The concentration of n-type impurities in the drift region 32 is, for example, 4 × 10⁻⁶. 14 cm -3 The above 5 x 10 17 cm -3 The following applies: The thickness of the drift region 32 is, for example, between 3 μm and 100 μm.

[0036] The drift region 32 includes a lower region 32a and an upper region 32b. The upper region 32b is located between the lower region 32a and the first surface F1. The n-type impurity concentration in the upper region 32b is, for example, higher than the n-type impurity concentration in the lower region 32a. The n-type impurity concentration in the upper region 32b may be, for example, substantially equal to the n-type impurity concentration in the lower region 32a.

[0037] The depth of the upper region 32b is, for example, between 0.5 μm and 2 μm.

[0038] The p-shaped cell base region 34 is provided between the drift region 32 and the first surface F1. The cell base region 34 is provided between the upper region 32b and the first surface F1.

[0039] The cell base region 34 functions, for example, as the channel region of the MOSFET 100.

[0040] A portion of the cell base region 34 faces the gate electrode 16. A gate insulating layer 18 is sandwiched between the portion of the cell base region 34 and the gate electrode 16.

[0041] The cell base region 34 contains, for example, aluminum (Al) as a p-type impurity. The concentration of p-type impurities in the cell base region 34 is, for example, 5 × 10⁻⁶ 16 cm -3 The above 1 x 10 19 cm -3 The following applies:

[0042] The cell base region 34 is electrically connected to the source electrode 12. The cell base region 34 is fixed at the potential of the source electrode 12.

[0043] n + The source region 36 of the shape is provided between the cell base region 34 and the first surface F1. The source region 36 extends, for example, in a second direction.

[0044] The source region 36 contains, for example, phosphorus (P) or nitrogen (N) as n-type impurities. The concentration of n-type impurities in the source region 36 is higher than the concentration of n-type impurities in the drift region 32. The concentration of n-type impurities in the source region 36 is, for example, 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0045] The source region 36 is physically and electrically connected to the source electrode 12. The contact between the source region 36 and the source electrode 12 is, for example, an ohmic contact. The source region 36 is fixed at the potential of the source electrode 12.

[0046] p + The shaped cell contact region 38 is provided between the cell base region 34 and the first surface F1. The cell contact region 38 is in contact with the cell base region 34. The cell contact region 38 extends, for example, in a second direction.

[0047] The cell contact region 38 contains, for example, aluminum (Al) as a p-type impurity. The concentration of p-type impurities in the cell contact region 38 is higher than the concentration of p-type impurities in the cell base region 34. The concentration of p-type impurities in the cell contact region 38 is, for example, 1 × 10⁻⁶. 19 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0048] The cell contact region 38 is physically and electrically connected to the source electrode 12. The contact between the cell contact region 38 and the source electrode 12 is, for example, an ohmic contact. The cell contact region 38 is fixed to the potential of the source electrode 12.

[0049] p +The cell bottom region 40 is located between the lower region 32a and the upper region 32b. The cell bottom region 40 is located between the gate trench 56 and the lower region 32a. The cell bottom region 40 is in contact with the gate trench 56. The cell bottom region 40 extends, for example, in a second direction.

[0050] The cell bottom region 40 has the function of mitigating the intensity of the electric field applied to the gate insulating layer 18 at the bottom of the gate trench 56 when the MOSFET 100 is in the off state.

[0051] The cell bottom region 40 contains, for example, aluminum (Al) as a p-type impurity. The concentration of p-type impurities in the cell bottom region 40 is higher than the concentration of p-type impurities in the cell base region 34. The concentration of p-type impurities in the cell bottom region 40 is, for example, 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0052] The gate trench 56 is provided on the side of the first surface F1 of the silicon carbide layer 10. The gate trench 56 is a groove provided in the silicon carbide layer 10. The gate trench 56 is part of the silicon carbide layer 10.

[0053] The gate trench 56 extends, for example, in a second direction on the first surface F1. The gate trench 56 is repeatedly provided, for example, in a first direction on the first surface F1.

[0054] The gate trench 56 is in contact with, for example, the cell bottom region 40, the upper region 32b, the cell base region 34, and the source region 36.

[0055] The depth of the gate trench 56 is, for example, between 0.5 μm and 2 μm.

[0056] The gate electrode 16 is located within the gate trench 56. The gate electrode 16 faces the cell bottom region 40, the upper region 32b, the cell base region 34, and the source region 36. For example, in a first direction, the gate electrode 16 is located between a portion of the cell base region 34 and another portion of the cell base region 34.

[0057] The gate electrode 16 extends, for example, in a second direction. Multiple gate electrode 16s are arranged, for example, parallel to each other in a first direction. The gate electrode 16 has, for example, a stripe shape.

[0058] The gate electrode 16 is a conductor. The gate electrode 16 is, for example, polycrystalline silicon containing p-type or n-type impurities.

[0059] The gate insulating layer 18 is provided between the gate electrode 16 and the silicon carbide layer 10. The gate insulating layer 18 is provided between the gate electrode 16 and the cell bottom region 40. The gate insulating layer 18 is provided between the gate electrode 16 and the upper region 32b. The gate insulating layer 18 is provided between the gate electrode 16 and the cell base region 34. The gate insulating layer 18 is provided between the gate electrode 16 and the source region 36.

[0060] The gate insulating layer 18 is an insulator. For example, the gate insulating layer 18 is silicon oxide. For example, a high-k insulating material (high dielectric constant insulating material) can be used for the gate insulating layer 18.

[0061] The interlayer insulating layer 26 is provided on the gate electrode 16 and the silicon carbide layer 10. The interlayer insulating layer 26 is, for example, silicon oxide.

[0062] The interlayer insulating layer 26 has the function of electrically isolating the gate electrode 16 and the source electrode 12, for example.

[0063] The p-type termination base region 42 is provided between the upper region 32b and the first surface F1. A portion of the termination base region 42 is in contact with the first surface F1. A portion of the termination base region 42 is in contact with, for example, the interlayer insulating layer 26 or the field insulating layer 24. The termination base region 42 is in contact with, for example, the upper region 32b.

[0064] The termination base region 42, for example, surrounds the element region 101 on the first plane F1. The termination base region 42, for example, is annular on the first plane F1. The termination base region 42, for example, surrounds the cell base region 34 and the source region 36 on the first plane F1.

[0065] The termination base region 42 has the function of mitigating the intensity of the electric field applied to the termination of the pn junction of the element region 101 when the MOSFET 100 is in the off state.

[0066] The terminal base region 42 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration in the terminal base region 42 is substantially equal to, for example, the p-type impurity concentration in the cell base region 34. The p-type impurity concentration in the terminal base region 42 is, for example, 5 × 10⁻⁶ 16 cm -3 The above 1 x 10 19 cm -3 The following applies:

[0067] The terminal base region 42 is electrically connected to the source electrode 12. The terminal base region 42 is fixed at the potential of the source electrode 12.

[0068] The terminal base region 42 is formed, for example, by the same manufacturing process using the same mask pattern as the cell base region 34.

[0069] p + The terminal contact region 52 is provided between the terminal base region 42 and the first surface F1. The terminal contact region 52 is in contact with the terminal base region 42.

[0070] The terminal contact region 52 contains, for example, aluminum (Al) as a p-type impurity. The concentration of p-type impurities in the terminal contact region 52 is higher than the concentration of p-type impurities in the terminal base region 42. The concentration of p-type impurities in the terminal contact region 52 is, for example, 1 × 10⁻⁶. 19 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0071] The terminal contact region 52 is physically and electrically connected to the source electrode 12. The contact between the terminal contact region 52 and the source electrode 12 is, for example, an ohmic contact. The terminal contact region 52 is fixed at the potential of the source electrode 12.

[0072] Multiple p-shaped upper guard ring regions 44 are provided between the upper region 32b and the first surface F1. The upper guard ring regions 44 are in contact with, for example, the first surface F1. The upper guard ring regions 44 are in contact with, for example, the field insulating layer 24. The upper guard ring regions 44 are in contact with, for example, the upper region 32b.

[0073] The upper guard ring region 44 is located in a first direction relative to the terminal base region 42. The upper guard ring region 44 is spaced apart from the terminal base region 42. The upper guard ring regions 44 are spaced apart from each other in a first direction. Figure 3 illustrates the case where there are four upper guard ring regions 44, but there may be two, three, or five or more upper guard ring regions 44.

[0074] The upper guard ring region 44 surrounds the element region 101 on the first surface F1, for example. The upper guard ring region 44 is annular on the first surface F1, for example. The upper guard ring region 44 surrounds the terminal base region 42 on the first surface F1, for example.

[0075] The upper guard ring region 44 has the function of mitigating the intensity of the electric field applied to the end of the termination base region 42 when the MOSFET 100 is in the off state.

[0076] When three or more upper guard ring regions 44 are provided, for example, the distance between two adjacent upper guard ring regions 44 in the first direction increases in the direction of the first. For example, the second distance (d2 in Figure 3) between the fourth upper guard ring region 44d and the third upper guard ring region 44c is greater than the third distance (d3 in Figure 3) between the third upper guard ring region 44c and the second upper guard ring region 44b. Similarly, the third distance (d3 in Figure 3) between the third upper guard ring region 44c and the second upper guard ring region 44b is greater than, for example, the distance between the second upper guard ring region 44b and the first upper guard ring region 44a.

[0077] Furthermore, it is also possible to make the distance between two adjacent upper guard ring regions 44 in the first direction substantially equal.

[0078] The width of the upper guard ring region 44 in the first direction is, for example, 0.5 μm or more and 4 μm or less. The distance between two adjacent upper guard ring regions 44 in the first direction is, for example, 0.5 μm or more and 4 μm or less.

[0079] The upper guard ring region 44 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration in the upper guard ring region 44 is substantially equal to, for example, the p-type impurity concentration in the terminal base region 42. The p-type impurity concentration in the terminal base region 42 is, for example, 5 × 10⁻⁶. 16 cm -3 The above 1 x 10 19 cm -3 The following applies:

[0080] The upper guard ring region 44 is electrically isolated from the source electrode 12. The upper guard ring region 44 is, for example, electrically floating.

[0081] The upper guard ring region 44 is formed, for example, using the same manufacturing process as the terminal base region 42, with the same mask pattern.

[0082] p + The terminal bottom region 46 is provided between the lower region 32a and the upper region 32b. The terminal bottom region 46 is provided between the terminal trench 58 and the lower region 32a. The terminal bottom region 46 is in contact with, for example, the lower region 32a and the upper region 32b. The terminal bottom region 46 is in contact with the terminal trench 58.

[0083] The terminal bottom region 46 surrounds the element region 101 in a cross-section parallel to the first plane F1, for example. The terminal bottom region 46 is annular in a cross-section parallel to the first plane F1, for example. The terminal bottom region 46 surrounds the cell bottom region 40 in a cross-section parallel to the first plane F1, for example.

[0084] The termination bottom region 46 has the function of mitigating the strength of the electric field applied to the gate insulating layer 18 at the bottom of the termination trench 58. In addition, the termination bottom region 46 has the function of mitigating the strength of the electric field applied to the termination of the pn junction of the element region 101 when the MOSFET 100 is in the off state.

[0085] The first position (P1 in Figure 3) of the end of the terminal bottom region 46 in the first direction opposite to the element region 101 is located closer to the element region 101 than the second position (P2 in Figure 3) of the end of the terminal base region 42 in the first direction opposite to the element region 101.

[0086] The terminal bottom region 46 contains, for example, aluminum (Al) as a p-type impurity. The concentration of p-type impurities in the terminal bottom region 46 is, for example, higher than the concentration of p-type impurities in the terminal base region 42. The concentration of p-type impurities in the terminal bottom region 46 is, for example, 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0087] The terminal bottom region 46 is electrically connected to the source electrode 12. The terminal bottom region 46 is fixed at the potential of the source electrode 12.

[0088] The terminal bottom region 46 is formed, for example, by the same manufacturing process using the same mask pattern as the cell bottom region 40.

[0089] p + The shaped connection region 54 is in contact with the terminal base region 42 and the terminal bottom region 46. The connection region 54 is provided, for example, between the terminal contact region 52 and the terminal bottom region 46. The connection region 54 is in contact with the terminal contact region 52, for example. The connection region 54 is in contact with the terminal trench 58, for example.

[0090] The connection region 54 has the function of electrically connecting the source electrode 12 and the terminal bottom region 46.

[0091] The connecting region 54 contains, for example, aluminum (Al) as a p-type impurity. The concentration of p-type impurities in the connecting region 54 is higher than, for example, the concentration of p-type impurities in the terminal base region 42. The concentration of p-type impurities in the connecting region 54 is, for example, 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0092] p + The lower guard ring region 48 is provided between the lower region 32a and the upper region 32b. The lower guard ring region 48 is in contact with, for example, the lower region 32a and the upper region 32b.

[0093] The lower guard ring region 48 is located in a first direction relative to the terminal bottom region 46. The lower guard ring region 48 is separated from the terminal bottom region 46.

[0094] For example, multiple lower guard ring regions 48 may be provided. For example, two or more lower guard ring regions 48 may be provided. When multiple lower guard ring regions 48 are provided, they are spaced apart from each other in the first direction. Figure 3 shows an example where there are five lower guard ring regions 48, but there may be one to four or six or more lower guard ring regions 48.

[0095] The lower guard ring region 48 surrounds the element region 101 in a cross-section parallel to the first plane F1, for example. The lower guard ring region 48 is annular in a cross-section parallel to the first plane F1. The lower guard ring region 48 surrounds the terminal bottom region 46 in a cross-section parallel to the first plane F1, for example.

[0096] The lower guard ring region 48 has the function of mitigating the intensity of the electric field applied to the end of the termination bottom region 46 when the MOSFET 100 is in the off state.

[0097] When three or more lower guard ring regions 48 are provided, for example, the distance between two adjacent lower guard ring regions 48 in the first direction increases in the direction of the first. For example, the fourth distance (d4 in Figure 3) between the fifth lower guard ring region 48e and the fourth lower guard ring region 48d is greater than the fifth distance (d5 in Figure 3) between the fourth lower guard ring region 48d and the third lower guard ring region 48c. Similarly, the fifth distance (d5 in Figure 3) between the fourth lower guard ring region 48d and the third lower guard ring region 48c is greater than, for example, the distance between the third lower guard ring region 48c and the second lower guard ring region 48b. Similarly, the distance between the third lower guard ring region 48c and the second lower guard ring region 48b is greater than, for example, the distance between the second lower guard ring region 48b and the first lower guard ring region 48a.

[0098] Furthermore, it is also possible to make the distance between two adjacent lower guard ring regions 48 in the first direction substantially equal.

[0099] The third position (P3 in Figure 3) at the end of the fifth lower guard ring region 48e, which is the furthest from the element region 101 in the first direction within the lower guard ring region 48, opposite to the element region 101, is located closer to the element region 101 than the fourth position (P4 in Figure 3) at the end of the fourth upper guard ring region 44d, which is the furthest from the element region 101 in the first direction within the upper guard ring region 44, opposite to the element region 101. Furthermore, the third position P3 is located further from the element region 101 in the first direction than the fifth position (P5 in Figure 3) at the end of the third upper guard ring region 44c, which is the second furthest from the element region 101 in the first direction within the upper guard ring region 44, opposite to the element region 101.

[0100] The width of the lower guard ring region 48 in the first direction is, for example, 0.5 μm or more and 4 μm or less. The distance between two adjacent lower guard ring regions 48 in the first direction is, for example, 0.5 μm or more and 4 μm or less.

[0101] The lower guard ring region 48 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration in the lower guard ring region 48 is substantially equal to, for example, the p-type impurity concentration in the terminal bottom region 46. The p-type impurity concentration in the lower guard ring region 48 is higher than, for example, the p-type impurity concentration in the terminal base region 42. The p-type impurity concentration in the lower guard ring region 48 is higher than, for example, the p-type impurity concentration in the upper guard ring region 44. The p-type impurity concentration in the lower guard ring region 48 is higher than, for example, the p-type impurity concentration in the outer guard ring region 50. The p-type impurity concentration in the lower guard ring region 48 is, for example, 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0102] The lower guard ring region 48 is electrically isolated from the source electrode 12. The lower guard ring region 48 is, for example, electrically floating.

[0103] The lower guard ring region 48 is formed, for example, using the same manufacturing process as the terminal bottom region 46, with the same mask pattern.

[0104] The p-shaped outer peripheral guard ring region 50 is provided between the upper region 32b and the first surface F1. The outer peripheral guard ring region 50 contacts, for example, the first surface F1. The outer peripheral guard ring region 50 contacts, for example, the field insulating layer 24. The outer peripheral guard ring region 50 contacts, for example, the upper region 32b.

[0105] The outer periphery guard ring region 50 is located in a first direction relative to the upper guard ring region 44. The outer periphery guard ring region 50 is provided on the outside of the upper guard ring region 44. The outer periphery guard ring region 50 is spaced apart from the upper guard ring region 44.

[0106] For example, multiple outer perimeter guard ring regions 50 may be provided. For example, two or more outer perimeter guard ring regions 50 may be provided. When multiple outer perimeter guard ring regions 50 are provided, they are spaced apart from each other in the first direction. Figure 3 shows an example where there are three outer perimeter guard ring regions 50, but there may be one, two, or four or more outer perimeter guard ring regions 50.

[0107] The outer periphery guard ring region 50 surrounds the element region 101 on the first surface F1, for example. The outer periphery guard ring region 50 is annular on the first surface F1, for example. The outer periphery guard ring region 50 surrounds the upper guard ring region 44 on the first surface F1, for example.

[0108] The outer guard ring region 50 has the function of mitigating the intensity of the electric field applied to the end of the upper guard ring region 44 when the MOSFET 100 is in the off state.

[0109] When three or more outer perimeter guard ring regions 50 are provided, for example, the distance between two adjacent outer perimeter guard ring regions 50 in the first direction increases in the direction of the first direction. For example, the sixth distance (d6 in Figure 3) between the third outer perimeter guard ring region 50c and the second outer perimeter guard ring region 50b is greater than the seventh distance (d7 in Figure 3) between the second outer perimeter guard ring region 50b and the first outer perimeter guard ring region 50a.

[0110] Furthermore, it is also possible to make the distance between two adjacent outer perimeter guard ring regions 50 in the first direction substantially equal.

[0111] The first distance (d1 in Figure 3) between the first outer guard ring region 50a, which is closest to the element region in the first direction within the outer guard ring region 50, and the fourth upper guard ring region 44d, which is furthest from the element region 101 in the first direction within the upper guard ring region 44, is smaller than the second distance (d2 in Figure 3) between the fourth upper guard ring region 44d, which is furthest from the element region 101 in the first direction within the upper guard ring region 44, and the third upper guard ring region 44c, which is the second furthest from the element region 101 in the first direction within the upper guard ring region 44.

[0112] The first distance d1 is, for example, between one-tenth and one-quarter of the second distance d2.

[0113] The width of the outer peripheral guard ring region 50 in the first direction is, for example, 0.5 μm or more and 4 μm or less. The distance between two adjacent outer peripheral guard ring regions 50 in the first direction is, for example, 0.5 μm or more and 4 μm or less.

[0114] The outer guard ring region 50 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration in the outer guard ring region 50 is substantially equal to, for example, the p-type impurity concentration in the upper guard ring region 44. The p-type impurity concentration in the outer guard ring region 50 is, for example, 5 × 10⁻⁶ 16 cm -3 The above 1 x 10 19 cm-3 The following applies:

[0115] The outer peripheral guard ring region 50 is electrically isolated from the source electrode 12. The outer peripheral guard ring region 50 is, for example, electrically floating.

[0116] The outer periphery guard ring region 50 is formed, for example, using the same mask pattern as the terminal base region 42 or the upper guard ring region 44 in the same manufacturing process.

[0117] The terminal trench 58 is provided on the side of the first surface F1 of the silicon carbide layer 10. The terminal trench 58 is a groove provided in the silicon carbide layer 10. The terminal trench 58 is part of the silicon carbide layer 10.

[0118] The termination trench 58 is in contact with, for example, the termination bottom region 46, the connection region 54, and the termination contact region 52.

[0119] The depth of the terminal trench 58 is, for example, 0.5 μm to 2 μm.

[0120] The conductive layer 20 is provided within the termination trench 58. The conductive layer 20 faces the termination bottom region 46, the connection region 54, and the termination contact region 52.

[0121] The conductive layer 20 is a conductor. The conductive layer 20 is, for example, polycrystalline silicon containing p-type or n-type impurities.

[0122] The conductive layer 20 is electrically connected to the source electrode 12, for example. The conductive layer 20 may also be in an electrically floating state, for example.

[0123] The trench insulating layer 22 is provided between the conductive layer 20 and the silicon carbide layer 10. The trench insulating layer 22 is provided between the conductive layer 20 and the terminal bottom region 46. The trench insulating layer 22 is provided between the conductive layer 20 and the connection region 54. The trench insulating layer 22 is provided between the conductive layer 20 and the terminal contact region 52.

[0124] The trench insulating layer 22 is an insulator. The trench insulating layer 22 is, for example, silicon oxide. For the trench insulating layer 22, for example, a high-k insulating material (high dielectric constant insulating material) can be applied.

[0125] The interlayer insulating layer 26 is provided on the conductive layer 20 and the silicon carbide layer 10. The interlayer insulating layer 26 is, for example, silicon oxide.

[0126] The field insulating layer 24 is provided between the silicon carbide layer 10 and the interlayer insulating layer 26. The field insulating layer 24 is in contact with, for example, the first surface F1. The field insulating layer 24 is, for example, silicon oxide.

[0127] Next, the operation and effects of the semiconductor device according to the first embodiment will be described.

[0128] In a vertical MOSFET using silicon carbide, for example, a termination region is provided around the element region containing the transistor. The termination region reduces the intensity of the electric field applied to the termination of the pn junction of the element region when the MOSFET is in the off state. The termination region also has the function of improving the dielectric breakdown voltage of the MOSFET.

[0129] During MOSFET operation, charges may be trapped, for example, in the insulating layer above the termination region. These charges may be, for example, electrons or holes injected from the silicon carbide layer, or mobile ions entering from outside the MOSFET.

[0130] When charges are trapped in the insulating layer, the electric field distribution in the termination region changes, which can reduce the dielectric breakdown voltage of the MOSFET. A decrease in the dielectric breakdown voltage of the MOSFET reduces its reliability.

[0131] Figure 4 is a schematic cross-sectional view of the semiconductor device of the first comparative example. Figure 4 corresponds to Figure 3 of the first embodiment.

[0132] The semiconductor device of the first comparative example is MOSFET901. MOSFET901 differs from MOSFET100 of the first embodiment in that a p-shaped outer peripheral guard ring region 50 is not provided outside the p-shaped upper guard ring region 44.

[0133] For example, consider the case where a negative charge is trapped in the field insulating layer 24 above the upper guard ring region 44, or in the interlayer insulating layer 26 above the upper guard ring region 44, during the operation of the MOSFET 901. When a negative charge is trapped in the field insulating layer 24 or the interlayer insulating layer 26, the depletion layer in the drift region 32 is more likely to elongate due to the influence of the negative charge.

[0134] As the depletion layer tends to expand in the drift region 32, the strength of the electric field applied to the outer edge of the fourth upper guard ring region 44d, which is located on the outermost side of the upper guard ring region 44, increases. As a result, the dielectric breakdown voltage of the MOSFET 901 decreases.

[0135] In the first embodiment, the MOSFET 100 has an outer peripheral guard ring region 50 outside the upper guard ring region 44. The first distance d1 between the first outer peripheral guard ring region 50a, which is closest to the element region in the first direction within the outer peripheral guard ring region 50, and the fourth upper guard ring region 44d, which is furthest from the element region 101 in the first direction within the upper guard ring region 44, is smaller than the second distance d2 between the fourth upper guard ring region 44d, which is furthest from the element region 101 in the first direction within the upper guard ring region 44, and the third upper guard ring region 44c, which is the second furthest from the element region 101 in the first direction within the upper guard ring region 44.

[0136] With the above structure, even when the depletion layer tends to expand in the drift region due to the influence of negative charges, the strength of the electric field applied to the outer edge of the fourth upper guard ring region 44d can be reduced. Therefore, the decrease in dielectric breakdown voltage when negative charges are trapped in the insulating layer above the termination region can be suppressed.

[0137] Figure 5 is a schematic cross-sectional view of the semiconductor device of the second comparative example. Figure 5 corresponds to Figure 3 of the first embodiment.

[0138] The semiconductor device of the second comparative example is MOSFET902. MOSFET902 differs from MOSFET100 of the first embodiment in that the first position P1 at the end of the termination bottom region 46 in the first direction opposite to the element region 101 is located further from the element region 101 than the second position P2 at the end of the termination base region 42 in the first direction opposite to the element region 101.

[0139] For example, consider the case where a positive charge is trapped in the field insulating layer 24 above the termination bottom region 46, or in the interlayer insulating layer 26 above the termination bottom region 46, during the operation of the MOSFET 902. When a positive charge is trapped in the field insulating layer 24 or the interlayer insulating layer 26, the depletion layer in the drift region 32 becomes less likely to expand due to the influence of the positive charge.

[0140] As the depletion layer does not extend as easily in the drift region 32, the strength of the electric field applied to the outer edge of the termination bottom region 46 increases, for example. This causes the dielectric breakdown voltage of the MOSFET 902 to decrease.

[0141] In the first embodiment of the MOSFET 100, the first position (P1 in Figure 3) of the end of the termination bottom region 46 in the first direction opposite to the element region 101 is located closer to the element region 101 than the second position (P2 in Figure 3) of the end of the termination base region 42 in the first direction opposite to the element region 101.

[0142] With the above structure, even when the depletion layer does not extend easily in the drift region due to the influence of positive charges, the strength of the electric field applied to the outer edge of the terminal bottom region 46 can be reduced. Therefore, the decrease in dielectric breakdown voltage when positive charges are trapped in the insulating layer above the terminal region can be suppressed.

[0143] According to the first embodiment described above, even when either negative charges or positive charges are trapped in the field insulating layer 24 over the termination region 102 or the interlayer insulating layer 26 over the termination region 102 during the operation of the MOSFET 100, a decrease in the breakdown voltage of the MOSFET 100 can be suppressed. Therefore, a highly reliable MOSFET 100 can be realized.

[0144] As described above, according to the first embodiment, a MOSFET capable of suppressing a decrease in breakdown voltage can be realized.

[0145] (Second Embodiment) The semiconductor device of the second embodiment is different from the semiconductor device of the first embodiment in that the concentration of the second-conductivity-type impurity in the sixth silicon carbide region is higher than the concentration of the second-conductivity-type impurity in the fifth silicon carbide region. Hereinafter, for the content overlapping with the first embodiment, some descriptions may be omitted.

[0146] FIG. 6 is a schematic cross-sectional view of the semiconductor device of the second embodiment. FIG. 6 corresponds to FIG. 3 of the first embodiment.

[0147] The semiconductor device of the second embodiment is a MOSFET 200.

[0148] The p-type impurity concentration of the upper guard ring region 44 (the sixth silicon carbide region) is higher than the p-type impurity concentration of the termination base region 42 (the fifth silicon carbide region). The p-type impurity concentration of the upper guard ring region 44 is lower than the p-type impurity concentration of the lower guard ring region 48 (the eighth silicon carbide region).

[0149] The p-type impurity concentration of the upper guard ring region 44 is, for example, 1×10 18 cm -3 or more and 5×10 20 cm -3 or less.

[0150] Also, for example, the p-type impurity concentration of the outer peripheral guard ring region 50 is substantially equal to the p-type impurity concentration of the upper guard ring region 44.

[0151] As described above, according to the second embodiment, similar to the first embodiment, a MOSFET capable of suppressing a decrease in breakdown voltage can be realized.

[0152] (Third Embodiment) The semiconductor device of the third embodiment is different from the semiconductor device of the first embodiment in that the concentration of the second-conductivity-type impurity in the eighth silicon carbide region is lower than the concentration of the second-conductivity-type impurity in the seventh silicon carbide region. Hereinafter, some descriptions may be omitted for the content overlapping with the first embodiment.

[0153] FIG. 7 is a schematic cross-sectional view of the semiconductor device of the third embodiment. FIG. 7 corresponds to FIG. 3 of the first embodiment.

[0154] The semiconductor device of the third embodiment is MOSFET300.

[0155] The p-type impurity concentration in the lower guard ring region 48 (the eighth silicon carbide region) is lower than the p-type impurity concentration in the terminal bottom region 46 (the seventh silicon carbide region). Also, the p-type impurity concentration in the lower guard ring region 48 is higher than the p-type impurity concentration in the upper guard ring region 44 (the sixth silicon carbide region).

[0156] The p-type impurity concentration in the lower guard ring region 48 is, for example, 1×10 17 cm -3 or more and 5×10 20 cm<所提供原文中此位置缺少对应编号or less.

[0157] As described above, according to the third embodiment, similar to the first embodiment, a MOSFET capable of suppressing a decrease in breakdown voltage can be realized.

[0158] In the first to third embodiments, the case of 4H-SiC as the crystal structure of SiC has been described as an example, but the present invention can also be applied to devices using SiC with other crystal structures such as 6H-SiC and 3C-SiC. Also, it is possible to apply a plane other than the (0001) plane to the surface of the silicon carbide layer 10.

[0159] In the first to third embodiments, the case where the first conductivity type is n-type and the second conductivity type is p-type was explained as an example, but it is also possible to have the first conductivity type be p-type and the second conductivity type be n-type.

[0160] In the first to third embodiments, aluminum (Al) was exemplified as a p-type impurity, but boron (B) can also be used. Similarly, nitrogen (N) and phosphorus (P) were exemplified as n-type impurities, but arsenic (As), antimony (Sb), etc., can also be applied.

[0161] In the first to third embodiments, the case in which the gate electrode 16 has a stripe shape in the element region 101 was described as an example, but it is also possible to have a structure in which the gate electrode 16 has a mesh shape, for example.

[0162] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0163] 10. Silicon carbide layer 12 Source electrode (first electrode) 14. Drain electrode (second electrode) 16 Shuttle gates 18 Gate insulating layer 20 Conductive layer 22 Trench Insulation Layer (Insulation Layer) 32 n-type drift region (first silicon carbide region) 32a Lower region (first region) 32b Upper region (second region) 34 p-type cell base region (second silicon carbide region) 36 n + Source region of the shape (third silicon carbide region) 38 p + Shape of cell contact area 40 pages + The cell bottom region of the shape (the fourth silicon carbide region) 42 p-type terminal base region (5th silicon carbide region) 44. Upper guard ring region of type p (6th silicon carbide region) 46 p + The terminal bottom region of the shape (the 7th silicon carbide region) 48 pages + Lower guard ring region of the shape (8th silicon carbide region) 50 p-type outer guard ring region (9th silicon carbide region) 52 p + Shape of the terminal contact area 54 p + Shape connection region (10th silicon carbide region) 100 MOSFETs (Semiconductor Devices) 101 Element Region 102 Termination area 200 MOSFETs (Semiconductor Devices) 201 MOSFET (Semiconductor Device) F1 First Side F2 Second side P1 First position P2 Second position P3 Third position P4, 4th position P5, 5th position d1 First distance d2 Second distance

Claims

1. Element region and, The system comprises a termination region surrounding the aforementioned element region, The aforementioned element region is The first electrode and The second electrode and A silicon carbide layer provided between the first electrode and the second electrode, having a first surface on the side of the first electrode and a second surface on the side of the second electrode, A first silicon carbide region of a first conductive type, including a first region and a second region provided between the first region and the first surface, A second silicon carbide region of a second conductivity type is provided between the second region and the first surface and is electrically connected to the first electrode, A third silicon carbide region of first conductivity type is provided between the second silicon carbide region and the first surface and is electrically connected to the first electrode, A fourth silicon carbide region of second conductivity type is provided between the first region and the second region, A silicon carbide layer containing, A gate electrode is provided within the silicon carbide layer and faces the fourth silicon carbide region, the second region, the second silicon carbide region, and the third silicon carbide region, A gate insulating layer is provided between the gate electrode and the silicon carbide layer, Includes, The aforementioned termination region is The first electrode 2, The first silicon carbide region includes the first region and the second region, A fifth silicon carbide region of second conductivity type is provided between the second region and the first surface and is electrically connected to the first electrode, A plurality of sixth silicon carbide regions of second conductivity type are provided between the second region and the first surface, located in a first direction toward the terminal region from the element region with respect to the fifth silicon carbide region, separated from the fifth silicon carbide region, and separated from each other in the first direction, A seventh silicon carbide region of second conductivity type is provided between the first region and the second region and is electrically connected to the first electrode, A second conductive eighth silicon carbide region is provided between the first region and the second region, positioned in the first direction with respect to the seventh silicon carbide region, and separated from the seventh silicon carbide region, A second conductive type, at least one ninth silicon carbide region, is provided between the second region and the first surface, is located in a first direction relative to the sixth silicon carbide region, and is separated from the sixth silicon carbide region, The silicon carbide layer containing, Includes, The first position of the end of the seventh silicon carbide region in the first direction opposite to the element region is located closer to the element region than the second position of the end of the fifth silicon carbide region in the first direction opposite to the element region, In at least one of the eighth silicon carbide regions, the third position at the end of the eighth silicon carbide region in the first direction that is furthest from the element region in the first direction is located closer to the element region than the fourth position at the end of the sixth silicon carbide region in the first direction that is furthest from the element region in the first direction is located closer to the element region than the fourth position at the end of the sixth silicon carbide region in the first direction that is furthest from the element region in the first direction, and the third position is located further from the element region in the first direction than the fifth position at the end of the sixth silicon carbide region in the first direction that is second furthest from the element region in the first direction, A semiconductor device wherein the first distance between the ninth silicon carbide region that is closest to the element region in the first direction among the at least one ninth silicon carbide region and the sixth silicon carbide region that is furthest from the element region in the first direction among the sixth silicon carbide region is smaller than the second distance between the sixth silicon carbide region that is furthest from the element region in the first direction among the sixth silicon carbide region and the sixth silicon carbide region that is second furthest from the element region in the first direction among the sixth silicon carbide region.

2. The semiconductor device according to claim 1, wherein the concentration of the first conductivity type impurity in the second region is higher than the concentration of the first conductivity type impurity in the first region.

3. The semiconductor device according to claim 1, wherein the fifth silicon carbide region, the sixth silicon carbide region, the seventh silicon carbide region, the eighth silicon carbide region, and the ninth silicon carbide region surround the element region.

4. The semiconductor device according to claim 1, wherein the concentration of the second conductivity type impurity in at least one eighth silicon carbide region is higher than the concentration of the second conductivity type impurity in the sixth silicon carbide region and the concentration of the second conductivity type impurity in at least one ninth silicon carbide region.

5. The semiconductor device according to claim 1, wherein three or more of the sixth silicon carbide regions are provided, and the distance between two adjacent sixth silicon carbide regions in the first direction increases toward the first direction.

6. The semiconductor device according to claim 1, wherein at least one of the eighth silicon carbide regions is provided in two or more locations.

7. The semiconductor device according to claim 1, wherein at least one eighth silicon carbide region is provided in three or more locations, and the distance between two adjacent eighth silicon carbide regions in the first direction increases toward the first direction.

8. The semiconductor device according to claim 1, wherein at least one of the ninth silicon carbide regions is provided in two or more locations.

9. The semiconductor device according to claim 1, wherein at least one of the ninth silicon carbide regions is provided in three or more locations, and the distance between two adjacent ninth silicon carbide regions in the first direction increases toward the first direction.

10. The semiconductor device according to claim 1, wherein the concentration of the second conductivity type impurity in the sixth silicon carbide region is equal to or higher than the concentration of the second conductivity type impurity in the fifth silicon carbide region.

11. The semiconductor device according to claim 1, wherein the concentration of the second conductivity type impurity in at least one eighth silicon carbide region is lower than the concentration of the second conductivity type impurity in the seventh silicon carbide region, and the concentration of the second conductivity type impurity in at least one eighth silicon carbide region is higher than the concentration of the second conductivity type impurity in the sixth silicon carbide region.

12. The semiconductor device according to claim 1, wherein the silicon carbide layer in the terminal region further comprises a tenth silicon carbide region in contact with the fifth silicon carbide region and the seventh silicon carbide region.

13. The terminal region is provided within the silicon carbide layer and comprises a conductive layer facing the seventh silicon carbide region and the tenth silicon carbide region, An insulating layer provided between the conductive layer and the silicon carbide layer, The semiconductor device according to claim 12, further comprising:

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