Semiconductor device and its manufacturing method

Abstract

This suppresses electric field concentration near the edges of the conductive layer provided on the insulating layer. [Solution] A semiconductor device comprising a semiconductor substrate (12), an insulating layer (50) provided on the semiconductor substrate, and a conductive layer (24) provided on the insulating layer. The conductive layer has an upper surface (24a), a lower surface (24b), and an end surface (24c) connecting the upper surface and the lower surface. The end surface (24e) of the conductive layer is formed by a connection between the upper surface and the end surface. When the direction from the center of the conductive layer toward the end surface is considered outward in the direction along the semiconductor substrate, the end surface is displaced upward as it moves outward.

Description

Technical Field

[0001] The technology disclosed in this specification relates to a semiconductor device and a method for manufacturing the same.

[0002] A semiconductor device having an insulating layer provided on the upper surface of a semiconductor substrate and a conductive layer provided on the upper surface of the insulating layer is known. In this type of semiconductor device, electric field concentration may occur inside the insulating layer located between the conductive layer and the semiconductor substrate. Patent Document 1 discloses a technique for suppressing electric field concentration in a field oxide film by adopting a structure in which the thickness of the field insulating film gradually increases at a portion where a gate lead-out portion rides on the field insulating film.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Electric field concentration may occur near the end of a conductive layer provided on an insulating layer. In this specification, a technique for suppressing electric field concentration near the end of a conductive layer provided on an insulating layer is proposed.

Means for Solving the Problems

[0005] The semiconductor device disclosed in this specification includes a semiconductor substrate, an insulating layer provided on the semiconductor substrate, and a conductive layer provided on the insulating layer. The conductive layer has an upper surface, a lower surface, and an end surface connecting the upper surface and the lower surface. An end of the conductive layer is formed by a connection portion between the upper surface and the end surface. When the direction from the center of the conductive layer toward the end in the direction along the semiconductor substrate is defined as the outer side, the upper surface extends further to the outer side than the lower surface, and the end surface is displaced upward as it faces the outer side.

[0006] In this semiconductor device, the edge of the conductive layer is displaced upward as it moves outward, which suppresses electric field concentration near the edge of the conductive layer.

[0007] Furthermore, this specification proposes a method for manufacturing a semiconductor device. This manufacturing method comprises the steps of: forming an insulating layer on a semiconductor substrate; forming a groove in the insulating layer that is shallower than the thickness of the insulating layer, wherein the groove has a bottom surface and side surfaces, the end of the groove is formed by the upper end of the side surfaces, and the groove is formed such that, when the direction from the center of the groove toward the end is considered outward in the direction along the semiconductor substrate, the side surfaces are displaced upward as they move outward; and forming a conductive layer within the groove.

[0008] This manufacturing method allows the end face of the conductive layer to be displaced upward as it extends outward. Therefore, it is possible to manufacture a semiconductor device in which electric field concentration near the end of the conductive layer is less likely to occur. [Brief explanation of the drawing]

[0009] [Figure 1] A plan view of the semiconductor device of the embodiment. [Figure 2] Cross-sectional view along line A in Figure 1. [Figure 3] Cross-sectional view along line B in Figure 1. [Figure 4] Enlarged cross-sectional view of the end of the gate wiring in the embodiment. [Figure 5] Enlarged cross-sectional view of the end of the gate wiring in the comparative example. [Figure 6] An explanatory diagram of the manufacturing method of the semiconductor device according to the embodiment. [Figure 7] An explanatory diagram of the manufacturing method of the semiconductor device according to the embodiment. [Figure 8] An explanatory diagram of the manufacturing method of the semiconductor device according to the embodiment. [Figure 9] An explanatory diagram of the manufacturing method of the semiconductor device according to the embodiment. [Figure 10] Enlarged cross-sectional view of the end of the gate wiring in the second embodiment. [Figure 11] Enlarged cross-sectional view of the end of the gate wiring in the third embodiment. [Modes for carrying out the invention]

[0010] In the semiconductor device disclosed herein, the end face may be a convex curved surface.

[0011] This configuration allows for more effective suppression of electric field concentration near the edges of the conductive layer.

[0012] In the semiconductor device disclosed herein, the end face may be displaced upward in a stepped manner as it moves outward.

[0013] In the semiconductor device disclosed herein, a switching element having a gate electrode may be provided on the semiconductor substrate. The conductive layer may be a gate wiring connected to the gate electrode.

[0014] The semiconductor device 10 in the embodiment shown in Figure 1 has a semiconductor substrate 12. The semiconductor substrate 12 is made of silicon carbide. However, the semiconductor substrate 12 may be made of other semiconductor materials such as silicon or gallium nitride. The semiconductor substrate 12 has two element regions 20. A gate-type switching element (in this embodiment, a MOSFET: metal-oxide-semiconductor field effect transistor) is provided in each element region 20. Gate wiring 24 is provided around the element region 20. Four electrode pads 22a to 22d are provided adjacent to the element region 20. The electrode pads 22a to 22d include a gate electrode pad, a source electrode pad, etc. The gate electrode pad is connected to the gate electrode in the element region 20 by gate wiring 24. The source electrode pad is connected to the source electrode in the element region 20 by wiring (not shown).

[0015] FIG. 2 is a cross-sectional view taken along the straight line A in FIG. 1. That is, FIG. 2 is a cross-sectional view of the element region 20 along the y direction. As shown in FIG. 2, a plurality of trenches 30 are provided on the upper surface 12a of the semiconductor substrate 12. The inner surface of the trench 30 is covered with a gate insulating film 32. A gate electrode 34 is provided in the trench 30. The gate electrode 34 is insulated from the semiconductor substrate 12 by the gate insulating film 32. The upper surface of the gate electrode 34 is covered with an interlayer insulating film 36. The upper surface 12a of the semiconductor substrate 12 is covered with a source electrode 38. The source electrode 38 is insulated from the gate electrode 34 by the interlayer insulating film 36. The lower surface 12b of the semiconductor substrate 12 is covered with a drain electrode 39.

[0016] The semiconductor substrate 12 has an n-type source region 40, a p-type contact region 42, a p-type body region 44, an n-type drift region 46, and an n-type drain region 48. The source region 40 makes an ohmic contact with the source electrode 38. The source region 40 is in contact with the gate insulating film 32. The contact region 42 makes an ohmic contact with the source electrode 38. The body region 44 has a lower p-type impurity concentration than the contact region 42. The body region 44 is in contact with the source region 40 and the contact region 42 from below. The body region 44 is in contact with the gate insulating film 32. The drift region 46 is in contact with the body region 44 from below. The drift region 46 is in contact with the gate insulating film 32. The drain region 48 has a higher n-type impurity concentration than the drift region 46. The drain region 48 is in contact with the drift region 46 from below. The drain region 48 makes an ohmic contact with the drain electrode 39. The MOSFET is formed by the source region 40, the contact region 42, the body region 44, the drift region 46, the drain region, the gate insulating film 32, the gate electrode 34, etc.

[0017] Figure 3 is a cross-sectional view along line B in Figure 1. That is, Figure 3 is a cross-sectional view of the element region 20 and its periphery along the x-direction. As shown in Figure 3, in the periphery of the element region 20, the upper surface 12a of the semiconductor substrate 12 is covered by a field insulating film 50. The field insulating film 50 is made of silicon oxide. Gate wiring 24 is arranged on the field insulating film 50. The gate wiring 24 is insulated from the semiconductor substrate 12 by the field insulating film 50. The gate wiring 24 is made of polysilicon. The gate wiring 24 is connected to the gate electrode 34 at the end of each trench 30. The upper surface of the gate wiring 24 is covered by a protective insulating film 51. An electrode 52 is provided on the upper surface 12a on the outer periphery side of the field insulating film 50. The electrode 52 is connected to the source electrode 38 at a position not shown. In the periphery of the element region 20, a surface p-type region 54 is provided inside the semiconductor substrate 12. The surface p-type region 54 is provided in an area including the upper surface 12a of the semiconductor substrate 12 and is in contact with the field insulating film 50. The surface p-type region 54 is in contact with the electrode 52. A drift region 46 is provided below the surface p-type region 54.

[0018] As shown in Figure 3, the gate wiring 24 has an end 24e in the x-direction. Hereinafter, the direction from the center C of the gate wiring 24 toward the end 24e in the x-direction will be referred to as the outward direction, and the opposite direction will be referred to as the inward direction. As shown in Figure 4, the gate wiring 24 has an upper surface 24a, a lower surface 24b, and an end surface 24c. The upper surface 24a and the lower surface 24b are planar. The end surface 24c connects the upper surface 24a and the lower surface 24b. In the x-direction, the boundary position between the end surface 24c and the lower surface 24b is the position where the distance from the lower surface 24b to the upper surface 24a begins to decrease. In the x-direction, the upper surface 24a extends further outward than the lower surface 24b. Therefore, the connection between the upper surface 24a and the end surface 24c constitutes the end 24e of the gate wiring 24. The connection portion 24d between the lower surface 24b and the end surface 24c is positioned inward from the end portion 24e. The end surface 24c extends so as to be displaced upward as it extends outward. In Figure 4, the end surface 24c is a convex curved surface that is displaced upward as it extends outward.

[0019] Depending on the operating state of the switching element within the element region 20, a Hall current may flow below the gate wiring 24 as shown by the arrow 100 in FIG. 4. The Hall current flows from the drift region 46 into the surface p-type region 54 and along the field insulating film 50 to the electrode 52. In this case, as shown by the arrow 200, an electric field is generated between each hole constituting the Hall current and the gate wiring 24, and the electric field is applied to the field insulating film 50. FIG. 5 shows, as a comparative example, a semiconductor device in which the end face 24c of the gate wiring 24 is perpendicular to the lower face 24b. In this semiconductor device, since the connection portion 24d between the end face 24c and the lower face 24b has a right-angled shape, the electric lines of force concentrate on the connection portion 24d as shown by the arrow 200. Therefore, the electric field concentrates on the field insulating film 50 in the vicinity of the connection portion 24d. On the other hand, in the semiconductor device 10 of the embodiment shown in FIG. 4, since the end face 24c is displaced upward as it goes outward, the gate wiring 24 exists up to the outside of the connection portion 24d. Therefore, the electric lines of force are dispersed in the range outside the connection portion 24d, and the concentration of the electric field on the field insulating film 50 in the vicinity of the connection portion 24d is suppressed. In particular, in FIG. 4, since the end face 24c is a convex curved surface, the end face 24c is smoothly connected to the lower face 24b. Therefore, the concentration of the electric field on the field insulating film 50 in the vicinity of the connection portion 24d is more effectively suppressed. Thus, in the semiconductor device 10 of the embodiment, the concentration of the electric field in the vicinity of the end 24e of the gate wiring 24 can be suppressed.

[0020] Next, a method for manufacturing the semiconductor device 10 of the embodiment will be described. Here, a method for forming the gate wiring 24 of the semiconductor device 10 of the embodiment will be described. First, as shown in Figure 6, a field insulating film 50 is deposited on a semiconductor substrate 12, and a mask layer 60 (for example, a resist mask) is formed on the field insulating film 50. The mask layer 60 has an opening 60a. Next, as shown in Figure 7, a groove 62 is formed in the field insulating film 50 by wet etching the field insulating film 50 within the opening 60a. Here, the groove 62 is formed such that its depth is smaller than the thickness of the field insulating film 50. Therefore, the field insulating film 50 remains below the bottom surface 62b of the groove 62. Also, since wet etching is isotropic etching, the field insulating film 50 is etched even below the mask layer 60 in the vicinity of the opening 60a. Therefore, the end 62e of the groove 62 is formed below the field insulating film 50. Once the groove 62 is formed in this way, the side surface 62c of the groove 62 becomes an inclined surface that is displaced upward as it moves outward. After the groove 62 is formed, the mask layer 60 is removed. Next, as shown in Figure 8, gate wiring 24 is deposited inside the groove 62 and on the field insulating film 50. Then, as shown in Figure 9, the gate wiring 24 is etched back, leaving the gate wiring 24 inside the groove 62. This completes the gate wiring 24, in which the end face 24c is displaced upward as it faces outward.

[0021] In the above embodiment, the end face 24c of the gate wiring 24 was a curved surface, but the end face 24c may be configured as shown in Figures 10 and 11. In Figure 10, the end face 24c is composed of a plane that is displaced upward as it extends outward. In Figure 11, the end face 24c is composed of a bent surface that is displaced upward in a stepped manner as it extends outward. Even if the end face 24c is configured as shown in Figures 10 and 11, electric field concentration in the field insulating film 50 can be suppressed.

[0022] In the above embodiment, the electric field when a Hall current flows beneath the gate wiring was described, but an electric field is also generated near the end of the gate wiring in other operating conditions. The shape of the gate wiring end described above can suppress the electric field near the end of the gate wiring in various operating conditions. Furthermore, although the above embodiment described gate wiring, by applying the technology disclosed herein to the ends of conductive layers other than gate wiring (e.g., wiring, electrodes), electric field concentration near the ends of conductive layers can be suppressed.

[0023] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of Symbols]

[0024] 12: Semiconductor substrate, 24: Gate wiring, 24a: Top surface, 24b: Bottom surface, 24c: Edge surface, 24e: Edge, 50: Field insulating film

Claims

1. A semiconductor device, A semiconductor substrate (12) and An insulating layer (50) provided on the semiconductor substrate, A conductive layer (24) provided on the insulating layer, It has, The conductive layer has an upper surface (24a), a lower surface (24b), and an end surface (24c) connecting the upper surface and the lower surface. The end portion (24e) of the conductive layer is formed by the connection portion between the upper surface and the end surface. When the direction from the center of the conductive layer toward the edge is considered outward along the semiconductor substrate, the upper surface extends further outward than the lower surface, and the end surface is displaced upward as it extends outward. Semiconductor equipment.

2. The semiconductor device according to claim 1, wherein the end face is a convex curved surface.

3. The semiconductor device according to claim 1, wherein the end face is displaced upward in a stepped manner as it moves outward.

4. The semiconductor substrate is provided with a switching element having a gate electrode. The conductive layer is a gate wiring connected to the gate electrode. A semiconductor device according to any one of claims 1 to 3.

5. A method for manufacturing a semiconductor device, A process of forming an insulating layer on a semiconductor substrate, A step of forming a groove in the insulating layer that is shallower than the thickness of the insulating layer, wherein the groove has a bottom surface and a side surface, the end of the groove is formed by the upper end of the side surface, and the groove is formed such that when the direction from the center of the groove toward the end is considered outward in the direction along the semiconductor substrate, the side surface is displaced upward as it moves outward, A step of forming a conductive layer in the groove, A manufacturing method having the following characteristics.

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