Printed circuit board

Abstract

In a substrate structure including a glass layer on which metal vias are formed, it is possible to improve adhesion with the insulating material, thereby providing a printed circuit board that can improve voids and delamination. [Solution] The present invention relates to a printed circuit board comprising a glass layer having an upper surface and a lower surface, a side surface connecting the upper surface and the lower surface, a through hole penetrating between the upper surface and the lower surface of the glass layer, and a metal via filling at least a portion of the through hole, wherein one or more of the upper surface and the lower surface of the glass layer and one or more of the upper surface and the lower surface of the metal via each have a surface roughness greater than that of the side surface of the glass layer.

Description

Technical Field

[0001] The present invention relates to a printed circuit board.

Background Art

[0002] In order to meet the high-performance and miniaturization strategies of semiconductors, the levels of miniaturization and high density required for printed circuit boards are increasing. For example, in order to manufacture high-end products such as server boards, high-multi-layer and large-sized boards are required. However, the more wiring layers and the larger the body size, the more vulnerable the board may be to warpage. In order to solve such problems, the use of a glass core is considered. However, since the surface of glass is smooth and may have poor adhesion to insulating materials, glass damage, voids, delamination, etc. may occur.

Summary of the Invention

Problems to be Solved by the Invention

[0003] One of the various objects of the present invention is to provide a printed circuit board capable of improving the adhesion to an insulating material and thus improving voids, delamination, etc. in a substrate structure including a glass layer in which metal vias are formed.

Means for Solving the Problems

[0004] One of the several solutions of the present invention is to perform scribing using a laser on the surface of the glass layer and the exposed surface of the metal via to form surface roughness.

[0005] For example, a printed circuit board according to an example includes a glass layer having an upper surface, a lower surface, and side surfaces connecting the upper surface and the lower surface, through holes penetrating between the upper surface and the lower surface of the glass layer, and metal vias filling at least a part of the through holes. One or more of the upper surface and the lower surface of the glass layer and one or more of the upper surface and the lower surface of the metal via may each have a surface roughness greater than that of the side surface of the glass layer.

[0006] For example, a printed circuit board according to one example includes a glass layer having an upper surface and a lower surface and a side surface connecting the upper surface and the lower surface, through holes penetrating between the upper and lower surfaces of the glass layer, and metal vias filling at least a portion of the through holes, wherein the upper and lower surfaces of the glass layer and the upper and lower surfaces of the metal vias may each have an average roughness (Ra) of 0.1 μm or more and less than 10 μm. [Effects of the Invention]

[0007] One of the various effects of the present invention is that, in a substrate structure including a glass layer on which metal vias are formed, the adhesion with the insulating material can be improved, thereby providing a printed circuit board that can improve voids and delamination. [Brief explanation of the drawing]

[0008] [Figure 1] This is a block diagram illustrating an example of an electronic equipment system. [Figure 2] This is a schematic cross-sectional view showing an example of a printed circuit board. [Figure 3] This is a schematic top-view image of the surface of a glass layer on which metal vias have been formed, taken with an electron microscope. [Figure 4] Figure 3 schematically shows a cross-sectional image taken with an electron microscope of the cross-section along the line A-A' in the glass layer where metal vias are formed. [Modes for carrying out the invention]

[0009] The present invention will be described below with reference to the attached drawings. The shapes and sizes of the elements in the drawings may be exaggerated or reduced for clearer explanation.

[0010] Figure 1 is a block diagram illustrating an example of an electronic equipment system.

[0011] Referring to the drawing, the electronic device 1000 houses the main board 1010. The main board 1010 is physically and / or electrically connected to chip-related components 1020, network-related components 1030, and other components 1040, etc. These are also coupled with other electronic components, which will be described later, to form various signal lines 1090.

[0012] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPUs), graphics processors (e.g., GPUs), digital signal processors, cryptographic processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). It goes without saying that other different forms of chip-related electronic components may also be included. Furthermore, these chip-related components 1020 may be combined with each other. The chip-related components 1020 may also be in the form of a package that includes the chips and electronic components mentioned above.

[0013] Network-related component 1030 includes, but is not limited to, any other wireless and wired protocols designated as Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and later. It also includes any other diverse wireless or wired standards and protocols. Furthermore, it goes without saying that network-related component 1030 may be combined with chip-related component 1020.

[0014] Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCCs (low-temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCCs (multi-layer ceramic condensers), etc. However, they are not limited to these, and may also include other passive elements in chip component form used for various other applications. It goes without saying that other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030.

[0015] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the main board 1010 or not. Examples of other electronic components include, but are not limited to, audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage devices (e.g., hard disk drives), CDs (compact disks), DVDs (digital versatile disks), etc. Needless to say, other electronic components used for various purposes may also be included depending on the type of electronic device 1000.

[0016] The electronic device 1000 may be a smartphone, personal digital assistant, digital video camera, digital still camera, network system, computer, monitor, tablet, laptop, netbook, television, video game, smartwatch, automobile, server, etc. However, it is not limited to these, and it goes without saying that it may be any other electronic device that processes data.

[0017] Figure 2 is a schematic cross-sectional view showing an example of a printed circuit board.

[0018] Referring to the drawings, an example of a printed circuit board 100 may include a glass layer 111 having an upper surface S1 and a lower surface S2, and a side surface S3 connecting them, a through hole V penetrating between the upper surface S1 and the lower surface S2 of the glass layer 111, and a metal via 131 filling at least a portion of the through hole V. In this case, surface roughness may be formed on the upper surface S1 and / or lower surface S2 of the glass layer 111. Surface roughness may also be formed on the upper surface and / or lower surface of the metal via 131. For example, the surface roughness of the upper surface S1 and / or lower surface S2 of the glass layer 111 and the upper surface and / or lower surface of the metal via 131 may each be greater than that of the side surface S3 of the glass layer 111. For example, the upper surface S1 and / or lower surface S2 of the glass layer 111 and the upper surface and / or lower surface of the metal via 131 can each be skived with a laser, as will be described later. Therefore, each average roughness (Ra) can be approximately 0.1 μm or more and less than 10 μm, or 0.1 μm or more and 2 μm or less. On the other hand, since such processing is not required on the side surface of the glass layer 111, the average roughness (Ra) can be 0.001 μm or more and less than 0.1 μm.

[0019] Thus, the printed circuit board 100 according to this example can basically include a glass layer 111, and metal vias 131 can be formed on the glass layer 111 in a landless form, that is, without separate pads or lands. This may make it easier to realize fine circuits on the insulating material 112 described later, improve process capability, and enable warping control with a low coefficient of thermal expansion. Furthermore, the printed circuit board 100 according to this example can have surface roughness formed on the upper and / or lower surfaces of the glass layer 111, and surface roughness can also be formed on the upper and / or lower surfaces of the metal vias 131 that are exposed from the glass layer 111. Therefore, the adhesion between the glass layer 111 and the metal vias 131 and the insulating material 112 described later can be improved, and as a result, problems such as damage to the glass layer 111 and problems such as voids and delamination of the insulating material 112 can be improved. Furthermore, the adhesion between the metal via 131 and the first and second connecting vias 132 and 133, described later, can also be improved, potentially leading to further improvements in reliability.

[0020] On the other hand, the surface roughness of the upper surface S1 and / or lower surface S2 of the glass layer 111, and the upper and / or lower surface of the metal via 131, can be formed by laser skiving. Both ultraviolet lasers and infrared lasers can be used as the laser. The roughness can be formed in either the X or Y direction on a plane, and if necessary, it can be formed in only one direction, either the X or Y direction. The size of the roughness may be adjustable depending on the laser source and energy amount. The roughness can be formed selectively in desired areas, and formation over large areas may also be possible. In this case, the surface roughness of the upper surface of the glass layer 111 can be formed to be greater than that of the upper surface of the metal via 131, and the surface roughness of the lower surface of the glass layer 111 can be formed to be greater than that of the lower surface of the metal via 131, but this is not necessarily limited to this.

[0021] Referring to the drawings, a printed circuit board 100 according to an example may further include an insulating material 112 covering at least a part of each of the upper surface S1 and the lower surface S2 of the glass layer 111, and the upper and lower surfaces of the metal via 131, a first wiring layer 121 disposed on the upper surface of the insulating material 112, a first connection via 132 penetrating at least a part of the upper side of the insulating material 112 and directly connecting at least a part of the first wiring layer 121 to the upper surface of the metal via 131, a second wiring layer 122 disposed on the lower surface of the insulating material 112, and / or a second connection via 133 penetrating at least a part of the lower side of the insulating material 112 and directly connecting at least a part of the second wiring layer 122 to the lower surface of the metal via 131. The glass layer 111 and the metal via 131 can be protected via the insulating material 112. Further, by forming the first wiring layer and the second wiring layers 121, 122 on the insulating material 112 instead of the glass layer 111, the reliability of the first wiring layer and the second wiring layers 121, 122 can be improved by improving the adhesion, etc., and more diverse design designs can be applied. Further, by directly connecting the first connection via and the second connection vias 132, 133 to the metal via 131 without pads or lands, the total thickness of the substrate can be made thinner and the signal transmission path can be reduced.

[0022] On the other hand, the upper surface S1 and / or the lower surface S2 of the glass layer 111 and the upper surface and / or the lower surface of the metal via 131 may each have a surface roughness that is even greater than the upper surface and / or the lower surface of the insulating material 112. For example, the upper surface S1 and / or the lower surface S2 of the glass layer 111 and the upper surface and / or the lower surface of the metal via 131 can each have an average roughness (Ra) of about 0.1 μm or more and less than 10 μm, or 0.1 μm or more and 2 μm or less, respectively, since scribing can be performed with a laser as described above. On the other hand, in the case of the insulating material 112 that may include a Ajinomoto build-up film (ABF), the surface roughness, for example, the average roughness (Ra) can be about 400 nm to 800 nm.

[0023] Referring to the drawings, a printed circuit board 100 according to an example may further include a frame 105 having a through-hole H. The glass layer 111 may be at least partially disposed within the through-hole H. The insulating material 112 can cover at least a part of each of the upper and lower surfaces of the frame 105. The insulating material 112 can fill at least a part between the frame 105 and the glass layer 111 within the through-hole H. If necessary, at least a part between the frame 105 and the glass layer 111 within the through-hole H may be filled with a separate filling material. The frame 105 can include a material with excellent rigidity. Since the frame 105 can be used as a jig during the process, the process can be performed at the panel level through the frame 105. Further, after singulation, leaving the frame 105 in the final unit can be more advantageous in warpage control.

[0024] Referring to the drawings, a printed circuit board 100 according to an example may further include a plurality of first build-up insulating layers 141 disposed on the upper surface of the insulating material 112, a plurality of first build-up wiring layers 142 respectively disposed on or within the plurality of first build-up insulating layers 141, and / or a plurality of first build-up via layers 143 respectively disposed within the plurality of first build-up insulating layers 141 and each connected to one or more of the plurality of first build-up wiring layers 142. For example, a build-up layer may be formed on the upper side of the glass layer 111. For example, the printed circuit board 100 may include the glass layer 111 as a core layer, a build-up layer may be formed on at least one side of the core layer, and it may be used as a package substrate or an interposer substrate, etc.

[0025] Referring to the drawings, an example of a printed circuit board 100 may further include a plurality of second build-up insulating layers 151 disposed on the lower surface of the insulating material 112, a plurality of second build-up wiring layers 152 disposed on or within the plurality of second build-up insulating layers 151, and / or a plurality of second build-up via layers 153 disposed within the plurality of second build-up insulating layers 151 and each connected to one or more of the plurality of second build-up wiring layers 152. For example, the printed circuit board 100 may include a glass layer 111 as a core layer, build-up layers may be formed on both sides of the core layer, and may be used as a package substrate or an interposer substrate, etc.

[0026] Referring to the drawings, an example of a printed circuit board 100 may further include a first passivation layer 161 disposed on the uppermost of a plurality of first build-up insulating layers 141, having a first opening that covers at least a portion of the uppermost of a plurality of first build-up wiring layers 142 and exposes at least another portion, and / or a second passivation layer 162 disposed on the lowermost of a plurality of second build-up insulating layers 151, having a second opening that covers at least a portion of the lowermost of a plurality of second build-up wiring layers 152 and exposes at least another portion. This makes it easier to protect the internal structure of the printed circuit board 100.

[0027] In the following section, the components of an example printed circuit board 100 will be described in more detail with reference to the drawings.

[0028] The frame 105 may include an organic insulating material. The organic insulating material may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or an inorganic filler, organic filler and / or glass fiber (glass cloth, glass fabric) together with the resin. For example, the organic insulating material may include, but is not limited to, CCL (copper clad laminate) or unclad CCL, and may also include other organic or inorganic materials with superior rigidity. The penetration H can penetrate between the upper and lower surfaces of the frame 105. The penetration H can continuously surround the perimeter of the side surface S3 of the glass layer 111.

[0029] The glass layer 111 may include glass, which is an amorphous solid. The glass may include, for example, pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, aluminosilicate glass, etc. However, it is not limited to these, and alternative glass materials such as fluorine glass, phosphoric acid glass, and chalcogen glass can also be used. Furthermore, other additives may be included to form glass with specific physical properties. Such additives may include not only calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda), but also magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, as well as carbonates and / or oxides of other elements. On the other hand, the glass layer 111 can be distinguished from organic insulating materials containing glass fibers (glass fiber, glass cloth, glass fabric), such as CCL (copper clad laminate) and PPG (prepreg). The glass layer 111 may be in the form of, for example, a glass plate. The through hole V can penetrate between the upper and lower surfaces of the glass layer 111. The side surface S3 may be one or multiple, depending on the shape of the glass layer 111. For example, if the glass layer 111 has a substantially rectangular shape on a plane, there may be multiple side surfaces S3, for example, four, but it is not limited to this. If the glass layer 111 has a substantially elliptical shape on a plane, there may be one side surface S3, but it is not limited to this.

[0030] The insulating material 112 may include an organic insulating material. The organic insulating material may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or an inorganic filler, an organic filler, and / or glass fiber (glass cloth, glass fabric) together with the resin. For example, the organic insulating material may include, but is not limited to, PPG (Prepreg), ABF (Ajinomoto Build-up Film), and PID (Photo Imageable Dielectric). The insulating material 112 may consist of multiple layers. In this case, each of the multiple layers may be integrated without boundaries, or interlayer boundaries may be defined. Also, the multiple layers may contain substantially the same insulating material, but may also contain different insulating materials.

[0031] The first and second wiring layers 121 and 122 can each contain metals. These metals can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the first and second wiring layers 121 and 122 can each contain chemical copper formed by electroless plating as a seed layer, and electroplated copper formed by electroplating based on this as a pattern plating layer. The first and second wiring layers 121 and 122 can each perform various functions depending on the design. For example, they can include signal patterns, power patterns, ground patterns, etc. These patterns can each have various forms such as lines, traces, planes, and pads.

[0032] The metal via 131 may contain metals such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the metal via 131 may contain a titanium layer and a copper layer formed by sputtering, i.e., sputtered titanium and sputtered copper, as seed layers, and based on this, electroplated copper formed by electroplating may be included as a pattern plating layer. The metal via 131 can perform various functions depending on the design. For example, it may include through-holes for signal transmission, through-holes for power transmission, and through-holes for ground transmission. The metal via 131 may include filled vias in which the through-hole V is filled with metal. The metal via 131 may have a cylindrical shape or an hourglass shape. There may be multiple metal vias 131.

[0033] The first and second connection vias 132 and 133 can each contain metal. The metals can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the first and second connection vias 132 and 133 can each contain chemical copper formed by electroless plating as a seed layer, and electrocopper formed by electroplating based on this as a pattern plating layer. The first and second connection vias 132 and 133 can each perform various functions depending on the design. For example, they can include signal transmission vias, power transmission vias, ground transmission vias, etc. The first and second connection vias 132 and 133 may each contain filled vias in which the via hole is filled with metal, or they may contain conformal vias in which metal is arranged along the wall surface of the via hole. The first and second connecting vias 132 and 133 may have tapered shapes in opposite directions. There may also be multiple first and second connecting vias 132 and 133.

[0034] The multiple first build-up insulating layers and the second build-up insulating layers 141, 151 may each contain an organic insulating material. The organic insulating material may be a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or may contain an inorganic filler, an organic filler, and / or glass fiber (glass cloth, glass fabric) together with the resin. Examples of organic insulating materials include, but are not limited to, PPG (Prepreg), ABF (Ajinomoto Build-up Film), and PID (Photo Imageable Dielectric). The multiple first build-up insulating layers and the second build-up insulating layers 141, 151 may each consist of multiple layers. In this case, each of the multiple layers may be integrated without boundaries, or interlayer boundaries may be separated. Furthermore, each of the multiple layers may contain substantially the same insulating material, or may contain different insulating materials. The multiple first build-up insulating layers and the second build-up insulating layers 141, 151 may have the same number of layers as each other, but are not limited to this, and the multiple first build-up insulating layers 141 may have a relatively larger number of layers.

[0035] The multiple first and second build-up wiring layers 142, 152 can each contain a metal. The metals can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the multiple first and second build-up wiring layers 142, 152 can each contain chemical copper formed by electroless plating as a seed layer, and electrocopper formed by electroplating based on this as a pattern plating layer. The multiple first and second build-up wiring layers 142, 152 can each perform various functions depending on the design. For example, they can include signal patterns, power patterns, ground patterns, etc. These patterns can each have various forms such as lines, traces, planes, and pads. The multiple first build-up wiring layers and second build-up wiring layers 142, 152 may have the same number of layers as the others, but the multiple first build-up wiring layers 142 may have a relatively larger number of layers.

[0036] The multiple first build-up via layers and second build-up via layers 143, 153 can each contain a metal. The metals can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the multiple first build-up via layers and second build-up via layers 143, 153 can each contain chemical copper formed by electroless plating as a seed layer, and electrocopper formed by electroplating based on this as a pattern plating layer. The multiple first build-up via layers and second build-up via layers 143, 153 can each perform various functions depending on the design. For example, they can include signal transmission connection vias, power transmission connection vias, ground transmission connection vias, and so on. The multiple first build-up via layers and second build-up via layers 143, 153 may each include filled vias in which the via holes are filled with metal, or they may include conformal vias in which metal is arranged along the walls of the via holes. The multiple first build-up via layers and second build-up via layers 143, 153 may each include multiple connecting vias. The connecting vias included in each of the multiple first build-up via layers 143 may have a tapered shape in the opposite direction to the connecting vias included in each of the multiple second build-up via layers 153. The multiple first build-up via layers and second build-up via layers 143, 153 may have the same number of layers, but the multiple first build-up via layers 143 may have a relatively larger number of layers.

[0037] The first passivation layer and the second passivation layers 161 and 162 may each contain an organic insulating material. The organic insulating material may be a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or may contain an inorganic filler and / or organic filler together with the resin. For example, the organic insulating material may be, but is not limited to, ABF (Ajinomoto Build-up Film), PID (Photo Imageable Dielectric), SR (Solder Resist), etc. The first passivation layer and the second passivation layers 161 and 162 may each consist of multiple layers. The first and second passivation layers 161 and 162 may each have multiple openings, and the patterns exposed through each opening may be, but are not limited to, SMD (Solder Mask Defined) and / or NSMD (Non Solder Mask Defined) types.

[0038] Figure 3 schematically shows a top-view image of the surface of the glass layer on which the metal vias are formed, taken with an electron microscope. Figure 4 schematically shows a cross-sectional image of the glass layer on which the metal vias are formed, taken with an electron microscope, taken along the line A-A' in Figure 3.

[0039] Referring to the drawings, surface roughness can be formed on the surface of the glass layer and the surface of the metal via. For example, as described above, roughness can be formed on the surface of the glass layer and the surface of the metal via by skiving using a laser. In this case, the upper surface of the glass layer may have a height difference of 10 μm or more and less than 100 μm, 30 μm or more and less than 90 μm, or 50 μm or more and less than 80 μm. For example, during the skiving process, at least a portion of the upper surface of the glass layer may be removed more than at least another portion, resulting in a significant height difference that falls outside the range of surface roughness, e.g., the surface roughness (Ra) described above. Surface roughness can be formed on at least a portion and at least another portion of the upper surface of the glass layer within the height difference. Furthermore, the metal via has a landless structure, and its upper surface can protrude beyond at least a portion of the upper surface of the glass layer. For example, during the skiving process, the glass layer around the metal via can be removed, resulting in a structure in which the metal via protrudes. For example, the upper surface of a metal via can protrude by 10 μm to less than 100 μm, 30 μm to less than 90 μm, or 50 μm to less than 80 μm from at least a portion of the upper surface of the glass layer. On the other hand, the above-described content can be applied not only to the upper surface of the glass layer and the upper surface of the metal via, but also to the lower surface of the glass layer and the lower surface of the metal via. On the other hand, an electron microscope such as an SEM (Scanning Electron Microscope) or a TEM (Transmission Electron Microscope) can be used. Such technical content can be applied to the printed circuit board 100 according to the example described above.

[0040] In this invention, the expression "cover" can include not only covering the entire object but also covering at least a part of it, and can include not only directly covering the object but also indirectly covering it. Furthermore, the expression "fill" can include not only completely filling the object but also filling at least a part of it, and can also include nearly filling the object. For example, it can include cases where there are some gaps or voids. Also, the expression "enclose" can include not only completely enclosing the object but also partially enclosing it and generally enclosing it. Furthermore, "expose" can include not only completely exposing the object but also partially exposing it, and "exposure" can mean that the component is exposed from what it is embedded in.

[0041] In the present invention, "displayed within a cavity, cavity, through-hole, or through-hole" can include not only cases where the object is completely placed within a cavity, cavity, through-hole, or through-hole, but also cases where a portion of it protrudes upward or downward in cross-section. For example, if the object is placed within a cavity, cavity, through-hole, or through-hole on a plane, it can be interpreted in a broader sense.

[0042] In this invention, the determination can be made including process errors, positional deviations, and measurement errors that substantially occur during the manufacturing process. For example, "substantially the same direction" can include not only completely identical directions but also nearly identical directions. Similarly, "substantially coplanar" can include not only completely coplanar surfaces but also nearly coplanar surfaces. Furthermore, "substantially having a specific shape" can include not only completely having such a shape but also having nearly such a shape. Moreover, "substantially the same insulating material" can mean not only completely identical insulating materials but also insulating materials of the same type. Therefore, even if the composition of the insulating materials is substantially the same, their specific composition ratios may differ slightly.

[0043] In this invention, "on a cross-section" can mean the cross-sectional shape when the object is cut vertically, or the cross-sectional shape when the object is viewed from the side. "On a plane" can mean the planar shape when the object is cut horizontally, or the planar shape when the object is viewed from the top or bottom.

[0044] In this invention, terms such as "lower side," "lower part," and "bottom surface" are used for convenience to mean the downward direction relative to the cross-section in the drawing, while terms such as "upper side," "upper part," and "top surface" are used to mean the opposite direction. However, this is merely a definition of direction for explanatory purposes, and it goes without saying that the scope of rights in the patent claims is not particularly limited by such descriptions of direction, and the concepts of up / down can be changed at any time.

[0045] In this invention, "connected" is a concept that includes not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, "electrically connected" is a concept that includes both cases where they are physically connected and cases where they are not connected. In addition, expressions such as "first," "second," etc., are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, within the scope of the rights, the first component may be named the second component, and similarly, the second component may be named the first component.

[0046] In this invention, "thickness, width, length, depth, line width, spacing, pitch, separation distance, surface roughness," etc., can be measured using a scanning microscope or optical microscope based on a cross-section obtained by polishing or cutting the printed circuit board. The cut cross-section can be a vertical or horizontal cross-section, and each value can be measured based on the required cut cross-section. For example, the width of the upper and / or lower ends of a via can be measured on a cross-section cut along the central axis of the via. In this case, if the values ​​are not constant, the values ​​can be determined by the average value of the values ​​measured at any five points.

[0047] The expression "example" as used in this invention does not mean that each embodiment is the same as another, but is provided to highlight and illustrate the unique and distinct features of each. However, the examples presented above do not preclude their realization in combination with features of other examples. For example, even if a matter described in a particular example is not described in another example, it can be understood as a description related to that other example, unless there is a description in the other example that contradicts or is contrary to that description.

[0048] The terms used in this invention are for illustrative purposes only and are not intended to limit the invention. In this context, singular expressions include plural expressions unless the context clearly indicates a different meaning. [Explanation of symbols]

[0049] 1000:Electronic equipment 1010: Mainboard 1020: Chip-related components 1030: Network-related components 1040: Other parts 1050: Camera 1060: Antenna 1070: Display 1080: Battery 1090: Signal line 100: Printed circuit board 111: Glass layer 112: Insulating material 121, 122: Wiring layer 131: Metal Via 132, 133: Connection vias 141, 151: Build-up insulating layer 142, 152: Build-up wiring layer 143, 153: Build-up via layer 161, 162: Passivation layer H: Penetration part V: Through hole S1:Top surface S2: Bottom surface S3: Side view

Claims

1. A glass layer having an upper surface and a lower surface, and a side surface connecting the upper surface and the lower surface, A through hole penetrating between the upper and lower surfaces of the glass layer, Includes a metal via that fills at least a portion of the through hole, A printed circuit board in which one or more of the upper and lower surfaces of the glass layer and one or more of the upper and lower surfaces of the metal vias each have a surface roughness greater than that of the side surfaces of the glass layer.

2. The printed circuit board according to claim 1, wherein the upper and lower surfaces of the glass layer and the upper and lower surfaces of the metal vias have a surface roughness that is even greater than that of the side surfaces of the glass layer.

3. The upper surface of the glass layer has a surface roughness even greater than that of the upper surface of the metal via. The printed circuit board according to claim 2, wherein the lower surface of the glass layer has a surface roughness even greater than that of the lower surface of the metal via.

4. The printed circuit board according to claim 2, wherein the upper and lower surfaces of the glass layer and the upper and lower surfaces of the metal vias each have an average roughness (Ra) of 0.1 μm or more and less than 10 μm.

5. The printed circuit board according to claim 2, wherein the side surface of the glass layer has an average roughness (Ra) of 0.001 μm or more and less than 0.1 μm.

6. An insulating material covering at least a portion of the upper and lower surfaces of the glass layer, and the upper and lower surfaces of the metal vias, A first wiring layer is placed on the upper surface of the insulating material, A first connecting via that penetrates at least a portion of the upper side of the insulating material and directly connects at least a portion of the first wiring layer to the upper surface of the metal via, A second wiring layer is placed on the lower surface of the insulating material, The printed circuit board according to claim 1, further comprising: a second connecting via that penetrates at least a portion of the lower side of the insulating material and directly connects at least a portion of the second wiring layer to the lower surface of the metal via.

7. The printed circuit board according to claim 6, wherein the upper and lower surfaces of the glass layer and the upper and lower surfaces of the metal vias have a surface roughness that is even greater than that of the upper and lower surfaces of the insulating material.

8. The frame further includes a through portion, At least a portion of the glass layer is disposed within the penetration portion, The printed circuit board according to claim 6, wherein the insulating material covers at least a portion of the upper and lower surfaces of the frame and fills at least a portion of the space between the frame and the glass layer within the through-hole.

9. A plurality of first build-up insulating layers are arranged on the upper surface of the insulating material, A plurality of first build-up wiring layers, each disposed on or within the plurality of first build-up insulating layers, The printed circuit board according to claim 6, further comprising a plurality of first build-up via layers, each disposed within the plurality of first build-up insulating layers and each connected to one or more of the plurality of first build-up wiring layers.

10. A plurality of second build-up insulating layers are disposed on the lower surface of the insulating material, A plurality of second build-up wiring layers, each disposed on or within the plurality of second build-up insulating layers, The printed circuit board according to claim 9, further comprising a plurality of second build-up via layers, each disposed within the plurality of second build-up insulating layers and each connected to one or more of the plurality of second build-up wiring layers.

11. A glass layer having an upper surface and a lower surface, and a side surface connecting the upper surface and the lower surface, A through hole penetrating between the upper and lower surfaces of the glass layer, Includes a metal via that fills at least a portion of the through hole, A printed circuit board in which the upper and lower surfaces of the glass layer and the upper and lower surfaces of the metal vias each have an average roughness (Ra) of 0.1 μm or more and less than 10 μm.

12. The printed circuit board according to claim 11, wherein the upper and lower surfaces of the glass layer and the upper and lower surfaces of the metal vias each have an average roughness (Ra) of 0.1 μm or more and 2 μm or less.

13. The printed circuit board according to claim 11, wherein at least a portion and at least another portion of the upper surface of the glass layer have height differences that fall outside the range of average roughness (Ra) formed on the upper surface of the glass layer.

14. The printed circuit board according to claim 11, wherein the metal vias have a landless structure.

15. The printed circuit board according to claim 14, wherein the upper surface of the metal via protrudes more than at least a portion of the upper surface of the glass layer.

16. An insulating material covering at least a portion of the upper and lower surfaces of the glass layer, and the upper and lower surfaces of the metal vias, A first wiring layer is placed on the upper surface of the insulating material, A first connecting via that penetrates at least a portion of the upper side of the insulating material and directly connects at least a portion of the first wiring layer to the upper surface of the metal via, A second wiring layer is placed on the lower surface of the insulating material, The printed circuit board according to claim 11, further comprising: a second connecting via that penetrates at least a portion of the lower side of the insulating material and directly connects at least a portion of the second wiring layer to the lower surface of the metal via.

17. The frame further includes a through portion, At least a portion of the glass layer is disposed within the penetration portion, The printed circuit board according to claim 16, wherein the insulating material covers at least a portion of the upper and lower surfaces of the frame and fills at least a portion of the space between the frame and the glass layer within the through-hole.

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