Semiconductor equipment

Abstract

The present invention provides a semiconductor device that can reduce malfunctions caused by current noise and effectively protect switching elements from overcurrent, a semiconductor device equipped therewith, and a semiconductor module equipped therewith. [Solution] The semiconductor device has a temperature sense region 9 which includes a semiconductor substrate 6, a switching element formed on the semiconductor substrate 6, and a temperature sense diode 20 provided independently of the switching element on the surface side of the semiconductor substrate 6 and having temperature-dependent characteristics.

Description

[Technical Field]

[0001] This invention relates to a semiconductor device. [Background technology]

[0002] In switching devices, thermal damage can occur if an overcurrent continues to flow, for example, during a short circuit. To prevent this malfunction, for example, Patent Document 1 discloses a semiconductor device that includes a semiconductor switching element, a semiconductor drive circuit, a sense element formed on the semiconductor switching element, and an overcurrent detection unit formed on the semiconductor drive circuit. The sense element consists of a sense terminal through which a current proportional to the main current of the semiconductor switching element flows, and a sense resistor connected between the main terminal and the sense terminal of the semiconductor switching element to convert the sense current into a voltage. The overcurrent detection unit detects the sense current flowing through the sense element, and if the sense current exceeds a predetermined value, it turns off the semiconductor switching element to protect it from overcurrent. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2013-247804 [Overview of the project] [Problems that the invention aims to solve]

[0004] The overcurrent protection method described in Patent Document 1 is a method that turns off a semiconductor switching element based on the sense current, and is therefore susceptible to noise. In some cases, it may mistakenly detect a noisy sense current as an overcurrent. To prevent such malfunctions due to noise, there is a method that does not immediately turn off the semiconductor switching element when the sense current exceeds a predetermined threshold, but rather turns it off after a certain waiting time (mask time) has elapsed.

[0005] However, this method of incorporating a waiting time still has its challenges. A certain waiting time is necessary to account for the effects of noise (for example, around 500 nanoseconds), but as the on-resistance of devices decreases, the time it takes for a device to be destroyed by overcurrent becomes shorter than the waiting time, and there are cases where the overcurrent protection system itself becomes ineffective.

[0006] Therefore, one embodiment of the present invention provides a semiconductor device that can reduce malfunctions caused by current noise and effectively protect switching elements from overcurrent. [Means for solving the problem]

[0007] One embodiment of the present invention provides a semiconductor device comprising a semiconductor substrate, a switching element formed on the semiconductor substrate, and a temperature sensing element provided independently of the switching element on the surface side of the semiconductor substrate and having temperature-dependent characteristics.

[0008] Furthermore, one embodiment of the present invention provides a single-function semiconductor device comprising a semiconductor substrate, a switching element formed on the semiconductor substrate, and a temperature sensing element provided independently of the switching element on the surface side of the semiconductor substrate and having temperature-dependent characteristics, wherein the switching element is used.

[0009] With the above configuration, if a temperature change occurs on the surface side of the semiconductor substrate, the characteristics of the temperature sensing element (voltage value, resistance value, etc.) will change accordingly. Therefore, by monitoring the change in the characteristics of the temperature sensing element, temperature changes of the semiconductor substrate can be detected. Using this relationship, for example, when an overcurrent flows through a switching element due to a short circuit, the temperature rise of the semiconductor substrate due to the overcurrent can be detected, and based on the detection result, it can be determined whether or not an overcurrent is flowing through the switching element. Moreover, since the monitored object is not the sense current flowing through the switching element, even if noise is superimposed on the sense current, it will not be mistakenly detected as an overcurrent due to the superimposed current. Therefore, malfunctions due to current noise can be reduced.

[0010] One embodiment of the present invention includes a pair of first and second electrodes on the semiconductor substrate, wherein the electrical circuit between the first and second electrodes is provided only with the temperature sensing element as a circuit element.

[0011] In one embodiment of the present invention, the temperature sensing element includes a pn diode made of a polysilicon layer formed on the semiconductor substrate.

[0012] Polysilicon can be easily formed in the desired shape and position using already established semiconductor manufacturing technologies. Therefore, by forming a polysilicon layer (pn diode) near the surface, which is a heat-generating area of ​​the semiconductor substrate, temperature changes of the semiconductor substrate can be detected with high accuracy. For example, by continuously applying a constant current to the pn diode, the forward voltage V of the pn diode can be measured. F By monitoring this, temperature changes in the semiconductor substrate can be detected.

[0013] In one embodiment of the present invention, the switching element includes a planar gate type MISFET having a gate electrode formed along the surface of the semiconductor substrate, and the polysilicon layer is formed in the same layer as the gate electrode.

[0014] This configuration allows the polysilicon layer (pn diode) to be formed in the same process as the gate electrode, thus suppressing the increase in the number of steps associated with pn diode formation. Furthermore, since the pn diode can be placed on the semiconductor substrate via a thin gate insulating film compared to relatively thick films such as interlayer insulating films, the position of the pn diode can be brought closer to the current path on the surface side of the semiconductor substrate. This improves the accuracy of detecting temperature changes in the semiconductor substrate.

[0015] In one embodiment of the present invention, the pn diode includes a p-type region and an n-type region surrounding the p-type region in a plan view.

[0016] With this configuration, the p-type and n-type regions do not overlap in a plan view, so no additional wiring is required, and contact can be easily made with either the p-type or n-type region.

[0017] In one embodiment of the present invention, the switching element includes a trench-gate type MISFET having a gate trench formed in the semiconductor substrate and a gate electrode embedded in the gate trench, and the polysilicon layer is embedded in a second trench formed independently of the gate trench in the semiconductor substrate.

[0018] This configuration allows for the formation of a second trench in the same process as the gate trench, and the formation of a polysilicon layer (pn diode) in the same process as the gate electrode, thereby suppressing the increase in the number of steps associated with the formation of the pn diode. Furthermore, because the pn diode is embedded in the surface of the semiconductor substrate, its position can be brought very close to the current path on the surface side of the semiconductor substrate. This improves the accuracy of detecting temperature changes in the semiconductor substrate.

[0019] In one embodiment of the present invention, the gate trench and the second trench are formed with the same width as each other.

[0020] This configuration allows for nearly identical etching rates when forming the gate trench and the second trench, ultimately resulting in the formation of gate trenches and second trenches of approximately the same depth. By making the depth of the second trench approximately the same as that of the gate trench where the MISFET channel is formed, temperature rise in the semiconductor substrate due to overcurrent can be quickly detected.

[0021] In one embodiment of the present invention, the temperature sensing element includes a pn diode consisting of an impurity region formed on the surface of the semiconductor substrate.

[0022] Impurity regions can be easily formed at desired locations using already established semiconductor manufacturing technologies. Therefore, by forming impurity regions (pn diodes) in close proximity to the current path on the surface side, which is the heat-generating part of the semiconductor substrate, temperature changes of the semiconductor substrate can be detected with high accuracy. For example, by continuously applying a constant current to the pn diode, the forward voltage V of the pn diode can be measured. F By monitoring this, temperature changes in the semiconductor substrate can be detected. Furthermore, pn diodes consisting of impurity regions operate well even in high-temperature regions (e.g., above 200°C), making them particularly effective for power devices such as SiC and GaN.

[0023] In one embodiment of the present invention, the pn diode includes a p-type region and an n-type region surrounding the p-type region in a plan view.

[0024] With this configuration, the p-type and n-type regions do not overlap in a plan view, so no additional wiring is required, and contact can be easily made with either the p-type or n-type region.

[0025] In one embodiment of the present invention, the temperature sensing element includes a series connection unit in which a plurality of the pn diodes are connected in series.

[0026] With this configuration, the forward voltage V F Since the amount of temperature change increases in proportion to the number of connected pn diodes, the sensitivity for detecting temperature changes can be improved. For example, the forward voltage V per pn diode F When the amplitude of the voltage is XmV / °C, if five of these pn diodes are connected in series to form a series unit, the total amplitude of the series unit can be made 5XmV / °C.

[0027] In one embodiment of the present invention, the temperature sensing element includes a configuration in which at least one pair of the series connection units are connected in parallel in opposite directions.

[0028] This configuration eliminates the distinction between anode and cathode polarity at the terminals of the pn diode assembly, thus improving the flexibility of wiring such as bonding wires when assembling modules.

[0029] In one embodiment of the present invention, the temperature sensing element includes an inverse series connection unit in which at least one pair of the pn diodes are connected in series in opposite directions.

[0030] In this configuration, a reverse bias is applied to at least one of the pair of pn diodes, increasing the total resistance of the reverse series connection unit. Therefore, the current required to monitor temperature changes can be kept low, achieving power savings.

[0031] In one embodiment of the present invention, the temperature sensing element includes a configuration in which a plurality of the inverse series connection units are connected in series.

[0032] This configuration allows for further power savings.

[0033] In one embodiment of the present invention, the temperature sensing element includes a configuration in which at least one pair of the pn diodes are connected in parallel in opposite directions.

[0034] This configuration eliminates the distinction between anode and cathode polarity at the terminals of the pair of pn diodes, thus improving the flexibility of wiring such as bonding wires when assembling modules.

[0035] In one embodiment of the present invention, the temperature sensing element is located at the peripheral edge of the semiconductor substrate.

[0036] This configuration allows for a relatively large area to be secured outside the installation area of ​​the temperature sensing element, thus enabling a larger area for the terminals used by the switching element. As a result, even with a smaller chip size, wiring components such as bonding plates and relatively thick bonding wires can be connected to these terminals.

[0037] In one embodiment of the present invention, the semiconductor substrate includes a SiC semiconductor substrate.

[0038] This configuration allows for good protection of low on-resistance SiC switching elements from overcurrent.

[0039] One embodiment of the present invention provides a semiconductor module that includes the semiconductor device and a second semiconductor device, which is electrically connected to the switching element and the temperature sensing element, and which has a circuit that interrupts the current path of the switching element when it is determined that an overcurrent is flowing through the switching element based on a change in the characteristics of the temperature sensing element.

[0040] This configuration allows for the realization of a semiconductor module that, because it includes the semiconductor device described above, can reduce malfunctions caused by current noise and effectively protect the switching element from overcurrent. [Brief explanation of the drawing]

[0041] [Figure 1] Figure 1 is a schematic external view of a semiconductor device according to one embodiment of the present invention. [Figure 2] Figure 2 is a circuit diagram of a semiconductor module equipped with the semiconductor device shown in Figure 1. [Figure 3] Figure 3 is a diagram that shows the planar structure of the semiconductor device shown in Figure 1 in more detail. [Figure 4A] Figure 4A is a schematic plan view showing the structure of the cell region of the semiconductor device shown in Figure 3. [Figure 4B] Figure 4B is a cross-sectional view of Figure 4A (cross-sectional view along line BB). [Figure 5A]Figure 5A is a schematic plan view showing the structure of the temperature sense region of the semiconductor device shown in Figure 3. [Figure 5B] Figure 5B is a cross-sectional view of Figure 5A (cross-sectional view along line BB). [Figure 5C] Figure 5C shows a modified version of the structure shown in Figure 5B. [Figure 6] Figure 6 is a flowchart of the manufacturing process for the semiconductor device. [Figure 7A] Figure 7A shows a part of the manufacturing process for the semiconductor device. [Figure 7B] Figure 7B shows the next step after Figure 7A. [Figure 7C] Figure 7C shows the next step after Figure 7B. [Figure 7D] Figure 7D shows the next step after Figure 7C. [Figure 7E] Figure 7E shows the next step after Figure 7D. [Figure 7F] Figure 7F shows the next step after Figure 7E. [Figure 7G] Figure 7G shows the next step after Figure 7F. [Figure 7H] Figure 7H shows the next step after Figure 7G. [Figure 7I] Figure 7I shows the next step after Figure 7H. [Figure 7J] Figure 7J shows the next step after Figure 7I. [Figure 7K] Figure 7K shows the next step after Figure 7J. [Figure 7L] Figure 7L shows the next step after Figure 7K. [Figure 8] Figure 8 is a graph illustrating how the forward voltage of the temperature sense diode changes with temperature. [Figure 9A] Figure 9A is a schematic plan view showing the structure of the temperature sense region of the semiconductor device shown in Figure 3. [Figure 9B] Figure 9B is a cross-sectional view of Figure 9A (cross-sectional view along line BB). [Figure 10]Figure 10 shows an example of the connection configuration of the temperature sense diode. [Figure 11] Figure 11 shows an example of the connection configuration of the temperature sense diode. [Figure 12] Figure 12 shows an example of the connection configuration of the temperature sense diode. [Figure 13] Figure 13 shows an example of the connection configuration of the temperature sense diode. [Figure 14] Figure 14 shows an example of the connection configuration of the temperature sense diode. [Figure 15A] Figure 3 is a schematic plan view showing the structure of the cell region of the semiconductor device. [Figure 15B] Figure 15B is a cross-sectional view of Figure 15A (cross-sectional view along line BB). [Figure 16A] Figure 16A is a schematic plan view showing the structure of the temperature sense region of the semiconductor device shown in Figure 3. [Figure 16B] Figure 16B is a cross-sectional view of Figure 16A (cross-sectional view along line BB). [Figure 16C] Figure 16C is a cross-sectional view (cross-sectional view along line CC) of Figure 16A. [Modes for carrying out the invention]

[0042] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0043] Figure 1 is a schematic external view of a semiconductor device 1 according to one embodiment of the present invention.

[0044] The semiconductor device 1 is a discrete semiconductor device having a single function due to a switching element SW. The switching element SW may be, for example, a MISFET (Metal Insulator Semiconductor Field Effect Transistor), or other types such as an IGBT (Insulated Gate Bipolar Transistor) or a JFET (Junction Field Effect Transistor). These may be bipolar transistors, thyristors, etc. In this embodiment, the switching element SW is shown as a MISFET. A source pad 2 and a gate pad 3 are formed on the surface of the semiconductor device 1, which is formed as a rectangular chip in plan view. The source pad 2 covers almost the entire surface, and the gate pad 3 is located in the inner region of the source pad 2. Although not shown in the figures, a drain electrode is formed on the back surface of the semiconductor device 1.

[0045] In addition to the switching element SW described above, the semiconductor device 1 is also provided with a temperature sensing element TS. The temperature sensing element TS is located on the surface side of the semiconductor device 1. The temperature sensing element TS is independent of the switching element SW and does not directly contribute to the switching operation of the switching element SW.

[0046] Next, an overview of the overcurrent protection method in the semiconductor module 4 equipped with the semiconductor device 1 will be described. Figure 2 is a circuit diagram of the semiconductor module 4 equipped with the semiconductor device 1 shown in Figure 1.

[0047] The semiconductor module 4 includes a semiconductor device 1 and a gate driver G / D as an example of a second semiconductor device of the present invention having a short-circuit protection circuit 5. The semiconductor module 4 may also include semiconductor chips (ICs, discretes, etc.) other than those shown in Figure 2.

[0048] The short-circuit protection circuit 5 is electrically connected independently to the gate G of the switching element SW and the temperature sensing element TS. The short-circuit protection circuit 5 constantly monitors the characteristics of the temperature sensing element TS. For example, if a short circuit occurs in the switching element SW and an overcurrent flows, the resulting heat generation changes the characteristics of the temperature sensing element TS. The short-circuit protection circuit 5 detects this change in characteristics as the occurrence of a short circuit in the switching element SW and turns off the gate G of the switching element SW. This interrupts the drain current Id flowing between the source and drain (SD) of the switching element SW, thereby protecting the switching element SW.

[0049] Figure 3 is a diagram that shows the planar structure of the semiconductor device 1 in Figure 1 in more detail.

[0050] The semiconductor device 1 includes a semiconductor substrate 6 that defines its external shape, and has a structure on which a switching element SW and a temperature sensing element TS are formed on the semiconductor substrate 6.

[0051] The semiconductor substrate 6 has a rectangular shape in plan view, and almost its entire surface is covered by a roughly rectangular source pad 2 in plan view. A cell region 7 constituting a switching element SW is formed in most of the area below the source pad 2. A gate pad 3 is located on at least one side of the outer periphery of the semiconductor substrate 6. A gate finger 8 is connected to the gate pad 3. The gate finger 8 extends to the center of the semiconductor substrate 6, distributing the cell region 7 to one side and the other, and also extends to the periphery of the semiconductor substrate 6, surrounding the cell region 7.

[0052] A temperature sense region 9, which constitutes the temperature sense element TS, is formed in the inner region of the cell region 7. The temperature sense region 9 is surrounded by the cell region 7. The location of the temperature sense region 9 may be, for example, the peripheral edge of the semiconductor substrate 6. If the temperature sense region 9 is located at the peripheral edge of the semiconductor substrate 6, a relatively large area can be secured on the semiconductor substrate 6 other than the temperature sense region 9, so the area of ​​the source pad 2 can be made larger. Therefore, even if the chip size is reduced, wiring components such as bonding plates and relatively thick bonding wires can be connected to the source pad 2.

[0053] In a plan view, the first electrode 10 and the second electrode 11 are arranged so as to sandwich the temperature sensing region 9. That is, a pair of first electrodes 10 and second electrodes 11 are arranged on the semiconductor substrate 6 with a gap between them, and the temperature sensing region 9 is formed in the region between the first electrode 10 and the second electrode 11. The first electrode 10 and the second electrode 11 are arranged side by side along one side of the semiconductor substrate 6 on which the gate pad 3 is located. This makes it easier to pull out wiring members such as bonding wires from the gate pad 3, the first electrode 10 and the second electrode 11 in the same direction (to the left in Figure 3). In addition, the first electrode 10 and the second electrode 11, as well as the source pad 2, gate pad 3 and gate finger 8, are made of electrode films of the same material and can be formed simultaneously, for example, by forming the electrode film on the semiconductor substrate 6 and then patterning the electrode film. <Cell structure> Figure 4A is a schematic plan view showing the structure (planar gate structure) of the cell region 7 of the semiconductor device 1 in Figure 3. Figure 4B is a cross-sectional view (cross-sectional view along line BB) of Figure 4A.

[0054] The semiconductor substrate 6 may be, for example, a SiC substrate, or alternatively, a GaN substrate, a Si substrate, etc. Further, the semiconductor substrate 6 may be an epitaxial substrate including a base substrate and an epitaxial layer grown thereon. In this embodiment, the case where the semiconductor substrate 6 is an n-type SiC epitaxial substrate is shown. The n-type SiC epitaxial substrate may include an n + -type base substrate and an n + -type epitaxial layer on the n - -type base substrate. The impurity concentration of the n + -type base substrate is, for example, 1.0×10 18 cm -3 ~1.0×10 20 cm -3 , and the impurity concentration of the n - -type epitaxial layer is, for example, 5.0×10 14 cm -3 ~5.0×10 16 cm -3 . Examples of the n-type impurity include N (nitrogen), As (arsenic), P (phosphorus), etc.

[0055] As shown in FIGS. 4A and 4B, in the cell region 7, a plurality of p-type body regions 12 are formed on the surface portion of the semiconductor substrate 6. The plurality of p-type body regions 12 may be formed, for example, in a matrix shape (row and column shape) in a plan view as shown in FIG. 4A, or alternatively, in a stripe shape, a honeycomb shape. A line partitioning each unit cell 13 of the switching element SW is set between adjacent p-type body regions 12. The p-type impurity concentration of the p-type body region 12 is, for example, 1×10 15 cm -3 ~1×10 20 cm -3 . Examples of the p-type impurity include B (boron), Al (aluminum) , etc.

[0056] On the surface portion of the inner region of the p-type body region 12, an n + -type source region 14 is formed at a distance from the periphery of the p-type body region 12. The n+ The n-type impurity concentration in the n-type source region 14 is higher than the impurity concentration in the n-type semiconductor substrate 6, for example, 1 × 10⁻⁶ 18 cm -3 ~5×10 21 cm -3 That's fine.

[0057] n + In the inner region of type source region 14, p + A type body contact region 15 is formed. + The type body contact region 15 is n + It is formed by penetrating the mold source region 14 in the depth direction. + The p-type impurity concentration in the p-type body contact region 15 is higher than that in the p-type body region 12, for example, 1 × 10⁻⁶ 18 cm -3 ~5×10 21 cm -3 That's fine.

[0058] A gate insulating film 16 is formed on the surface of the semiconductor substrate 6. The gate insulating film 16 may be made of, for example, silicon oxide (SiO2). The thickness of the gate insulating film 16 may be, for example, 300 Å to 600 Å.

[0059] A gate electrode 17 is formed on the gate insulating film 16. The gate electrode 17 is located on the peripheral edge of the p-type body region 12 (in plan view, n) with the gate insulating film 16 in between. + It faces the part surrounding the source region 14. The gate electrode 17 is made of, for example, n-type polysilicon (n-type doped polysilicon), but may also be made of p-type polysilicon. The thickness of the gate electrode 17 may be, for example, 6000 Å to 12000 Å.

[0060] An interlayer insulating film 18 covering the gate electrode 17 is formed over the entire surface of the semiconductor substrate 6. The interlayer insulating film 18 may be made of, for example, silicon oxide (SiO2), or, as will be described later, it may have a structure in which multiple films made of silicon oxide are stacked (see Figures 7I to 7L). The thickness of the interlayer insulating film 18 (total thickness if it consists of multiple films) may be, for example, 1000 Å to 2000 Å. Although not shown in the figures, the interlayer insulating film 18 has a source pad 2 and n + Type source region 14 and p + Wiring for electrically connecting the mold body contact area 15, and wiring for electrically connecting the gate pad 3 and the gate electrode 17 are formed to penetrate the mold body contact area 15, respectively. <Temperature sensing element structure> Figure 5A is a schematic plan view showing the structure of the temperature sense region 9 of semiconductor device 1 in Figure 3. Figure 5B is a cross-sectional view (cross-sectional view along line BB) of Figure 5A. Figure 5C shows a modified example of the structure in Figure 5B.

[0061] As shown in Figures 5A and 5B, a p-type region 19 is formed on the surface of the semiconductor substrate 6 in the temperature-sensing region 9. The p-type region 19 may be an impurity region of the same conductivity type as the p-type body region 12, and its p-type impurity concentration and depth may also be the same as those of the p-type body region 12.

[0062] On the surface of the semiconductor substrate 6, the gate insulating film 16 of the cell region 7 is formed and extends to the temperature sense region 9. In the temperature sense region 9, a temperature sense diode 20 (pn diode), which is an example of a temperature sense element TS, is formed on the gate insulating film 16. The temperature sense diode 20 faces the semiconductor substrate 6 with the gate insulating film 16 in between. For example, as shown in Figure 5B, the entire temperature sense diode 20 may face a single impurity region (in this embodiment, a p-type region 19) of the semiconductor substrate 6.

[0063] The temperature sense diode 20 is, for example, made of a single layer of polysilicon 21. The temperature sense diode 20 made of the polysilicon layer 21 may be formed in the same process as the gate electrode 17, so that it is in the same single layer as the gate electrode 17. In other words, the polysilicon layer 21 may be formed with a thickness of 6000 Å to 12000 Å, similar to the gate electrode 17. Of course, the polysilicon layer 21 may be formed in a different process than the gate electrode 17, or it may have a different thickness than the gate electrode 17.

[0064] The temperature sense diode 20 has a p-type region 22 and an n-type region surrounding the p-type region 22. + Includes type region 23. p-type region 22 is n + If the configuration is surrounded by type region 23, then p-type region 22 and n + Since the type region 23 does not overlap in a plan view, no additional wiring is required, and the p-type region 22 and n + It is possible to easily make contact with either of the type regions 23.

[0065] p-type region 22 and n + The type regions 23 may be formed so as to extend from the surface to the back surface of the polysilicon layer 21, as shown in Figure 5B, or they may be selectively formed on the surface portion of the polysilicon layer 21, although this is not shown. Note that the p-type region 22 is n + It does not have to be surrounded by type region 23; for example, p-type region 22 and n + The p-type regions 23 may have a partial non-shared periphery because they are formed adjacent to each other. Also, the p-type impurity concentration in the p-type region 22 is, for example, 1 × 10⁻⁶ 15 cm -3 ~1 × 10 20 cm -3 (Same as p-type body region 12) may exist. + The n-type impurity concentration in type region 23 is, for example, 1 × 10⁻⁶. 18 cm -3 ~5×10 21 cm -3 (n + It may be the same as type source area 14.

[0066] The temperature sense diode 20 is further p + It may include a type contact region 24 and a p-type outer peripheral region 25. + The p-type contact region 24 is formed in the inner region of the p-type region 22, with a gap between it and the periphery of the p-type region 22, and the p-type outer peripheral region 25 is n + It may be formed to surround the type region 23. + The p-type contact region 24 and the p-type outer peripheral region 25 may be formed to extend from the surface to the back surface of the polysilicon layer 21, as shown in Figure 5B, or they may be selectively formed on the surface portion of the polysilicon layer 21, although this is not shown. + The p-type impurity concentration in the type contact region 24 is, for example, 1 × 10⁻⁶. 18 cm -3 ~5×10 21 cm -3 (p + It may be the same as the p-type body contact region 15. The p-type impurity concentration in the p-type outer peripheral region 25 is, for example, 1 × 10⁻⁶. 15 cm -3 ~1 × 10 20 cm -3 (This may be the same as the p-type body region 12)

[0067] As shown in Figure 5C, the temperature sense diode 20 consists of a p-type base layer 26 made of p-type polysilicon (p-type doped polysilicon) with the opposite conductivity to the gate electrode 17, and an n-type base layer selectively formed on the surface of the p-type base layer 26. + Type region 23 and p + The configuration may include a type contact area 24.

[0068] The temperature sense diode 20 is covered by an interlayer insulating film 18 on a semiconductor substrate 6. The first electrode 10 is connected to the anode electrode via a contact hole 27 in the interlayer insulating film 18. + It is connected to the type contact region 24. The second electrode 11 is connected as the cathode electrode through the contact hole 28 of the interlayer insulating film 18. +It is connected to the type region 23. The first electrode 10 and the second electrode 11 connected to both ends of the temperature sense diode 20 are formed separately from the source pad 2 and gate pad 3 for the switching element SW, as described above. Therefore, the temperature sense diode 20 is electrically independent from the switching element SW.

[0069] Polysilicon can be easily formed in the desired shape and position using already established semiconductor manufacturing technologies. Therefore, the temperature sense diode 20 can be formed near the switching element SW and near the heat-generating surface of the semiconductor substrate 6, allowing for highly accurate detection of temperature changes in the semiconductor substrate 6. For example, by applying a constant current to the temperature sense diode 20, the forward voltage V of the temperature sense diode 20 can be detected. F By monitoring this, temperature changes in the semiconductor substrate 6 can be detected. For example, a constant current of 1 μA is applied, and the forward voltage V F You just need to monitor that. The current should be a constant current in the range of 1μA to 100μA.

[0070] The second electrode 11 integrally includes an annular contact portion 30 having a partial open portion 29 on the interlayer insulating film 18, and a linear lead portion 31 extending from the contact portion 30. The contact portion 30 surrounds the p-type region 22 in a plan view. The contact hole 28 is formed in an annular shape with a partial open portion along the contact portion 30.

[0071] The first electrode 10 integrally includes a contact portion 32 surrounded by the contact portion 30 of the second electrode 11 on the interlayer insulating film 18, and a line-shaped lead portion 33 extending from the contact portion 32 through the open portion 29. The contact portion 32 is p + It is positioned on the type contact area 24. The contact hole 27 is formed to overlap the lower part of the contact portion 32.

[0072] Next, the manufacturing method of semiconductor device 1 will be described. Figure 6 is a flowchart of the manufacturing process of semiconductor device 1. Figures 7A to 7L are diagrams showing some of the manufacturing processes of semiconductor device 1 in order. Note that Figures 7A to 7L do not correspond to each individual step in Figure 6. In the following, the manufacturing process of semiconductor device 1 will be described according to the flowchart in Figure 6, and Figures 7A to 7L will be referred to as needed.

[0073] To manufacture semiconductor device 1, for example, by epitaxial growth, n + n - A type epitaxial layer is formed (step S1). This forms the semiconductor substrate 6.

[0074] Next, p-type body regions 12 and p-type regions 19 are formed by selectively implanting p-type impurities into the semiconductor substrate 6 (step S2). Similarly, n-type and p-type impurities are formed by selectively implanting them into the semiconductor substrate 6. + Type source region 14 and p + A mold body contact region 15 is formed (steps S3, S4).

[0075] Next, as shown in Figure 7A, a gate insulating film 16 is formed on the surface of the semiconductor substrate 6 by thermal oxidation (step S5). Next, a polysilicon layer 21, which will be the base for the gate electrode 17 and the temperature sense diode 20, is formed by, for example, CVD (step S6). Next, a hard mask 34 made of silicon oxide (SiO2) (for example, with a thickness of about 9000 Å) is formed by, for example, CVD (step S7).

[0076] Next, as shown in Figure 7B, a resist film 35 for lithography of the hard mask 34 is formed (step S8). The resist film 35 has p-type regions 22 and n + It is formed to cover the hard mask 34 on the region 36 where the mold region 23 is to be formed.

[0077] Next, as shown in Figure 7C, the hard mask 34 is selectively etched through the resist film 35 (step S9). Etching may be performed, for example, by wet etching with hydrofluoric acid. After etching, the resist film 35 is removed.

[0078] Next, as shown in Figure 7D, n-type impurities (for example, phosphorus) are deposited in the region 37 exposed from the hard mask 34 of the polysilicon layer 21 (the region of the polysilicon layer 21 other than region 36), and the impurities are introduced into the region 37 by diffusion at, for example, around 1000°C (step S10). As a result, the region 37 including the gate electrode 17 portion of the polysilicon layer 21 becomes n-type polysilicon, while region 36 remains undoped.

[0079] Next, as shown in Figure 7E, the hard mask 34 remaining on the polysilicon layer 21 is removed by etching (step S11). Etching may be performed, for example, by wet etching with hydrofluoric acid.

[0080] Next, as shown in Figure 7F, with the gate electrode 17 portion of the polysilicon layer 21 selectively covered with a mask (not shown), boron, a p-type impurity, is injected into the entire surface of the polysilicon layer 21 (step S12). As a result, the region from the surface of the polysilicon layer 21 to partway along its thickness becomes a p-type region 38.

[0081] Next, as shown in Figure 7G, the n of the polysilicon layer 21 + After a mask (not shown) that selectively exposes the region to which the n-type region 23 should be formed is formed by lithography, n-type impurities are injected into the region 36 through the mask (step S13). + A type region 23 is formed. At this time n + As shown in Figure 7G, the mold region 23 may only be formed from the surface of the polysilicon layer 21 to a certain point in the thickness direction.

[0082] Next, as shown in Figure 7H, the p of the polysilicon layer 21+ After a mask (not shown) that selectively exposes the area to be formed as a p-type contact region 24 is formed by lithography, p-type impurities are injected into the region 36 through the mask (step S14). + A type contact region 24 is formed. At this time, p + As shown in Figure 7H, the mold contact region 24 may only be formed from the surface of the polysilicon layer 21 to a certain point in the thickness direction.

[0083] Next, as shown in Figure 7I, a hard mask 39 is formed that selectively covers the region of the polysilicon layer 21 where the temperature sense diode 20 and gate electrode 17 are to be formed. Then, the polysilicon layer 21 is selectively etched through the hard mask 39. This forms the temperature sense diode 20 and gate electrode 17 (not shown in Figure 7I).

[0084] Next, as shown in Figure 7J, with the hard mask 39 remaining, multiple insulating films are formed, for example, by a CVD method. The multiple insulating films may include, for example, a lower silicon oxide film 40 (for example, an NSG (Non-doped Silicate Glass) film) and an upper silicon oxide film 41 (for example, a PSG (Phosphorus Silicate Glass) film, a BPSG (Boron Phosphorus Silicate Glass) film, etc.), as shown in Figure 7J. This forms an interlayer insulating film 18 consisting of the hard mask 39, the silicon oxide film 40, and the silicon oxide film 41 (step S15).

[0085] Next, as shown in Figure 7K, contact holes 27 and 28 are formed by selectively etching the interlayer insulating film 18 (step S16).

[0086] Next, as shown in FIG. 7L, the semiconductor substrate 6 is heat-treated (reflowed) (step S17). The heat treatment is performed, for example, at 900°C to 1200°C for 5 to 15 minutes in a nitrogen (N2) atmosphere. As a result, the p-type region 38, n + -type region 23 and p + -type contact region 24 remaining on the surface portion of the polysilicon layer 21 diffuse until they reach the back surface of the polysilicon layer 21.

[0087] Thereafter, by forming various wirings, source pad 2, gate pad 3, first electrode 10, second electrode 11, passivation film, etc., the semiconductor device 1 is obtained.

[0088] Next, the operation of the semiconductor device 1 in the semiconductor module 4 and the overcurrent protection method will be described more specifically.

[0089] The electrical circuit configuration in the semiconductor module 4 is as shown in FIG. 2. A voltage is applied to the semiconductor device 1 connected in such a manner by a gate driver G / D. Specifically, mainly referring to FIGS. 3 and 4B, a bias voltage with the drain electrode side being positive is applied between the source pad 2 and the drain electrode (not shown). As a result, a reverse voltage is applied to the pn junction at the interface between the n-type semiconductor substrate 6 and the p-type body region 12. As a result, n + -type source region 14 and the semiconductor substrate 6, that is, the source-drain is in an off state. In this state, when a predetermined voltage with the gate pad 3 side being positive is applied between the source pad 2 and the gate pad 3, a bias to the p-type body region 12 is applied to the gate electrode 17. As a result, electrons are induced at the peripheral portion of the p-type body region 12, and an inversion channel is formed. Through this inversion channel, n + -type source region 14 and the semiconductor substrate 6 become conductive. Thus, the source-drain becomes conductive and a drain current Id flows.

[0090] On the other hand, referring to Figures 5A and 5B, a constant current is applied to the temperature sense diode 20 by the gate driver G / D. Furthermore, the short-circuit protection circuit 5 of the gate driver G / D controls the forward voltage V of the temperature sense diode 20. F This is constantly monitored. Under normal conditions, the IV characteristics of the temperature-sensing diode 20 follow the curve shown by the solid line in Figure 8, for example.

[0091] Then, when a short circuit occurs in the switching element SW (MISFET) shown in Figures 4A and 4B, causing an overcurrent to flow, a temperature rise occurs on the surface side of the semiconductor substrate 6. This temperature rise is also transmitted to the temperature sense region 9 (see Figure 5B) formed on the semiconductor substrate 6, which is common to the cell region 7. As a result, the forward voltage V of the temperature sense diode 20 in the temperature sense region 9 increases in response to this temperature rise. F The forward voltage V decreases. For example, as shown by the dashed curve in Figure 8, the rise voltage of the temperature sense diode 20 shifts to the low voltage side. The short-circuit protection circuit 5 controls this forward voltage V F A decrease in this voltage is detected as a short circuit in the switching element SW, and the voltage applied to the gate pad 3 is turned off. This interrupts the drain current Id flowing between the source and drain (SD) of the switching element SW, protecting the switching element SW.

[0092] Thus, when an overcurrent flows through the switching element SW due to a short circuit or the like, the temperature rise of the semiconductor substrate 6 caused by the overcurrent is measured by the forward voltage V of the temperature sense diode 20. FBased on the decrease, it can be detected, and according to the detection result, it is possible to determine whether an overcurrent is flowing through the switching element SW. Moreover, since the monitoring target is not the sense current flowing through the switching element SW, even when noise enters and is superimposed on the sense current, it will not be erroneously detected as an overcurrent due to the superimposed current. Therefore, malfunction due to current noise can be reduced. Also, different from the conventional overcurrent protection method, even if a certain waiting time (mask time) is provided, it can be completed in a short time, so it is very effective for low on-resistance devices (such as SiC, GaN, etc.) where the time for the device to be destroyed by an overcurrent is relatively short.

[0093] Also, in this embodiment, as shown in FIG. 5B, since the temperature sense diode 20 is made of a polysilicon layer 21 in the same layer as the gate electrode 17, an increase in the number of processes associated with the formation of the temperature sense diode 20 can be suppressed. Also, the temperature sense diode 20 can be disposed on the semiconductor substrate 6 through a thin gate insulating film 16 compared to a relatively thick film such as the interlayer insulating film 18. Therefore, the position of the temperature sense diode 20 can be brought close to the immediate vicinity of the current path on the surface side of the semiconductor substrate 6. Thereby, the accuracy of detecting the temperature change of the semiconductor substrate 6 can be improved.

[0094] FIG. 9A is a schematic plan view showing the structure of the temperature sense region 9 of the semiconductor device 1 in FIG. 3. FIG. 9B is a cross-sectional view (cross-sectional view taken along line B - B) of FIG. 9A. FIGS. 9A and 9B show another example of the structure of the temperature sense region 9. In FIGS. 9A and 9B, the same components as those shown in FIGS. 5A and 5B described above are denoted by the same reference numerals, and the description thereof is omitted.

[0095] In FIGS. 5A and 5B, the temperature sense diode 20 was made of a polysilicon layer 21 on the semiconductor substrate 6, but the temperature sense diode 42 (pn diode) in FIGS. 9A and 9B is composed of impurity regions selectively formed on the surface portion of the semiconductor substrate 6. Specifically, the temperature sense diode 42 includes a p-type region 43 and an n +Includes type region 44. p-type region 43 is n + If the configuration is surrounded by type region 44, then p-type region 43 and n + Since the type region 44 does not overlap in a plan view, no additional wiring is required, and the p-type region 43 and n + It is possible to easily make contact with either of the type regions 44.

[0096] The p-type region 43 consists of a part of the p-type region 19. On the other hand, n + The type region 44 is formed in a floating state on the surface of the p-type region 19. + Type region 44 is n + It may be formed in the same process as the type source region 14 (see Figure 4B). That is, n + Type region 44 is n + Similar to the type source area 14, 1 × 10 18 cm -3 ~5×10 21 cm -3 The n-type impurity concentration may be the same, and the impurities may be formed at the same depth.

[0097] The temperature sense diode 42 is further p + It may include a type contact region 45 and a p-type outer peripheral region 46. + The type contact region 45 is formed in the inner region of the p-type region 43, with a gap between it and the periphery of the p-type region 43, and the p-type outer peripheral region 46 is n + It may be formed to surround the p-type region 44. The p-type outer peripheral region 46 consists of a part of the p-type region 19, and n + The p-type region 43 is electrically connected to the p-type region 44 via the p-type region 19 below it. + The p-type contact region 45 is formed in a floating state on the surface of the p-type region 19. + The type contact area 45 is p + It may be formed in the same process as the mold body contact region 15 (see Figure 4B). That is, p + The type contact area 45 is p + Similar to the body contact area 15, 1 × 1018 cm -3 ~5×10 21 cm -3 The p-type impurity concentration may be the same, and the impurities may be formed at the same depth.

[0098] The first electrode 10, through the contact hole 27 of the interlayer insulating film 18, acts as the anode electrode. + It is connected to the type contact region 45. The second electrode 11 is connected as the cathode electrode through the contact hole 28 of the interlayer insulating film 18. + It is connected to type region 44.

[0099] As described above, the temperature sense diode 42 can perform the same function as the temperature sense diode 20. Furthermore, since the temperature sense diode 42 is formed on the semiconductor substrate 6 itself, the pn junction can be brought closer to the current path on the surface side, which is the heat-generating part of the semiconductor substrate 6, than in the case of the temperature sense diode 20. This allows for highly accurate detection of temperature changes in the semiconductor substrate 6. In addition, a pn diode made of impurity regions will operate well even in high-temperature regions (for example, above 200°C), making it particularly effective for power devices such as SiC and GaN.

[0100] Next, we will explain the variations in connection configurations when multiple temperature sense diodes 20 and 42 are provided. Figures 10 to 14 show examples of connection configurations for the temperature sense diodes 20 and 42, respectively. In Figures 10 to 14, reference numerals are given only to the elements necessary for explanation from the components shown in Figures 5A and 9A mentioned above.

[0101] First, as shown in Figure 10, the multiple temperature sense diodes 20, 42 may include a series connection unit 47 formed by connecting one first electrode 10 (anode) and the other second electrode 11 (cathode) in series. The series connection unit 47 may consist of two temperature sense diodes 20, 42 as shown in Figure 10, or, although not shown, it may consist of three or more temperature sense diodes 20, 42.

[0102] According to the configuration in Figure 10, the forward voltage V shown in Figure 8 F Since the amount of temperature change (shift) increases in proportion to the number of temperature sense diodes 20 and 42 connected, the sensitivity of temperature change detection can be improved. For example, the forward voltage V per temperature sense diode 20 or 42 F When the amplitude of the temperature is XmV / °C, five temperature sense diodes 20 and 42 are connected in series to form a series unit 47, and the total amplitude of the series unit 47 can be made 5XmV / °C.

[0103] Next, as shown in Figure 11, at least one pair of series connection units 47 may be connected in parallel in opposite directions. That is, the terminal first electrode 10 of one series connection unit 47 may be connected to the terminal second electrode 11 of the other series connection unit 47 to form terminal 48, and the terminal second electrode 11 of one series connection unit 47 may be connected to the terminal first electrode 10 of the other series connection unit 47 to form terminal 49.

[0104] According to the configuration shown in Figure 11, the terminals 48 and 49 of the assembly of temperature sense diodes 20 and 42, which are made up of multiple series-connected units 47, do not have a distinction between anode and cathode polarity. This improves the flexibility of wiring such as bonding wires when assembling semiconductor modules 4 (see Figure 2), etc. In other words, even if a reverse bias is applied to one series-connected unit 47, a forward bias is applied to the other series-connected unit 47 at that time, so at least one of them can function as a temperature sense diode.

[0105] Next, as shown in Figure 12, the multiple temperature sense diodes 20,42 may include an inverse series connection unit 50 formed by connecting the first electrodes 10 (anodes) of one and the other in series, or the second electrodes 11 (cathodes) of one and the other in series. The inverse series connection unit 50 may consist of two temperature sense diodes 20,42 as shown in Figure 12, or it may consist of three or more temperature sense diodes 20,42, although this is not shown. Furthermore, multiple inverse series connection units 50 may be connected in inverse series, as shown in Figure 13.

[0106] According to the configurations shown in Figures 12 and 13, at least one of the temperature sense diodes 20 and 42 constituting the reverse series connection unit 50 will have a reverse bias applied, thus increasing the total resistance of the reverse series connection unit 50. As a result, the current required to monitor the temperature changes of the temperature sense diodes 20 and 42 can be kept low, thereby achieving power savings.

[0107] Next, as shown in Figure 14, the temperature sense diodes 20 and 42 may include a configuration in which at least one pair are connected in parallel in opposite directions. That is, the first electrode 10 of one temperature sense diode 20 or 42 may be connected to the second electrode 11 of the other temperature sense diode 20 or 42 to form terminal 51, and the second electrode 11 of one temperature sense diode 20 or 42 may be connected to the first electrode 10 of the other temperature sense diode 20 or 42 to form terminal 52.

[0108] According to the configuration in Figure 14, similar to the configuration in Figure 11, there is no distinction between anode and cathode polarity at terminals 51 and 52 of the assembly of temperature sense diodes 20 and 42. This improves the flexibility of wiring such as bonding wires when assembling semiconductor modules 4 (see Figure 2), etc. In other words, even if a reverse bias is applied to one of the temperature sense diodes 20 and 42, a forward bias is applied to the other temperature sense diode 20 and 42 at that time, so at least one of them can function as a temperature sense diode.

[0109] As described above, the connection configurations of the multiple temperature sense diodes 20 and 42 are not limited to those shown in Figures 10 to 14, and any appropriate configuration can be adopted. Furthermore, the connection configuration concepts shown above (series, series + antiparallel, anti-series, multiple anti-series, anti-parallel, etc.) can also be applied to the temperature sense diodes 66 shown in Figures 16A to 16C, which will be described later.

[0110] Figure 15A is a schematic plan view showing the structure (trench gate structure) of the cell region 7 of the semiconductor device 1 in Figure 3. Figure 15B is a cross-sectional view (cross-sectional view along line BB) of Figure 15A. Figures 15A and 15B show another example of the structure of the cell region 7. In Figures 15A and 15B, the same reference numerals are used for components that are the same as those shown in Figures 4A and 4B, and their descriptions are omitted.

[0111] As shown in Figures 15A and 15B, gate trenches 53 are formed in the semiconductor substrate 6 in the cell region 7. The gate trenches 53 demarcate each unit cell 54 of the switching element SW. The gate trenches 53 may be formed in a grid pattern in plan view, for example, as shown in Figure 15A, or they may be formed in a stripe pattern, honeycomb pattern, or other configurations.

[0112] A p-type body region 55 is formed on the surface of each unit cell 54, and n + A p-type source region 56 is formed. The p-type impurity concentration in the p-type body region 55 is, for example, 1 × 10⁻⁶ 15 cm -3 ~1 × 10 20 cm -3 It is acceptable for it to be n + The n-type impurity concentration in the n-type source region 56 is higher than the impurity concentration in the n-type semiconductor substrate 6, for example, 1 × 10⁻⁶ 18 cm -3 ~5×10 21 cm -3 That's fine.

[0113] n + In the inner region of type source area 56, p +A type body contact region 57 is formed. + The body contact area 57 is n + It is formed by penetrating the mold source region 56 in the depth direction. + The p-type impurity concentration in the p-type body contact region 57 is higher than in the p-type body region 55, for example, 1 × 10⁻⁶ 18 cm -3 ~5×10 21 cm -3 That's fine.

[0114] A gate insulating film 58 is formed on the inner surface of the gate trench 53 and on the surface of the semiconductor substrate 6. The gate insulating film 58 may be made of, for example, silicon oxide (SiO2). The thickness of the gate insulating film 58 may be, for example, 300 Å to 600 Å.

[0115] A gate electrode 59 is embedded in the gate trench 53. The gate electrode 59 faces the p-type body region 55 on the side of the gate trench 53, separated by a gate insulating film 58. The gate electrode 59 is made of, for example, n-type polysilicon (n-type doped polysilicon), but may also be made of p-type polysilicon.

[0116] Next, the structure of the temperature sense region 9 when the cell region 7 is as shown in Figures 15A and 15B will be described. Figure 16A is a schematic plan view showing the structure of the temperature sense region 9 of the semiconductor device 1 in Figure 3. Figure 16B is a cross-sectional view of Figure 16A (cross-sectional view along line BB). Figure 16C is a cross-sectional view of Figure 16A (cross-sectional view along line CC). In Figures 16A to 16C, the same reference numerals are used for components that are the same as those shown in Figures 5A and 5B, and their explanations are omitted.

[0117] As shown in Figures 16A to 16C, the temperature sensing region 9 is demarcated by gate trenches 53 and surrounded by gate trenches 53. The temperature sensing region 9 may be, for example, a rectangular shape in plan view, surrounded on all four sides by gate trenches 53, as shown in Figure 16A.

[0118] In the temperature sensing region 9, the surface portion of the semiconductor substrate 6 has n + A type region 60 is formed, n + A p-type region 61 is formed below the n-type region 60. The p-type region 61 is n + It is adjacent to type region 60. + The n-type region 60 has an n-type impurity concentration and depth of n + The p-type source region 56 may be the same as the p-type body region 55. The p-type region 61 may have the same p-type impurity concentration and depth as the p-type body region 55, but in terms of depth, as shown in Figures 16B and 16C, it may be deeper than the p-type body region 55 and have a selectively downward-projecting protrusion 62.

[0119] A temperature sense trench 63, as an example of a second trench of the present invention, is formed in the inner region of the temperature sense area 9. That is, the temperature sense trench 63 is independent of the gate trench 53 that surrounds the temperature sense area 9. This temperature sense trench 63 may be formed with the same width as the gate trench 53, for example.

[0120] The temperature sense trench 63 may be formed to penetrate the p-type region 61, but as shown in Figures 16B and 16C, it may be formed on the protrusion 62 so as not to penetrate the p-type region 61, with its bottom located inside the p-type region 61 (protrusion 62).

[0121] Furthermore, the temperature sense trench 63 is formed in an annular shape in plan view, and a closed region 64 is partitioned inside it. In this closed region 64, p + A type contact region 65 is formed. + The type contact region 65 may be formed over the entire closed region 64, as shown in Figure 16A, or, although not shown, it may be selectively formed only on a part of the closed region 64. + The p-type contact region 65 has a p-type impurity concentration and depth. + It may be the same as the body contact area 57.

[0122] On the inner surface of the temperature sense trench 63, the gate insulating film 58 of the cell region 7 is formed, extending to the temperature sense region 9. Inside the gate insulating film 58, a temperature sense diode 66 (pn diode), which is an example of a temperature sense element TS, is formed.

[0123] The temperature sense diode 66 consists of an embedded polysilicon layer 67 embedded in the temperature sense trench 63. The temperature sense diode 66, consisting of the embedded polysilicon layer 67, may be formed in the same process as the gate electrode 59, or in a separate process from the gate electrode 59.

[0124] The temperature sense diode 66 has a p-type region 68 and an n-type region adjacent to the p-type region 68 in the lateral direction. + It includes a p-type region 69. In other words, a p-type region 68 is embedded to the bottom in a certain region of the annular temperature sense trench 63, and adjacent to this p-type region 68, n + The type region 69 may be embedded to the bottom in other regions of the temperature sense trench 63. p-type region 68 and n + If the type region 69 and the other are adjacent in the lateral direction, then the p-type region 68 and n + Since the type region 69 does not overlap in a plan view, no additional wiring is required, and the p-type region 68 and n + It is possible to easily make contact with either of the type regions 69.

[0125] Furthermore, the p-type impurity concentration in the p-type region 68 is, for example, 1 × 10⁻⁶. 15 cm -3 ~1 × 10 20 cm -3 (Same as p-type body region 55) may exist. + The n-type impurity concentration in type region 69 is, for example, 1 × 10⁻⁶. 18 cm -3 ~5×10 21 cm -3 (n + It may be the same as type source area 56.

[0126] The temperature sense diode 66 is further p+ It may include a type contact area 70. + The type contact region 70 is formed to be in contact with the p-type region 68, but n + The p-type region 69 is separated from the p-type region 68. + The type contact region 70 may be embedded to the bottom of the temperature sense trench 63 and be laterally adjacent to the p-type region 68, as shown in Figure 16C, or, although not shown, it may be adjacent to the p-type region 68 and n + It may be selectively formed on the surface of the p-type region 68 at a position away from the boundary with the type region 69. + The p-type impurity concentration in the type contact region 70 is, for example, 1 × 10⁻⁶. 18 cm -3 ~5×10 21 cm -3 (p + It may be the same as the body contact area 57.

[0127] Note that the first electrode 10 in Figure 3 is the anode electrode, p + The second electrode 11 in Figure 3 is connected to the type contact region 70 and acts as the cathode electrode. + It is connected to type region 69.

[0128] As described above, the temperature sense diode 66 can perform the same function as the temperature sense diode 20. Furthermore, because the temperature sense diode 66 (pn diode) is embedded in the surface of the semiconductor substrate 6, the pn junction can be brought closer to the current path on the surface side, which is the heat-generating part of the semiconductor substrate 6, than in the case of the temperature sense diode 20. This allows for the detection of temperature changes in the semiconductor substrate 6 with high accuracy.

[0129] Although one embodiment of the present invention has been described above, the present invention can also be implemented in other forms.

[0130] For example, a configuration in which the conductivity types of each semiconductor portion of the semiconductor device 1 are reversed may be adopted. That is, in the semiconductor device 1, the p-type portion may be n-type, and the n-type portion may be p-type.

[0131] Furthermore, in addition to the aforementioned temperature sense diodes 20 and 42 (pn diodes), Schottky barrier diodes and the like can also be used as the temperature sense element TS.

[0132] Furthermore, various design modifications can be made within the scope of the matters described in the patent claims. [Explanation of Symbols]

[0133] 1 Semiconductor device 2 Source Pads 3 Gate Pads 4. Semiconductor Modules 5. Short-circuit protection circuit 6 Semiconductor substrates 7 Cell Area 9. Temperature sensing region 10 1st electrode 11 Second electrode 12 p-type body region 13 unit cells 14 n + Type source area 16 Gate insulating film 17 Gate 20 Temperature-sensing diodes 21 Polysilicon layer 22 p-type region 23 n + type area 24 pages + Type Contact Area 25 p-type outer region 26 p-type base layer 42 Temperature-sensing diodes 43 p-type region 44 n + type area 45 p + Type Contact Area 46 p-type outer region 47 Series connection units 48 terminals 49 terminals 50 reverse series connection units 51 terminals 52 terminals 53 Gate Trench 54 unit cells 55 p-type body region 56 n + Type source area 58 Gate Insulator 59 🙏 63 Temperature Sensing Trench 66 Temperature-sensing diode 67 Embedded polysilicon layer 68 p-type region 69 n + type area 70 p + Type Contact Area SW switching element TS temperature sensing element G / D Gate Driver

Claims

1. A semiconductor chip with a rectangular shape in plan view, comprising a semiconductor substrate having a surface and a back surface facing the surface, A switching element formed on the semiconductor substrate, which performs a switching operation between a first electrode provided on the surface side and a second electrode provided on the back side of the semiconductor substrate in response to a signal input to a control electrode formed on the surface side of the semiconductor substrate, A gate finger extends from the control electrode along the outer circumference of the semiconductor chip and extends across the central part of the semiconductor chip, A temperature sensing element provided on the surface side and capable of outputting a temperature-dependent signal, The temperature sensing element includes a third electrode and a fourth electrode that are electrically connected to the temperature sensing element. The control electrode, the third electrode, and the fourth electrode have the same size and shape as each other. The control electrode is positioned in the center of the first edge of the semiconductor chip, and the third and fourth electrodes are positioned along the first edge between the first edge on which the control electrode is located and the second edge of the semiconductor chip adjacent to the first edge, on one side of the control electrode. The temperature sensing element is positioned adjacent to the gate finger, The semiconductor substrate includes a semiconductor layer, The temperature sensing element is formed in the polysilicon layer of the semiconductor layer, A semiconductor device comprising a polysilicon layer forming the temperature sensing element, the polysilicon layer having the same thickness as the gate electrode of the switching element.

2. The semiconductor device according to claim 1, further comprising a diode element capable of outputting a temperature-dependent signal as the temperature sensing element.

3. The semiconductor device according to claim 2, wherein the anode and cathode of the diode element are connected to the third electrode and the fourth electrode, respectively.

4. The switching element is a MISFET in which the first electrode is the source electrode, the second electrode is the drain electrode, and the control electrode is the gate electrode. The source electrode has two regions separated by the gate finger that crosses the central part of the semiconductor chip. The semiconductor device according to claim 1, wherein the third electrode and the fourth electrode are arranged adjacent to the periphery of one of the two separated regions of the source electrode.

5. The semiconductor device according to any one of claims 1 to 3, wherein the switching element is a MISFET in which the first electrode is a source electrode, the second electrode is a drain electrode, and the control electrode is a gate electrode.

6. The semiconductor device according to any one of claims 1 to 5, wherein the third electrode and the fourth electrode are connected to terminals electrically independent from the terminals to which the first electrode and the second electrode of the switching element are connected, respectively.

7. The semiconductor device according to claim 1 or 2, wherein the temperature sensing element includes a series connection unit in which at least one pair of pn diodes are connected in series or in reverse series.

8. The semiconductor device according to claim 1 or 2, wherein the temperature sensing element comprises at least one pair of pn diodes connected in antiparallel.

9. The semiconductor device according to claim 1, wherein the polysilicon layer forming the temperature sensing element includes selectively introduced impurity regions of a first conductivity type and impurity regions of a second conductivity type.

10. The semiconductor device according to claim 1, wherein the polysilicon layer forming the temperature sensing element includes a base layer of a second conductivity type and an impurity region of a first conductivity type selectively introduced on the surface of the base layer.

11. The semiconductor device according to any one of claims 1 to 10, wherein the switching element includes a trench-gate type MISFET having a gate trench formed on the semiconductor chip and defining a unit cell, a gate electrode embedded in the gate trench, a body region of a first conductivity type formed on the surface of the unit cell, a source region of a second conductivity type formed on the surface of the body region, and a drain region of a second conductivity type formed on the opposite side of the source region from the body region.

12. The semiconductor device according to any one of claims 1 to 11, wherein the temperature sensing element is disposed in the temperature sensing region between the third electrode and the fourth electrode.

13. The semiconductor device according to any one of claims 1 to 8, wherein the temperature sensing element comprises a first conductivity type region formed on the semiconductor substrate and a second conductivity type region surrounding the first conductivity type region.

14. The semiconductor device according to claim 1, wherein the semiconductor chip has, in a plan view, the first side, the second side, the third side, and the fourth side in the circumferential direction in that order.

15. The semiconductor device according to claim 1, wherein the semiconductor layer includes a SiC semiconductor layer.

16. The semiconductor device according to claim 15, wherein the temperature sensing terminal is formed in the polysilicon layer of the SiC semiconductor layer.

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