Timing generator, imaging device, and automated testing device

Abstract

It can suitably generate signals at any desired timing. [Solution] The timing generator comprises a counter, a control unit, a plurality of basic pulse generation units, and one or more latch output units. The counter performs a counting operation based on a clock signal. The control unit controls the operating state of each basic pulse generation unit by setting an operation start counter value for each of the basic pulse generation units. When the counter value input from the counter becomes the operation start counter value, the basic pulse generation unit enters an operating state and controls the logic level of at least one of the latch output units. The latch output unit outputs a timing signal corresponding to the control by at least one of the basic pulse generation units.

Description

Technical Field

[0001] The present invention relates to a timing generator, a photographing device, and an automatic test device.

Background Art

[0002] Conventionally, in applications where a single pulse must be precisely output, digital data indicating transition timing is input from the outside, and the output signal transitions (L→H or H→L) are accurately performed according to the transition timing. Also, in scenarios where multiple outputs are required, a timing generator (a timing generator with built-in memory) equipped with a memory for storing time-series data representing the pattern of timing pulses and a counter for sequentially providing read addresses to this memory is generally used. Furthermore, there are those that prepare multiple memories in a similar mechanism to obtain further multiple outputs.

[0003] Patent Document 1 discloses a technique for obtaining a high-resolution timing pulse by changing the timing of the output signal of a latch section according to the input bit data value.

[0004] Patent Document 2 discloses a technique for reducing the amount of data to be stored in a memory by having rising and falling addresses as edge data for timing pulses that need to be individually set while having the pulse repetition pattern itself as time-series data.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, in the case of a typical generator, a memory with enormous capacity is required to output arbitrary waveforms for a long period of time. The technology described in Patent Document 1 requires the preparation of multiple stages of the same circuit for continuous timing pulse output, which increases the complexity of the circuit. Furthermore, the technologies described in Patent Documents 1 and 2 can only generate timing patterns that are predetermined before the output starts, and it is difficult to dynamically change the timing generation content in response to some event or instruction from the user during execution.

[0007] Therefore, the present invention has been made in view of the above points, and aims to suitably generate arbitrary timing signals. [Means for solving the problem]

[0008] One aspect of the present invention is a timing generator comprising a counter, a control unit, a plurality of basic pulse generation units, and one or more latch output units, wherein the counter performs a counting operation based on a clock signal, the control unit controls the operating state of each basic pulse generation unit by setting an operation start counter value for each basic pulse generation unit, the basic pulse generation unit enters an operating state when the counter value input from the counter becomes the operation start counter value, and controls the logic level of at least one of the latch output units, and the latch output unit outputs a timing signal corresponding to the control by at least one of the basic pulse generation units.

[0009] Furthermore, in one embodiment of the present invention, the control unit sets a pulse generation pattern for each of the basic pulse generation units, which includes at least one of the following operations: logic level transition, single pulse generation, periodic pulse generation, and predetermined pulse generation based on time-series data, and the control unit controls the logic level of the latch output unit by performing an operation according to the set pulse generation pattern.

[0010] Furthermore, in one aspect of the present invention, the control unit schedules the operations of the multiple basic pulse generators by performing control to change the assignment state of the basic pulse generator to unassigned, based on an output queue indicating a plurality of elements representing pulse generation rules for the basic pulse generator, which are determined by including the pulse generation pattern and the operation start counter value, and which are to be assigned to a plurality of the basic pulse generators, and the latch output unit outputs a timing signal corresponding to the control by the plurality of basic pulse generators that have been scheduled.

[0011] Furthermore, in one embodiment of the present invention, the control unit swaps the element assigned to the basic pulse generation unit with the unassigned element in the output queue when the counter value of the counter and the operation start counter value of any of the unassigned elements in the output queue are closer to the counter value of the counter than the operation start counter value of any of the basic pulse generation units whose assignment status is already assigned.

[0012] Furthermore, in one embodiment of the present invention, the control unit performs at least one of the following operations when an input signal input to the timing generator from an external source transitions: editing the output queue and assigning the elements related to the transitioned input signal to the basic pulse generation unit.

[0013] Furthermore, in one aspect of the present invention, the timing generator further comprises one or more timestamp assigning units, the timestamp assigning units assigning a timestamp by recording the counter value of the counter at the time the input signal transitions, together with information related to the transition, and the control unit performs an operation to edit the output queue or an operation to assign the elements related to the transitioned input signal to the basic pulse generation unit based on the recorded information.

[0014] Furthermore, in one embodiment of the present invention, the timing generator further comprises a clock division unit that generates a second clock signal by dividing the clock signal based on a division ratio that is changed according to the control of the control unit, the counter performs a count operation corresponding to the division ratio at least on the rising or falling edge of the second clock signal, and the control unit controls the clock division unit to make the frequency of the second clock signal lower than the frequency of the second clock signal when the logic level of any of the basic pulse generation units does not transition after a predetermined time, compared to the frequency of the second clock signal when the logic level of at least one of the basic pulse generation units does transition after a predetermined time.

[0015] Furthermore, in one embodiment of the present invention, the control unit increases the frequency of the second clock signal by controlling the clock frequency divider after any of the input signals are input to the timing generator from an external source, when the input signals input to the timing generator transition multiple times.

[0016] Furthermore, in one embodiment of the present invention, the control unit lowers the frequency of the second clock signal by controlling the clock frequency divider when the input signal does not transition for a predetermined period of time.

[0017] Also, in one aspect of the present invention, the timing generator further includes a clock phase shifter that adjusts at least one of the phase and the frequency of the clock signal, and the control unit is information input from the outside, which is clock correction information indicating at least one of the phase difference and the frequency difference between the clock signal and the reference clock, or controls the phase shift amount of the clock phase shifter based on the history of the clock correction information.

[0018] Also, one aspect of the present invention includes the above-described timing generator and an imaging element, and is an imaging apparatus that performs imaging by driving the imaging element according to the timing signal generated by the timing generator.

[0019] Also, one aspect of the present invention is an automatic test apparatus including the timing generator according to any one of the above items.

Advantages of the Invention

[0020] According to the present invention, an arbitrary timing signal can be preferably generated.

Brief Description of the Drawings

[0021] [Figure 1] It is a block diagram for explaining a configuration example of the timing generator 1 according to Embodiment 1. [Figure 2] It is a state transition diagram for explaining the transition of the operating state of the basic pulse generation unit 13. [Figure 3] It is an operation time chart for explaining the transition of the operating state of the basic pulse generation unit 13. [Figure 4] It is a diagram showing a first example of the basic pulse possessed by the basic pulse generation unit 13. [Figure 5] It is a diagram showing a second example of the basic pulse possessed by the basic pulse generation unit 13. [Figure 6] It is a diagram showing a third example of the basic pulse possessed by the basic pulse generation unit 13. [Figure 7]This diagram illustrates the combination of multiple basic pulse generation units 13. [Figure 8] This is the first diagram illustrating pulse synthesis by combining multiple basic pulse generation units 13. [Figure 9] This is the second diagram illustrating pulse synthesis by combining multiple basic pulse generation units 13. [Figure 10] This diagram illustrates a first control example of the control unit 12 using an output queue. [Figure 11] This figure illustrates a second control example of the control unit 12 using an output queue. [Figure 12] This is a block diagram illustrating an example configuration of the timing generator 2 according to Embodiment 2. [Figure 13] This is an example of a timing chart for explaining the control of the timing generator 2 according to Embodiment 2. [Figure 14] This is a block diagram showing an example configuration of the timing generator 3 according to Embodiment 3. [Figure 15] This figure shows a schematic example of the hardware configuration of the information processing device 90 applied to this embodiment. [Modes for carrying out the invention]

[0022] [Conventional timing generators] Conventional timing generators store time-series bit patterns in ROM (Read Only Memory) or RAM (Random Access Memory) and generate timing by outputting the bit pattern at the address pointed to by a counter. However, even for simple pulse patterns, one bit pattern is required for each clock cycle, and when there are many output destinations, when the output is long-term, or when the clock frequency is high to ensure time resolution, the data becomes bloated, leading to increased size and cost.

[0023] Furthermore, because a delay time (tens to hundreds of nanoseconds) is inherently required for memory access, strict time precision cannot be demanded. To minimize delay, SRAM (Static Random Access Memory) becomes an alternative to DRAM (Dynamic Random Access Memory), but its high cost per bit makes it difficult to increase capacity, leading to increased costs. In addition, memory that can read and write simultaneously is more complex, and it is not possible to dynamically switch patterns or output destinations during pattern output.

[0024] To reduce data size, one method involves storing a counter value for pulse transition timing in ROM or RAM and transitioning the level based on whether the counter value has been reached. While this is effective for sparse pulses, it actually increases data size for dense pulses. Furthermore, its effectiveness is limited for complex pulses with a mix of dense and sparse pulses. It also remains difficult to adapt to changes during execution. Note that a high frequency of logical level transitions per unit of time is called dense, and a low frequency is called sparse.

[0025] [Comparison with the timing generator according to the embodiment] In contrast, the timing generator according to the embodiment, by adopting a configuration based on the example described later, can generate arbitrary pulse signals while reducing the required memory capacity. Furthermore, it is possible to generate complex pulse signals without complicating the circuit and easily handle specification changes by dynamically changing the generated pulse signals.

[0026] [First Embodiment] The timing generator, imaging device, and automatic testing device according to this embodiment will be described in detail below with reference to the attached drawings, with reference to preferred embodiments. In the drawings, identical or similar parts are denoted by the same or similar reference numerals. This embodiment is not limited to these embodiments and includes various modifications or improvements. In other words, the components described below include those that can be easily imagined by those skilled in the art, and those that are substantially the same, and the components described below can be combined as appropriate. Furthermore, this embodiment may include various omissions, substitutions, or modifications of components without departing from the spirit of the present invention.

[0027] In all the figures used to illustrate the embodiments, components with the same function are given the same reference numerals, and repeated explanations are omitted. Furthermore, in this application, "based on XX" means "based on at least XX," and includes cases where it is based on other elements in addition to XX. Also, "based on XX" is not limited to cases where XX is used directly, but also includes cases where it is based on XX after calculations or processing have been performed on it. "XX" is any element (for example, any information). Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0028] [Example configuration of a timing generator] Figure 1 is a block diagram illustrating an example configuration of a timing generator 1 according to Embodiment 1. The timing generator 1 comprises a counter 11, a control unit 12, a plurality of basic pulse generation units 13, and one or more latch output units 14 as its functional units. Figure 1 shows an example in which a plurality of latch output units 14 are provided, but there may be only one. Each of these functional units may be implemented, for example, using a computer and software equipped with a central processing unit (CPU) and memory, or may be implemented using electronic circuits as needed. Furthermore, each functional unit does not have to be included in a single device, and the timing generator 1 may be configured from a plurality of devices.

[0029] The counter 11 performs counting operations (timing operations) based on a clock obtained from inside or outside the timing generator 1. The timing generator 1 may obtain a clock from, for example, a PLL (Phase Locked Loop) 111 provided in the timing generator 1 from the viewpoint of noise suppression. The PLL 111 outputs an operating clock (the clock described above) when an external clock is input. The counter 11 may also obtain a clock from, for example, an internal oscillator such as a clock source 112, or it may obtain a final clock (the clock used for the operation of the basic pulse generation unit 13) from an external device.

[0030] The counter value shown by counter 11 can be interpreted as the number of rising edges of the clock, elapsed time, or time of day. For example, if the counter value shows the number of rising edges of the clock, a 125 [MHz] clock may be interpreted as 8 [ns steps]. Alternatively, if the counter value shows elapsed time, a 125 [MHz] clock may count up by 8 with each rising edge, and the counter value may be interpreted as elapsed time [ns] (8 [ns] resolution). Alternatively, if the counter value shows time of day, the counter value may be interpreted as UNIX® time, and the units may be seconds, milliseconds, microseconds, or nanoseconds. UNIX time, also called the UNIX epoch, represents the elapsed time from 00:00:00 AM on January 1, 1970, Coordinated Universal Time (UTC).

[0031] The clock may be any frequency, such as 10 MHz, 100 MHz, or 125 MHz. The counter value may be 32-bit or 64-bit. A 64-bit counter value is preferable to generate a timing signal for a sufficiently long duration.

[0032] The control unit 12 controls the basic pulses output by each basic pulse generation unit 13 and the operating state (i.e., operating timing) of each basic pulse generation unit 13 by controlling each basic pulse generation unit 13. The control unit 12 may be, for example, a microcontroller.

[0033] The basic pulse generation unit 13 outputs commonly used pulse types, such as one-shot pulses and periodic signals, to one or more latch output units 14 designated by the control unit 12. In other words, the basic pulse generation unit 13 controls the logic level of at least one of the latch output units 14.

[0034] The latch output unit 14 serves as an output interface to the outside. The latch output unit 14 retains its previous value unless there is a transition instruction from the basic pulse generation unit 13. The latch output unit 14 generates a timing signal and provides a timing output by changing its value according to transition instructions from one or more latch output units 14.

[0035] [Basic pulse generation unit] The basic pulse generation unit 13 may have parameters such as valid bits, operating state, operation start counter value, output destination port, high width counter value, period counter value, duration counter value, pulse type (pulse generation pattern), time series pattern bit sequence, or assignment state. These parameters are set or changed by the control unit 12 or the basic pulse generation unit 13 as needed. It is desirable that the basic pulse generation unit 13 has at least an operation start count, an output destination port, and an operating state as parameters in order to realize its function. These parameters may be called pulse generation rules.

[0036] [Basic pulse generation unit: parameters] The active bit is one of the parameters that determine the operating state of the basic pulse generation unit 13. The basic pulse generation unit 13 can start operating when the active bit is active, and immediately stops operating when the active bit is inactive. The active bit corresponds to a parameter called the assignment state, which indicates whether the operation performed by the basic pulse generation unit 13 has been assigned (set) by the control unit 12. The assignment state may include, for example, "assigned" and "unassigned".

[0037] The operating state is a parameter that indicates the operating state of the basic pulse generation unit 13. The operating state may include, for example, "operating" and "standby" when it is not operating. The operating state may be further subdivided. For example, "operating" may include "executing". Also, "standby" may include "not executing", "execution waiting", "execution completed", "forced termination 0", and "forced termination 1".

[0038] The operation start counter value is one of the parameters that determine the operating state of the basic pulse generation unit 13. The operation start counter value is the counter value at which the basic pulse generation unit 13 starts operating. The basic pulse generation unit 13 starts operating (its operating state becomes "operating") when the counter value input from counter 11 reaches the operation start counter value. The operation start counter value may also be called the reservation time.

[0039] The conditions for transitioning the operating state during operation may include when the counter value becomes equal to the operation start count, when it exceeds the operation start count, or when it is equal considering the time adjustment offset, etc., and will simply be referred to as "when it reaches the counter value." The values ​​that function as thresholds are the same as the operation start counter value, and will not be explained further.

[0040] The output destination port is information indicating one or more latch output units 14 that the basic pulse generation unit 13 will transition the logic level of.

[0041] The High-Width Counter value is a counter value that indicates the interval in which the logic level is high (H). For example, if the High-Width Counter value at 125 MHz is 10, the H interval is 80 ns. The High-Width Counter value may also be called the 1-bit width counter value.

[0042] The duration counter value is a counter value that indicates the time of one cycle from when the basic pulse generation unit 13 starts operating until it stops operating. For example, the basic pulse generation unit 13 starts operating when the counter value reaches the operation start counter value and stops operating when a time corresponding to the duration counter value has elapsed. Alternatively, the basic pulse generation unit 13 may have a parameter called an operation end counter value, and stop operating when the counter value reaches the operation end counter value.

[0043] The period counter value is information indicating the period during which the basic pulse generation unit 13 operates periodically. For example, if the duration count value is 30 and the period count value is 60, the basic pulse generation unit 13 operates twice. That is, the basic pulse generation unit 13 generates periodic pulses. If the duration count value and the period count value are the same, the basic pulse generation unit 13 operates once. That is, the basic pulse generation unit 13 generates single pulses.

[0044] The pulse type is information indicating the logic level control pattern performed by the basic pulse generation unit 13. The pulse type may also be called the pulse type, pulse output pattern, or pulse generation pattern. Various control patterns can be set for the pulse type, such as logic level transitions (L→H, H→L), single pulses (L→H→L, H→L→H), periodic pulses, or pattern outputs (L→H→L→H→…).

[0045] A time-series pattern bit sequence is a bit sequence required to generate irregular pulses, i.e., pattern pulses. A time-series pattern bit sequence may also be referred to simply as a bit sequence.

[0046] [Basic pulse generation unit: Transition of operating states] Figure 2 is a state transition diagram illustrating the transitions in the operating states of the basic pulse generation unit 13. Figure 3 is an operation time chart illustrating the transitions in the operating states of the basic pulse generation unit 13.

[0047] If no operation is assigned, or if the valid bit indicates invalid, the operating state of the basic pulse generation unit 13 is "not executed". If the valid bit indicates valid, the operating state transitions from "not executed" to "waiting for execution" or "executing".

[0048] If the valid bit indicates valid, and the counter value is not equal to the start counter value (there is still time until the scheduled time), the operation status transitions from "Not executed" to "Waiting for execution". If the valid bit indicates invalid, the operation status transitions from "Waiting for execution" to "Not executed". Also, if the counter value becomes equal to the start counter value, the operation status transitions from "Waiting for execution" to "Executing".

[0049] If the valid bit indicates valid and the scheduled time is approaching immediately, the operating state transitions from "Not Executed" to "Executing". When the operating state is "Executing", the basic pulse generation unit 13 operates according to the set parameters and controls the logic level of the latch output unit 14. When the operation is completed, the operating state transitions from "Executing" to "Execution Complete", "Forced Termination 0", or "Forced Termination 1".

[0050] When the time indicated by the duration counter expires, the operating state transitions from "Running" to "Completed". "Running" indicates that the execution has completed without any particular problems.

[0051] If the valid bit indicates invalid, the operating state transitions from "running" to "forced termination 0". "Forced termination 0" indicates that the program was forcibly terminated by the control unit 12, etc., even though it was running.

[0052] When a new operation is assigned, or when the scheduled time for that operation arrives, the status changes from "Running" to "Force Termination 1". "Force Termination 1" indicates that the program is being forcibly terminated in order to execute another operation.

[0053] Subsequently, the operating state transitions from "Execution Complete," "Forced Termination 0," or "Forced Termination 1" to "Not Executed," and repeats the transitions as described above.

[0054] [Basic pulse generation unit: Example of a basic pulse] The basic pulse generation unit 13 operates according to the parameters shown as an example above, and transitions the logic level of the latch output unit 14 to output the pulse pattern indicated by the pulse type. The basic pulse generation unit 13 stores basic (representative) pulse patterns and frequently used patterns.

[0055] Figure 4 shows a first example of a basic pulse generated by the basic pulse generation unit 13. Figure 4 shows an example of a single pulse output according to the settings when the 1-bit width count is set to 5, the period counter value is 15, and the duration counter value is 15. In Figure 4, since the 1-bit width count is 5, the basic pulse generation unit 13 rises by 5 counter values ​​when the counter value becomes the operation start counter value. Since the duration counter value is 15, the basic pulse generation unit 13 rises by 5 counter values ​​and then falls by the remaining 10 counter values. Since the period counter value is 15 and the duration counter value is the same, the basic pulse generation unit 13 terminates its operation, and the generated pulse becomes a single pulse.

[0056] Figure 5 shows a second example of a basic pulse generated by the basic pulse generation unit 13. Figure 5 shows an example of a periodic pulse output according to the settings when the 1-bit width count is set to 5, the period counter value is 15, and the duration counter value is 32. In Figure 5, since the 1-bit width count is 5, the basic pulse generation unit 13 rises by 5 counter values ​​when the counter value reaches the operation start counter value. Since the duration counter value is 15, the basic pulse generation unit 13 rises by 5 counter values ​​and then falls by 10 counter values. Since the period counter value is 32, the basic pulse generation unit 13 repeats the above operation twice, rises, and after 2 counter values ​​have elapsed, terminates its operation. That is, the logic level at the end of operation is different from the logic level at the start of operation and is H. Also, the generated pulse is a periodic pulse.

[0057] Figure 6 shows a third example of a basic pulse possessed by the basic pulse generation unit 13. Figure 6 shows an example of a pattern output (pattern pulse) that is output according to the settings when the 1-bit width count is set to 3, the period counter value is 24, and the duration counter value is 39. In Figure 6, since the 1-bit width count is 3 and the time-series pattern bit sequence is "10110010 (8 [bit])", the basic pulse generation unit 13 generates a pulse pattern for a total of 24 counter values, with rising edges for 3 counter values, falling edges for 3 counter values, rising edges for 6 counter values, falling edges for 6 counter values, rising edges for 3 counter values, and falling edges for 3 counter values, when the counter value becomes the operation start counter value. Since the duration counter value is 24 and the period counter value is 39, the basic pulse generation unit 13 performs the above operation once, then performs an operation for 15 counter values ​​(10110), and then terminates its operation.

[0058] Figures 4 to 6 show the case where the output polarity is positive logic (Active High), but it may also be negative logic (Active Low), and the logic level is transitioned according to the parameters. In addition to generating single pulses (Figure 2), generating periodic pulses (Figure 3), and generating pulse patterns (predetermined pulses) based on time-series data (Figure 4), the operation of the basic pulse generation unit 13 may also include logic level transitions, i.e., simple transitions. In the case of a simple transition, the basic pulse generation unit 13 simply transitions the logic level from L to H or H to L when it reaches the operation start counter value, latches that state, and terminates its operation.

[0059] [Basic pulse generation unit: pulse combinations] The timing generator 1 ensures flexibility and expandability of pulse output by arranging multiple basic pulse generation units 13 in an array relative to one or more latch output units 14. Figure 7 is a diagram illustrating the combination of multiple basic pulse generation units 13. Figure 7 shows an example in which the timing generator 1 comprises a first basic pulse generation unit 131, a second basic pulse generation unit 132, a third basic pulse generation unit 133, a fourth basic pulse generation unit 134, a first latch output unit 141, a second latch output unit 142, and a third latch output unit 143.

[0060] Figure 8 is the first diagram illustrating pulse synthesis using a combination of multiple basic pulse generation units 13. Figure 8(A) shows the parameters set for each basic pulse generation unit 13. Figure 8(B) shows a timing chart illustrating the operation of each basic pulse generation unit 13 and the latch output unit 14 when operating according to the set parameters.

[0061] In Figure 8, the start timing of the operation of the second basic pulse generation unit 132 is set to the end timing of the operation of the first basic pulse generation unit 131, which has the same output port as the second basic pulse generation unit 132. As a result, the first latch output unit 141, which is the output destination, combines the pulse generated by the first basic pulse generation unit 131 and the pulse generated by the second basic pulse generation unit 132 to output a continuous pulse over a long period of time.

[0062] Furthermore, if different pattern types are set for the first basic pulse generation unit 131 and the second basic pulse generation unit 132, irregular pulses can be generated from the basic pulses. This eliminates the need to store the irregular pulses themselves, thus reducing the capacity required for generation.

[0063] Furthermore, by providing multiple latch output units 14, the timing signals output from the latch output units 14 can be output to multiple ports. This is because the clock is input to each basic pulse generation unit 13 at the same timing. Each basic pulse generation unit 13 operates synchronously and can be used to synchronize multiple devices. In addition, by outputting signals from multiple latch output units 14 to a single device, the information can be handled not only as serial communication (1 bit) but also as multi-bit information.

[0064] [Scheduling by the control unit] The control unit 12 can form more complex and longer-lasting patterns by setting various parameters, including the pulse type of the basic pulse generation unit 13, based on the timing pattern of the multiple outputs that are ultimately to be obtained. The control of the control unit 12 may be performed before the basic pulse generation unit 13 starts output operation, or it may be dynamically modified while the output is in progress.

[0065] Figure 9 is a second diagram illustrating pulse synthesis using a combination of multiple basic pulse generation units 13. Figure 9(A) shows how the first latch output unit 141 is controlled using the first basic pulse generation unit 131 to the fourth basic pulse generation unit 134. For example, if it is desired to output an arbitrary pattern of 1024 bits, and the basic pulse generation unit 13 can only store a bit sequence of 256 bits, the control unit 12 may be configured to operate the four basic pulse generation units 13 continuously without any gaps.

[0066] Figure 9(B) shows how the first latch output unit 141 is controlled using the first basic pulse generation unit 131 and the second basic pulse generation unit 132. When only two basic pulse generation units 13 are available, the first 512 bits of output are set for the first basic pulse generation unit 131 and the second basic pulse generation unit 132, as this is the earliest possible output. When the operation of the first basic pulse generation unit 131 is completed, an additional 256 bits of operation are set for the first basic pulse generation unit 131 while the second basic pulse generation unit 132 is operating. Also, when the operation of the second basic pulse generation unit 132 is completed, an additional 256 bits of operation are set for the second basic pulse generation unit 132 while the first basic pulse generation unit 131 is operating for the second time. By assigning further operations after the operation is completed, the unassigned basic pulse generation units 13 can be used efficiently. This makes it possible to realize complex patterns even with a simple arrangement or matrix configuration of the basic pulse generation units 13.

[0067] [Output queue] The control unit 12 may control the parameters to be set for each basic pulse generation unit 13 by referring to an output queue stored in the internal memory of the timing generator 1 (for example, within the control unit 12) or outside the timing generator 1. Figure 10 is a diagram illustrating a first control example of the control unit 12 using an output queue. Figure 10(A) shows an example of an output queue. The output queue comprises multiple elements that indicate parameters to be set for any of the basic pulse generation units 13. That is, the output queue is a list of timing patterns for multiple outputs that are ultimately to be obtained. An element is a task that is set and executed in any of the basic pulse generation units 13 in order to create a timing pattern. The output queue may have more elements than the number of basic pulse generation units 13 that the control unit 12 can control (for example, 128 elements). Since low latency is not required for the output queue, it is desirable to store a large number of them in low-cost memory such as RAM. It is desirable that each element in the output queue be retrieved in order of the earliest start of operation, i.e., in order of the smallest operation start counter value. For example, it is desirable that the queue be sorted when elements are added or modified.

[0068] The control unit 12 extracts elements from the output queue in order (for example, in order of earliest start time) and dynamically assigns them to the basic pulse generation unit 13. By sequentially filling in the empty slots (basic pulse generation unit 13 that have not yet been assigned elements) while performing precise timing processing in hardware, it is possible to avoid situations where a large amount of high-speed memory or registers are required on the hardware.

[0069] Figure 10(B) shows the assignment state in the first control example. The control unit 12 efficiently assigns tasks related to the most recent pulse output to the basic pulse generation unit 13 by assigning elements as shown in Figure 10(B) (scheduling). In the following description, elements in the output queue that are not assigned to any basic pulse generation unit 13 will be referred to as unassigned elements, and elements that are assigned to any basic pulse generation unit 13 will be referred to as assigned elements. Furthermore, among the basic pulse generation units 13, the assignment state of a basic pulse generation unit 13 to which no elements are assigned will be referred to as unassigned, and the assignment state of a basic pulse generation unit 13 to which any elements are assigned will be referred to as assigned.

[0070] [1] The control unit 12 assigns unassigned elements from the output queue to the basic pulse generation unit 13 whose assignment status is unassigned. This allows the control unit 12 to schedule so that there are no basic pulse generation units 13 that are not operating for no reason.

[0071] [2] When the operation of the basic pulse generation unit 13 to which an element has been assigned is completed, the control unit 12 sets the assignment status of the basic pulse generation unit 13 to unassigned.

[0072] By performing the controls described in [1] and [2] above, the control unit 12 schedules the operation of the multiple basic pulse generation units 13 and generates a desired pulse pattern using the multiple basic pulse generation units 13.

[0073] Furthermore, the control unit 12 may reallocate if there are additions or changes to the output queue. Figure 11 is a diagram illustrating a second control example of the control unit 12 using the output queue. Figure 11(A) shows an example of the output queue, and Figure 10(B) shows the allocation state in the second control example. Figure 11 is an example in which "element 6'" is added to the output queue shown in Figure 10.

[0074] [3] The control unit 12 swaps elements by assigning an element to a basic pulse generation unit 13 if the start counter value of any unassigned element in the output queue is smaller than the start counter value of any assigned basic pulse generation unit 13, and making the previously assigned element unassigned. The reverse process is performed if the counter 11 is counting down. That is, the control unit 12 swaps elements if the counter value of counter 11 and the start counter value of any unassigned element in the output queue are closer than the counter value of counter 11 and the start counter value of any assigned basic pulse generation unit 13.

[0075] The control unit 12 further performs the control described in [3], namely, the control that swaps operations that can be done later with operations that should be done first, thereby responding to the addition and modification of the output queue during the operation of the basic pulse generation unit 13.

[0076] If the number of basic pulse generation units 13 in the timing generator 1 is too large, the complexity of the circuit will increase, and the number of non-operating basic pulse generation units 13 will increase. On the other hand, if the number of basic pulse generation units 13 is too small, reallocation will not be fast enough, resulting in gaps in the generated timing signal. Therefore, it is desirable to provide only the number of basic pulse generation units 13 necessary to obtain the desired bit pattern, taking into account the delay time required for the control unit 12 to reconfigure the elements assigned to the basic pulse generation units 13. For general applications, for example, it is desirable to have about 16 basic pulse generation units 13.

[0077] [Embodiment 2] The timing generator 2 according to Embodiment 2 is similar to the timing generator 1 according to Embodiment 1 in that it generates a desired pulse pattern by scheduling the operation of a plurality of basic pulse generation units 13. The timing generator 2 further differs from the timing generator 1 in that it controls the operating state of the basic pulse generation units 13 using an external input as a trigger. This makes it possible to output timing signals from multiple devices at appropriate timings.

[0078] Figure 12 is a block diagram illustrating an example configuration of the timing generator 2 according to Embodiment 2. The timing generator 2 further includes a timestamp assignment unit 21. In Figure 12, an example is shown in which the timing generator 2 is provided with a timestamp assignment unit 21 for each input signal port, but one timestamp assignment unit 21 may be provided for one or more input signal ports.

[0079] The timestamp assignment unit 21 acquires the input signal input to the timing generator 2 and assigns a timestamp to the acquired input signal. Specifically, the timestamp assignment unit 21 assigns a timestamp by recording the counter value of the counter 11 at the time the input signal transitions (for example, from H to L) in a timestamp buffer (not shown) or the like, along with information related to the transition. Information related to the transition may include, for example, information indicating the transition time such as a timestamp, information identifying the input source of the input signal such as a value that identifies the port from which the input originated (from timing input 1 to timing input 3, etc.), or information related to the input signal such as the polarity of the input signal and the logical level before and after the transition. When assigning a timestamp, the timestamp assignment unit 21 may provide a dead period of several tens of nanoseconds after the input signal transition to prevent chattering, etc.

[0080] The control unit 12 may reschedule after receiving notification of timestamp stamping from the timestamp assignment unit 21 or the timestamp buffer. Specifically, the control unit 12 may perform editing operations on the output queue, such as adding elements to the output queue, changing the operation start counter value of an element, or changing the order of elements within the output queue, and then perform allocation control of the elements added or changed by the editing operations based on the input signal (control of [1] and [2]). In addition, the control unit 12 may, if necessary, interrupt an element already assigned to the basic pulse generation unit 13 and perform element allocation control based on the transition of the input signal (control of [3]).

[0081] The timestamp obtained by the timestamp assignment unit 21 may be temporarily stored in a timestamp buffer or FIFO (First-In First-Out), and then used by the control unit 12, etc. by referencing it, or it may be used directly by the control unit 12 or the basic pulse generation unit 13 without going through these.

[0082] Note that the configuration including the timestamp assignment unit 21 is merely an example, and the timing generator 2 does not necessarily have to be included. In this case, the control unit 12 and the basic pulse generation unit 13 may directly acquire an external input signal and use the transition (generation) of the input signal as a trigger to perform editing operations or assignment control, dynamically changing the timing signal according to the input signal. When the timestamp assignment unit 21 directly operates the basic pulse generation unit 13, or when an input signal is directly input to the basic pulse generation unit 13, the basic pulse generation unit 13 may perform the operation indicated by the element related to the input signal. For example, the basic pulse generation unit 13 may be assigned an element for which no operation start counter value has been set or for which there is sufficient time until the operation start counter value is reached, and may start operation when an input signal or control signal is acquired, assuming that the operation start counter value has been reached.

[0083] Figure 13 is an example of a timing chart for explaining the control of the timing generator 2 according to Embodiment 2. Figure 13(A) shows an example of sequence control using timing signals when starting up multiple external devices. When a startup sequence is defined, the timing generator 2 supplies the clock (timing signal) necessary for operation to the external device A from the first basic pulse generation unit 131.

[0084] After receiving an input signal from device A at timing input 1 indicating that device A is ready to start up, the timing generator 2 may immediately send a trigger signal or the like (timing signal) from the second basic pulse generation unit 132 to an external device B.

[0085] Furthermore, the timing generator 2 may, after receiving an input signal from device B indicating the start of operation of device B, wait for a specified time and then issue a timing signal to the external device C from the third basic pulse generation unit 133. As described above, the timing generator 2 may operate immediately upon triggering the input signal, or it may operate after a predetermined time.

[0086] In Figure 13(A), for example, device A may be a PLC (Programmable Logic Controller) device that operates based on an external clock, device B may be a robot, and device C may be a test device for the DUT (Device Under Test). According to the timing generator 2, when the PLC is started up and overall control becomes possible, a timing signal that enables the robot's operation is supplied, and tests on the DUT can be performed at the appropriate timing.

[0087] Figure 13(B) shows an example of sequence control using timing signals when an appropriate termination operation is required. The timing generator 2 controls the first basic pulse generation unit 131, which supplies timing signals to device A, to stop the timing signals when a stop sequence is defined.

[0088] After receiving an input signal at timing input 1 that confirms the shutdown of device A, timing generator 2 reserves (reassigns) the second basic pulse generation unit 132, which supplies the timing signal to device B, to stop the timing signal after a specified time. After receiving an input signal at timing input 2 that confirms the shutdown of device B, timing generator 2 reserves the third basic pulse generation unit 133, which supplies the timing signal to device C, to stop operation, similar to the case of device B.

[0089] In Figure 13(B), for example, device A may be a shooting device, device B may be a video recording device, and device C may be an overall control device. According to the timing generator 2, after the shooting device stops, the video recording device will stop after it has finished recording the last frame, and finally the operation of the overall control device can be stopped. The preparation for stopping can be easily implemented by configuring the system so that the first basic pulse generation unit 131 is automatically disabled when the second basic pulse generation unit 132, which is attempting to drive the same output port while the first basic pulse generation unit 131 is running, becomes active (forced termination 1 due to "start of other schedule execution" in Figure 2).

[0090] As explained above, the timestamp assignment unit 21 is an example of a configuration when using an input signal as a trigger signal, and it is not necessarily required to be provided in the timing generator 2. Even if the timestamp assignment unit 21 is not provided, the control unit 12 can operate in strict accordance with the transition timing of the input signal. However, when complex scheduling reconfiguration is required, it is difficult to ensure temporal precision without a timestamp. By providing the timestamp assignment unit 21, the processing time required for schedule changes (a time offset α with a margin) can be added to the timestamp, and the schedule can be reconfigured from that point in time. For example, in applications where the same input signal is branched and input to multiple timing generators 2, a delay will occur, but the multiple timing generators 2 can be operated in a synchronized state. In this case, if necessary, control signals may be input from other timing generators 2 to the control unit 12 of the unit.

[0091] [Embodiment 3] The method of storing time-series bit sequences in ROM, RAM, etc., and address referencing them, the method of storing time-series edge data, and the method of the present invention all depend on the clock used for the minimum time resolution of the timing control. Generally, a clock of several tens of MHz is generated by an external crystal oscillator, etc., and a higher frequency clock is generated and used by a PLL, etc. For example, the resolution when using the timing generator 1 etc. with a 125 MHz clock is 8 ns. In addition, since the timing generator 1 has multiple basic pulse generation units 13 that can operate completely independently in parallel, high-speed operation of several hundred MHz or more is possible, and the clock can be increased even further by configuring the basic pulse generation units 13 etc. in a pipeline configuration.

[0092] When precise time control is required, it is generally desirable to use a high clock frequency, which is realistically within the range of 100 MHz to 1 GHz. However, higher clock frequencies result in greater noise radiation and power consumption, and using consistently high clock frequencies can be problematic, especially in mobile devices with significant power constraints.

[0093] The timing generator 3 according to Embodiment 3 is similar to the timing generator 1 according to Embodiment 1 and the timing generator 2 according to Embodiment 2 in that it generates a desired pulse pattern by scheduling the operation of a plurality of basic pulse generation units 13. The timing generator 3 differs from the timing generator 1 and the timing generator 2 in that it can reduce power consumption, etc., without degrading the performance of the timing generator 3 during operation by dynamically changing the clock division ratio.

[0094] [Clock frequency adjustment: Basic pulse generation unit] Figure 14 is a block diagram showing an example configuration of the timing generator 3 according to Embodiment 3. The timing generator 3 further includes a clock frequency divider 31. The clock frequency divider 31 divides a clock obtained from inside or outside the timing generator 3 according to a set frequency division ratio. The clock before division by the clock frequency divider 31 may be referred to as the first clock or first clock signal, and the clock generated as a result of the division may be referred to as the second clock or second clock signal. The frequency division ratio of the clock frequency divider 31 is set and changed, for example, based on the control of the control unit 12.

[0095] The counter 11 performs its counting operation in a way that avoids temporal inconsistencies, taking into account the increase or decrease in the division ratio of the clock division unit 31. When the clock division ratio is 1 / 2, the frequency of the second clock becomes half the frequency of the first clock. If the increase or decrease in the counter value at the rising edge is kept constant regardless of the division ratio, the advance of the count value when using the second clock will be half the advance of the counter value when using the first clock. Temporal consistency is ensured by performing a counting operation a number of times corresponding to the division ratio when the counter 11 counts. The number of counting operations corresponding to the division ratio is, for example, the reciprocal of the division ratio; if the first clock at 100 MHz counts up by 1, the second clock at 50 MHz may count up by 2.

[0096] As described above, since the operating clock can be changed during operation, the operating clock frequency can be lowered at times when high time resolution is not required, specifically at times when it is not expected that a transition will occur in the immediate output pulse, thereby reducing power consumption and other factors.

[0097] Conventional timing generators sometimes require complex determination circuits to determine whether or not an output pulse transition is scheduled in the near future. For example, in the case of ROM / RAM data, a seek operation is required to search for locations where no bit changes occur. In contrast, timing generator 3 only needs to refer to the operation start count of each element included in the basic pulse generation unit 13 or the output queue to determine the scheduled pulse transition in the near future, and the earliest operation start time among them can be easily identified as the timing for the next pulse transition.

[0098] Furthermore, if the control unit 12 appropriately allocates elements (tasks), the pulse generation task assigned to the basic pulse generation unit 13 may be executed earlier than any task included in the output queue. Therefore, it is sufficient to simply refer to the operation start counter value of the task assigned to the basic pulse generation unit 13 to find the minimum value.

[0099] The control unit 12 can significantly reduce power consumption by lowering (or dividing) the frequency if this minimum value (the most recent reservation time) is more than a predetermined amount ahead of the current counter value and there are no operating basic pulse generation units 13. When the current counter value approaches the minimum value, the control unit 12 increases the frequency of the operating clock (disables or decreases the frequency division) so as not to affect the accuracy of pulse generation by the basic pulse generation units 13. In other words, by controlling the frequency division ratio of the clock frequency division unit 31, the control unit 12 lowers the frequency of the second clock signal when none of the basic pulse generation units 13 start operating after a predetermined time (power saving mode) than the frequency of the second clock signal when at least one of the basic pulse generation units 13 starts operating after a predetermined time (preparing for operation or in operation). The predetermined time is set, for example, taking into account the effects of circuit delay, and is sufficient time for the basic pulse generation units 13 to start operating with the frequency increased. The timing for increasing the frequency should preferably be the reciprocal of the frequency division ratio, for example, 2 counts before if the frequency is divided by 1 / 2, or 5 counts before if the frequency is divided by 1 / 5. By performing this operation, power consumption and other factors can be reduced without affecting the operation of the basic pulse generation unit 13. For example, in the case of a first clock that ticks in the order of nanoseconds, it is worthwhile to lower the frequency if there is a period of a few microseconds during which the unit is not operating. Furthermore, by using the timing generator 3 to lower the frequency without stopping the counting operation of the counter 11, power consumption and other factors can be reduced while maintaining awareness of the time. In addition, the configuration can be simplified compared to gating the basic pulse generation unit 13 when it is not operating.

[0100] The timing generator 3 may reduce power consumption, etc., by providing a first clock signal to the operating basic pulse generation unit 13 and a second clock signal to the inactive basic pulse generation unit 13. In other words, the control unit 12 may determine whether or not to start operation after a predetermined time for each basic pulse generation unit 13 and decide which basic pulse generation unit 13 to input the second clock signal to. However, in this case, the configuration becomes complex, so it is desirable to input the second clock signal to all basic pulse generation units 13 and increase or decrease the frequency of the second clock signal.

[0101] Furthermore, if the timing generator 3 is equipped with a PLL 111 for generating the operating clock, the clock frequency divider 31 may use that to control the increase or decrease of the frequency. Alternatively, the clock frequency divider 31 may have two separate clock systems with different clock frequencies and operate the operating clock by switching between them as appropriate.

[0102] Furthermore, for example, when the basic pulse generation unit 13 performs long-period operation, there may be a period of time during which the logic levels of all basic pulse generation units 13 do not transition, even if the basic pulse generation unit 13 is in operation. The control unit 12 may control the clock frequency divider 31 to lower the clock frequency even while the basic pulse generation unit 13 is in operation. In other words, the control unit 12 may determine whether or not to divide the clock frequency based on whether or not the logic level transitions after any predetermined time. In this case, the control unit 12 may not use whether or not the basic pulse generation unit 13 is in operation as the criterion for determination, but rather make the decision based on a standby signal that is output separately by the basic pulse generation unit 13, which indicates whether or not lowering the second clock will not affect its operation.

[0103] [Clock frequency adjustment: Timestamp assignment section] Furthermore, the same operation as increasing or decreasing the clock frequency supplied to the basic pulse generation unit 13 may be performed on the clock frequency divider unit 31. That is, the frequency of the second clock may be lowered when no input transition occurs, and the frequency of the second clock may be increased just before an input transition occurs.

[0104] In situations where the input signal occurs with some degree of periodicity, it is possible to predict the time period when the next input signal will be received. Therefore, when no input transition occurs, the frequency of the second clock can be lowered, and just before the input transition occurs, the frequency of the second clock can be raised to reduce power consumption, etc. "With some degree of periodicity" means that it is sufficient to identify the time period when the input signal does not transition, and even if the exact time of the next input signal transition cannot be predicted, the frequency of the second clock can be raised earlier. If the input signal does not transition for a predetermined period, the control unit 12 may lower the frequency of the second clock signal by controlling the clock frequency divider 31. When the input is periodic with some degree of periodicity, for example, by operating the basic pulse generation unit 13 in synchronization with its period, the mechanism for increasing or decreasing the clock for the basic pulse generation unit 13 can be used as is.

[0105] In situations where input signals occur irregularly, predicting the time frame for the next input signal is difficult. The control unit 12 may, for example, increase the frequency of the second clock when the first input occurs if multiple inputs occur. In this case, the accuracy of the timestamp assigned to the first input may be insufficient, but accurate timestamps can be assigned to subsequent inputs. This process is effective, for example, when dealing with burst signals. The control unit 12 may also decrease the frequency of the second clock after a predetermined period has elapsed since the input signal was received. With this configuration, the timing generator 3 does not need to add a configuration to determine clock increase or decrease for the timestamp assignment unit 21, thus simplifying the circuit.

[0106] Furthermore, the timing generator 3 may request (control) an external device to intentionally input an output twice. That is, it may request that a pre-signal be input the first time. Also, by clearly defining the interval between the first input and the second input, the timing generator 3 can determine the accurate time (timestamp) for the first input by subtracting the predetermined interval from the accurate timestamp assigned to the second input. The control unit 12 may lower the frequency of the second clock from the point when an accurate timestamp is no longer needed, such as when a predetermined period of time has elapsed since the input signal was received.

[0107] Furthermore, in cases where an external device returns a feedback signal with a nearly constant delay in accordance with the timing output, such as the exposure control signal of the imaging device and the vertical synchronization signal after the completion of imaging, it is often sufficient to increase or decrease the second clock according to the basic pulse generation unit, and control may not be necessary. It is desirable that the timing generator 3 can, if necessary, increase the second clock in advance to secure a time margin, or change the length of the time margin as appropriate.

[0108] The timestamp assignment unit 21 may record or notify the control unit 12, etc., of information indicating the degree of temporal accuracy of the timestamp or pulse output, depending on the frequency of the second clock input to the timestamp assignment unit 21. By referring to this information, the user of the timing generator 3 can determine whether the time indicated for input or output is reliable.

[0109] [Adjusting clock phase or frequency] When the timing generator 3 operates using an external clock source, and the discrepancy between the ideal and actual operation is actually known, it is desirable to have a means to correct the discrepancy due to changes in wiring conditions such as wiring length and wiring bends up to the timing generator 3, or when synchronizing with other reference time sources. In other words, the timing generator 3 acquires the discrepancy caused by the wiring conditions and the discrepancy with the synchronization source, and adjusts the discrepancy spontaneously without waiting for external synchronization.

[0110] The timing generator 3 further includes a clock phase shift unit 32. The clock phase shift unit 32 adjusts at least one of the phase of the first clock or the frequency of the first clock. The amount by which the clock phase shift unit 32 makes adjustment is called the phase shift amount. The control unit 12 controls the shift amount of the clock phase shift unit 32 based on clock correction information or the history of clock correction information. This makes it possible for the timing generator 3 to correct the first clock signal to an ideal phase or frequency. The clock phase shift unit 32 may include a phase shifter or a PLL as a component. Alternatively, a PLL intended for raising the frequency of an external clock may be used in the clock phase shift unit 32.

[0111] Clock correction information is information input from an external source that indicates at least one of the phase difference and frequency difference between an external clock source (reference clock) and the first clock signal. By having the control unit 12 determine the phase shift amount based on the external clock correction information, the timing generator 3 can utilize a highly accurate clock in synchronization with changes in wiring length or bends, or with other synchronization references.

[0112] The clock correction information history refers to the clock correction information that has been input to the timing generator 3 in the past. The control unit 12 can determine the amount of phase shift to adjust future phase differences and frequency differences from the trend of the clock correction information by calculating a moving average or performing extrapolation interpolation on the clock correction information history, thereby responding to future phase differences and frequency differences.

[0113] [Applications of timing generators] The timing generators 1 to 3 described above may be connected to, for example, an external camera, image sensor, recording device, video processing device, distribution device, switcher, microphone, lighting device, or other shooting equipment, and used as a shooting device for shooting or broadcasting. For example, the timing generator may be used for synchronized shooting, such as inputting timing signals to each image sensor in the shooting device and driving them in a synchronized manner. More specifically, with the timing generator, the shooting device exposes multiple image sensors in a frame-synchronized manner, the recording device records the video to an external storage device in a synchronized manner based on the signals, the video processing device processes multiple frames in a synchronized manner at the same time, and the video is distributed along with the results, the distributed video is switched smoothly according to instructions from the control center as needed, microphones and other equipment accompanying the video are synchronized in accordance with the frames, and strobe lighting can be appropriately controlled.

[0114] Furthermore, the timing generator can be used in automated testing equipment. Specifically, the timing generator may be connected to external sensors, robots, actuators, PLCs, computers, or automated machines, and output timing signals for automated production, assembly, evaluation, and testing. With the timing generator, the automated testing equipment can, for example, synchronize the control of multiple robots or actuators under automated testing, and the sensors can observe the state of the DUT in real time, while the PLC or computer also operates in synchronization, thereby maintaining and managing the state of other robots, logs, etc., in a synchronized manner.

[0115] Furthermore, the timing generator may be connected to an external sensor, energy source (light source, laser source, or electron gun), processing unit, measuring instrument, or signal generator, and used in a measuring device to observe the response of an object under test. With a timing generator, for example, the measuring device can observe the time response of an object under test by emitting short-wavelength light from a pulsed light source, synchronously controlling the timing of a sensor to observe the response after a certain delay, quantitatively evaluating the synchronous sensor with a processing unit or measuring instrument, and gradually changing the delay.

[0116] While each component in the aforementioned application devices has an independent timing generator, the timing generator according to this embodiment distributes timing signals to multiple devices simultaneously to achieve precise time synchronization and reduce the complexity of each piece of equipment.

[0117] [Timing generator hardware configuration] Figure 15 is a schematic diagram of an example hardware configuration of an information processing device 90 applied to this embodiment. The information processing device 90 comprises a processor 91, main memory 92, communication interface 93, auxiliary storage device 94, input / output interface 95, and internal bus 96. The processor 91, main memory 92, communication interface 93, auxiliary storage device 94, and input / output interface 95 are connected to each other via the internal bus 96 so as to be able to communicate with each other. The information processing device 90 may be applied to, for example, timing generator 1, timing generator 2, and timing generator 3. In this case, for example, the input port and output port may be configured using the communication interface 93. For example, the timestamp buffer may be configured using the auxiliary storage device 94. Furthermore, the control unit 12 may be configured using the processor 91 and main memory 92.

[0118] [Summary of Embodiments] According to the embodiment described above, the timing generator 1 comprises a counter 11, a control unit 12, a plurality of basic pulse generation units 13, and one or a latch output unit 14. The counter 11 performs a counting operation based on a clock signal, and the control unit 12 controls the operating state of each basic pulse generation unit 13 by setting an operation start counter value for each basic pulse generation unit 13. When the counter value input from the counter 11 becomes the operation start counter value, the basic pulse generation unit 13 enters an operating state and controls the logic level of at least one of the latch output units 14. The latch output unit 14 outputs a timing signal corresponding to the control by at least one of the basic pulse generation units 13. Compared to a method of recording time-series data in memory, the timing generator 1 can represent any pulse with a smaller amount of data, and compared to conventional methods that require developing a time-series transition of logic levels at minute time intervals to represent periodic pulses, the timing generator 1 can reduce the cost of generating time-series data. Furthermore, by combining multiple basic pulse generation units 13 in a matrix, the timing generator 1 can efficiently generate dense, irregular pulses that are difficult to represent using edge data, thus keeping the circuit configuration relatively simple. Therefore, the timing generator 1 can suitably generate any timing signal.

[0119] Furthermore, according to the above-described embodiment, the control unit 12 sets a pulse generation pattern (parameter) for each basic pulse generation unit 13 that indicates the operation to be performed by the basic pulse generation unit 13, which includes at least one of the following: logic level transition, single pulse generation, periodic pulse generation, and predetermined pulse generation based on time-series data. The basic pulse generation unit 13 controls the logic level of the latch output unit 14 by performing an operation according to the set pulse generation pattern. The basic pulse generation unit 13 can reduce the data required for pulse generation and increase the expressiveness of the pulse by continuously generating or combining basic pulses (one-shot signals, periodic signals, etc.) that tend to be frequently used.

[0120] Furthermore, according to the embodiment described above, the control unit 12 schedules the operation of multiple basic pulse generation units 13 by assigning unassigned elements from the output queue to basic pulse generation units 13 whose assignment status is unassigned, based on an output queue that shows elements indicating pulse generation rules for a basic pulse generation unit 13, which are determined by including a pulse generation pattern and an operation start counter value, and assigning multiple elements to a plurality of basic pulse generation units 13, and by performing control to set the assignment status of the basic pulse generation unit 13 to unassigned when the operation of the basic pulse generation unit 13 to which an element has been assigned is completed, and the latch output unit 14 outputs a timing signal corresponding to the control by the plurality of basic pulse generation units 13 that have been scheduled. The timing generator 1 can efficiently handle both dense and sparse pulse generation by sequentially reading the output queue that shows the rules for generating complex time-series pulses and dynamically assigning them to the basic pulse generation units 13. In addition, the timing generator 1 can dynamically assign elements and appropriately schedule them in response to operations such as adding or changing different pulse patterns based on instructions from the user, and generate the desired pulse pattern. In other words, it is possible to easily deal with specification changes, etc. Furthermore, in the timing generator 1, a CPU is typically used for the control unit 12 and an FPGA (field-programmable gate array) for the basic pulse generation unit 13. The timing generator 1 can accurately and flexibly generate the desired pulse pattern by controlling multiple basic pulse generation units 13, which have a limited storage capacity but high operating speed, with a control unit 12 that can store a large amount of information but does not operate at a very high speed.

[0121] Furthermore, according to the embodiment described above, the control unit 12 swaps an element assigned to the basic pulse generation unit 13 with an unassigned element in the output queue if the counter value of the counter 11 and the operation start counter value of any unassigned element in the output queue are closer to the counter value of the counter 11 than the operation start counter value of any assigned basic pulse generation unit 13. In other words, the timing generator 1 swaps an unassigned element with an earlier start and an assigned element with a later start to reconfigure the schedule. The timing generator 1 can flexibly respond to operations such as interrupting some of the existing pulse outputs by a user, etc., by interrupting the existing queue and generating a desired pulse pattern.

[0122] Furthermore, according to the above-described embodiment, when an input signal input to the timing generator 2 from an external source transitions, the control unit 12 performs at least one of the following operations: editing the output queue and assigning elements related to the transitioned input signal to the basic pulse generation unit 13. In other words, the timing generator 2 can control the operation of the basic pulse generation unit 13 using an external input signal as a trigger. This allows for appropriate control according to the completion order and start order of processing of multiple devices.

[0123] Furthermore, according to the embodiment described above, the timing generator 2 further comprises one or more timestamp assigning units 21, which assign a timestamp by recording the counter value of the counter 11 at the time the input signal transitions, together with information related to the transition, and the control unit 12 performs operations to edit the output queue or assign elements related to the transitioned input signal to the basic pulse generation unit 13 based on the recorded information. As a result, when it is necessary to perform complex schedule reconstruction, the timing generator 2 can perform time-strict control (for example, synchronized control with other devices) based on the timestamp.

[0124] Furthermore, according to the above-described embodiment, the timing generator 3 further includes a clock divider 31 that generates a second clock signal by dividing the clock signal (first clock signal) based on a division ratio that is changed according to the control of the control unit 12. The counter 11 counts a number of times corresponding to the division ratio at at least one of the rising or falling edges of the second clock signal. The control unit 12 controls the clock divider 31 to make the frequency of the second clock signal lower than the frequency of the second clock signal when the logic level of at least one of the basic pulse generation units does not transition after a predetermined time. In other words, the timing generator 3 adjusts the frequency of the clock signal based on whether or not a transition occurs after a predetermined time. As a result, the timing generator 3 reduces power consumption and suppresses heat generation by operating with a low-frequency clock during periods when low time resolution is acceptable, for example, during periods when no events occur. In addition, by reducing power consumption by dividing the clock, the circuit configuration can be simplified.

[0125] Furthermore, according to the embodiment described above, when the input signal input to the timing generator 3 from an external source undergoes multiple transitions, the control unit 12 increases the frequency of the second clock signal by controlling the clock frequency divider 31 after any input signal has occurred. When assigning timestamps to signals that are expected to receive multiple inputs from an external source, the first timestamp is set to a low-frequency clock with low accuracy, at which point the system switches to a high-frequency clock, and subsequent timestamps are set to high accuracy. In most cases, the first signal is discarded as inaccurate data. By requiring the external device to precisely define the interval between the first and second signals, the accurate time of the first signal can be easily determined from the timestamp of the second signal.

[0126] Furthermore, according to the embodiment described above, the control unit 12 lowers the frequency of the second clock signal by controlling the clock frequency divider 31 when the input signal does not transition for a predetermined period of time. When the input signal is somewhat periodic, lowering the clock frequency when there is no particular input or when no output level transition is expected can reduce power consumption and heat generation during standby.

[0127] Furthermore, according to the embodiment described above, the timing generator 3 further includes a clock phase shift unit 32 that adjusts at least one of the phase of the clock signal and the frequency of the clock signal, and the control unit 12 controls the amount of phase shift of the basic pulse generation unit 13 based on clock correction information input from an external source, which indicates at least one of the phase difference and frequency difference between the clock signal and a reference clock, or the history of clock correction information. When the timing generator 1 receives notification of a clock deviation compared to some reference clock, the clock phase shift unit 32 corrects the phase difference or frequency difference, thereby enabling timing generation based on an accurate clock.

[0128] Furthermore, the entirety or a part thereof of the functions of each part of the timing generator 1, timing generator 2, and timing generator 3 in the above-described embodiment may be realized by recording a program for realizing these functions on a computer-readable recording medium, having a computer system read the program recorded on this recording medium, and executing it. The term "computer system" here includes hardware such as the operating system and peripheral devices.

[0129] Furthermore, "computer-readable recording media" refers to portable media such as flexible disks, magneto-optical disks, ROMs, and CD-ROMs, as well as recording units such as hard disks built into computer systems. In addition, "computer-readable recording media" may include those that dynamically hold programs for a short period of time, such as communication lines used when transmitting programs over networks such as the Internet or communication lines such as telephone lines, and those that hold programs for a certain period of time, such as volatile memory inside computer systems that act as servers or clients in such cases. Moreover, the above-mentioned program may be for the purpose of realizing some of the functions described above, and may also be able to realize the above-mentioned functions in combination with programs already recorded in the computer system.

[0130] Although one embodiment of this invention has been described in detail above with reference to the drawings, the specific configuration is not limited to that described above, and various design changes can be made without departing from the spirit of this invention. Furthermore, the configurations described in each embodiment and example above may be combined. [Explanation of Symbols]

[0131] 1...Timing generator, 11...Counter, 111...PLL, 112...Clock source, 12...Control unit, 13...Basic pulse generation unit, 14...Latch output unit, 2...Timing generator, 21...Timestamp assignment unit, 3...Timing generator, 31...Clock frequency divider unit, 32...Clock phase shift unit

Claims

1. It comprises a counter, a control unit, a plurality of basic pulse generation units, and one or more latch output units. The counter performs counting operations based on the clock signal. The control unit controls the operating state of each basic pulse generation unit by setting an operation start counter value for each basic pulse generation unit. The basic pulse generation unit, when the counter value input from the counter becomes the operation start counter value, enters the operation state and controls the logic level of at least one of the latch output units. The latch output unit outputs a timing signal corresponding to the control by at least one of the basic pulse generation units. Timing generator.

2. The control unit sets a pulse generation pattern for each of the basic pulse generation units, which includes at least one of the following operations: logic level transition, single pulse generation, periodic pulse generation, and predetermined pulse generation based on time-series data, and which indicates the operation performed by the basic pulse generation unit. The basic pulse generation unit controls the logic level of the latch output unit by performing an operation according to the set pulse generation pattern. The timing generator according to claim 1.

3. The control unit schedules the operations of multiple basic pulse generators by performing control to set the assignment state of a basic pulse generator to unassigned, based on an output queue that shows a plurality of elements indicating a pulse generation rule for the basic pulse generator, which is determined by including the pulse generation pattern and the operation start counter value, and assigning a plurality of elements to be assigned to a plurality of basic pulse generators, and assigning the unassigned elements from the output queue to the basic pulse generator whose assignment state is unassigned, and when the operation of the basic pulse generator to which the elements were assigned is completed, setting the assignment state of the basic pulse generator to unassigned. The latch output unit outputs a timing signal corresponding to the control by the scheduled plurality of basic pulse generation units. The timing generator according to claim 2.

4. The control unit swaps the element assigned to the basic pulse generation unit with the unassigned element in the output queue if the counter value of the counter and the operation start counter value of any of the unassigned elements in the output queue are closer to the counter value of the counter than the operation start counter value of any of the basic pulse generation units whose assignment status is already assigned. The timing generator according to claim 3.

5. The control unit, when an input signal input to the timing generator from an external source transitions, performs at least one of the following operations: editing the output queue, and assigning the elements related to the transitioned input signal to the basic pulse generation unit. A timing generator according to either claim 3 or claim 4.

6. It further comprises one or more timestamping units, The timestamp assigning unit assigns a timestamp by recording the counter value of the counter at the time the input signal transitioned, together with the information related to the transition. The control unit performs operations to edit the output queue based on the recorded information, or to assign elements related to the transitioned input signal to the basic pulse generation unit. The timing generator according to claim 5.

7. The system further includes a clock frequency divider that generates a second clock signal by dividing the clock signal based on a frequency division ratio that is changed according to the control of the control unit, The counter performs a count operation a number of times corresponding to the frequency division ratio at at least one of the rising or falling edges of the second clock signal. The control unit controls the clock frequency divider so that the frequency of the second clock signal when none of the basic pulse generation units undergo a logic level transition after a predetermined time is lower than the frequency of the second clock signal when at least one of the basic pulse generation units undergoes a logic level transition after a predetermined time. A timing generator according to any one of claims 1 to 4.

8. The control unit increases the frequency of the second clock signal by controlling the clock frequency divider after any of the input signals are input to the timing generator from an external source when the input signal transitions multiple times. The timing generator according to claim 7.

9. The control unit, when the input signal does not transition for a predetermined period of time, controls the clock frequency divider to lower the frequency of the second clock signal. The timing generator according to claim 8.

10. The system further includes a clock phase shift unit that adjusts at least one of the phase of the clock signal and the frequency of the clock signal, The control unit controls the amount of phase shift of the clock phase shift unit based on information input from an external source, which is clock correction information indicating at least one of the phase difference and frequency difference between the clock signal and the reference clock, or based on the history of the clock correction information. A timing generator according to any one of claims 1 to 4.

11. A timing generator according to any one of claims 1 to 4, Equipped with an image sensor, The image sensor is driven according to the timing signal generated by the timing generator to take an image. A photographic device.

12. A timing generator according to any one of claims 1 to 4, Automatic testing equipment.

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