Semiconductor package including top die

Abstract

We provide semiconductor packages that can increase the available free space within electronic products. [Solution] The semiconductor package according to the present invention includes a buffer die, a middle core die stacked vertically on the buffer die, a top core die positioned on the uppermost middle core die, a dummy die stacked vertically on the top core die, a first bonding film structure sandwiched between the middle core dies and joining them together, including a first bonding pad structure, a second bonding film structure sandwiched between the top core die and the lowermost dummy die and joining them together, and a third bonding film structure sandwiched between the dummy dies and joining them together.

Description

Technical Field

[0001] The present invention relates to a semiconductor package, and more particularly to a multi-chip package including a plurality of stacked chips.

Background Art

[0002] A high bandwidth memory (HBM) package includes a plurality of memory chips vertically stacked on a logic chip, and these are joined to each other via an adhesive layer. In order for the HBM package to have excellent performance, the joining state between the memory chips must be good, so research on this is necessary.

Summary of the Invention

Problems to be Solved by the Invention

[0003] An object of the present invention is to provide a semiconductor package having improved electrical characteristics.

Means for Solving the Problems

[0004] A semiconductor package according to an aspect of the present invention made to achieve the above object includes a buffer die, a plurality of middle core dies vertically stacked on the buffer die, a top core die disposed on the uppermost middle core die among the plurality of middle core dies, a plurality of dummy dies vertically stacked on the top core die, a first bonding film structure including a first bonding pad structure sandwiched between adjacent middle core dies among the plurality of middle core dies to join them to each other, a second bonding film structure sandwiched between the top core die and the lowermost dummy die among the plurality of dummy dies to join them to each other, and a third bonding film structure sandwiched between adjacent dummy dies among the plurality of dummy dies to join them to each other.

[0005] To achieve the above objective, another aspect of the present invention provides a semiconductor package comprising: a first semiconductor chip; a plurality of second semiconductor chips stacked vertically on the first semiconductor chip, each including a substrate and a through-electrode extending vertically through the substrate; a third semiconductor chip disposed on the uppermost second semiconductor chip of the plurality of second semiconductor chips; a plurality of dummy chips stacked vertically on the third semiconductor chip; and a semiconductor chip sandwiched between vertically adjacent second semiconductor chips, bonding them together, and connecting at least one of the plurality of second semiconductor chips to each other. The invention is characterized by comprising: a first bonding film structure including a first bonding pad structure electrically connected to the through-electrode included therein; a second bonding film structure sandwiched between the uppermost second semiconductor chip and the third semiconductor chip among the plurality of second semiconductor chips, bonding them together, and including a second bonding pad structure electrically connected to the through-electrode included in the uppermost second semiconductor chip; a third bonding film structure sandwiched between the third semiconductor chip and the lowest dummy chip among the dummy chips, bonding them together; and a fourth bonding film structure sandwiched between the dummy chips, bonding them together.

[0006] A semiconductor package according to yet another aspect of the present invention made to achieve the above objectives includes: a first semiconductor chip including a first substrate and a first through-electrode extending vertically through the first substrate; a first bonding film structure including a first bonding pad structure disposed on the first semiconductor chip and electrically connected to the first through-electrode; a plurality of second semiconductor chips stacked vertically on the first bonding film, each including a second substrate and a second through-electrode extending vertically through the second substrate; and a second through-electrode sandwiched between vertically adjacent second semiconductor chips among the plurality of second semiconductor chips, bonding them together and electrically connected to the second through-electrode included in at least one of the plurality of second semiconductor chips. The present invention is characterized by comprising: a second bonding film structure including a bonding pad structure; a third bonding film structure including a third bonding pad structure disposed on the uppermost second semiconductor chip among the plurality of second semiconductor chips and electrically connected to the second through-electrode contained therein; a third semiconductor chip disposed on the third bonding film structure; a fourth bonding film structure disposed on the third semiconductor chip; a plurality of dummy chips stacked vertically on the fourth bonding film structure; a fifth bonding film structure sandwiched between adjacent dummy chips among the plurality of dummy chips to bond them together; and a mold member formed on the first semiconductor chip that covers the side walls of the first to third semiconductor chips, the side walls of the plurality of dummy chips, and the side walls of the first to fifth bonding film structures. [Effects of the Invention]

[0007] The semiconductor package according to the present invention includes a plurality of semiconductor chips stacked vertically, and the bonding film structure that joins the semiconductor chips to each other does not contain any voids inside. As a result, the semiconductor chips are well joined to each other, and the semiconductor package can ensure improved structural and electrical characteristics.

[0008] However, the effects of the present invention are not limited to those mentioned above, and can be extended in various ways without departing from the spirit and scope of the present invention. [Brief explanation of the drawing]

[0009] [Figure 1] This is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention. [Figure 2] This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to one embodiment of the present invention. [Figure 3] This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to one embodiment of the present invention. [Figure 4] This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to one embodiment of the present invention. [Figure 5] This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to one embodiment of the present invention. [Figure 6] This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to one embodiment of the present invention. [Figure 7] This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to one embodiment of the present invention. [Figure 8] This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to one embodiment of the present invention. [Figure 9] This is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention. [Figure 10] This is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention. [Figure 11] This is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention. [Figure 12] This is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention. [Figure 13] This is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention. [Figure 14] This is a cross-sectional view showing an electronic device according to one embodiment of the present invention. [Modes for carrying out the invention]

[0010] Hereinafter, with reference to the drawings, preferred embodiments of the present invention will be described in more detail.

[0011] In this specification, when a substance, layer (film), region, pad, electrode, pattern, structure, or process is referred to as "first", "second", and / or "third", it is not for limiting such members, but merely for distinguishing each substance, layer (film), region, electrode, pad, pattern, structure, and process. Therefore, "first", "second", and / or "third" can be selectively or alternatively used for each substance, layer (film), region, electrode, pad, pattern, structure, and process.

[0012] Hereinafter, the direction parallel to the upper surface of each substrate or wafer is defined as the horizontal direction, and the direction perpendicular to the upper surface is defined as the vertical direction.

[0013] FIG. 1 is a cross-sectional view for explaining a semiconductor package according to an embodiment of the present invention.

[0014] As shown in FIG. 1, the semiconductor package includes a first semiconductor chip 100, a plurality of second semiconductor chips 200 stacked on the first semiconductor chip 100, a third semiconductor chip 300 disposed on the uppermost second semiconductor chip 200, and a dummy chip stack structure 500 disposed on the third semiconductor chip 300.

[0015] Further, the semiconductor package further includes first to fifth bonding film structures 710, 720, 730, 740, 750, a conductive pad 140, a first conductive connection member 150, and a mold member 600.

[0016] In one embodiment, the semiconductor package is a high-bandwidth memory package.

[0017] In one embodiment, the first semiconductor chip 100 is a buffer die and includes, for example, a logic element such as a controller. Each of the second and third semiconductor chips 200 and 300 is a core die and includes, for example, a volatile memory element such as a DRAM element or a SRAM element, or a non-volatile memory element such as a flash memory element or an EEPROM element. Here, each of the second semiconductor chips 200 is referred to as a middle core die, and the third semiconductor chip 300 is referred to as a top core die.

[0018] On the other hand, the first semiconductor chip 100 is a logic chip or a logic die, each of the second and third semiconductor chips 200 and 300 is a memory chip or a memory die, and the dummy chip 400 is also referred to as a dummy die.

[0019] The first semiconductor chip 100 includes a first substrate 110 having first and second surfaces 112 and 114 formed on opposite sides in the vertical direction, a first through-electrode structure 120 penetrating the first substrate 110, first and second interlayer insulating films 130 sequentially stacked along the vertical direction under the first surface 112 of the first substrate 110, and a first protection pattern structure 160 formed on the second surface 114 of the first substrate 110.

[0020] The first substrate 110 includes, for example, a semiconductor material such as silicon, germanium, silicon-germanium, or a III-V compound semiconductor such as gallium phosphide (GaP), gallium arsenide (GaAs), gallium antimonide (GaSb). According to another embodiment, the first substrate 110 is a SOI (Silicon-On-Insulator) substrate or a GOI (Germanium-On-Insulator) substrate.

[0021] Under the first surface 112 of the first substrate 110, circuit elements such as logic elements are formed. The circuit elements include a plurality of circuit patterns, which are covered with the first interlayer insulating film.

[0022] The second interlayer insulating film 130 houses the first wiring structure 135 inside. The first wiring structure 135 includes, for example, wiring, vias, contact plugs, etc., but to avoid complexity in the drawing, the structure is simply shown as a single layer in Figure 1.

[0023] The first interlayer insulating film and the second interlayer insulating film 130 include, for example, a low dielectric material such as silicon oxide or, for example, an oxide doped with carbon or fluorine. Wiring, vias, contact plugs, etc., include conductive materials such as, for example, metals, metal nitrides, or metal silicides.

[0024] The conductive pad 140 is formed beneath the second interlayer insulating film 130, contacts the first wiring structure 135, and is electrically connected to it. In one embodiment, multiple conductive pads 140 are formed spaced apart from each other along the horizontal direction.

[0025] In one embodiment, the conductive pad 140 includes a first seed pattern sequentially laminated downward from the second interlayer insulating film 130, and first and second conductive patterns. Here, the first seed pattern includes, for example, titanium, and the first and second conductive patterns include, for example, nickel and gold, respectively.

[0026] The first conductive connecting member 150 contacts the lower surface of the conductive pad 140. The first conductive connecting member 150 is, for example, a conductive bump or a conductive ball. The first conductive connecting member 150 includes, for example, a metal such as tin (Sn), or solder, i.e., a tin alloy such as tin / silver (Sn / Ag), tin / copper (Sn / Cu), tin / indium (Sn / In), or tin / silver / copper (Sn / Ag / Cu).

[0027] The first through-electrode structure 120 extends vertically within the first substrate 110 and penetrates it, and a portion of it protrudes vertically and is surrounded by the first protective pattern structure 160. Multiple first through-electrode structures 120 are formed spaced apart from each other along the horizontal direction. In one embodiment, the first through-electrode structure 120 includes a first through-electrode extending vertically, a first barrier pattern covering the side wall of the first through-electrode, and a first insulating pattern covering the outer wall of the first barrier pattern. However, in one embodiment, the first insulating pattern does not cover the upper part of the outer wall of the first barrier pattern.

[0028] The first through electrode includes a metal such as copper or aluminum, the first barrier pattern includes a metal nitride such as titanium nitride or tantalum nitride, and the first insulating pattern includes an oxide such as silicon oxide, or an insulating nitride such as silicon nitride.

[0029] In one embodiment, the first through-electrode structure 120 penetrates the first protective pattern structure 160, the first substrate 110, and the first interlayer insulating film, contacts the first wiring structure 135, and is electrically connected to the conductive pad 140 via the first wiring structure 135.

[0030] In another embodiment, the first through-electrode structure 120 penetrates the first protective pattern structure 160, the first substrate 110, the first interlayer insulating film, and the second interlayer insulating film 130 to contact the conductive pad 140 and is electrically connected to it. In yet another embodiment, the first through-electrode structure 120 penetrates the first protective pattern structure 160 and the first substrate 110 to contact a portion of the circuit pattern constituting a circuit element covered by the first interlayer insulating film, and is electrically connected to the conductive pad 140 via the portion of the circuit pattern and the first wiring structure 135 electrically connected thereto.

[0031] The first protective pattern structure 160 is formed on the second surface 114 of the first substrate 110 and surrounds the upper part of the first through-electrode structure 120. In one embodiment, the first protective pattern structure 160 contacts the upper outer wall of the first barrier pattern contained in the first through-electrode structure 120.

[0032] In one embodiment, the first protective pattern structure 160 includes a first protective pattern and a second protective pattern stacked vertically on the second surface 114 of the first substrate 110. Here, the portion of the first protective pattern adjacent to the first through-electrode structure 120 protrudes vertically upward, with its upper surface being formed at substantially the same height as the upper surface of the first through-electrode structure 120, and the outer wall of this portion is covered by the second protective pattern.

[0033] The first protective pattern includes, for example, an oxide such as silicon oxide, and the second protective pattern includes, for example, an insulating nitride such as silicon nitride.

[0034] A first bonding film 170 is placed on the first protective pattern structure 160 and the first through electrode structure 120, and the first bonding film 170 houses a first bonding pad 175 inside. In one embodiment, a plurality of first bonding pads 175 are formed spaced apart from each other along the horizontal direction, and each of the first bonding pads 175 contacts the upper surface of the first through electrode structure 120.

[0035] In one embodiment, the first bonding film 170 includes an insulating material such as silicon carbonitride (SiCN), silicon nitride (SiN), or silicon oxide (SiO2), and the first bonding pad 175 includes a metal such as copper (Cu).

[0036] In one embodiment, the thickness of the first semiconductor chip 100 in the vertical direction is approximately 50 μm to 120 μm, and the first bonding film 170 formed on the first semiconductor chip 100 has a thickness of approximately 1 μm or less in the vertical direction.

[0037] Each second semiconductor chip 200 includes a second substrate 210 having first and second surfaces 212 and 214 formed on opposite sides in the vertical direction, a second through-electrode structure 220 penetrating the second substrate 210, a third interlayer insulating film and a fourth interlayer insulating film 230 sequentially stacked vertically below the first surface 212 of the second substrate 210, and a second protective pattern structure 260 formed on the second surface 214 of the second substrate 210.

[0038] The second semiconductor chip 200 is stacked on the first semiconductor chip 100 in a number such as 3, 7, or 11, but the present invention is not limited thereto, and any number of chips can be stacked.

[0039] The second substrate 210 includes, for example, a semiconductor material such as silicon, germanium, or silicon-germanium, or a III-V compound semiconductor such as gallium phosphide (GaP), gallium arsenide (GaAs), or gallium antimonide (GaSb). According to other embodiments, the second substrate 210 is an SOI substrate or a GOI substrate.

[0040] Beneath the first surface 212 of the second substrate 210, circuit elements such as volatile memory elements like DRAM elements and SRAM elements, or non-volatile memory elements like flash memory elements and EEPROM elements, are formed. The circuit elements include multiple circuit patterns, which are covered by a third interlayer insulating film.

[0041] The fourth interlayer insulating film 230 houses the second wiring structure 235. The second wiring structure 235 includes, for example, wiring, vias, contact plugs, etc., but to avoid complexity in the drawing, the structure is simply shown as a single layer in Figure 1.

[0042] The third and fourth interlayer insulating films 230 include, for example, a low dielectric material such as silicon oxide or, for example, a carbon or fluorine-doped oxide. Wiring, vias, contact plugs, etc., include conductive materials such as metals, metal nitrides, and metal silicides.

[0043] A second bonding film 240 is formed beneath the fourth interlayer insulating film 230, and the second bonding film 240 houses a second bonding pad 245 inside. In one embodiment, a plurality of second bonding pads 245 are formed spaced apart from each other along the horizontal direction, and each second bonding pad 245 contacts at least a portion of the second wiring structure 235 and is electrically connected to it.

[0044] In one embodiment, the second bonding film 240 includes an insulating material such as silicon carbonitride (SiCN), silicon nitride (SiN), or silicon oxide (SiO2), and the second bonding pad 245 includes a metal such as copper (Cu).

[0045] In one embodiment, the lower surface of the second bonding film 240 formed on the second semiconductor chip 200, which is located in the lowest layer of the second semiconductor chip 200, is bonded to the upper surface of the first bonding film 170 formed on the first semiconductor chip 100 to form a first bonding film structure 710, and the second bonding pad 245 formed on the second bonding film 240 is bonded to the first bonding pad 175 formed on the first bonding film 170 to form a first bonding pad structure 715.

[0046] Here, the first and second bonding films 170 and 240 may be indistinguishable from each other if they contain substantially the same insulating material, or they may be distinguishable from each other if they contain different insulating materials. Similarly, the first and second bonding pads 175 and 245 may be indistinguishable from each other if they contain the same metal, or they may be distinguishable from each other if they contain different metals.

[0047] The second through-electrode structure 220 extends vertically within the second substrate 210 and penetrates it, and a portion of it protrudes vertically and is surrounded by the second protective pattern structure 260. Multiple second through-electrode structures 220 are formed spaced apart from each other along the horizontal direction. In one embodiment, the second through-electrode structure 220 includes a second through-electrode extending vertically, a second barrier pattern covering the side wall of the second through-electrode, and a second insulating pattern covering the outer wall of the second barrier pattern. However, in one embodiment, the second insulating pattern does not cover the upper part of the outer wall of the second barrier pattern.

[0048] The second through electrode includes a metal such as copper or aluminum, the second barrier pattern includes a metal nitride such as titanium nitride or tantalum nitride, and the second insulating pattern includes an oxide such as silicon oxide, or an insulating nitride such as silicon nitride.

[0049] In one embodiment, the second through-electrode structure 220 penetrates the second protective pattern structure 260, the second substrate 210, and the third interlayer insulating film, contacts the second wiring structure 235, and is electrically connected to the second bonding pad 245 via the second wiring structure 235.

[0050] In another embodiment, the second through-electrode structure 220 penetrates the second protective pattern structure 260, the second substrate 210, the third interlayer insulating film, and the fourth interlayer insulating film 230 to contact the second bonding pad 245 and is electrically connected to it. In yet another embodiment, the second through-electrode structure 220 penetrates the second protective pattern structure 260 and the second substrate 210 to contact a portion of the circuit pattern constituting a circuit element covered by the third interlayer insulating film, and is electrically connected to the second bonding pad 245 via the portion of the circuit pattern and the second wiring structure 235 electrically connected thereto.

[0051] The second protective pattern structure 260 is formed on the second surface 214 of the second substrate 210 and surrounds the upper part of the second through-electrode structure 220. In one embodiment, the second protective pattern structure 260 contacts the upper outer wall of the second barrier pattern contained in the second through-electrode structure 220.

[0052] In one embodiment, the second protective pattern structure 260 includes a third protective pattern and a fourth protective pattern stacked vertically on the second surface 214 of the second substrate 210. Here, the portion of the third protective pattern adjacent to the second through-electrode structure 220 protrudes vertically upward, with its upper surface being formed at substantially the same height as the upper surface of the second through-electrode structure 220, and the outer wall of this portion is covered by the fourth protective pattern.

[0053] The third protection pattern includes, for example, an oxide such as silicon oxide, and the fourth protection pattern includes, for example, an insulating nitride such as silicon nitride.

[0054] A third bonding film 270 is formed on the second protective pattern structure 260 and the second through-electrode structure 220, and the third bonding film 270 houses a third bonding pad 275 inside. In one embodiment, a plurality of third bonding pads 275 are formed spaced apart from each other along the horizontal direction, and each of the third bonding pads 275 contacts the upper surface of the second through-electrode structure 220.

[0055] In one embodiment, the third bonding film 270 includes an insulating material such as silicon carbonitride (SiCN), silicon nitride (SiN), or silicon oxide (SiO2), and the third bonding pad 275 includes a metal such as copper (Cu).

[0056] In one embodiment, the vertical thickness of each second semiconductor chip 200 is approximately 30 μm to 100 μm, and each of the second and third bonding films 240 and 270 formed on each second semiconductor chip 200 has a thickness of approximately 1 μm or less in the vertical direction.

[0057] In one embodiment, among the second semiconductor chips 200 stacked vertically, the lower surface of a second bonding film 240 formed on a second semiconductor chip 200 located in a relatively upper layer is bonded to the upper surface of a third bonding film 270 formed on a second semiconductor chip 200 located in a relatively lower layer to form a second bonding film structure 720, and the second bonding pad 245 formed on the second bonding film 240 is bonded to the third bonding pad 275 formed on the third bonding film 270 to form a second bonding pad structure 725.

[0058] Here, the second and third bonding films 240 and 270 may be indistinguishable from each other by containing substantially the same insulating material, or they may be distinguishable from each other by containing different insulating materials. Similarly, the second and third bonding pads 245 and 275 may be indistinguishable from each other by containing the same metal, or they may be distinguishable from each other by containing different metals.

[0059] The third semiconductor chip 300 includes a third substrate 310 having first and second surfaces 312 and 314 formed on opposite sides in the vertical direction, and a fifth interlayer insulating film and a sixth interlayer insulating film 330 sequentially stacked along the vertical direction below the first surface 312 of the third substrate 310.

[0060] The third substrate 310 includes, for example, a semiconductor material such as silicon, germanium, or silicon-germanium, or a III-V compound semiconductor such as gallium phosphide (GaP), gallium arsenide (GaAs), or gallium antimonide (GaSb). According to other embodiments, the third substrate 310 is an SOI substrate or a GOI substrate.

[0061] Beneath the first surface 312 of the third substrate 310, circuit elements such as memory elements are formed. The circuit elements include multiple circuit patterns, which are covered by a fifth interlayer insulating film. The sixth interlayer insulating film 330 houses a third wiring structure 335 inside.

[0062] A fourth bonding film 340 is formed beneath the sixth interlayer insulating film 330, and the fourth bonding film 340 houses a fourth bonding pad 345 inside. In one embodiment, a plurality of fourth bonding pads 345 are formed spaced apart from each other along the horizontal direction, and each fourth bonding pad 345 contacts at least a portion of the third wiring structure 335 and is electrically connected to it.

[0063] Meanwhile, a fifth bonding film 370 is formed on the second surface 314 of the third substrate 310.

[0064] In one embodiment, each of the fourth and fifth bonding films 340, 370 includes an insulating material such as silicon carbonitride (SiCN), silicon nitride (SiN), or silicon oxide (SiO2), and the fourth bonding pad 345 includes a metal such as copper (Cu).

[0065] In one embodiment, the vertical thickness of the third semiconductor chip 300 is approximately 30 μm to 100 μm, and each of the fourth and fifth bonding films 340 and 370 formed on the third semiconductor chip 300 has a vertical thickness of approximately 1 μm or less. In one embodiment, the vertical thickness of the third semiconductor chip 300 is substantially the same as the vertical thickness of each second semiconductor chip 200.

[0066] In one embodiment, the lower surface of the fourth bonding film 340 formed on the third semiconductor chip 300 is bonded to the upper surface of the third bonding film 270 formed on the second semiconductor chip 200, which is arranged in the uppermost layer, to form a third bonding film structure 730, and the fourth bonding pad 345 formed on the fourth bonding film 340 is bonded to the third bonding pad 275 formed on the third bonding film 270, respectively, to form a third bonding pad structure 735.

[0067] Here, the third and fourth bonding films 270 and 340 may be indistinguishable from each other if they contain substantially the same insulating material, or they may be distinguishable from each other if they contain different insulating materials. Similarly, the third and fourth bonding pads 275 and 345 may be indistinguishable from each other if they contain the same metal, or they may be distinguishable from each other if they contain different metals.

[0068] The dummy chip stacked structure 500 includes a plurality of dummy chips 400 stacked along the vertical direction and a fifth bonding membrane structure 750 sandwiched between them.

[0069] The drawings illustrate that the dummy chip stacked structure 500 includes three dummy chips 400 stacked vertically, but the present invention is not limited thereto and may include any number of dummy chips 400.

[0070] Here, each dummy chip 400 includes a fourth substrate 410 having first and second surfaces 412 and 414 that face each other in the vertical direction. The fourth substrate 410 includes, for example, a semiconductor material such as silicon, germanium, silicon-germanium, or a III-V compound semiconductor such as gallium phosphide (GaP), gallium arsenide (GaAs), or gallium antimonide (GaSb). Alternatively, the fourth substrate 410 may include glass, an inorganic insulator, an organic insulator, and the like.

[0071] On the other hand, a sixth bonding film 440 is formed beneath the first surface 412 of the fourth substrate 410, and a seventh bonding film 470 is formed on the second surface 414 of the fourth substrate 410. However, the seventh bonding film 470 may not be formed on the second surface 414 of the fourth substrate 410 contained in the uppermost dummy chip 400, as shown in the drawing.

[0072] The lower surface of the sixth bonding film 440 formed on the bottommost dummy chip 400 contacts the upper surface of the fifth bonding film 370 formed on the third semiconductor chip 300, and the fifth and sixth bonding films 370 and 440 bond to each other to form the fourth bonding film structure 740. Also, the lower surface of the sixth bonding film 440 formed on the dummy chip 400 stacked relatively higher contacts the upper surface of the seventh bonding film 470 formed on the dummy chip 400 positioned relatively lower, and the sixth and seventh bonding films 440 and 470 bond to each other to form the fifth bonding film structure 750.

[0073] In one embodiment, each of the sixth and seventh bonding films 440 and 470 includes an insulating material such as silicon carbonitride (SiCN), silicon nitride (SiN), or silicon oxide (SiO2).

[0074] The fifth and sixth bonding films 370 and 440 may be indistinguishable from each other if they contain substantially the same insulating material, or they may be distinguishable from each other if they contain different insulating materials. Similarly, the sixth and seventh bonding films 440 and 470 may be indistinguishable from each other if they contain substantially the same insulating material, or they may be distinguishable from each other if they contain different insulating materials.

[0075] In one embodiment, the vertical thickness of each dummy chip 400 is approximately 30 μm to 60 μm, and each of the sixth and seventh bonding films 440 and 470 formed on each dummy chip 400 has a vertical thickness of approximately 1 μm or less.

[0076] In one embodiment, the vertical thickness of each dummy chip 400 is substantially the same as or less than the vertical thickness of the second and third semiconductor chips 200 and 300, respectively. Here, the vertical thicknesses of the dummy chips 400 are either the same as or different from each other.

[0077] In one embodiment, the sum of the vertical thicknesses of the dummy chips 400 included in the dummy chip stacked structure 500, or the vertical thickness of the dummy chip stacked structure 500, is greater than the vertical thickness of each of the first to third semiconductor chips 100, 200, and 300.

[0078] In one embodiment, each of the first to third semiconductor chips 100, 200, and 300, the dummy chip 400, and the dummy chip stacked structure 500 have a flat plate shape and, when viewed from above, have a rectangular shape.

[0079] The mold member 600 is formed on the first semiconductor chip 100 and covers the side walls of the second and third semiconductor chips 200, 300, the first to fourth bonding film structures 710, 720, 730, 740, and the dummy chip stacked structure 500, with its upper surface being formed at substantially the same height as the upper surface of the dummy chip stacked structure 500.

[0080] The mold member 600 includes, for example, a polymer material such as epoxy-based molding resin (EMC).

[0081] In the above semiconductor package, the multiple second semiconductor chips 200 stacked on the first semiconductor chip 100 are joined to each other by a copper hybrid bonding (HCB) process, as detailed in Figures 2 to 8. Specifically, they are joined to each other via a second bonding film structure 720 including second and third bonding films 240 and 270 stacked vertically, and a second bonding pad structure 725 including second and third bonding pads 245 and 275 housed therein, respectively.

[0082] In the copper hybrid bonding (HCB) process, voids may form between the second and third bonding films 240 and 270. However, because each second semiconductor chip 200 has a thin thickness, pressure is applied to the upper surface of the second semiconductor chip 200 positioned above it, causing the voids to be expelled to the outside.

[0083] On the other hand, the third semiconductor chip 300 and the bottommost dummy chip 400 are joined to each other via a fourth bonding film structure 740 which includes fifth and sixth bonding films 370 and 440 stacked vertically, and the vertically stacked dummy chips 400 are joined to each other via a fifth bonding film structure 750 which includes sixth and seventh bonding films 440 and 470 stacked vertically.

[0084] When the dummy chip 400 is stacked on the third semiconductor chip 300, voids may occur between the fifth and sixth bonding films 370, 440, or between the sixth and seventh bonding films 440, 470. However, because each dummy chip 400 has a thin thickness, pressure is applied to the upper surface of the dummy chip 400 placed on top, causing the voids to be expelled. As a result, the bottom layer dummy chip 400 and the third semiconductor chip 300 are bonded well to each other without the bonding force between them being reduced by the voids, and similarly, the dummy chips 400 are also bonded well to each other.

[0085] As a result, the semiconductor package, including the first to third semiconductor chips 100, 200, 300 and the dummy chip 400, can ensure improved structural and electrical characteristics.

[0086] Figures 2 to 8 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to one embodiment of the present invention.

[0087] As shown in Figure 2, a first wafer (W1) is provided.

[0088] In one embodiment, the first wafer (W1) includes a first substrate 110 having first and second surfaces 112 and 114 that face each other in the vertical direction. The first wafer (W1) also includes a plurality of die regions (DRs) and scribe line regions (SRs) surrounding each die region (DR). The first wafer (W1) is subsequently cut along the scribe line regions (SRs) by a sawing process to form first semiconductor chips on each die region (DR).

[0089] Within the die region (DR), circuit elements are formed on the first surface 112 of the first substrate 110. In one embodiment, the circuit elements include logic elements. The circuit elements include a plurality of circuit patterns, and a first interlayer insulating film is formed on the first surface 112 of the first substrate 110 to cover the circuit patterns.

[0090] A second interlayer insulating film 130 is formed on the first interlayer insulating film, and the first wiring structure 135 is housed within it.

[0091] A conductive pad 140 is formed on the second interlayer insulating film 130, in contact with a part of the first wiring structure 135 and electrically connected to it.

[0092] In one embodiment, the conductive pad 140 is formed by the following process.

[0093] Specifically, a first seed film is formed on the second interlayer insulating film 130, and a first photoresist pattern including a first opening that partially exposes the upper surface of the first seed film is formed on the first seed film. Then, for example, an electroplating process or an electroless plating process is performed to form the first and second conductive patterns within the first opening.

[0094] Subsequently, the first photoresist pattern is removed, for example, by an ashing and / or stripping process to partially expose the first seed film, and the exposed portion of the first seed film is removed to form the first seed pattern beneath the first conductive pattern.

[0095] This forms a conductive pad 140 including a first seed pattern and first and second conductive patterns that are sequentially stacked along the vertical direction.

[0096] Subsequently, the first conductive connecting member 150 is formed on the conductive pad 140. In one embodiment, the first conductive connecting member 150 is formed by the following process.

[0097] Specifically, a second photoresist pattern having a second opening that exposes the upper surface of the conductive pad 140 is formed on the second interlayer insulating film 130. Then, for example, an electroplating process or an electroless plating process is performed to form a preliminary first conductive connecting member in the second opening. After removing the second photoresist pattern, a reflow process is performed to convert the preliminary first conductive connecting member into the first conductive connecting member 150.

[0098] In one embodiment, the first conductive connecting member 150 has a hemispherical or elliptical hemispherical shape.

[0099] In one embodiment, a first through-electrode structure 120 is formed on the upper part of the first substrate 110, that is, the portion adjacent to the first surface 112, extending vertically and penetrating it. In one embodiment, multiple first through-electrode structures 120 are formed within each die region (DR) of the first wafer (W1), spaced apart from each other along the horizontal direction.

[0100] In one embodiment, the first through-electrode structure 120 includes a first through-electrode extending vertically, a first barrier pattern covering its side walls and bottom surface, and a first insulating pattern covering its side walls and bottom surface.

[0101] As shown in Figure 3, the first temporary adhesive film 910 is attached to the first carrier substrate (C1), and the first carrier substrate (C1) is bonded to the first wafer (W1) by having the first temporary adhesive film 910 come into contact with the upper surface of the second interlayer insulating film 130 on which the first wiring structure 135 is formed, while covering the first conductive connecting member 150 and conductive pad 140 formed on the first wafer (W1).

[0102] The first temporary adhesive film 910 contains a substance that loses its adhesive strength when irradiated with light such as ultraviolet (UV) light or when heated. In one embodiment, the first temporary adhesive film 910 contains glue.

[0103] After covering the first wafer (W1), the portion of the first substrate 110 adjacent to the second surface 114 of the first substrate 110 is removed, for example, by a grinding process, to expose the upper part of the first through-electrode structure 120.

[0104] In one embodiment, during the grinding process, the upper part of the first insulating pattern included in the first through electrode structure 120 is also removed, thereby exposing the upper surface and upper outer wall of the first barrier pattern.

[0105] Thereafter, a first protective film structure is formed on the second surface 114 of the first substrate 110 to cover the first through-electrode structure 120, and a planarization process is performed on the first protective film structure until the upper surface of the first through-electrode contained in the first through-electrode structure 120 is exposed, thereby forming the first protective pattern structure 160.

[0106] In one embodiment, the planarization step includes a chemical mechanical polishing (CMP) step and / or an etch bag step.

[0107] In one embodiment, the first protective film structure includes first to third protective films sequentially laminated along the vertical direction, and in the planarization process, the third protective film is completely removed, while the second protective film is partially left. As a result, the first protective pattern structure 160 includes a first protective pattern and a second protective pattern laminated in the vertical direction. Here, the upper outer wall of the portion of the first protective pattern adjacent to the first through electrode structure 120 is covered by the second protective pattern.

[0108] Thereafter, a first bonding film 170, which accommodates the first bonding pad 175, is formed on the first protective pattern structure 160 and the first through electrode structure 120.

[0109] In one embodiment, a plurality of first bonding pads 175 are formed spaced apart from each other along the horizontal direction, and at least some of them contact the upper surface of the first through electrode structure 120.

[0110] In one embodiment, the first bonding film 170 includes an insulating material such as silicon carbonitride (SiCN), silicon nitride (SiN), or silicon oxide (SiO2), and the first bonding pad 175 includes a metal such as copper (Cu).

[0111] As shown in Figure 4, a second wafer (W2) is provided.

[0112] In one embodiment, the second wafer (W2) includes a second substrate 210 having first and second surfaces 212 and 214 that face each other in the vertical direction. The second wafer (W2) also includes a plurality of die regions (DRs) and scribe line regions (SRs) surrounding each die region (DR). The second wafer (W2) is subsequently cut along the scribe line regions (SRs) by a sawing process to form second semiconductor chips on each die region (DR).

[0113] Within the die region (DR), circuit elements are formed on the first surface 212 of the second substrate 210. In one embodiment, the circuit elements include memory elements. The circuit elements include a plurality of circuit patterns, and a third interlayer insulating film is formed on the first surface 212 of the second substrate 210 to cover the circuit patterns.

[0114] A fourth interlayer insulating film 230 is formed on the third interlayer insulating film, and the second wiring structure 235 is housed therein.

[0115] In one embodiment, a second through-electrode structure 220 is formed on the upper part of the second substrate 210, that is, the portion adjacent to the first surface 212, extending vertically and penetrating it. In one embodiment, a plurality of second through-electrode structures 220 are formed within each die region (DR) of the second wafer (W2), spaced apart from each other along the horizontal direction.

[0116] In one embodiment, the second through-electrode structure 220 includes a second through-electrode extending vertically, a second barrier pattern covering its side walls and bottom surface, and a second insulating pattern covering its side walls and bottom surface.

[0117] Subsequently, a second bonding film 240, which accommodates the second bonding pad 245, is formed on the fourth interlayer insulating film 230, which accommodates the second wiring structure 235.

[0118] In one embodiment, a plurality of second bonding pads 245 are formed spaced apart from each other along the horizontal direction, and at least some of them contact the upper surface of the second wiring structure 235.

[0119] In one embodiment, the second bonding film 240 includes an insulating material such as silicon carbonitride (SiCN), silicon nitride (SiN), or silicon oxide (SiO2), and the second bonding pad 245 includes a metal such as copper (Cu).

[0120] As shown in Figure 5, the second temporary adhesive film 920 is attached to the second carrier substrate (C2), and the second temporary adhesive film 920 is brought into contact with the upper surface of the second bonding film 240 formed on the second wafer (W2) that accommodates the second bonding pad 245, thereby bonding the second carrier substrate (C2) to the second wafer (W2).

[0121] The second temporary adhesive film 920 contains a substance that loses its adhesive strength when exposed to light, such as ultraviolet (UV), or when heated. In one embodiment, the second temporary adhesive film 920 contains glue.

[0122] After covering the second wafer (W2), the portion of the second substrate 210 adjacent to the second surface 214 of the second substrate 210 is removed, for example, by a grinding process, to expose the upper part of the second through-electrode structure 220.

[0123] In one embodiment, during the grinding process, the upper part of the second insulating pattern included in the second through electrode structure 220 is also removed, thereby exposing the upper surface and upper outer wall of the second barrier pattern.

[0124] Thereafter, a second protective film structure is formed on the second surface 214 of the second substrate 210 to cover the second through-electrode structure 220, and a planarization process is performed on the second protective film structure until the upper surface of the second through-electrode contained in the second through-electrode structure 220 is exposed, thereby forming the second protective pattern structure 260.

[0125] In one embodiment, the second protective film structure includes fourth to sixth protective films sequentially stacked along the vertical direction, and in the planarization step, the sixth protective film is completely removed, while the fifth protective film is partially left. As a result, the second protective pattern structure 260 includes fourth and fifth protective patterns stacked in the vertical direction. Here, the upper outer wall of the portion of the fourth protective pattern adjacent to the second through electrode structure 220 is covered by the fifth protective pattern.

[0126] Thereafter, a third bonding film 270, which accommodates the third bonding pad 275, is formed on the second protective pattern structure 260 and the second through electrode structure 220.

[0127] In one embodiment, a plurality of third bonding pads 275 are formed spaced apart from each other along the horizontal direction, and at least some of them contact the upper surface of the second through electrode structure 220.

[0128] In one embodiment, the third bonding film 270 includes an insulating material such as silicon carbonitride (SiCN), silicon nitride (SiN), or silicon oxide (SiO2), and the third bonding pad 275 includes a metal such as copper (Cu).

[0129] As shown in Figure 6, the second wafer (W2) is covered and attached to the upper surface of a release tape formed on, for example, a ring-shaped frame.

[0130] Here, the release tape comes into contact with the upper surface of the third bonding film 270 formed on the second surface 214 of the second wafer (W2).

[0131] Subsequently, the second temporary adhesive film 920 attached to the second carrier substrate (C2) is separated from the second bonding film 240, thereby separating the second carrier substrate (C2) from the second wafer (W2).

[0132] Subsequently, the second wafer (W2) is separated into multiple second semiconductor chips 200 by cutting along the scribe line region (SR) using, for example, a sawing process.

[0133] In one embodiment, the vertical thickness of each second semiconductor chip 200, which includes a second substrate 210, a third interlayer insulating film, a fourth interlayer insulating film 230, a second through-electrode structure 220, and a second protective pattern structure 260, is approximately 30 μm to 100 μm, and each of the second and third bonding films 240 and 270 formed on the second semiconductor chip 200 has a vertical thickness of approximately 1 μm or less.

[0134] Thereafter, each individualized second semiconductor chip 200 is separated from the release tape, and each second semiconductor chip 200 is mounted on the first wafer (W1) such that the second bonding film 240 formed on each separated second semiconductor chip 200 contacts the upper surface of the first bonding film 170 on the first wafer (W1).

[0135] Here, the second semiconductor chip 200 is placed on the first wafer (W1) so as to correspond to the die region (DR) of the first wafer (W1), and the second bonding pad 245 of the second semiconductor chip 200 contacts the upper surface of the corresponding first bonding pad 175 of the first semiconductor chip. As a result, the first and second bonding films 170 and 240 are bonded to each other to form a first bonding film structure 710, and the first and second bonding pads 175 and 245 are bonded to each other to form a first bonding pad structure 715. In other words, each second semiconductor chip 200 is bonded to the first wafer (W) by a hybrid copper bonding (HCB) process.

[0136] As shown in Figure 7, by performing a process that is substantially the same as or similar to the process described in Figures 4 to 6, multiple second semiconductor chips 200 are further bonded onto each second semiconductor chip 200 bonded on the first wafer (W1).

[0137] Here, the second bonding film 240 formed on the second semiconductor chip 200 stacked relatively above contacts the third bonding film 270 formed on the second semiconductor chip 200 located relatively below, and the second and third bonding pads 245 and 275 formed on these respectively contact each other. As a result, the second and third bonding films 240 and 270 are bonded to each other to form a second bonding film structure 720, and the second and third bonding pads 245 and 275 are bonded to each other to form a second bonding pad structure 725.

[0138] As described above, each second semiconductor chip 200 has a thin thickness of approximately 30 μm to 100 μm. Therefore, when joining them to each other via the second bonding film structure 720, even if voids occur between the second and third bonding films 240 and 270, applying pressure to the upper surface of the second semiconductor chip 200 stacked on top expels the voids to the outside. As a result, no voids remain within the second bonding film structure 720, and the second semiconductor chips 200 are well joined to each other.

[0139] Subsequently, the third semiconductor chip 300 is bonded onto the uppermost second semiconductor chip 200 by performing a process that is substantially the same as or similar to the process described in Figures 4 to 6.

[0140] Here, the third semiconductor chip 300 includes a third substrate 310 having first and second surfaces 312 and 314 that face each other in the vertical direction, and a fifth interlayer insulating film and a sixth interlayer insulating film 330 that accommodates the third wiring structure 335 are formed below the first surface 312 of the third substrate 310.

[0141] Furthermore, a fourth bonding film 340, which accommodates the fourth bonding pad 345, is formed on the lower surface of the sixth interlayer insulating film 330, and a fifth bonding film 370 is formed on the second surface 314 of the third substrate 310.

[0142] The fourth bonding film 340 formed on the third semiconductor chip 300 contacts the third bonding film 270 formed on the uppermost second semiconductor chip 200, and the fourth and third bonding pads 345 and 275 formed on these contact each other. As a result, the third and fourth bonding films 270 and 340 are bonded to each other to form the third bonding film structure 730, and the third and fourth bonding pads 275 and 345 are bonded to each other to form the third bonding pad structure 735.

[0143] In one embodiment, each of the fourth and fifth bonding films 340, 370 includes an insulating material such as silicon carbonitride (SiCN), silicon nitride (SiN), or silicon oxide (SiO2), and the fourth bonding pad 345 includes a metal such as copper (Cu).

[0144] In one embodiment, the vertical thickness of each third semiconductor chip 300, which includes a third substrate 310, a fifth interlayer insulating film, and a sixth interlayer insulating film 330, is approximately 30 μm to 100 μm, and each of the fourth and fifth bonding films 340 and 370 formed on the third semiconductor chip 300 has a vertical thickness of approximately 1 μm or less.

[0145] As shown in Figure 8, multiple dummy chips 400 are bonded onto the third semiconductor chip 300 by performing a process that is substantially the same as or similar to the process described in Figures 4 to 6.

[0146] Here, each dummy chip 400 includes a fourth substrate 410 having first and second surfaces 412 and 414 that face each other in the vertical direction. A sixth bonding film 440 is formed beneath the first surface 412 of the fourth substrate 410, and a seventh bonding film 470 is formed on the second surface 414 of the fourth substrate 410. However, the seventh bonding film 470 is not formed on the second surface 414 of the fourth substrate 410 included in the uppermost dummy chip 400, as shown in the drawing.

[0147] The sixth bonding film 440 formed on the bottommost dummy chip 400 contacts the fifth bonding film 370 formed on the third semiconductor chip 300, and the fifth and sixth bonding films 370 and 440 are bonded to each other to form the fourth bonding film structure 740. Also, the sixth bonding film 440 formed on the dummy chip 400 stacked relatively above it contacts the seventh bonding film 470 formed on the dummy chip 400 located relatively below it, and the sixth and seventh bonding films 440 and 470 are bonded to each other to form the fifth bonding film structure 750.

[0148] In one embodiment, each of the sixth and seventh bonding films 440 and 470 includes an insulating material such as silicon carbonitride (SiCN), silicon nitride (SiN), or silicon oxide (SiO2).

[0149] In one embodiment, the vertical thickness of the dummy chip 400 is approximately 30 μm to 60 μm, and each of the sixth and seventh bonding films 440 and 470 formed on the dummy chip 400 has a thickness of approximately 1 μm or less in the vertical direction.

[0150] Since each dummy chip 400 has a thin thickness of approximately 30 μm to 60 μm, when the bottommost dummy chip 400 and the third semiconductor chip 300 are joined to each other via the fourth bonding film structure 740, or when the dummy chips 400 are joined to each other via the fifth bonding film structure 750, even if voids occur between the fifth and sixth bonding films 370, 440, or between the sixth and seventh bonding films 440, 470, the voids are expelled to the outside by applying pressure to the upper surface of the dummy chip 400 stacked on top. As a result, no voids remain in each of the fourth and fifth bonding film structures 740, 750, and the bottommost dummy chip 400 and the third semiconductor chip 300 or dummy chip 400 are well joined to each other.

[0151] On the other hand, the dummy chips 400 stacked along the vertical direction and the fifth bonding membrane structure 750 sandwiched between them form a dummy chip stacked structure 500.

[0152] Referring again to Figure 1, after forming a mold member 600 on the first wafer (W1) that covers the second and third semiconductor chips 200, 300, the first to fourth bonding film structures 710, 720, 730, 740, and the dummy chip stacked structure 500, the first wafer (W1) is then separated into multiple first semiconductor chips 100 by cutting along the scribe line region (SR) using, for example, a sawing process.

[0153] In the above sawing process, the mold member 600 is also cut out and formed on each individual first semiconductor chip 100, covering the side walls of the second and third semiconductor chips 200, 300, the first to fourth bonding film structures 710, 720, 730, 740, and the dummy chip stacked structure 500.

[0154] Thereafter, the manufacturing of the semiconductor package is completed by separating the first temporary adhesive film 910 and the first carrier substrate (C1) from each first semiconductor chip (C1) by, for example, a grinding process on the mold member 600 until the upper surface of the top layer dummy chip 400 is exposed.

[0155] As described above, since each second semiconductor chip 200 stacked on the first wafer (W1) and bonded to each other using the copper hybrid bonding (HCB) method has a thin thickness, even if voids occur within the second bonding film structure 720 sandwiched between them, applying pressure to the upper surface of the second semiconductor chip 200 effectively expels the voids to the outside, thereby ensuring that the second semiconductor chips 200 are well bonded to each other.

[0156] Similarly, since each dummy chip 400 stacked on the third semiconductor chip 300 and bonded to each other also has a thin thickness, even if voids occur in the fourth bonding film structure 740 sandwiched between the third semiconductor chip 300 and the bottommost dummy chip 400, or in the fifth bonding film structure 750 sandwiched between the dummy chips 400, applying pressure to the upper surface of the dummy chip 400 will expel the voids to the outside, thereby ensuring that the third semiconductor chip 300 and the dummy chip 400 are well bonded to each other.

[0157] If, for example, instead of multiple thin dummy chips 400 on the third semiconductor chip 300, a single dummy chip with a thickness similar to the sum of these thicknesses is stacked, then even if pressure is applied to the upper surface of the dummy chip, its high rigidity makes it difficult for voids generated within the fourth bonding film structure 740 to be expelled to the outside. As a result, the fifth and sixth bonding films 370 and 440 contained within the fourth bonding film structure 740 are not properly bonded to each other.

[0158] However, in one embodiment, instead of a single thick dummy chip, multiple thin dummy chips 400 are stacked on the third semiconductor chip 300, thereby allowing voids generated within the fourth bonding film structure 740 sandwiched between the third semiconductor chip 300 and the bottommost dummy chip 400, and voids generated within the fifth bonding film structure 750 sandwiched between the vertically stacked dummy chips 400, to be easily discharged to the outside.

[0159] In other words, for example, when the upper surface of each dummy chip 400 is pressed using a bonding tool that has a bulge on the lower surface of the central part, each dummy chip 400 has a thin thickness rather than a thick thickness, resulting in low rigidity and making it easily deformable. As a result, voids formed in the fourth bonding film structure 740 sandwiched between the uppermost dummy chip 400 and the third semiconductor chip 300, or voids formed in the fifth bonding film structure 750 sandwiched between the dummy chips 400, are easily discharged to the outside by the bonding tool.

[0160] Figures 9 to 11 are cross-sectional views illustrating a semiconductor package according to one embodiment of the present invention. Each semiconductor package is substantially identical or similar to the semiconductor package described in Figure 1, except for the dummy chip stack structure, so redundant explanations are omitted.

[0161] As shown in Figure 9, the planar area of ​​the dummy chip stacked structure 500 is larger than the planar area of ​​the second and third semiconductor chips 200 and 300, respectively.

[0162] In one embodiment, when viewed from above, each of the second and third semiconductor chips 200 and 300 is positioned within the region where the dummy chip stack structure 500 is formed, thereby the horizontal width of the dummy chip stack structure 500 is greater than the horizontal width of each of the second and third semiconductor chips 200 and 300.

[0163] As shown in Figure 10, the side walls of the dummy chips 400 contained in the dummy chip stacked structure 500 are not aligned with each other along the vertical direction.

[0164] This type of arrangement occurs when the dummy chips 400 are not properly aligned with each other during the process of stacking them vertically.

[0165] As shown in Figure 11, among the dummy chips 400 contained in the dummy chip stack structure 500, the vertical thickness of the uppermost dummy chip 400 is smaller than the vertical thickness of the remaining dummy chips 400.

[0166] In other words, when the mold member 600 is subjected to a grinding process, the upper part of the top layer of dummy chip 400 is partially removed, resulting in a vertical thickness that is smaller than the vertical thickness of the other dummy chips 400.

[0167] Figures 12 and 13 are cross-sectional views illustrating a semiconductor package according to one embodiment of the present invention, and correspond to Figure 1. Each semiconductor package is substantially identical or similar to the semiconductor package described in Figure 1, except for the dummy chip stacking structure, so redundant explanations are omitted.

[0168] As shown in Figure 12, the dummy chip stacked structure 500 includes vertically stacked dummy chips 400 and a sixth bonding film 440 formed beneath the first surface 412 of each dummy chip 400, and no seventh bonding film 470 is formed on the second surface 414 of each dummy chip 400.

[0169] As shown in Figure 13, the dummy chip stacked structure 500 includes vertically stacked dummy chips 400 and a seventh bonding film 470 formed on the second surface 414 of each dummy chip 400, and no sixth bonding film 440 is formed below the first surface 412 of each dummy chip 400.

[0170] Figure 14 is a cross-sectional view showing an electronic device according to one embodiment of the present invention. The electronic device includes the semiconductor package shown in Figure 1 as the second semiconductor device 50; however, the present invention is not limited thereto, and the electronic device may also include the semiconductor packages shown in Figures 9 to 13 as the second semiconductor package 50.

[0171] As shown in Figure 14, the electronic device 10 includes a package substrate 20, an interposer 30, and first and second semiconductor devices 40 and 50. The electronic device 10 further includes first to third underfill members 34, 44, and 54, a heat slug 60, and a heat dissipation member 62.

[0172] In one embodiment, the electronic device 10 is a memory module having a 2.5D package structure, and includes an interposer 30 for electrically connecting the first and second semiconductor devices 40 and 50 to each other.

[0173] In one embodiment, the first semiconductor device 40 includes a logic device, and the second semiconductor device 50 includes a memory device. The logic device is an application-specific integrated circuit (ASIC) chip that includes, for example, a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor, a microcontroller, an application processor (AP), a digital signal processing core, etc. The memory device includes, for example, a semiconductor package such as an HBM package.

[0174] In one embodiment, the package substrate 20 has an upper surface and a lower surface that face each other in the vertical direction, and is, for example, a printed circuit board (PCB). The printed circuit board is a multilayer circuit board having various circuit patterns inside.

[0175] The interposer 30 is mounted on the package substrate 20 via a third conductive connecting member 32. In one embodiment, when viewed from above, the interposer 30 is located inside the region where the package substrate 20 is formed, and the planar area of ​​the interposer 30 is smaller than the planar area of ​​the package substrate 20.

[0176] The interposer 30 is a silicon interposer or rewiring interposer that includes a plurality of wirings formed inside it. The first semiconductor device 40 and the second semiconductor device 50 are connected to each other via wiring within the interposer 30, or are electrically connected to the package substrate 20 via a third conductive connecting member 32. The third conductive connecting member 32 includes, for example, microbumps. The silicon interposer provides high-density interconnection between the first and second semiconductor devices 40 and 50.

[0177] The first semiconductor device 40 is placed on the interposer 30 and mounted on the interposer 30, for example, by a flip-chip bonding method. Here, the first semiconductor device 40 is mounted on the interposer 30 with the active surface on which the conductive pads are formed facing downwards towards the interposer 30. The conductive pads of the first semiconductor device 40 are electrically connected to the conductive pads of the interposer 30 via a fourth conductive connecting member 42. The fourth conductive connecting member 42 includes, for example, microbumps.

[0178] In contrast, the first semiconductor device 40 is mounted on the interposer 30 using a wire bonding method, in which case the active surface of the first semiconductor device 40 is positioned on top.

[0179] The second semiconductor device 50 is positioned on the interposer 30 and is horizontally separated from the first semiconductor device 40. The second semiconductor device 50 is mounted on the interposer 30, for example, by a flip-chip bonding method. Here, the conductive pads of the second semiconductor device 50 are electrically connected to the conductive pads of the interposer 30 via the fifth conductive connecting member 52.

[0180] Although the drawing shows only one first semiconductor device 40 and one second semiconductor device 50 arranged on the interposer 30, the present invention is not limited to this, and multiple first and second semiconductor devices 40 and 50 can be arranged on the interposer 30.

[0181] In one embodiment, the first underfill member 34 fills the space between the interposer 30 and the package substrate 20, while the second and third underfill members 44 and 54 fill the space between the first semiconductor device 40 and the interposer 30, and the space between the second semiconductor device 50 and the interposer 30, respectively.

[0182] The first to third underfill members 34, 44, and 54 contain a material with relatively high fluidity so as to effectively fill the small space between the first and second semiconductor devices 40, 50 and the interposer 30, or the small space between the interposer 30 and the package substrate 20. For example, each of the first to third underfill members 34, 44, and 54 contains an adhesive containing an epoxy material.

[0183] The second semiconductor device 50 includes a buffer die and a plurality of memory dies (chips) sequentially stacked on the buffer die. The buffer die and the memory dies are electrically connected to each other via through-electrodes, such as through-silicon vias (TSVs), and the through-electrodes are electrically connected to each other via bonding pads. The buffer die and the memory dies communicate data signals and control signals via the through-electrodes.

[0184] In one embodiment, the heat slag 60 covers the first and second semiconductor devices 40 and 50 on the package substrate 20 so as to be in thermal contact with them. Meanwhile, a heat dissipation member 62 is placed on the upper surface of each of the first and second semiconductor devices 40 and 50, and the heat dissipation member 62 includes, for example, a thermal interface material (TIM). The heat slag 60 is in thermal contact with the first and second semiconductor devices 40 and 50 via the heat dissipation member 62.

[0185] A conductive pad is formed on the lower part of the package substrate 20, and the second conductive connecting member 22 contacts the lower surface of the conductive pad and is electrically connected to it. In one embodiment, a plurality of the second conductive connecting members 22 are formed spaced apart from each other along the horizontal direction. The second conductive connecting member 22 is, for example, a solder ball. The electronic device 10 is mounted on a module substrate (not shown) via the second conductive connecting members 22 to constitute a memory module.

[0186] While embodiments of the present invention have been described above with reference to the present invention, those skilled in the art will understand that the present invention can be modified and altered in various ways without departing from the spirit and art of the present invention. [Explanation of Symbols]

[0187] 100 First Semiconductor Chip 110 First board 120 1st through electrode structure 130 Second Interlayer Insulating Film 135 1st wiring structure 140 conductive pads 150 First conductive connecting member 160 First protective pattern structure 170 1st bonding film 175 First icing pad 200 Second Semiconductor Chip 210 Second board 220 2nd through electrode structure 230 Fourth Interlayer Insulation Film 235 2nd wiring structure 240 Second bonding film 245 Second bonding pad 260 Second protective pattern structure 270 Third bonding film 275 Third bonding pad 300 Third Semiconductor Chips 310 Third board 330 Interlayer Insulation Film #6 335 Third wiring structure 340 4th bonding film 345 Fourth bonding pad 370 5th bonding film 400 dummy chips 410 Fourth board 440 6th bonding film 470 7th bonding film 500 Dummy Chip Stacked Structure 600 molded components 710 First bonding membrane structure 715 First Joining Pad Structure 720 Second bonding membrane structure 725 Second Joining Pad Structure 730 Third bonding membrane structure 735 Third Joint Pad Structure 740 4th bonding membrane structure 750 5th bonding membrane structure

Claims

1. Buffer die and A plurality of middle core dies stacked vertically on the buffer die, A top core die positioned on the uppermost middle core die among the plurality of middle core dies, The top core die is stacked vertically on a plurality of dummy dies, A first bonding film structure, which includes a first bonding pad structure, is sandwiched between adjacent middle core dies among the plurality of middle core dies, and these are joined together. A second bonding membrane structure is sandwiched between the top core die and the lowest dummy die among the plurality of dummy dies, thereby joining them together. A semiconductor package characterized by including a third bonding film structure sandwiched between adjacent dummy dies among the plurality of dummy dies to bond them together.

2. The semiconductor package according to claim 1, characterized in that the third bonding film structure includes first and second bonding films stacked along the vertical direction.

3. Each of the first and second bonding films is made of silicon carbonitride (SiCN), silicon nitride (SiN), or silicon oxide (SiO ２ The semiconductor package according to claim 2, characterized by including ).

4. Each of the aforementioned middle core dies is First circuit board and A first interlayer insulating film formed beneath the first substrate and housing the first wiring structure, A through electrode extending vertically through the first substrate, The first substrate includes a protective pattern structure formed on the first substrate and surrounding the upper part of the through electrode, The semiconductor package according to claim 1, characterized in that the through electrode is in contact with the first bonding pad structure.

5. The aforementioned top core die is The second circuit board and It includes a second interlayer insulating film formed beneath the second substrate and housing a second wiring structure, The semiconductor package according to claim 4, further comprising a fourth bonding film structure which includes a second bonding pad structure sandwiched between the uppermost middle core die and the top core die among the plurality of middle core dies, bonding them together, and in contact with the through electrode formed on the uppermost middle core die.

6. The semiconductor package according to claim 1, characterized in that the sum of the vertical thicknesses of the plurality of dummy dies is greater than the vertical thickness of each of the plurality of middle core dies and the vertical thickness of the top core die.

7. The semiconductor package according to claim 1, characterized in that the planar area of ​​each of the plurality of dummy dies is larger than the planar area of ​​each of the plurality of middle core dies or the planar area of ​​the top core die.

8. The semiconductor package according to claim 1, characterized in that the side walls of the plurality of dummy dies are not aligned with each other along the vertical direction.

9. First semiconductor chip and A plurality of second semiconductor chips are stacked vertically on the first semiconductor chip, each including a substrate and a through-electrode extending vertically through the substrate. A third semiconductor chip is placed on the uppermost second semiconductor chip among the plurality of second semiconductor chips, The plurality of dummy chips stacked vertically on the third semiconductor chip, A first bonding film structure includes a first bonding pad structure sandwiched between the second semiconductor chips that are adjacent to each other in the vertical direction, bonding them together, and electrically connected to the through-electrode included in at least one of the plurality of second semiconductor chips, A second bonding film structure is sandwiched between the uppermost second semiconductor chip and the third semiconductor chip among the plurality of second semiconductor chips, bonding them together, and includes a second bonding pad structure electrically connected to the through-electrode contained in the uppermost second semiconductor chip, A third bonding film structure is sandwiched between the third semiconductor chip and the bottommost dummy chip among the plurality of dummy chips to bond them together, A semiconductor package characterized by including a fourth bonding film structure sandwiched between adjacent dummy chips among the plurality of dummy chips to bond them together.

10. A first semiconductor chip comprising a first substrate and a first through-electrode extending vertically through the first substrate, A first bonding film structure including a first bonding pad structure disposed on the first semiconductor chip and electrically connected to the first through-electrode, A plurality of second semiconductor chips are stacked on the first bonding film structure along the vertical direction, each including a second substrate and a second through-electrode extending vertically through the second substrate. A second bonding film structure includes a second bonding pad structure sandwiched between vertically adjacent second semiconductor chips among the plurality of second semiconductor chips, which bond them together, and which is electrically connected to the second through-electrode included in at least one of the plurality of second semiconductor chips, A third bonding film structure including a third bonding pad structure disposed on the uppermost second semiconductor chip among the plurality of second semiconductor chips and electrically connected to the second through-electrode contained therein, A third semiconductor chip disposed on the third bonding film structure, A fourth junction film structure disposed on the third semiconductor chip, A plurality of dummy chips stacked vertically on the fourth bonding film structure, A fifth bonding membrane structure is sandwiched between adjacent dummy chips among the plurality of dummy chips, and these dummy chips are joined together. A semiconductor package characterized by comprising a mold member formed on the first semiconductor chip and covering the side walls of the first to third semiconductor chips, the side walls of the plurality of dummy chips, and the side walls of the first to fifth bonding film structures.

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